mirror of
https://github.com/The-OpenROAD-Project/OpenSTA.git
synced 2026-09-05 09:02:12 +02:00
Jaehyun Kim
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--- bus port queries ---
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total ports: 27
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data_a* ports: 8
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data_b* ports: 8
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result* ports: 8
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--- individual bus bit queries ---
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data_a[0] direction: input
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data_a[1] direction: input
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data_a[2] direction: input
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data_a[3] direction: input
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data_a[4] direction: input
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data_a[5] direction: input
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data_a[6] direction: input
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data_a[7] direction: input
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result[0] direction: output
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result[1] direction: output
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result[2] direction: output
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result[3] direction: output
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result[4] direction: output
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result[5] direction: output
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result[6] direction: output
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result[7] direction: output
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--- wildcard bus subscript ---
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data_a[*] ports: 8
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data_b[*] ports: 8
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result[*] ports: 8
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--- bus-style pin queries ---
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all pins: 98
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buf_a* pins: 16
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and* pins: 27
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reg* pins: 48
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--- bus-style net queries ---
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all nets: 45
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stage1* nets: 8
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stage2* nets: 8
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--- cell pattern queries ---
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total cells: 28
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buf* cells: 10
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and* cells: 9
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reg* cells: 8
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or* cells: 1
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--- hierarchical queries ---
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hierarchical cells: 28
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hierarchical nets: 45
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hierarchical pins: 98
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--- report_net on bus nets ---
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Net stage1[0]
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Pin capacitance: 0.87-0.92
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Wire capacitance: 0.00
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Total capacitance: 0.87-0.92
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Number of drivers: 1
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Number of loads: 1
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Number of pins: 2
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Driver pins
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buf_a0/Z output (BUF_X1)
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Load pins
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and0/A1 input (AND2_X1) 0.87-0.92
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report_net stage1[0]: done
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Net stage1[7]
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Pin capacitance: 0.87-0.92
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Wire capacitance: 0.00
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Total capacitance: 0.87-0.92
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Number of drivers: 1
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Number of loads: 1
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Number of pins: 2
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Driver pins
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buf_a7/Z output (BUF_X1)
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Load pins
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and7/A1 input (AND2_X1) 0.87-0.92
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report_net stage1[7]: done
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Net stage2[0]
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Pin capacitance: 1.06-1.14
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Wire capacitance: 0.00
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Total capacitance: 1.06-1.14
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Number of drivers: 1
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Number of loads: 1
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Number of pins: 2
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Driver pins
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and0/ZN output (AND2_X1)
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Load pins
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reg0/D input (DFF_X1) 1.06-1.14
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report_net stage2[0]: done
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Net stage2[7]
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Pin capacitance: 2.73-3.01
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Wire capacitance: 0.00
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Total capacitance: 2.73-3.01
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Number of drivers: 1
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Number of loads: 3
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Number of pins: 4
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Driver pins
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and7/ZN output (AND2_X1)
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Load pins
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and_ovfl/A1 input (AND2_X1) 0.87-0.92
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or_carry/A1 input (OR2_X1) 0.79-0.95
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reg7/D input (DFF_X1) 1.06-1.14
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report_net stage2[7]: done
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--- report_instance on cells ---
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Instance buf_a0
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Cell: BUF_X1
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Library: NangateOpenCellLibrary
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Path cells: BUF_X1
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Input pins:
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A input data_a[0]
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Output pins:
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Z output stage1[0]
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Other pins:
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VDD power (unconnected)
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VSS ground (unconnected)
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report_instance buf_a0: done
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Instance and0
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Cell: AND2_X1
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Library: NangateOpenCellLibrary
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Path cells: AND2_X1
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Input pins:
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A1 input stage1[0]
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A2 input data_b[0]
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Output pins:
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ZN output stage2[0]
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Other pins:
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VDD power (unconnected)
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VSS ground (unconnected)
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report_instance and0: done
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Instance reg0
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Cell: DFF_X1
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Library: NangateOpenCellLibrary
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Path cells: DFF_X1
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Input pins:
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D input stage2[0]
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CK input clk
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Output pins:
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Q output result[0]
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QN output (unconnected)
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Other pins:
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IQ internal (unconnected)
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IQN internal (unconnected)
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VDD power (unconnected)
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VSS ground (unconnected)
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report_instance reg0: done
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Instance or_carry
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Cell: OR2_X1
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Library: NangateOpenCellLibrary
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Path cells: OR2_X1
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Input pins:
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A1 input stage2[7]
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A2 input stage2[6]
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Output pins:
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ZN output internal_carry
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Other pins:
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VDD power (unconnected)
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VSS ground (unconnected)
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report_instance or_carry: done
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Instance buf_carry
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Cell: BUF_X1
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Library: NangateOpenCellLibrary
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Path cells: BUF_X1
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Input pins:
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A input internal_carry
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Output pins:
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Z output carry
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Other pins:
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VDD power (unconnected)
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VSS ground (unconnected)
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report_instance buf_carry: done
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--- lib cell queries ---
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BUF* lib cells: 6
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AND* lib cells: 9
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OR* lib cells: 9
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INV* lib cells: 6
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DFF* lib cells: 8
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--- timing analysis ---
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Startpoint: data_a[6] (input port clocked by clk)
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Endpoint: carry (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v data_a[6] (in)
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0.02 0.02 v buf_a6/Z (BUF_X1)
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0.03 0.05 v and6/ZN (AND2_X1)
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0.05 0.10 v or_carry/ZN (OR2_X1)
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0.02 0.12 v buf_carry/Z (BUF_X1)
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0.00 0.12 v carry (out)
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0.12 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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0.00 10.00 output external delay
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10.00 data required time
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---------------------------------------------------------
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10.00 data required time
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-0.12 data arrival time
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---------------------------------------------------------
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9.88 slack (MET)
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Startpoint: data_b[0] (input port clocked by clk)
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Endpoint: reg0 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: min
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ input external delay
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0.00 0.00 ^ data_b[0] (in)
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0.03 0.03 ^ and0/ZN (AND2_X1)
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0.00 0.03 ^ reg0/D (DFF_X1)
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0.03 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 ^ reg0/CK (DFF_X1)
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0.01 0.01 library hold time
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0.01 data required time
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---------------------------------------------------------
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0.01 data required time
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-0.03 data arrival time
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---------------------------------------------------------
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0.02 slack (MET)
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No paths found.
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Warning: network_bus_parse.tcl line 1, unknown field nets.
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Startpoint: data_a[6] (input port clocked by clk)
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Endpoint: carry (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Fanout Cap Slew Delay Time Description
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-----------------------------------------------------------------------------
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0.00 0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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1 0.88 0.00 0.00 0.00 v data_a[6] (in)
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0.00 0.00 0.00 v buf_a6/A (BUF_X1)
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1 0.87 0.00 0.02 0.02 v buf_a6/Z (BUF_X1)
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0.00 0.00 0.02 v and6/A1 (AND2_X1)
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3 2.85 0.01 0.03 0.05 v and6/ZN (AND2_X1)
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0.01 0.00 0.05 v or_carry/A2 (OR2_X1)
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1 0.88 0.01 0.05 0.10 v or_carry/ZN (OR2_X1)
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0.01 0.00 0.10 v buf_carry/A (BUF_X1)
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1 0.00 0.00 0.02 0.12 v buf_carry/Z (BUF_X1)
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0.00 0.00 0.12 v carry (out)
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0.12 data arrival time
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0.00 10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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0.00 10.00 output external delay
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10.00 data required time
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-----------------------------------------------------------------------------
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10.00 data required time
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-0.12 data arrival time
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-----------------------------------------------------------------------------
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9.88 slack (MET)
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ALL PASSED
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Reference in New Issue
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