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test: Initial upload

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Signed-off-by: Jaehyun Kim <[email protected]>
This commit is contained in:
Jaehyun Kim
2026-02-13 19:19:09 +09:00
parent e872c55bfe
commit d6c09372ba
733 changed files with 2946117 additions and 38 deletions
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--- Test 1: baseline ---
Startpoint: d2 (input port clocked by clk)
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
1.00 1.00 v input external delay
0.00 1.00 v d2 (in)
0.06 1.06 v buf2/Z (BUF_X1)
0.05 1.11 v or1/ZN (OR2_X1)
0.02 1.12 ^ nand1/ZN (NAND2_X1)
0.00 1.12 ^ reg2/D (DFF_X1)
1.12 data arrival time
10.00 10.00 clock clk (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
10.00 ^ reg2/CK (DFF_X1)
-0.03 9.97 library setup time
9.97 data required time
---------------------------------------------------------
9.97 data required time
-1.12 data arrival time
---------------------------------------------------------
8.85 slack (MET)
PASS: baseline max
Startpoint: d3 (input port clocked by clk)
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: min
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
1.00 1.00 ^ input external delay
0.00 1.00 ^ d3 (in)
0.01 1.01 v inv1/ZN (INV_X1)
0.03 1.04 ^ nor1/ZN (NOR2_X1)
0.00 1.04 ^ reg3/D (DFF_X1)
1.04 data arrival time
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 clock reconvergence pessimism
0.00 ^ reg3/CK (DFF_X1)
0.01 0.01 library hold time
0.01 data required time
---------------------------------------------------------
0.01 data required time
-1.04 data arrival time
---------------------------------------------------------
1.03 slack (MET)
PASS: baseline min
Warning: graph_delete_modify.tcl line 1, unknown field nets.
Startpoint: d2 (input port clocked by clk)
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
1.00 1.00 v input external delay
1 0.88 0.10 0.00 1.00 v d2 (in)
0.10 0.00 1.00 v buf2/A (BUF_X1)
2 1.69 0.01 0.06 1.06 v buf2/Z (BUF_X1)
0.01 0.00 1.06 v or1/A1 (OR2_X1)
2 2.56 0.01 0.05 1.11 v or1/ZN (OR2_X1)
0.01 0.00 1.11 v nand1/A2 (NAND2_X1)
1 1.14 0.01 0.02 1.12 ^ nand1/ZN (NAND2_X1)
0.01 0.00 1.12 ^ reg2/D (DFF_X1)
1.12 data arrival time
0.00 10.00 10.00 clock clk (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
10.00 ^ reg2/CK (DFF_X1)
-0.03 9.97 library setup time
9.97 data required time
-----------------------------------------------------------------------------
9.97 data required time
-1.12 data arrival time
-----------------------------------------------------------------------------
8.85 slack (MET)
PASS: baseline fields
--- Test 2: add/delete multiple instances ---
PASS: added buffer chain
Startpoint: d2 (input port clocked by clk)
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
1.00 1.00 v input external delay
0.00 1.00 v d2 (in)
0.06 1.06 v buf2/Z (BUF_X1)
0.05 1.11 v or1/ZN (OR2_X1)
0.02 1.12 ^ nand1/ZN (NAND2_X1)
0.00 1.12 ^ reg2/D (DFF_X1)
1.12 data arrival time
10.00 10.00 clock clk (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
10.00 ^ reg2/CK (DFF_X1)
-0.03 9.97 library setup time
9.97 data required time
---------------------------------------------------------
9.97 data required time
-1.12 data arrival time
---------------------------------------------------------
8.85 slack (MET)
PASS: timing after add chain
Startpoint: d2 (input port clocked by clk)
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
1.00 1.00 v input external delay
0.00 1.00 v d2 (in)
0.06 1.06 v buf2/Z (BUF_X1)
0.05 1.11 v or1/ZN (OR2_X1)
0.02 1.12 ^ nand1/ZN (NAND2_X1)
0.00 1.12 ^ reg2/D (DFF_X1)
1.12 data arrival time
10.00 10.00 clock clk (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
10.00 ^ reg2/CK (DFF_X1)
-0.03 9.97 library setup time
9.97 data required time
---------------------------------------------------------
9.97 data required time
-1.12 data arrival time
---------------------------------------------------------
8.85 slack (MET)
PASS: timing after partial disconnect
Startpoint: d2 (input port clocked by clk)
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
1.00 1.00 v input external delay
0.00 1.00 v d2 (in)
0.06 1.06 v buf2/Z (BUF_X1)
0.05 1.11 v or1/ZN (OR2_X1)
0.02 1.12 ^ nand1/ZN (NAND2_X1)
0.00 1.12 ^ reg2/D (DFF_X1)
1.12 data arrival time
10.00 10.00 clock clk (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
10.00 ^ reg2/CK (DFF_X1)
-0.03 9.97 library setup time
9.97 data required time
---------------------------------------------------------
9.97 data required time
-1.12 data arrival time
---------------------------------------------------------
8.85 slack (MET)
PASS: timing after reconnect
PASS: full cleanup
Startpoint: d2 (input port clocked by clk)
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
1.00 1.00 v input external delay
0.00 1.00 v d2 (in)
0.06 1.06 v buf2/Z (BUF_X1)
0.05 1.11 v or1/ZN (OR2_X1)
0.02 1.12 ^ nand1/ZN (NAND2_X1)
0.00 1.12 ^ reg2/D (DFF_X1)
1.12 data arrival time
10.00 10.00 clock clk (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
10.00 ^ reg2/CK (DFF_X1)
-0.03 9.97 library setup time
9.97 data required time
---------------------------------------------------------
9.97 data required time
-1.12 data arrival time
---------------------------------------------------------
8.85 slack (MET)
PASS: timing after full cleanup
--- Test 3: replace_cell ---
Startpoint: d2 (input port clocked by clk)
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
1.00 1.00 v input external delay
0.00 1.00 v d2 (in)
0.06 1.06 v buf2/Z (BUF_X1)
0.05 1.11 v or1/ZN (OR2_X1)
0.02 1.12 ^ nand1/ZN (NAND2_X1)
0.00 1.12 ^ reg2/D (DFF_X1)
1.12 data arrival time
10.00 10.00 clock clk (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
10.00 ^ reg2/CK (DFF_X1)
-0.03 9.97 library setup time
9.97 data required time
---------------------------------------------------------
9.97 data required time
-1.12 data arrival time
---------------------------------------------------------
8.85 slack (MET)
A -> Z combinational
^ -> ^ 0.03:0.03
v -> v 0.05:0.05
PASS: buf1 -> BUF_X4
Startpoint: d2 (input port clocked by clk)
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
1.00 1.00 v input external delay
0.00 1.00 v d2 (in)
0.06 1.06 v buf2/Z (BUF_X1)
0.05 1.11 v or1/ZN (OR2_X1)
0.02 1.12 ^ nand1/ZN (NAND2_X1)
0.00 1.12 ^ reg2/D (DFF_X1)
1.12 data arrival time
10.00 10.00 clock clk (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
10.00 ^ reg2/CK (DFF_X1)
-0.03 9.97 library setup time
9.97 data required time
---------------------------------------------------------
9.97 data required time
-1.12 data arrival time
---------------------------------------------------------
8.85 slack (MET)
PASS: buf1 -> BUF_X2
Startpoint: d2 (input port clocked by clk)
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
1.00 1.00 v input external delay
0.00 1.00 v d2 (in)
0.06 1.06 v buf2/Z (BUF_X1)
0.05 1.11 v or1/ZN (OR2_X1)
0.02 1.12 ^ nand1/ZN (NAND2_X1)
0.00 1.12 ^ reg2/D (DFF_X1)
1.12 data arrival time
10.00 10.00 clock clk (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
10.00 ^ reg2/CK (DFF_X1)
-0.03 9.97 library setup time
9.97 data required time
---------------------------------------------------------
9.97 data required time
-1.12 data arrival time
---------------------------------------------------------
8.85 slack (MET)
PASS: buf1 restored
Startpoint: d2 (input port clocked by clk)
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
1.00 1.00 v input external delay
0.00 1.00 v d2 (in)
0.06 1.06 v buf2/Z (BUF_X1)
0.05 1.11 v or1/ZN (OR2_X1)
0.02 1.12 ^ nand1/ZN (NAND2_X1)
0.00 1.12 ^ reg2/D (DFF_X1)
1.12 data arrival time
10.00 10.00 clock clk (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
10.00 ^ reg2/CK (DFF_X1)
-0.03 9.97 library setup time
9.97 data required time
---------------------------------------------------------
9.97 data required time
-1.12 data arrival time
---------------------------------------------------------
8.85 slack (MET)
PASS: and1 -> AND2_X2
Startpoint: d2 (input port clocked by clk)
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
1.00 1.00 v input external delay
0.00 1.00 v d2 (in)
0.06 1.06 v buf2/Z (BUF_X1)
0.05 1.11 v or1/ZN (OR2_X1)
0.02 1.12 ^ nand1/ZN (NAND2_X1)
0.00 1.12 ^ reg2/D (DFF_X1)
1.12 data arrival time
10.00 10.00 clock clk (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
10.00 ^ reg2/CK (DFF_X1)
-0.03 9.97 library setup time
9.97 data required time
---------------------------------------------------------
9.97 data required time
-1.12 data arrival time
---------------------------------------------------------
8.85 slack (MET)
PASS: and1 restored
Startpoint: d2 (input port clocked by clk)
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
1.00 1.00 v input external delay
0.00 1.00 v d2 (in)
0.06 1.06 v buf2/Z (BUF_X1)
0.05 1.11 v or1/ZN (OR2_X1)
0.02 1.12 ^ nand1/ZN (NAND2_X1)
0.00 1.12 ^ reg2/D (DFF_X1)
1.12 data arrival time
10.00 10.00 clock clk (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
10.00 ^ reg2/CK (DFF_X1)
-0.03 9.97 library setup time
9.97 data required time
---------------------------------------------------------
9.97 data required time
-1.12 data arrival time
---------------------------------------------------------
8.85 slack (MET)
PASS: inv1 -> INV_X2
Startpoint: d2 (input port clocked by clk)
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
1.00 1.00 v input external delay
0.00 1.00 v d2 (in)
0.06 1.06 v buf2/Z (BUF_X1)
0.05 1.11 v or1/ZN (OR2_X1)
0.02 1.12 ^ nand1/ZN (NAND2_X1)
0.00 1.12 ^ reg2/D (DFF_X1)
1.12 data arrival time
10.00 10.00 clock clk (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
10.00 ^ reg2/CK (DFF_X1)
-0.03 9.97 library setup time
9.97 data required time
---------------------------------------------------------
9.97 data required time
-1.12 data arrival time
---------------------------------------------------------
8.85 slack (MET)
PASS: inv1 restored
--- Test 4: add/delete register ---
Startpoint: d2 (input port clocked by clk)
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
1.00 1.00 v input external delay
0.00 1.00 v d2 (in)
0.06 1.06 v buf2/Z (BUF_X1)
0.05 1.11 v or1/ZN (OR2_X1)
0.02 1.12 ^ nand1/ZN (NAND2_X1)
0.00 1.12 ^ reg2/D (DFF_X1)
1.12 data arrival time
10.00 10.00 clock clk (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
10.00 ^ reg2/CK (DFF_X1)
-0.03 9.97 library setup time
9.97 data required time
---------------------------------------------------------
9.97 data required time
-1.12 data arrival time
---------------------------------------------------------
8.85 slack (MET)
PASS: timing with added register
PASS: register removed
Startpoint: d2 (input port clocked by clk)
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
1.00 1.00 v input external delay
0.00 1.00 v d2 (in)
0.06 1.06 v buf2/Z (BUF_X1)
0.05 1.11 v or1/ZN (OR2_X1)
0.02 1.12 ^ nand1/ZN (NAND2_X1)
0.00 1.12 ^ reg2/D (DFF_X1)
1.12 data arrival time
10.00 10.00 clock clk (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
10.00 ^ reg2/CK (DFF_X1)
-0.03 9.97 library setup time
9.97 data required time
---------------------------------------------------------
9.97 data required time
-1.12 data arrival time
---------------------------------------------------------
8.85 slack (MET)
PASS: timing after register removal
--- Test 5: rapid connect/disconnect ---
Startpoint: d2 (input port clocked by clk)
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
1.00 1.00 v input external delay
0.00 1.00 v d2 (in)
0.06 1.06 v buf2/Z (BUF_X1)
0.05 1.11 v or1/ZN (OR2_X1)
0.02 1.12 ^ nand1/ZN (NAND2_X1)
0.00 1.12 ^ reg2/D (DFF_X1)
1.12 data arrival time
10.00 10.00 clock clk (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
10.00 ^ reg2/CK (DFF_X1)
-0.03 9.97 library setup time
9.97 data required time
---------------------------------------------------------
9.97 data required time
-1.12 data arrival time
---------------------------------------------------------
8.85 slack (MET)
cycle 1 done
Startpoint: d2 (input port clocked by clk)
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
1.00 1.00 v input external delay
0.00 1.00 v d2 (in)
0.06 1.06 v buf2/Z (BUF_X1)
0.05 1.11 v or1/ZN (OR2_X1)
0.02 1.12 ^ nand1/ZN (NAND2_X1)
0.00 1.12 ^ reg2/D (DFF_X1)
1.12 data arrival time
10.00 10.00 clock clk (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
10.00 ^ reg2/CK (DFF_X1)
-0.03 9.97 library setup time
9.97 data required time
---------------------------------------------------------
9.97 data required time
-1.12 data arrival time
---------------------------------------------------------
8.85 slack (MET)
cycle 2 done
Startpoint: d2 (input port clocked by clk)
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
1.00 1.00 v input external delay
0.00 1.00 v d2 (in)
0.06 1.06 v buf2/Z (BUF_X1)
0.05 1.11 v or1/ZN (OR2_X1)
0.02 1.12 ^ nand1/ZN (NAND2_X1)
0.00 1.12 ^ reg2/D (DFF_X1)
1.12 data arrival time
10.00 10.00 clock clk (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
10.00 ^ reg2/CK (DFF_X1)
-0.03 9.97 library setup time
9.97 data required time
---------------------------------------------------------
9.97 data required time
-1.12 data arrival time
---------------------------------------------------------
8.85 slack (MET)
cycle 3 done
PASS: rapid cycles
Startpoint: d2 (input port clocked by clk)
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
1.00 1.00 v input external delay
0.00 1.00 v d2 (in)
0.06 1.06 v buf2/Z (BUF_X1)
0.05 1.11 v or1/ZN (OR2_X1)
0.02 1.12 ^ nand1/ZN (NAND2_X1)
0.00 1.12 ^ reg2/D (DFF_X1)
1.12 data arrival time
10.00 10.00 clock clk (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
10.00 ^ reg2/CK (DFF_X1)
-0.03 9.97 library setup time
9.97 data required time
---------------------------------------------------------
9.97 data required time
-1.12 data arrival time
---------------------------------------------------------
8.85 slack (MET)
PASS: timing after rapid cycles
--- Test 6: edge queries ---
buf1 edges: 1
buf2 edges: 1
inv1 edges: 1
and1 edges: 1
or1 edges: 1
nand1 edges: 1
nor1 edges: 1
reg1 edges: 1
reg2 edges: 1
reg3 edges: 1
reg4 edges: 1
PASS: edge queries
d1 ^ 0.10:0.10 v 0.10:0.10
d2 ^ 0.10:0.10 v 0.10:0.10
d3 ^ 0.10:0.10 v 0.10:0.10
buf1/Z ^ 0.01:0.01 v 0.01:0.01
and1/ZN ^ 0.01:0.01 v 0.01:0.01
reg1/Q ^ 0.01:0.01 v 0.00:0.00
PASS: slew queries
--- Test 7: through pins ---
Startpoint: d2 (input port clocked by clk)
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
1.00 1.00 v input external delay
0.00 1.00 v d2 (in)
0.06 1.06 v buf2/Z (BUF_X1)
0.05 1.11 v or1/ZN (OR2_X1)
0.02 1.12 ^ nand1/ZN (NAND2_X1)
0.00 1.12 ^ reg2/D (DFF_X1)
1.12 data arrival time
10.00 10.00 clock clk (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
10.00 ^ reg2/CK (DFF_X1)
-0.03 9.97 library setup time
9.97 data required time
---------------------------------------------------------
9.97 data required time
-1.12 data arrival time
---------------------------------------------------------
8.85 slack (MET)
through nand1: done
Startpoint: d2 (input port clocked by clk)
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
1.00 1.00 v input external delay
0.00 1.00 v d2 (in)
0.06 1.06 v buf2/Z (BUF_X1)
0.04 1.09 v and1/ZN (AND2_X1)
0.02 1.11 ^ nor1/ZN (NOR2_X1)
0.00 1.11 ^ reg3/D (DFF_X1)
1.11 data arrival time
10.00 10.00 clock clk (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
10.00 ^ reg3/CK (DFF_X1)
-0.03 9.97 library setup time
9.97 data required time
---------------------------------------------------------
9.97 data required time
-1.11 data arrival time
---------------------------------------------------------
8.85 slack (MET)
through nor1: done
Startpoint: d2 (input port clocked by clk)
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
1.00 1.00 v input external delay
0.00 1.00 v d2 (in)
0.06 1.06 v buf2/Z (BUF_X1)
0.04 1.09 v and1/ZN (AND2_X1)
0.02 1.11 ^ nor1/ZN (NOR2_X1)
0.00 1.11 ^ reg3/D (DFF_X1)
1.11 data arrival time
10.00 10.00 clock clk (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
10.00 ^ reg3/CK (DFF_X1)
-0.03 9.97 library setup time
9.97 data required time
---------------------------------------------------------
9.97 data required time
-1.11 data arrival time
---------------------------------------------------------
8.85 slack (MET)
through and1: done
PASS: through pin queries
ALL PASSED