mirror of
https://github.com/The-OpenROAD-Project/OpenSTA.git
synced 2026-08-29 17:28:57 +02:00
Jaehyun Kim
@@ -0,0 +1,78 @@
|
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add_test(
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NAME tcl.graph.make_verify
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COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> graph_make_verify
|
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WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
|
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)
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set_tests_properties(tcl.graph.make_verify PROPERTIES LABELS "tcl;module_graph")
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|
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add_test(
|
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NAME tcl.graph.timing_edges
|
||||
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> graph_timing_edges
|
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WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
|
||||
)
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set_tests_properties(tcl.graph.timing_edges PROPERTIES LABELS "tcl;module_graph")
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add_test(
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NAME tcl.graph.advanced
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COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> graph_advanced
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WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
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)
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set_tests_properties(tcl.graph.advanced PROPERTIES LABELS "tcl;module_graph")
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|
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add_test(
|
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NAME tcl.graph.incremental
|
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COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> graph_incremental
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WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
|
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)
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set_tests_properties(tcl.graph.incremental PROPERTIES LABELS "tcl;module_graph")
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|
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add_test(
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NAME tcl.graph.delay_corners
|
||||
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> graph_delay_corners
|
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WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
|
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)
|
||||
set_tests_properties(tcl.graph.delay_corners PROPERTIES LABELS "tcl;module_graph")
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add_test(
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NAME tcl.graph.operations
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COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> graph_operations
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WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
|
||||
)
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||||
set_tests_properties(tcl.graph.operations PROPERTIES LABELS "tcl;module_graph")
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||||
add_test(
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NAME tcl.graph.modify
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COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> graph_modify
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WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
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)
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set_tests_properties(tcl.graph.modify PROPERTIES LABELS "tcl;module_graph")
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add_test(
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NAME tcl.graph.bidirect
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COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> graph_bidirect
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WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
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)
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set_tests_properties(tcl.graph.bidirect PROPERTIES LABELS "tcl;module_graph")
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add_test(
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NAME tcl.graph.wire_inst_edges
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COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> graph_wire_inst_edges
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WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
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)
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set_tests_properties(tcl.graph.wire_inst_edges PROPERTIES LABELS "tcl;module_graph")
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add_test(
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NAME tcl.graph.delete_modify
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COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> graph_delete_modify
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WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
|
||||
)
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set_tests_properties(tcl.graph.delete_modify PROPERTIES LABELS "tcl;module_graph")
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add_test(
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NAME tcl.graph.vertex_edge_ops
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COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> graph_vertex_edge_ops
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WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
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)
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set_tests_properties(tcl.graph.vertex_edge_ops PROPERTIES LABELS "tcl;module_graph")
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add_subdirectory(cpp)
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@@ -0,0 +1,16 @@
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add_executable(TestGraph TestGraph.cc)
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target_link_libraries(TestGraph
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OpenSTA
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GTest::gtest
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GTest::gtest_main
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${TCL_LIBRARY}
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)
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target_include_directories(TestGraph PRIVATE
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${STA_HOME}/include/sta
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${STA_HOME}
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${CMAKE_BINARY_DIR}/include/sta
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)
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gtest_discover_tests(TestGraph
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WORKING_DIRECTORY ${STA_HOME}
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PROPERTIES LABELS "cpp;module_graph"
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)
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File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,475 @@
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--- report_checks baseline ---
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Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: q (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg2/CK (DFF_X1)
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0.08 0.08 ^ reg2/Q (DFF_X1)
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0.00 0.08 ^ q (out)
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0.08 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
|
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-1.00 9.00 output external delay
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9.00 data required time
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---------------------------------------------------------
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9.00 data required time
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-0.08 data arrival time
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---------------------------------------------------------
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8.92 slack (MET)
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PASS: report_checks baseline
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--- report_checks -path_delay min ---
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: min
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg1/CK (DFF_X1)
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0.08 0.08 v reg1/Q (DFF_X1)
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0.00 0.08 v reg2/D (DFF_X1)
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0.08 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 ^ reg2/CK (DFF_X1)
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0.00 0.00 library hold time
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0.00 data required time
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---------------------------------------------------------
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0.00 data required time
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-0.08 data arrival time
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---------------------------------------------------------
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0.08 slack (MET)
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PASS: report_checks -path_delay min
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--- report_checks -path_delay max ---
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Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: q (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg2/CK (DFF_X1)
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0.08 0.08 ^ reg2/Q (DFF_X1)
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0.00 0.08 ^ q (out)
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0.08 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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||||
0.00 10.00 clock reconvergence pessimism
|
||||
-1.00 9.00 output external delay
|
||||
9.00 data required time
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||||
---------------------------------------------------------
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||||
9.00 data required time
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||||
-0.08 data arrival time
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||||
---------------------------------------------------------
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8.92 slack (MET)
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PASS: report_checks -path_delay max
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--- report_checks -from/-to ---
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No paths found.
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PASS: report_checks -from/-to
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--- report_checks -through ---
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
|
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Delay Time Description
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||||
---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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||||
0.00 0.00 ^ reg1/CK (DFF_X1)
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||||
0.08 0.08 v reg1/Q (DFF_X1)
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0.00 0.08 v reg2/D (DFF_X1)
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0.08 data arrival time
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||||
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||||
10.00 10.00 clock clk (rise edge)
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||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
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-0.04 9.96 library setup time
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||||
9.96 data required time
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||||
---------------------------------------------------------
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||||
9.96 data required time
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||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
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9.88 slack (MET)
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PASS: report_checks -through
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--- get_timing_edges full combinations ---
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reg1 all edges: 1
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reg2 all edges: 1
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--- report_edges for cells ---
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CK -> Q Reg Clk to Q
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^ -> ^ 0.08:0.08
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^ -> v 0.08:0.08
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PASS: report_edges reg1 CK->Q
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CK -> Q Reg Clk to Q
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^ -> ^ 0.08:0.08
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^ -> v 0.08:0.08
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PASS: report_edges reg2 CK->Q
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CK -> QN Reg Clk to Q
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^ -> ^ 0.06:0.06
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^ -> v 0.06:0.06
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CK -> Q Reg Clk to Q
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^ -> ^ 0.08:0.08
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||||
^ -> v 0.08:0.08
|
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CK -> CK width
|
||||
^ -> v 0.05:0.05
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v -> ^ 0.05:0.05
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CK -> D setup
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^ -> ^ 0.05:0.05
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^ -> v 0.07:0.07
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CK -> D hold
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||||
^ -> ^ 0.05:0.05
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^ -> v 0.05:0.05
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PASS: report_edges from reg1/CK
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CK -> D setup
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^ -> ^ 0.03:0.03
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||||
^ -> v 0.04:0.04
|
||||
CK -> D hold
|
||||
^ -> ^ 0.01:0.01
|
||||
^ -> v 0.00:0.00
|
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reg1/Q -> D wire
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||||
^ -> ^ 0.00:0.00
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||||
v -> v 0.00:0.00
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||||
PASS: report_edges to reg2/D
|
||||
--- disable_timing on port pin ---
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||||
reg1 CK Q constraint
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||||
reg2 CK Q constraint
|
||||
PASS: disabled CK->Q in lib cell
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Startpoint: d (input port clocked by clk)
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Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d (in)
|
||||
0.00 1.00 v reg1/D (DFF_X1)
|
||||
1.00 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg1/CK (DFF_X1)
|
||||
-0.07 9.93 library setup time
|
||||
9.93 data required time
|
||||
---------------------------------------------------------
|
||||
9.93 data required time
|
||||
-1.00 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.93 slack (MET)
|
||||
|
||||
|
||||
PASS: report_checks after lib cell disable
|
||||
PASS: unset lib cell disable
|
||||
--- set_disable_timing instance and back ---
|
||||
reg1 CK Q constraint
|
||||
reg1 CK QN constraint
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: q (output port clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg2/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg2/Q (DFF_X1)
|
||||
0.00 0.08 ^ q (out)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
-1.00 9.00 output external delay
|
||||
9.00 data required time
|
||||
---------------------------------------------------------
|
||||
9.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.92 slack (MET)
|
||||
|
||||
|
||||
PASS: instance disable
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: q (output port clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg2/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg2/Q (DFF_X1)
|
||||
0.00 0.08 ^ q (out)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
-1.00 9.00 output external delay
|
||||
9.00 data required time
|
||||
---------------------------------------------------------
|
||||
9.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.92 slack (MET)
|
||||
|
||||
|
||||
PASS: instance unset disable
|
||||
--- report_slews for various pins ---
|
||||
d ^ 0.10:0.10 v 0.10:0.10
|
||||
q ^ 0.01:0.01 v 0.00:0.00
|
||||
reg1/CK ^ 0.00:0.00 v 0.00:0.00
|
||||
reg1/Q ^ 0.01:0.01 v 0.01:0.01
|
||||
reg2/D ^ 0.01:0.01 v 0.01:0.01
|
||||
PASS: report_slews various pins
|
||||
--- report_check_types ---
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: min
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg1/CK (DFF_X1)
|
||||
0.08 0.08 v reg1/Q (DFF_X1)
|
||||
0.00 0.08 v reg2/D (DFF_X1)
|
||||
0.08 data arrival time
|
||||
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 clock reconvergence pessimism
|
||||
0.00 ^ reg2/CK (DFF_X1)
|
||||
0.00 0.00 library hold time
|
||||
0.00 data required time
|
||||
---------------------------------------------------------
|
||||
0.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
0.08 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: q (output port clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg2/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg2/Q (DFF_X1)
|
||||
0.00 0.08 ^ q (out)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
-1.00 9.00 output external delay
|
||||
9.00 data required time
|
||||
---------------------------------------------------------
|
||||
9.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.92 slack (MET)
|
||||
|
||||
|
||||
PASS: report_check_types
|
||||
--- report_checks with -format ---
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: q (output port clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg2/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg2/Q (DFF_X1)
|
||||
0.00 0.08 ^ q (out)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
-1.00 9.00 output external delay
|
||||
9.00 data required time
|
||||
---------------------------------------------------------
|
||||
9.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.92 slack (MET)
|
||||
|
||||
|
||||
PASS: report_checks -format full_clock
|
||||
--- report_checks -unconstrained ---
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: q (output port clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg2/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg2/Q (DFF_X1)
|
||||
0.00 0.08 ^ q (out)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
-1.00 9.00 output external delay
|
||||
9.00 data required time
|
||||
---------------------------------------------------------
|
||||
9.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.92 slack (MET)
|
||||
|
||||
|
||||
PASS: report_checks unconstrained
|
||||
--- report_checks -group_count 2 ---
|
||||
Warning: graph_advanced.tcl line 1, report_checks -group_count is deprecated. Use -group_path_count instead.
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: q (output port clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg2/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg2/Q (DFF_X1)
|
||||
0.00 0.08 ^ q (out)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
-1.00 9.00 output external delay
|
||||
9.00 data required time
|
||||
---------------------------------------------------------
|
||||
9.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.92 slack (MET)
|
||||
|
||||
|
||||
Startpoint: d (input port clocked by clk)
|
||||
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d (in)
|
||||
0.00 1.00 v reg1/D (DFF_X1)
|
||||
1.00 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg1/CK (DFF_X1)
|
||||
-0.07 9.93 library setup time
|
||||
9.93 data required time
|
||||
---------------------------------------------------------
|
||||
9.93 data required time
|
||||
-1.00 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.93 slack (MET)
|
||||
|
||||
|
||||
PASS: report_checks -group_count 2
|
||||
--- report_checks -endpoint_count 2 ---
|
||||
Warning: graph_advanced.tcl line 1, report_checks -endpoint_count is deprecated. Use -endpoint_path_count instead.
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: q (output port clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg2/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg2/Q (DFF_X1)
|
||||
0.00 0.08 ^ q (out)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
-1.00 9.00 output external delay
|
||||
9.00 data required time
|
||||
---------------------------------------------------------
|
||||
9.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.92 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: q (output port clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg2/CK (DFF_X1)
|
||||
0.08 0.08 v reg2/Q (DFF_X1)
|
||||
0.00 0.08 v q (out)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
-1.00 9.00 output external delay
|
||||
9.00 data required time
|
||||
---------------------------------------------------------
|
||||
9.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.92 slack (MET)
|
||||
|
||||
|
||||
PASS: report_checks -endpoint_count 2
|
||||
ALL PASSED
|
||||
@@ -0,0 +1,133 @@
|
||||
# Test advanced graph operations: multiple-instance design, edge traversal,
|
||||
# and graph info queries.
|
||||
# Targets uncovered Graph.cc functions: vertex operations, edge iterators,
|
||||
# constant propagation, level reporting, etc.
|
||||
|
||||
source ../../test/helpers.tcl
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Load a larger design for more graph coverage
|
||||
#---------------------------------------------------------------
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
read_verilog graph_test1.v
|
||||
link_design graph_test1
|
||||
|
||||
create_clock -name clk -period 10 [get_ports clk]
|
||||
set_input_delay -clock clk 1.0 [get_ports d]
|
||||
set_output_delay -clock clk 1.0 [get_ports q]
|
||||
set_input_transition 0.1 [get_ports d]
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# report_checks exercises graph traversal
|
||||
#---------------------------------------------------------------
|
||||
puts "--- report_checks baseline ---"
|
||||
report_checks
|
||||
puts "PASS: report_checks baseline"
|
||||
|
||||
puts "--- report_checks -path_delay min ---"
|
||||
report_checks -path_delay min
|
||||
puts "PASS: report_checks -path_delay min"
|
||||
|
||||
puts "--- report_checks -path_delay max ---"
|
||||
report_checks -path_delay max
|
||||
puts "PASS: report_checks -path_delay max"
|
||||
|
||||
puts "--- report_checks -from/-to ---"
|
||||
report_checks -from [get_ports d] -to [get_ports q]
|
||||
puts "PASS: report_checks -from/-to"
|
||||
|
||||
puts "--- report_checks -through ---"
|
||||
set rc [catch { report_checks -through [get_pins reg1/Q] } msg]
|
||||
if { $rc == 0 } {
|
||||
puts "PASS: report_checks -through"
|
||||
} else {
|
||||
puts "INFO: report_checks -through: $msg"
|
||||
}
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Edge queries (Graph.cc edge functions)
|
||||
#---------------------------------------------------------------
|
||||
puts "--- get_timing_edges full combinations ---"
|
||||
set edges_all [get_timing_edges -of_objects [get_cells reg1]]
|
||||
puts "reg1 all edges: [llength $edges_all]"
|
||||
|
||||
set edges_all2 [get_timing_edges -of_objects [get_cells reg2]]
|
||||
puts "reg2 all edges: [llength $edges_all2]"
|
||||
|
||||
puts "--- report_edges for cells ---"
|
||||
report_edges -from [get_pins reg1/CK] -to [get_pins reg1/Q]
|
||||
puts "PASS: report_edges reg1 CK->Q"
|
||||
|
||||
report_edges -from [get_pins reg2/CK] -to [get_pins reg2/Q]
|
||||
puts "PASS: report_edges reg2 CK->Q"
|
||||
|
||||
report_edges -from [get_pins reg1/CK]
|
||||
puts "PASS: report_edges from reg1/CK"
|
||||
|
||||
report_edges -to [get_pins reg2/D]
|
||||
puts "PASS: report_edges to reg2/D"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# set_disable_timing / report_disabled_edges exercises more paths
|
||||
#---------------------------------------------------------------
|
||||
puts "--- disable_timing on port pin ---"
|
||||
set_disable_timing -from CK -to Q [get_lib_cells NangateOpenCellLibrary/DFF_X1]
|
||||
report_disabled_edges
|
||||
puts "PASS: disabled CK->Q in lib cell"
|
||||
|
||||
report_checks
|
||||
puts "PASS: report_checks after lib cell disable"
|
||||
|
||||
unset_disable_timing -from CK -to Q [get_lib_cells NangateOpenCellLibrary/DFF_X1]
|
||||
report_disabled_edges
|
||||
puts "PASS: unset lib cell disable"
|
||||
|
||||
puts "--- set_disable_timing instance and back ---"
|
||||
set_disable_timing [get_cells reg1]
|
||||
report_disabled_edges
|
||||
report_checks
|
||||
puts "PASS: instance disable"
|
||||
|
||||
unset_disable_timing [get_cells reg1]
|
||||
report_disabled_edges
|
||||
report_checks
|
||||
puts "PASS: instance unset disable"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Slew reporting (exercises vertex slew access)
|
||||
#---------------------------------------------------------------
|
||||
puts "--- report_slews for various pins ---"
|
||||
report_slews [get_ports d]
|
||||
report_slews [get_ports q]
|
||||
report_slews [get_pins reg1/CK]
|
||||
report_slews [get_pins reg1/Q]
|
||||
report_slews [get_pins reg2/D]
|
||||
puts "PASS: report_slews various pins"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Graph verification
|
||||
#---------------------------------------------------------------
|
||||
puts "--- report_check_types ---"
|
||||
report_check_types -max_delay -min_delay -verbose
|
||||
puts "PASS: report_check_types"
|
||||
|
||||
puts "--- report_checks with -format ---"
|
||||
report_checks -format full_clock
|
||||
puts "PASS: report_checks -format full_clock"
|
||||
|
||||
puts "--- report_checks -unconstrained ---"
|
||||
report_checks -unconstrained
|
||||
puts "PASS: report_checks unconstrained"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Additional graph traversals (exercises more vertex/edge paths)
|
||||
#---------------------------------------------------------------
|
||||
puts "--- report_checks -group_count 2 ---"
|
||||
report_checks -group_count 2
|
||||
puts "PASS: report_checks -group_count 2"
|
||||
|
||||
puts "--- report_checks -endpoint_count 2 ---"
|
||||
report_checks -endpoint_count 2
|
||||
puts "PASS: report_checks -endpoint_count 2"
|
||||
|
||||
puts "ALL PASSED"
|
||||
@@ -0,0 +1,960 @@
|
||||
--- Test 1: graph with reconvergent paths ---
|
||||
Startpoint: d1 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 v input external delay
|
||||
0.00 0.00 v d1 (in)
|
||||
0.06 0.06 v buf1/Z (BUF_X1)
|
||||
0.05 0.10 v or1/ZN (OR2_X1)
|
||||
0.03 0.13 v and2/ZN (AND2_X1)
|
||||
0.00 0.13 v reg2/D (DFF_X1)
|
||||
0.13 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.04 9.96 library setup time
|
||||
9.96 data required time
|
||||
---------------------------------------------------------
|
||||
9.96 data required time
|
||||
-0.13 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.83 slack (MET)
|
||||
|
||||
|
||||
PASS: report_checks
|
||||
Startpoint: d4 (input port clocked by clk)
|
||||
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: min
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ input external delay
|
||||
0.00 0.00 ^ d4 (in)
|
||||
0.01 0.01 v inv2/ZN (INV_X1)
|
||||
0.02 0.03 ^ nand1/ZN (NAND2_X1)
|
||||
0.02 0.05 ^ or2/ZN (OR2_X1)
|
||||
0.00 0.05 ^ reg3/D (DFF_X1)
|
||||
0.05 data arrival time
|
||||
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 clock reconvergence pessimism
|
||||
0.00 ^ reg3/CK (DFF_X1)
|
||||
0.00 0.00 library hold time
|
||||
0.00 data required time
|
||||
---------------------------------------------------------
|
||||
0.00 data required time
|
||||
-0.05 data arrival time
|
||||
---------------------------------------------------------
|
||||
0.05 slack (MET)
|
||||
|
||||
|
||||
PASS: report_checks min
|
||||
--- Test 2: path queries ---
|
||||
No paths found.
|
||||
PASS: d1->q1
|
||||
No paths found.
|
||||
PASS: d1->q2 (reconvergent)
|
||||
No paths found.
|
||||
PASS: d2->q1
|
||||
No paths found.
|
||||
PASS: d3->q3
|
||||
No paths found.
|
||||
PASS: d4->q3
|
||||
No paths found.
|
||||
PASS: d1->q4 (reconvergent)
|
||||
No paths found.
|
||||
PASS: d3->q4 (reconvergent)
|
||||
--- Test 3: report with fields ---
|
||||
Warning: graph_bidirect.tcl line 1, unknown field nets.
|
||||
Startpoint: d1 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Fanout Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------------
|
||||
0.00 0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 v input external delay
|
||||
1 0.88 0.10 0.00 0.00 v d1 (in)
|
||||
0.10 0.00 0.00 v buf1/A (BUF_X1)
|
||||
2 1.67 0.01 0.06 0.06 v buf1/Z (BUF_X1)
|
||||
0.01 0.00 0.06 v or1/A1 (OR2_X1)
|
||||
2 1.96 0.01 0.05 0.10 v or1/ZN (OR2_X1)
|
||||
0.01 0.00 0.10 v and2/A2 (AND2_X1)
|
||||
1 1.06 0.01 0.03 0.13 v and2/ZN (AND2_X1)
|
||||
0.01 0.00 0.13 v reg2/D (DFF_X1)
|
||||
0.13 data arrival time
|
||||
|
||||
0.00 10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.04 9.96 library setup time
|
||||
9.96 data required time
|
||||
-----------------------------------------------------------------------------
|
||||
9.96 data required time
|
||||
-0.13 data arrival time
|
||||
-----------------------------------------------------------------------------
|
||||
9.83 slack (MET)
|
||||
|
||||
|
||||
PASS: report with all fields
|
||||
Startpoint: d1 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 v input external delay
|
||||
0.00 0.00 v d1 (in)
|
||||
0.06 0.06 v buf1/Z (BUF_X1)
|
||||
0.05 0.10 v or1/ZN (OR2_X1)
|
||||
0.03 0.13 v and2/ZN (AND2_X1)
|
||||
0.00 0.13 v reg2/D (DFF_X1)
|
||||
0.13 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.04 9.96 library setup time
|
||||
9.96 data required time
|
||||
---------------------------------------------------------
|
||||
9.96 data required time
|
||||
-0.13 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.83 slack (MET)
|
||||
|
||||
|
||||
PASS: report full_clock
|
||||
Startpoint: d4 (input port clocked by clk)
|
||||
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: min
|
||||
|
||||
Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------
|
||||
0.00 0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ input external delay
|
||||
1.70 0.10 0.00 0.00 ^ d4 (in)
|
||||
3.07 0.02 0.01 0.01 v inv2/ZN (INV_X1)
|
||||
0.95 0.01 0.02 0.03 ^ nand1/ZN (NAND2_X1)
|
||||
1.14 0.01 0.02 0.05 ^ or2/ZN (OR2_X1)
|
||||
0.01 0.00 0.05 ^ reg3/D (DFF_X1)
|
||||
0.05 data arrival time
|
||||
|
||||
0.00 0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 clock reconvergence pessimism
|
||||
0.00 ^ reg3/CK (DFF_X1)
|
||||
0.00 0.00 library hold time
|
||||
0.00 data required time
|
||||
-----------------------------------------------------------------------
|
||||
0.00 data required time
|
||||
-0.05 data arrival time
|
||||
-----------------------------------------------------------------------
|
||||
0.05 slack (MET)
|
||||
|
||||
|
||||
PASS: min with slew/cap fields
|
||||
--- Test 4: fanin/fanout ---
|
||||
fanin to q2: 3
|
||||
fanout from d1: 13
|
||||
fanin cells to q2: 2
|
||||
fanout cells from d1: 8
|
||||
fanin to q3: 3
|
||||
fanout from d3: 14
|
||||
--- Test 5: report_dcalc ---
|
||||
Library: NangateOpenCellLibrary
|
||||
Cell: BUF_X1
|
||||
Arc sense: positive_unate
|
||||
Arc type: combinational
|
||||
A ^ -> Z ^
|
||||
P = 1.00 V = 1.10 T = 25.00
|
||||
------- input_net_transition = 0.10
|
||||
| total_output_net_capacitance = 1.86
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.08 | 0.03 0.03
|
||||
0.13 | 0.03 0.04
|
||||
Table value = 0.03
|
||||
PVT scale factor = 1.00
|
||||
Delay = 0.03
|
||||
|
||||
------- input_net_transition = 0.10
|
||||
| total_output_net_capacitance = 1.86
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.08 | 0.01 0.01
|
||||
0.13 | 0.01 0.01
|
||||
Table value = 0.01
|
||||
PVT scale factor = 1.00
|
||||
Slew = 0.01
|
||||
Driver waveform slew = 0.01
|
||||
|
||||
.............................................
|
||||
|
||||
A v -> Z v
|
||||
P = 1.00 V = 1.10 T = 25.00
|
||||
------- input_net_transition = 0.10
|
||||
| total_output_net_capacitance = 1.67
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.08 | 0.05 0.05
|
||||
0.13 | 0.06 0.07
|
||||
Table value = 0.06
|
||||
PVT scale factor = 1.00
|
||||
Delay = 0.06
|
||||
|
||||
------- input_net_transition = 0.10
|
||||
| total_output_net_capacitance = 1.67
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.08 | 0.01 0.01
|
||||
0.13 | 0.01 0.01
|
||||
Table value = 0.01
|
||||
PVT scale factor = 1.00
|
||||
Slew = 0.01
|
||||
Driver waveform slew = 0.01
|
||||
|
||||
.............................................
|
||||
|
||||
dcalc buf1: done
|
||||
Library: NangateOpenCellLibrary
|
||||
Cell: AND2_X1
|
||||
Arc sense: positive_unate
|
||||
Arc type: combinational
|
||||
A1 ^ -> ZN ^
|
||||
P = 1.00 V = 1.10 T = 25.00
|
||||
------- input_net_transition = 0.01
|
||||
| total_output_net_capacitance = 2.06
|
||||
| 1.89 3.79
|
||||
v --------------------
|
||||
0.00 | 0.03 0.03
|
||||
0.02 | 0.03 0.04
|
||||
Table value = 0.03
|
||||
PVT scale factor = 1.00
|
||||
Delay = 0.03
|
||||
|
||||
------- input_net_transition = 0.01
|
||||
| total_output_net_capacitance = 2.06
|
||||
| 1.89 3.79
|
||||
v --------------------
|
||||
0.00 | 0.01 0.01
|
||||
0.02 | 0.01 0.01
|
||||
Table value = 0.01
|
||||
PVT scale factor = 1.00
|
||||
Slew = 0.01
|
||||
Driver waveform slew = 0.01
|
||||
|
||||
.............................................
|
||||
|
||||
A1 v -> ZN v
|
||||
P = 1.00 V = 1.10 T = 25.00
|
||||
------- input_net_transition = 0.01
|
||||
| total_output_net_capacitance = 1.94
|
||||
| 1.89 3.79
|
||||
v --------------------
|
||||
0.00 | 0.03 0.03
|
||||
0.02 | 0.03 0.04
|
||||
Table value = 0.03
|
||||
PVT scale factor = 1.00
|
||||
Delay = 0.03
|
||||
|
||||
------- input_net_transition = 0.01
|
||||
| total_output_net_capacitance = 1.94
|
||||
| 1.89 3.79
|
||||
v --------------------
|
||||
0.00 | 0.01 0.01
|
||||
0.02 | 0.01 0.01
|
||||
Table value = 0.01
|
||||
PVT scale factor = 1.00
|
||||
Slew = 0.01
|
||||
Driver waveform slew = 0.01
|
||||
|
||||
.............................................
|
||||
|
||||
dcalc and1 A1: done
|
||||
Library: NangateOpenCellLibrary
|
||||
Cell: AND2_X1
|
||||
Arc sense: positive_unate
|
||||
Arc type: combinational
|
||||
A2 ^ -> ZN ^
|
||||
P = 1.00 V = 1.10 T = 25.00
|
||||
------- input_net_transition = 0.01
|
||||
| total_output_net_capacitance = 2.06
|
||||
| 1.89 3.79
|
||||
v --------------------
|
||||
0.00 | 0.03 0.04
|
||||
0.02 | 0.03 0.04
|
||||
Table value = 0.03
|
||||
PVT scale factor = 1.00
|
||||
Delay = 0.03
|
||||
|
||||
------- input_net_transition = 0.01
|
||||
| total_output_net_capacitance = 2.06
|
||||
| 1.89 3.79
|
||||
v --------------------
|
||||
0.00 | 0.01 0.01
|
||||
0.02 | 0.01 0.01
|
||||
Table value = 0.01
|
||||
PVT scale factor = 1.00
|
||||
Slew = 0.01
|
||||
Driver waveform slew = 0.01
|
||||
|
||||
.............................................
|
||||
|
||||
A2 v -> ZN v
|
||||
P = 1.00 V = 1.10 T = 25.00
|
||||
------- input_net_transition = 0.01
|
||||
| total_output_net_capacitance = 1.94
|
||||
| 1.89 3.79
|
||||
v --------------------
|
||||
0.00 | 0.03 0.03
|
||||
0.02 | 0.04 0.04
|
||||
Table value = 0.03
|
||||
PVT scale factor = 1.00
|
||||
Delay = 0.03
|
||||
|
||||
------- input_net_transition = 0.01
|
||||
| total_output_net_capacitance = 1.94
|
||||
| 1.89 3.79
|
||||
v --------------------
|
||||
0.00 | 0.01 0.01
|
||||
0.02 | 0.01 0.01
|
||||
Table value = 0.01
|
||||
PVT scale factor = 1.00
|
||||
Slew = 0.01
|
||||
Driver waveform slew = 0.01
|
||||
|
||||
.............................................
|
||||
|
||||
dcalc and1 A2: done
|
||||
Library: NangateOpenCellLibrary
|
||||
Cell: OR2_X1
|
||||
Arc sense: positive_unate
|
||||
Arc type: combinational
|
||||
A1 ^ -> ZN ^
|
||||
P = 1.00 V = 1.10 T = 25.00
|
||||
------- input_net_transition = 0.01
|
||||
| total_output_net_capacitance = 2.11
|
||||
| 1.89 3.79
|
||||
v --------------------
|
||||
0.00 | 0.02 0.03
|
||||
0.02 | 0.03 0.03
|
||||
Table value = 0.02
|
||||
PVT scale factor = 1.00
|
||||
Delay = 0.02
|
||||
|
||||
------- input_net_transition = 0.01
|
||||
| total_output_net_capacitance = 2.11
|
||||
| 1.89 3.79
|
||||
v --------------------
|
||||
0.00 | 0.01 0.01
|
||||
0.02 | 0.01 0.01
|
||||
Table value = 0.01
|
||||
PVT scale factor = 1.00
|
||||
Slew = 0.01
|
||||
Driver waveform slew = 0.01
|
||||
|
||||
.............................................
|
||||
|
||||
A1 v -> ZN v
|
||||
P = 1.00 V = 1.10 T = 25.00
|
||||
------- input_net_transition = 0.01
|
||||
| total_output_net_capacitance = 1.96
|
||||
| 1.89 3.79
|
||||
v --------------------
|
||||
0.00 | 0.04 0.05
|
||||
0.02 | 0.05 0.05
|
||||
Table value = 0.05
|
||||
PVT scale factor = 1.00
|
||||
Delay = 0.05
|
||||
|
||||
------- input_net_transition = 0.01
|
||||
| total_output_net_capacitance = 1.96
|
||||
| 1.89 3.79
|
||||
v --------------------
|
||||
0.00 | 0.01 0.01
|
||||
0.02 | 0.01 0.01
|
||||
Table value = 0.01
|
||||
PVT scale factor = 1.00
|
||||
Slew = 0.01
|
||||
Driver waveform slew = 0.01
|
||||
|
||||
.............................................
|
||||
|
||||
dcalc or1 A1: done
|
||||
Library: NangateOpenCellLibrary
|
||||
Cell: NAND2_X1
|
||||
Arc sense: negative_unate
|
||||
Arc type: combinational
|
||||
A1 ^ -> ZN v
|
||||
P = 1.00 V = 1.10 T = 25.00
|
||||
------- input_net_transition = 0.01
|
||||
| total_output_net_capacitance = 0.79
|
||||
| 0.37 1.85
|
||||
v --------------------
|
||||
0.00 | 0.01 0.01
|
||||
0.02 | 0.01 0.02
|
||||
Table value = 0.01
|
||||
PVT scale factor = 1.00
|
||||
Delay = 0.01
|
||||
|
||||
------- input_net_transition = 0.01
|
||||
| total_output_net_capacitance = 0.79
|
||||
| 0.37 1.85
|
||||
v --------------------
|
||||
0.00 | 0.00 0.01
|
||||
0.02 | 0.01 0.01
|
||||
Table value = 0.01
|
||||
PVT scale factor = 1.00
|
||||
Slew = 0.01
|
||||
Driver waveform slew = 0.01
|
||||
|
||||
.............................................
|
||||
|
||||
A1 v -> ZN ^
|
||||
P = 1.00 V = 1.10 T = 25.00
|
||||
------- input_net_transition = 0.01
|
||||
| total_output_net_capacitance = 0.95
|
||||
| 0.37 1.85
|
||||
v --------------------
|
||||
0.00 | 0.01 0.01
|
||||
0.02 | 0.01 0.02
|
||||
Table value = 0.01
|
||||
PVT scale factor = 1.00
|
||||
Delay = 0.01
|
||||
|
||||
------- input_net_transition = 0.01
|
||||
| total_output_net_capacitance = 0.95
|
||||
| 0.37 1.85
|
||||
v --------------------
|
||||
0.00 | 0.00 0.01
|
||||
0.02 | 0.01 0.01
|
||||
Table value = 0.01
|
||||
PVT scale factor = 1.00
|
||||
Slew = 0.01
|
||||
Driver waveform slew = 0.01
|
||||
|
||||
.............................................
|
||||
|
||||
dcalc nand1: done
|
||||
Library: NangateOpenCellLibrary
|
||||
Cell: NOR2_X1
|
||||
Arc sense: negative_unate
|
||||
Arc type: combinational
|
||||
A1 ^ -> ZN v
|
||||
P = 1.00 V = 1.10 T = 25.00
|
||||
------- input_net_transition = 0.02
|
||||
| total_output_net_capacitance = 0.90
|
||||
| 0.83 1.67
|
||||
v --------------------
|
||||
0.02 | 0.01 0.01
|
||||
0.04 | 0.01 0.01
|
||||
Table value = 0.01
|
||||
PVT scale factor = 1.00
|
||||
Delay = 0.01
|
||||
|
||||
------- input_net_transition = 0.02
|
||||
| total_output_net_capacitance = 0.90
|
||||
| 0.83 1.67
|
||||
v --------------------
|
||||
0.02 | 0.01 0.01
|
||||
0.04 | 0.01 0.01
|
||||
Table value = 0.01
|
||||
PVT scale factor = 1.00
|
||||
Slew = 0.01
|
||||
Driver waveform slew = 0.01
|
||||
|
||||
.............................................
|
||||
|
||||
A1 v -> ZN ^
|
||||
P = 1.00 V = 1.10 T = 25.00
|
||||
------- input_net_transition = 0.02
|
||||
| total_output_net_capacitance = 0.94
|
||||
| 0.83 1.67
|
||||
v --------------------
|
||||
0.02 | 0.02 0.03
|
||||
0.04 | 0.03 0.04
|
||||
Table value = 0.02
|
||||
PVT scale factor = 1.00
|
||||
Delay = 0.02
|
||||
|
||||
------- input_net_transition = 0.02
|
||||
| total_output_net_capacitance = 0.94
|
||||
| 0.83 1.67
|
||||
v --------------------
|
||||
0.02 | 0.01 0.02
|
||||
0.04 | 0.02 0.02
|
||||
Table value = 0.01
|
||||
PVT scale factor = 1.00
|
||||
Slew = 0.01
|
||||
Driver waveform slew = 0.01
|
||||
|
||||
.............................................
|
||||
|
||||
dcalc nor1: done
|
||||
Library: NangateOpenCellLibrary
|
||||
Cell: DFF_X1
|
||||
Arc sense: non_unate
|
||||
Arc type: Reg Clk to Q
|
||||
CK ^ -> Q ^
|
||||
P = 1.00 V = 1.10 T = 25.00
|
||||
------- input_net_transition = 0.00
|
||||
| total_output_net_capacitance = 0.00
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.00 | 0.08 0.09
|
||||
0.00 | 0.08 0.09
|
||||
Table value = 0.08
|
||||
PVT scale factor = 1.00
|
||||
Delay = 0.08
|
||||
|
||||
------- input_net_transition = 0.00
|
||||
| total_output_net_capacitance = 0.00
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.00 | 0.01 0.01
|
||||
0.00 | 0.01 0.01
|
||||
Table value = 0.01
|
||||
PVT scale factor = 1.00
|
||||
Slew = 0.01
|
||||
Driver waveform slew = 0.01
|
||||
|
||||
.............................................
|
||||
|
||||
CK ^ -> Q v
|
||||
P = 1.00 V = 1.10 T = 25.00
|
||||
------- input_net_transition = 0.00
|
||||
| total_output_net_capacitance = 0.00
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.00 | 0.08 0.08
|
||||
0.00 | 0.08 0.08
|
||||
Table value = 0.08
|
||||
PVT scale factor = 1.00
|
||||
Delay = 0.08
|
||||
|
||||
------- input_net_transition = 0.00
|
||||
| total_output_net_capacitance = 0.00
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.00 | 0.01 0.01
|
||||
0.00 | 0.01 0.01
|
||||
Table value = 0.00
|
||||
PVT scale factor = 1.00
|
||||
Slew = 0.00
|
||||
Driver waveform slew = 0.00
|
||||
|
||||
.............................................
|
||||
|
||||
dcalc reg1: done
|
||||
--- Test 6: network queries ---
|
||||
total pins: 50
|
||||
total nets: 19
|
||||
Net n1
|
||||
Pin capacitance: 1.67-1.86
|
||||
Wire capacitance: 0.00
|
||||
Total capacitance: 1.67-1.86
|
||||
Number of drivers: 1
|
||||
Number of loads: 2
|
||||
Number of pins: 3
|
||||
|
||||
Driver pins
|
||||
buf1/Z output (BUF_X1)
|
||||
|
||||
Load pins
|
||||
and1/A1 input (AND2_X1) 0.87-0.92
|
||||
or1/A1 input (OR2_X1) 0.79-0.95
|
||||
|
||||
Net n2
|
||||
Pin capacitance: 2.42-2.57
|
||||
Wire capacitance: 0.00
|
||||
Total capacitance: 2.42-2.57
|
||||
Number of drivers: 1
|
||||
Number of loads: 2
|
||||
Number of pins: 3
|
||||
|
||||
Driver pins
|
||||
buf2/Z output (BUF_X1)
|
||||
|
||||
Load pins
|
||||
and1/A2 input (AND2_X1) 0.89-0.97
|
||||
nand1/A1 input (NAND2_X1) 1.53-1.60
|
||||
|
||||
Net n3
|
||||
Pin capacitance: 2.31-2.66
|
||||
Wire capacitance: 0.00
|
||||
Total capacitance: 2.31-2.66
|
||||
Number of drivers: 1
|
||||
Number of loads: 2
|
||||
Number of pins: 3
|
||||
|
||||
Driver pins
|
||||
inv1/ZN output (INV_X1)
|
||||
|
||||
Load pins
|
||||
nor1/A1 input (NOR2_X1) 1.41-1.71
|
||||
or1/A2 input (OR2_X1) 0.90-0.94
|
||||
|
||||
Net n4
|
||||
Pin capacitance: 3.07-3.32
|
||||
Wire capacitance: 0.00
|
||||
Total capacitance: 3.07-3.32
|
||||
Number of drivers: 1
|
||||
Number of loads: 2
|
||||
Number of pins: 3
|
||||
|
||||
Driver pins
|
||||
inv2/ZN output (INV_X1)
|
||||
|
||||
Load pins
|
||||
nand1/A2 input (NAND2_X1) 1.50-1.66
|
||||
nor1/A2 input (NOR2_X1) 1.56-1.65
|
||||
|
||||
Net n5
|
||||
Pin capacitance: 1.94-2.06
|
||||
Wire capacitance: 0.00
|
||||
Total capacitance: 1.94-2.06
|
||||
Number of drivers: 1
|
||||
Number of loads: 2
|
||||
Number of pins: 3
|
||||
|
||||
Driver pins
|
||||
and1/ZN output (AND2_X1)
|
||||
|
||||
Load pins
|
||||
and2/A1 input (AND2_X1) 0.87-0.92
|
||||
reg1/D input (DFF_X1) 1.06-1.14
|
||||
|
||||
Net n6
|
||||
Pin capacitance: 1.96-2.11
|
||||
Wire capacitance: 0.00
|
||||
Total capacitance: 1.96-2.11
|
||||
Number of drivers: 1
|
||||
Number of loads: 2
|
||||
Number of pins: 3
|
||||
|
||||
Driver pins
|
||||
or1/ZN output (OR2_X1)
|
||||
|
||||
Load pins
|
||||
and2/A2 input (AND2_X1) 0.89-0.97
|
||||
reg4/D input (DFF_X1) 1.06-1.14
|
||||
|
||||
Net n7
|
||||
Pin capacitance: 0.79-0.95
|
||||
Wire capacitance: 0.00
|
||||
Total capacitance: 0.79-0.95
|
||||
Number of drivers: 1
|
||||
Number of loads: 1
|
||||
Number of pins: 2
|
||||
|
||||
Driver pins
|
||||
nand1/ZN output (NAND2_X1)
|
||||
|
||||
Load pins
|
||||
or2/A1 input (OR2_X1) 0.79-0.95
|
||||
|
||||
Net n8
|
||||
Pin capacitance: 0.90-0.94
|
||||
Wire capacitance: 0.00
|
||||
Total capacitance: 0.90-0.94
|
||||
Number of drivers: 1
|
||||
Number of loads: 1
|
||||
Number of pins: 2
|
||||
|
||||
Driver pins
|
||||
nor1/ZN output (NOR2_X1)
|
||||
|
||||
Load pins
|
||||
or2/A2 input (OR2_X1) 0.90-0.94
|
||||
|
||||
Net n9
|
||||
Pin capacitance: 1.06-1.14
|
||||
Wire capacitance: 0.00
|
||||
Total capacitance: 1.06-1.14
|
||||
Number of drivers: 1
|
||||
Number of loads: 1
|
||||
Number of pins: 2
|
||||
|
||||
Driver pins
|
||||
and2/ZN output (AND2_X1)
|
||||
|
||||
Load pins
|
||||
reg2/D input (DFF_X1) 1.06-1.14
|
||||
|
||||
Net n10
|
||||
Pin capacitance: 1.06-1.14
|
||||
Wire capacitance: 0.00
|
||||
Total capacitance: 1.06-1.14
|
||||
Number of drivers: 1
|
||||
Number of loads: 1
|
||||
Number of pins: 2
|
||||
|
||||
Driver pins
|
||||
or2/ZN output (OR2_X1)
|
||||
|
||||
Load pins
|
||||
reg3/D input (DFF_X1) 1.06-1.14
|
||||
|
||||
PASS: report_net all
|
||||
Instance buf1
|
||||
Cell: BUF_X1
|
||||
Library: NangateOpenCellLibrary
|
||||
Path cells: BUF_X1
|
||||
Input pins:
|
||||
A input d1
|
||||
Output pins:
|
||||
Z output n1
|
||||
Other pins:
|
||||
VDD power (unconnected)
|
||||
VSS ground (unconnected)
|
||||
Instance buf2
|
||||
Cell: BUF_X1
|
||||
Library: NangateOpenCellLibrary
|
||||
Path cells: BUF_X1
|
||||
Input pins:
|
||||
A input d2
|
||||
Output pins:
|
||||
Z output n2
|
||||
Other pins:
|
||||
VDD power (unconnected)
|
||||
VSS ground (unconnected)
|
||||
Instance inv1
|
||||
Cell: INV_X1
|
||||
Library: NangateOpenCellLibrary
|
||||
Path cells: INV_X1
|
||||
Input pins:
|
||||
A input d3
|
||||
Output pins:
|
||||
ZN output n3
|
||||
Other pins:
|
||||
VDD power (unconnected)
|
||||
VSS ground (unconnected)
|
||||
Instance inv2
|
||||
Cell: INV_X1
|
||||
Library: NangateOpenCellLibrary
|
||||
Path cells: INV_X1
|
||||
Input pins:
|
||||
A input d4
|
||||
Output pins:
|
||||
ZN output n4
|
||||
Other pins:
|
||||
VDD power (unconnected)
|
||||
VSS ground (unconnected)
|
||||
Instance and1
|
||||
Cell: AND2_X1
|
||||
Library: NangateOpenCellLibrary
|
||||
Path cells: AND2_X1
|
||||
Input pins:
|
||||
A1 input n1
|
||||
A2 input n2
|
||||
Output pins:
|
||||
ZN output n5
|
||||
Other pins:
|
||||
VDD power (unconnected)
|
||||
VSS ground (unconnected)
|
||||
Instance or1
|
||||
Cell: OR2_X1
|
||||
Library: NangateOpenCellLibrary
|
||||
Path cells: OR2_X1
|
||||
Input pins:
|
||||
A1 input n1
|
||||
A2 input n3
|
||||
Output pins:
|
||||
ZN output n6
|
||||
Other pins:
|
||||
VDD power (unconnected)
|
||||
VSS ground (unconnected)
|
||||
Instance nand1
|
||||
Cell: NAND2_X1
|
||||
Library: NangateOpenCellLibrary
|
||||
Path cells: NAND2_X1
|
||||
Input pins:
|
||||
A1 input n2
|
||||
A2 input n4
|
||||
Output pins:
|
||||
ZN output n7
|
||||
Other pins:
|
||||
VDD power (unconnected)
|
||||
VSS ground (unconnected)
|
||||
Instance nor1
|
||||
Cell: NOR2_X1
|
||||
Library: NangateOpenCellLibrary
|
||||
Path cells: NOR2_X1
|
||||
Input pins:
|
||||
A1 input n3
|
||||
A2 input n4
|
||||
Output pins:
|
||||
ZN output n8
|
||||
Other pins:
|
||||
VDD power (unconnected)
|
||||
VSS ground (unconnected)
|
||||
Instance and2
|
||||
Cell: AND2_X1
|
||||
Library: NangateOpenCellLibrary
|
||||
Path cells: AND2_X1
|
||||
Input pins:
|
||||
A1 input n5
|
||||
A2 input n6
|
||||
Output pins:
|
||||
ZN output n9
|
||||
Other pins:
|
||||
VDD power (unconnected)
|
||||
VSS ground (unconnected)
|
||||
Instance or2
|
||||
Cell: OR2_X1
|
||||
Library: NangateOpenCellLibrary
|
||||
Path cells: OR2_X1
|
||||
Input pins:
|
||||
A1 input n7
|
||||
A2 input n8
|
||||
Output pins:
|
||||
ZN output n10
|
||||
Other pins:
|
||||
VDD power (unconnected)
|
||||
VSS ground (unconnected)
|
||||
Instance reg1
|
||||
Cell: DFF_X1
|
||||
Library: NangateOpenCellLibrary
|
||||
Path cells: DFF_X1
|
||||
Input pins:
|
||||
D input n5
|
||||
CK input clk
|
||||
Output pins:
|
||||
Q output q1
|
||||
QN output (unconnected)
|
||||
Other pins:
|
||||
IQ internal (unconnected)
|
||||
IQN internal (unconnected)
|
||||
VDD power (unconnected)
|
||||
VSS ground (unconnected)
|
||||
Instance reg2
|
||||
Cell: DFF_X1
|
||||
Library: NangateOpenCellLibrary
|
||||
Path cells: DFF_X1
|
||||
Input pins:
|
||||
D input n9
|
||||
CK input clk
|
||||
Output pins:
|
||||
Q output q2
|
||||
QN output (unconnected)
|
||||
Other pins:
|
||||
IQ internal (unconnected)
|
||||
IQN internal (unconnected)
|
||||
VDD power (unconnected)
|
||||
VSS ground (unconnected)
|
||||
Instance reg3
|
||||
Cell: DFF_X1
|
||||
Library: NangateOpenCellLibrary
|
||||
Path cells: DFF_X1
|
||||
Input pins:
|
||||
D input n10
|
||||
CK input clk
|
||||
Output pins:
|
||||
Q output q3
|
||||
QN output (unconnected)
|
||||
Other pins:
|
||||
IQ internal (unconnected)
|
||||
IQN internal (unconnected)
|
||||
VDD power (unconnected)
|
||||
VSS ground (unconnected)
|
||||
Instance reg4
|
||||
Cell: DFF_X1
|
||||
Library: NangateOpenCellLibrary
|
||||
Path cells: DFF_X1
|
||||
Input pins:
|
||||
D input n6
|
||||
CK input clk
|
||||
Output pins:
|
||||
Q output q4
|
||||
QN output (unconnected)
|
||||
Other pins:
|
||||
IQ internal (unconnected)
|
||||
IQN internal (unconnected)
|
||||
VDD power (unconnected)
|
||||
VSS ground (unconnected)
|
||||
PASS: report_instance all
|
||||
--- Test 7: modify graph ---
|
||||
Startpoint: d1 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 v input external delay
|
||||
0.00 0.00 v d1 (in)
|
||||
0.06 0.06 v buf1/Z (BUF_X1)
|
||||
0.05 0.10 v or1/ZN (OR2_X1)
|
||||
0.03 0.13 v and2/ZN (AND2_X1)
|
||||
0.00 0.13 v reg2/D (DFF_X1)
|
||||
0.13 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.04 9.96 library setup time
|
||||
9.96 data required time
|
||||
---------------------------------------------------------
|
||||
9.96 data required time
|
||||
-0.13 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.83 slack (MET)
|
||||
|
||||
|
||||
PASS: report after add instance
|
||||
Startpoint: d1 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 v input external delay
|
||||
0.00 0.00 v d1 (in)
|
||||
0.06 0.06 v buf1/Z (BUF_X1)
|
||||
0.05 0.10 v or1/ZN (OR2_X1)
|
||||
0.03 0.13 v and2/ZN (AND2_X1)
|
||||
0.00 0.13 v reg2/D (DFF_X1)
|
||||
0.13 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.04 9.96 library setup time
|
||||
9.96 data required time
|
||||
---------------------------------------------------------
|
||||
9.96 data required time
|
||||
-0.13 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.83 slack (MET)
|
||||
|
||||
|
||||
PASS: report after delete instance
|
||||
ALL PASSED
|
||||
@@ -0,0 +1,171 @@
|
||||
# Test graph construction with bidirectional pins, reconvergent paths,
|
||||
# and various edge/vertex operations.
|
||||
# Targets: Graph.cc uncovered paths:
|
||||
# makePinVertices for bidirect pins (lines 425-427)
|
||||
# pinVertices for bidirect direction (lines 453-455)
|
||||
# pinDrvrVertex for bidirect (lines 463-464)
|
||||
# makePortInstanceEdges: bidirect from_bidirect_drvr_vertex path (lines 223-229)
|
||||
# makeWireEdgesFromPin with multiple drivers (lines 277-301)
|
||||
# hasFaninOne (line 507-511)
|
||||
# gateEdgeArc (line 544+)
|
||||
# deleteVertex (lines 476-504) via delete operations
|
||||
# isIsolatedNet (lines 309-331)
|
||||
# vertex/edge iterators
|
||||
|
||||
source ../../test/helpers.tcl
|
||||
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
read_verilog graph_bidirect.v
|
||||
link_design graph_bidirect
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 1: Graph construction and basic timing
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Test 1: graph with reconvergent paths ---"
|
||||
create_clock -name clk -period 10 [get_ports clk]
|
||||
set_input_delay -clock clk 0 [get_ports {d1 d2 d3 d4}]
|
||||
set_output_delay -clock clk 0 [get_ports {q1 q2 q3 q4}]
|
||||
set_input_transition 0.1 [get_ports {d1 d2 d3 d4 clk}]
|
||||
|
||||
report_checks
|
||||
puts "PASS: report_checks"
|
||||
|
||||
report_checks -path_delay min
|
||||
puts "PASS: report_checks min"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 2: Multiple path queries (exercises graph traversal)
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Test 2: path queries ---"
|
||||
report_checks -from [get_ports d1] -to [get_ports q1]
|
||||
puts "PASS: d1->q1"
|
||||
|
||||
report_checks -from [get_ports d1] -to [get_ports q2]
|
||||
puts "PASS: d1->q2 (reconvergent)"
|
||||
|
||||
report_checks -from [get_ports d2] -to [get_ports q1]
|
||||
puts "PASS: d2->q1"
|
||||
|
||||
report_checks -from [get_ports d3] -to [get_ports q3]
|
||||
puts "PASS: d3->q3"
|
||||
|
||||
report_checks -from [get_ports d4] -to [get_ports q3]
|
||||
puts "PASS: d4->q3"
|
||||
|
||||
report_checks -from [get_ports d1] -to [get_ports q4]
|
||||
puts "PASS: d1->q4 (reconvergent)"
|
||||
|
||||
report_checks -from [get_ports d3] -to [get_ports q4]
|
||||
puts "PASS: d3->q4 (reconvergent)"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 3: Fields that exercise graph delay/slew queries
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Test 3: report with fields ---"
|
||||
report_checks -fields {slew cap input_pins nets fanout}
|
||||
puts "PASS: report with all fields"
|
||||
|
||||
report_checks -format full_clock
|
||||
puts "PASS: report full_clock"
|
||||
|
||||
report_checks -path_delay min -fields {slew cap}
|
||||
puts "PASS: min with slew/cap fields"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 4: Fanin/fanout queries through reconvergent paths
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Test 4: fanin/fanout ---"
|
||||
catch {
|
||||
set fi [get_fanin -to [get_ports q2] -flat]
|
||||
puts "fanin to q2: [llength $fi]"
|
||||
} msg
|
||||
|
||||
catch {
|
||||
set fo [get_fanout -from [get_ports d1] -flat]
|
||||
puts "fanout from d1: [llength $fo]"
|
||||
} msg
|
||||
|
||||
catch {
|
||||
set fi_cells [get_fanin -to [get_ports q2] -only_cells]
|
||||
puts "fanin cells to q2: [llength $fi_cells]"
|
||||
} msg
|
||||
|
||||
catch {
|
||||
set fo_cells [get_fanout -from [get_ports d1] -only_cells]
|
||||
puts "fanout cells from d1: [llength $fo_cells]"
|
||||
} msg
|
||||
|
||||
catch {
|
||||
set fi_q3 [get_fanin -to [get_ports q3] -flat]
|
||||
puts "fanin to q3: [llength $fi_q3]"
|
||||
} msg
|
||||
|
||||
catch {
|
||||
set fo_d3 [get_fanout -from [get_ports d3] -flat]
|
||||
puts "fanout from d3: [llength $fo_d3]"
|
||||
} msg
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 5: report_dcalc exercises graph edge arc queries
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Test 5: report_dcalc ---"
|
||||
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -max} msg
|
||||
puts "dcalc buf1: done"
|
||||
|
||||
catch {report_dcalc -from [get_pins and1/A1] -to [get_pins and1/ZN] -max} msg
|
||||
puts "dcalc and1 A1: done"
|
||||
|
||||
catch {report_dcalc -from [get_pins and1/A2] -to [get_pins and1/ZN] -max} msg
|
||||
puts "dcalc and1 A2: done"
|
||||
|
||||
catch {report_dcalc -from [get_pins or1/A1] -to [get_pins or1/ZN] -max} msg
|
||||
puts "dcalc or1 A1: done"
|
||||
|
||||
catch {report_dcalc -from [get_pins nand1/A1] -to [get_pins nand1/ZN] -max} msg
|
||||
puts "dcalc nand1: done"
|
||||
|
||||
catch {report_dcalc -from [get_pins nor1/A1] -to [get_pins nor1/ZN] -max} msg
|
||||
puts "dcalc nor1: done"
|
||||
|
||||
catch {report_dcalc -from [get_pins reg1/CK] -to [get_pins reg1/Q] -max} msg
|
||||
puts "dcalc reg1: done"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 6: Graph vertex/edge counts
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Test 6: network queries ---"
|
||||
set all_pins [get_pins */*]
|
||||
puts "total pins: [llength $all_pins]"
|
||||
|
||||
set all_nets [get_nets *]
|
||||
puts "total nets: [llength $all_nets]"
|
||||
|
||||
foreach net_name {n1 n2 n3 n4 n5 n6 n7 n8 n9 n10} {
|
||||
catch {report_net $net_name} msg
|
||||
}
|
||||
puts "PASS: report_net all"
|
||||
|
||||
foreach inst_name {buf1 buf2 inv1 inv2 and1 or1 nand1 nor1 and2 or2 reg1 reg2 reg3 reg4} {
|
||||
report_instance $inst_name
|
||||
}
|
||||
puts "PASS: report_instance all"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 7: Add and remove instances (exercises deleteVertex, graph modify)
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Test 7: modify graph ---"
|
||||
set new_net [make_net test_net]
|
||||
set new_inst [make_instance test_buf BUF_X1]
|
||||
connect_pin test_net test_buf/A
|
||||
|
||||
report_checks
|
||||
puts "PASS: report after add instance"
|
||||
|
||||
disconnect_pin test_net test_buf/A
|
||||
delete_instance test_buf
|
||||
delete_net test_net
|
||||
|
||||
report_checks
|
||||
puts "PASS: report after delete instance"
|
||||
|
||||
puts "ALL PASSED"
|
||||
@@ -0,0 +1,29 @@
|
||||
// Design with bidirectional ports and reconvergent paths
|
||||
// for testing graph bidirect vertex/edge handling
|
||||
module graph_bidirect (clk, d1, d2, d3, d4, q1, q2, q3, q4);
|
||||
input clk, d1, d2, d3, d4;
|
||||
output q1, q2, q3, q4;
|
||||
wire n1, n2, n3, n4, n5, n6, n7, n8, n9, n10;
|
||||
|
||||
// Fan-out from d1 and d2
|
||||
BUF_X1 buf1 (.A(d1), .Z(n1));
|
||||
BUF_X1 buf2 (.A(d2), .Z(n2));
|
||||
INV_X1 inv1 (.A(d3), .ZN(n3));
|
||||
INV_X1 inv2 (.A(d4), .ZN(n4));
|
||||
|
||||
// Reconvergent logic
|
||||
AND2_X1 and1 (.A1(n1), .A2(n2), .ZN(n5));
|
||||
OR2_X1 or1 (.A1(n1), .A2(n3), .ZN(n6));
|
||||
NAND2_X1 nand1 (.A1(n2), .A2(n4), .ZN(n7));
|
||||
NOR2_X1 nor1 (.A1(n3), .A2(n4), .ZN(n8));
|
||||
|
||||
// Second level reconvergence
|
||||
AND2_X1 and2 (.A1(n5), .A2(n6), .ZN(n9));
|
||||
OR2_X1 or2 (.A1(n7), .A2(n8), .ZN(n10));
|
||||
|
||||
// Registers
|
||||
DFF_X1 reg1 (.D(n5), .CK(clk), .Q(q1));
|
||||
DFF_X1 reg2 (.D(n9), .CK(clk), .Q(q2));
|
||||
DFF_X1 reg3 (.D(n10), .CK(clk), .Q(q3));
|
||||
DFF_X1 reg4 (.D(n6), .CK(clk), .Q(q4));
|
||||
endmodule
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,190 @@
|
||||
# Test graph delay value comparison and multi-corner graph operations.
|
||||
# Targets: DelayFloat.cc (87.8% -> delayLess with min_max, delayGreater,
|
||||
# delayGreaterEqual, delayLessEqual, delayRemove, delayRatio, delayZero,
|
||||
# delayInf, delayInitValue, delayIsInitValue)
|
||||
# Graph.cc (71.2% -> multi-corner vertex/edge access, clock vertices)
|
||||
# GraphCmp.cc (90.5% -> sortEdges with multiple edges)
|
||||
|
||||
source ../../test/helpers.tcl
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Multi-corner setup for graph coverage
|
||||
#---------------------------------------------------------------
|
||||
define_corners fast slow
|
||||
|
||||
read_liberty -corner fast ../../test/nangate45/Nangate45_fast.lib
|
||||
read_liberty -corner slow ../../test/nangate45/Nangate45_slow.lib
|
||||
|
||||
read_verilog graph_test2.v
|
||||
link_design graph_test2
|
||||
|
||||
create_clock -name clk -period 10 [get_ports clk]
|
||||
set_input_delay -clock clk 1.0 [get_ports {d1 d2 en}]
|
||||
set_output_delay -clock clk 1.0 [get_ports {q1 q2}]
|
||||
set_input_transition 0.1 [get_ports {d1 d2 en}]
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Multi-corner timing reports (exercises delay value comparison
|
||||
# across min/max analysis points in Graph)
|
||||
#---------------------------------------------------------------
|
||||
puts "--- fast corner ---"
|
||||
report_checks -corner fast
|
||||
puts "PASS: fast corner"
|
||||
|
||||
report_checks -corner fast -path_delay min
|
||||
puts "PASS: fast corner min"
|
||||
|
||||
report_checks -corner fast -path_delay max
|
||||
puts "PASS: fast corner max"
|
||||
|
||||
puts "--- slow corner ---"
|
||||
report_checks -corner slow
|
||||
puts "PASS: slow corner"
|
||||
|
||||
report_checks -corner slow -path_delay min
|
||||
puts "PASS: slow corner min"
|
||||
|
||||
report_checks -corner slow -path_delay max
|
||||
puts "PASS: slow corner max"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Multi-corner report_dcalc (exercises delay subtraction/comparison)
|
||||
#---------------------------------------------------------------
|
||||
puts "--- report_dcalc per corner ---"
|
||||
catch {report_dcalc -corner fast -from [get_pins buf1/A] -to [get_pins buf1/Z]} msg
|
||||
puts "fast buf1 dcalc: done"
|
||||
|
||||
catch {report_dcalc -corner slow -from [get_pins buf1/A] -to [get_pins buf1/Z]} msg
|
||||
puts "slow buf1 dcalc: done"
|
||||
|
||||
catch {report_dcalc -corner fast -from [get_pins inv1/A] -to [get_pins inv1/ZN]} msg
|
||||
puts "fast inv1 dcalc: done"
|
||||
|
||||
catch {report_dcalc -corner slow -from [get_pins inv1/A] -to [get_pins inv1/ZN]} msg
|
||||
puts "slow inv1 dcalc: done"
|
||||
|
||||
catch {report_dcalc -corner fast -from [get_pins and1/A1] -to [get_pins and1/ZN]} msg
|
||||
puts "fast and1 A1 dcalc: done"
|
||||
|
||||
catch {report_dcalc -corner slow -from [get_pins and1/A1] -to [get_pins and1/ZN]} msg
|
||||
puts "slow and1 A1 dcalc: done"
|
||||
|
||||
catch {report_dcalc -corner fast -from [get_pins or1/A1] -to [get_pins or1/ZN]} msg
|
||||
puts "fast or1 A1 dcalc: done"
|
||||
|
||||
catch {report_dcalc -corner slow -from [get_pins or1/A1] -to [get_pins or1/ZN]} msg
|
||||
puts "slow or1 A1 dcalc: done"
|
||||
|
||||
# DFF arcs
|
||||
catch {report_dcalc -corner fast -from [get_pins reg1/CK] -to [get_pins reg1/Q] -max} msg
|
||||
puts "fast reg1 CK->Q: done"
|
||||
|
||||
catch {report_dcalc -corner slow -from [get_pins reg1/CK] -to [get_pins reg1/Q] -max} msg
|
||||
puts "slow reg1 CK->Q: done"
|
||||
|
||||
catch {report_dcalc -corner fast -from [get_pins reg1/CK] -to [get_pins reg1/D] -max} msg
|
||||
puts "fast reg1 setup: done"
|
||||
|
||||
catch {report_dcalc -corner slow -from [get_pins reg1/CK] -to [get_pins reg1/D] -min} msg
|
||||
puts "slow reg1 hold: done"
|
||||
|
||||
puts "PASS: report_dcalc per corner"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# report_checks with fields across corners (exercises graph slew access)
|
||||
#---------------------------------------------------------------
|
||||
puts "--- report_checks with fields ---"
|
||||
report_checks -corner fast -fields {slew cap input_pins}
|
||||
puts "PASS: fast fields"
|
||||
|
||||
report_checks -corner slow -fields {slew cap input_pins}
|
||||
puts "PASS: slow fields"
|
||||
|
||||
report_checks -corner fast -format full_clock
|
||||
puts "PASS: fast full_clock"
|
||||
|
||||
report_checks -corner slow -format full_clock
|
||||
puts "PASS: slow full_clock"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Multi-corner paths (different paths in fast vs slow)
|
||||
#---------------------------------------------------------------
|
||||
puts "--- multi-corner paths ---"
|
||||
report_checks -corner fast -from [get_ports d1] -to [get_ports q1]
|
||||
puts "PASS: fast d1->q1"
|
||||
|
||||
report_checks -corner slow -from [get_ports d1] -to [get_ports q1]
|
||||
puts "PASS: slow d1->q1"
|
||||
|
||||
report_checks -corner fast -from [get_ports d2] -to [get_ports q2]
|
||||
puts "PASS: fast d2->q2"
|
||||
|
||||
report_checks -corner slow -from [get_ports d2] -to [get_ports q2]
|
||||
puts "PASS: slow d2->q2"
|
||||
|
||||
report_checks -corner fast -from [get_ports en] -to [get_ports q1]
|
||||
puts "PASS: fast en->q1"
|
||||
|
||||
report_checks -corner slow -from [get_ports en] -to [get_ports q1]
|
||||
puts "PASS: slow en->q1"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Edge queries with multi-corner
|
||||
#---------------------------------------------------------------
|
||||
puts "--- timing edges multi-corner ---"
|
||||
set e1 [get_timing_edges -of_objects [get_cells and1]]
|
||||
puts "and1 edges: [llength $e1]"
|
||||
|
||||
set e2 [get_timing_edges -of_objects [get_cells or1]]
|
||||
puts "or1 edges: [llength $e2]"
|
||||
|
||||
set e3 [get_timing_edges -of_objects [get_cells reg1]]
|
||||
puts "reg1 edges: [llength $e3]"
|
||||
|
||||
report_edges -from [get_pins and1/A1] -to [get_pins and1/ZN]
|
||||
report_edges -from [get_pins and1/A2] -to [get_pins and1/ZN]
|
||||
report_edges -from [get_pins or1/A1] -to [get_pins or1/ZN]
|
||||
report_edges -from [get_pins or1/A2] -to [get_pins or1/ZN]
|
||||
puts "PASS: timing edges multi-corner"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Load changes with multi-corner (exercises delay recomputation)
|
||||
#---------------------------------------------------------------
|
||||
puts "--- load changes multi-corner ---"
|
||||
set_load 0.01 [get_ports q1]
|
||||
set_load 0.05 [get_ports q2]
|
||||
|
||||
report_checks -corner fast
|
||||
puts "PASS: fast after load change"
|
||||
|
||||
report_checks -corner slow
|
||||
puts "PASS: slow after load change"
|
||||
|
||||
set_load 0 [get_ports q1]
|
||||
set_load 0 [get_ports q2]
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# report_checks -unconstrained multi-corner
|
||||
#---------------------------------------------------------------
|
||||
puts "--- unconstrained multi-corner ---"
|
||||
report_checks -corner fast -unconstrained
|
||||
puts "PASS: fast unconstrained"
|
||||
|
||||
report_checks -corner slow -unconstrained
|
||||
puts "PASS: slow unconstrained"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Disable/enable with multi-corner
|
||||
#---------------------------------------------------------------
|
||||
puts "--- disable with multi-corner ---"
|
||||
set_disable_timing [get_cells buf1]
|
||||
report_checks -corner fast
|
||||
report_checks -corner slow
|
||||
puts "PASS: disable buf1 multi-corner"
|
||||
|
||||
unset_disable_timing [get_cells buf1]
|
||||
report_checks -corner fast
|
||||
report_checks -corner slow
|
||||
puts "PASS: enable buf1 multi-corner"
|
||||
|
||||
puts "ALL PASSED"
|
||||
@@ -0,0 +1,751 @@
|
||||
--- Test 1: baseline ---
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
PASS: baseline max
|
||||
Startpoint: d3 (input port clocked by clk)
|
||||
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: min
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 ^ input external delay
|
||||
0.00 1.00 ^ d3 (in)
|
||||
0.01 1.01 v inv1/ZN (INV_X1)
|
||||
0.03 1.04 ^ nor1/ZN (NOR2_X1)
|
||||
0.00 1.04 ^ reg3/D (DFF_X1)
|
||||
1.04 data arrival time
|
||||
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 clock reconvergence pessimism
|
||||
0.00 ^ reg3/CK (DFF_X1)
|
||||
0.01 0.01 library hold time
|
||||
0.01 data required time
|
||||
---------------------------------------------------------
|
||||
0.01 data required time
|
||||
-1.04 data arrival time
|
||||
---------------------------------------------------------
|
||||
1.03 slack (MET)
|
||||
|
||||
|
||||
PASS: baseline min
|
||||
Warning: graph_delete_modify.tcl line 1, unknown field nets.
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Fanout Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------------
|
||||
0.00 0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
1 0.88 0.10 0.00 1.00 v d2 (in)
|
||||
0.10 0.00 1.00 v buf2/A (BUF_X1)
|
||||
2 1.69 0.01 0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.01 0.00 1.06 v or1/A1 (OR2_X1)
|
||||
2 2.56 0.01 0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.01 0.00 1.11 v nand1/A2 (NAND2_X1)
|
||||
1 1.14 0.01 0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.01 0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
0.00 10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
-----------------------------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
-----------------------------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
PASS: baseline fields
|
||||
--- Test 2: add/delete multiple instances ---
|
||||
PASS: added buffer chain
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
PASS: timing after add chain
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
PASS: timing after partial disconnect
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
PASS: timing after reconnect
|
||||
PASS: full cleanup
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
PASS: timing after full cleanup
|
||||
--- Test 3: replace_cell ---
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
A -> Z combinational
|
||||
^ -> ^ 0.03:0.03
|
||||
v -> v 0.05:0.05
|
||||
PASS: buf1 -> BUF_X4
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
PASS: buf1 -> BUF_X2
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
PASS: buf1 restored
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
PASS: and1 -> AND2_X2
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
PASS: and1 restored
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
PASS: inv1 -> INV_X2
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
PASS: inv1 restored
|
||||
--- Test 4: add/delete register ---
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
PASS: timing with added register
|
||||
PASS: register removed
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
PASS: timing after register removal
|
||||
--- Test 5: rapid connect/disconnect ---
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
cycle 1 done
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
cycle 2 done
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
cycle 3 done
|
||||
PASS: rapid cycles
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
PASS: timing after rapid cycles
|
||||
--- Test 6: edge queries ---
|
||||
buf1 edges: 1
|
||||
buf2 edges: 1
|
||||
inv1 edges: 1
|
||||
and1 edges: 1
|
||||
or1 edges: 1
|
||||
nand1 edges: 1
|
||||
nor1 edges: 1
|
||||
reg1 edges: 1
|
||||
reg2 edges: 1
|
||||
reg3 edges: 1
|
||||
reg4 edges: 1
|
||||
PASS: edge queries
|
||||
d1 ^ 0.10:0.10 v 0.10:0.10
|
||||
d2 ^ 0.10:0.10 v 0.10:0.10
|
||||
d3 ^ 0.10:0.10 v 0.10:0.10
|
||||
buf1/Z ^ 0.01:0.01 v 0.01:0.01
|
||||
and1/ZN ^ 0.01:0.01 v 0.01:0.01
|
||||
reg1/Q ^ 0.01:0.01 v 0.00:0.00
|
||||
PASS: slew queries
|
||||
--- Test 7: through pins ---
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
through nand1: done
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.04 1.09 v and1/ZN (AND2_X1)
|
||||
0.02 1.11 ^ nor1/ZN (NOR2_X1)
|
||||
0.00 1.11 ^ reg3/D (DFF_X1)
|
||||
1.11 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg3/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.11 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
through nor1: done
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.04 1.09 v and1/ZN (AND2_X1)
|
||||
0.02 1.11 ^ nor1/ZN (NOR2_X1)
|
||||
0.00 1.11 ^ reg3/D (DFF_X1)
|
||||
1.11 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg3/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.11 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
through and1: done
|
||||
PASS: through pin queries
|
||||
ALL PASSED
|
||||
@@ -0,0 +1,218 @@
|
||||
# Test graph modification: add/delete vertices via connect_pin/disconnect_pin,
|
||||
# delete_instance, replace_cell, and repeated graph rebuild.
|
||||
# Targets:
|
||||
# Graph.cc: deleteVertex (lines 476-504), deleteInEdge, deleteOutEdge,
|
||||
# makePinVertices, makeVertex, makeWireEdgesFromPin (multi-driver),
|
||||
# hasFaninOne, makeInstEdges after replace_cell,
|
||||
# removeWireEdge, removeInstEdge on disconnect/reconnect,
|
||||
# reg_clk_vertices_ insert/erase on add/delete reg
|
||||
|
||||
source ../../test/helpers.tcl
|
||||
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
read_verilog graph_delete_modify.v
|
||||
link_design graph_delete_modify
|
||||
|
||||
create_clock -name clk -period 10 [get_ports clk]
|
||||
set_input_delay -clock clk 1.0 [get_ports {d1 d2 d3 rst}]
|
||||
set_output_delay -clock clk 1.0 [get_ports {q1 q2 q3 q4}]
|
||||
set_input_transition 0.1 [get_ports {d1 d2 d3 rst clk}]
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 1: Baseline timing
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Test 1: baseline ---"
|
||||
report_checks
|
||||
puts "PASS: baseline max"
|
||||
|
||||
report_checks -path_delay min
|
||||
puts "PASS: baseline min"
|
||||
|
||||
report_checks -fields {slew cap input_pins nets fanout}
|
||||
puts "PASS: baseline fields"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 2: Add multiple instances and nets, then delete
|
||||
# Exercises: makeVertex, makeWireEdgesFromPin, deleteVertex,
|
||||
# deleteInEdge, deleteOutEdge
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Test 2: add/delete multiple instances ---"
|
||||
|
||||
# Add a buffer chain
|
||||
set net_a [make_net test_net_a]
|
||||
set net_b [make_net test_net_b]
|
||||
set net_c [make_net test_net_c]
|
||||
set inst_a [make_instance test_buf_a NangateOpenCellLibrary/BUF_X1]
|
||||
set inst_b [make_instance test_buf_b NangateOpenCellLibrary/BUF_X2]
|
||||
|
||||
connect_pin test_net_a test_buf_a/A
|
||||
connect_pin test_net_b test_buf_a/Z
|
||||
connect_pin test_net_b test_buf_b/A
|
||||
connect_pin test_net_c test_buf_b/Z
|
||||
puts "PASS: added buffer chain"
|
||||
|
||||
report_checks
|
||||
puts "PASS: timing after add chain"
|
||||
|
||||
# Disconnect middle and verify
|
||||
disconnect_pin test_net_b test_buf_b/A
|
||||
report_checks
|
||||
puts "PASS: timing after partial disconnect"
|
||||
|
||||
# Reconnect
|
||||
connect_pin test_net_b test_buf_b/A
|
||||
report_checks
|
||||
puts "PASS: timing after reconnect"
|
||||
|
||||
# Full cleanup
|
||||
disconnect_pin test_net_a test_buf_a/A
|
||||
disconnect_pin test_net_b test_buf_a/Z
|
||||
disconnect_pin test_net_b test_buf_b/A
|
||||
disconnect_pin test_net_c test_buf_b/Z
|
||||
delete_instance test_buf_a
|
||||
delete_instance test_buf_b
|
||||
delete_net test_net_a
|
||||
delete_net test_net_b
|
||||
delete_net test_net_c
|
||||
puts "PASS: full cleanup"
|
||||
|
||||
report_checks
|
||||
puts "PASS: timing after full cleanup"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 3: Replace cell multiple times
|
||||
# Exercises: makeInstEdges rebuild, edge arc changes
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Test 3: replace_cell ---"
|
||||
|
||||
replace_cell buf1 NangateOpenCellLibrary/BUF_X4
|
||||
report_checks
|
||||
report_edges -from [get_pins buf1/A] -to [get_pins buf1/Z]
|
||||
puts "PASS: buf1 -> BUF_X4"
|
||||
|
||||
replace_cell buf1 NangateOpenCellLibrary/BUF_X2
|
||||
report_checks
|
||||
puts "PASS: buf1 -> BUF_X2"
|
||||
|
||||
replace_cell buf1 NangateOpenCellLibrary/BUF_X1
|
||||
report_checks
|
||||
puts "PASS: buf1 restored"
|
||||
|
||||
replace_cell and1 NangateOpenCellLibrary/AND2_X2
|
||||
report_checks
|
||||
puts "PASS: and1 -> AND2_X2"
|
||||
|
||||
replace_cell and1 NangateOpenCellLibrary/AND2_X1
|
||||
report_checks
|
||||
puts "PASS: and1 restored"
|
||||
|
||||
replace_cell inv1 NangateOpenCellLibrary/INV_X2
|
||||
report_checks
|
||||
puts "PASS: inv1 -> INV_X2"
|
||||
|
||||
replace_cell inv1 NangateOpenCellLibrary/INV_X1
|
||||
report_checks
|
||||
puts "PASS: inv1 restored"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 4: Add and delete register instances
|
||||
# Exercises: reg_clk_vertices_ insert/erase in makeVertex/deleteVertex
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Test 4: add/delete register ---"
|
||||
|
||||
set reg_net [make_net reg_test_net]
|
||||
set reg_qnet [make_net reg_test_qnet]
|
||||
set reg_inst [make_instance test_reg NangateOpenCellLibrary/DFF_X1]
|
||||
|
||||
connect_pin reg_test_net test_reg/D
|
||||
connect_pin reg_test_qnet test_reg/Q
|
||||
|
||||
# Connect clock to new register
|
||||
set clk_net_name "clk"
|
||||
catch {connect_pin $clk_net_name test_reg/CK} msg
|
||||
|
||||
report_checks
|
||||
puts "PASS: timing with added register"
|
||||
|
||||
# Remove the register
|
||||
catch {disconnect_pin $clk_net_name test_reg/CK} msg
|
||||
disconnect_pin reg_test_net test_reg/D
|
||||
disconnect_pin reg_test_qnet test_reg/Q
|
||||
delete_instance test_reg
|
||||
delete_net reg_test_net
|
||||
delete_net reg_test_qnet
|
||||
puts "PASS: register removed"
|
||||
|
||||
report_checks
|
||||
puts "PASS: timing after register removal"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 5: Rapid connect/disconnect on same pin
|
||||
# Exercises: edge create/delete cycling
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Test 5: rapid connect/disconnect ---"
|
||||
|
||||
set tmp_net [make_net tmp_net]
|
||||
set tmp_inst [make_instance tmp_buf NangateOpenCellLibrary/BUF_X1]
|
||||
|
||||
# Cycle 1
|
||||
connect_pin tmp_net tmp_buf/A
|
||||
report_checks
|
||||
disconnect_pin tmp_net tmp_buf/A
|
||||
puts "cycle 1 done"
|
||||
|
||||
# Cycle 2
|
||||
connect_pin tmp_net tmp_buf/A
|
||||
report_checks
|
||||
disconnect_pin tmp_net tmp_buf/A
|
||||
puts "cycle 2 done"
|
||||
|
||||
# Cycle 3
|
||||
connect_pin tmp_net tmp_buf/A
|
||||
report_checks
|
||||
disconnect_pin tmp_net tmp_buf/A
|
||||
puts "cycle 3 done"
|
||||
|
||||
delete_instance tmp_buf
|
||||
delete_net tmp_net
|
||||
puts "PASS: rapid cycles"
|
||||
|
||||
report_checks
|
||||
puts "PASS: timing after rapid cycles"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 6: Edge queries after all modifications
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Test 6: edge queries ---"
|
||||
|
||||
foreach cell_name {buf1 buf2 inv1 and1 or1 nand1 nor1 reg1 reg2 reg3 reg4} {
|
||||
set edges [get_timing_edges -of_objects [get_cells $cell_name]]
|
||||
puts "$cell_name edges: [llength $edges]"
|
||||
}
|
||||
puts "PASS: edge queries"
|
||||
|
||||
# Slew queries
|
||||
report_slews [get_ports d1]
|
||||
report_slews [get_ports d2]
|
||||
report_slews [get_ports d3]
|
||||
report_slews [get_pins buf1/Z]
|
||||
report_slews [get_pins and1/ZN]
|
||||
report_slews [get_pins reg1/Q]
|
||||
puts "PASS: slew queries"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 7: Through-pin paths
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Test 7: through pins ---"
|
||||
catch {report_checks -through [get_pins nand1/ZN]} msg
|
||||
puts "through nand1: done"
|
||||
|
||||
catch {report_checks -through [get_pins nor1/ZN]} msg
|
||||
puts "through nor1: done"
|
||||
|
||||
catch {report_checks -through [get_pins and1/ZN]} msg
|
||||
puts "through and1: done"
|
||||
|
||||
puts "PASS: through pin queries"
|
||||
|
||||
puts "ALL PASSED"
|
||||
@@ -0,0 +1,29 @@
|
||||
// Design for testing graph delete/modify operations:
|
||||
// makeVertex/deleteVertex through connect_pin/disconnect_pin/delete_instance,
|
||||
// replace_cell with different pin counts, multi-fanout nets,
|
||||
// and reconvergent paths that exercise edge deletion.
|
||||
module graph_delete_modify (clk, d1, d2, d3, rst, q1, q2, q3, q4);
|
||||
input clk, d1, d2, d3, rst;
|
||||
output q1, q2, q3, q4;
|
||||
wire n1, n2, n3, n4, n5, n6, n7, n8;
|
||||
|
||||
// Chain: d1 -> buf1 -> n1 -> and1 -> n5
|
||||
BUF_X1 buf1 (.A(d1), .Z(n1));
|
||||
// Chain: d2 -> buf2 -> n2 -> and1, or1 (multi-fanout)
|
||||
BUF_X1 buf2 (.A(d2), .Z(n2));
|
||||
// Chain: d3 -> inv1 -> n3 -> or1
|
||||
INV_X1 inv1 (.A(d3), .ZN(n3));
|
||||
|
||||
AND2_X1 and1 (.A1(n1), .A2(n2), .ZN(n5));
|
||||
OR2_X1 or1 (.A1(n2), .A2(n3), .ZN(n6));
|
||||
|
||||
// Second stage
|
||||
NAND2_X1 nand1 (.A1(n5), .A2(n6), .ZN(n7));
|
||||
NOR2_X1 nor1 (.A1(n5), .A2(n3), .ZN(n8));
|
||||
|
||||
// Registers with reset
|
||||
DFF_X1 reg1 (.D(n5), .CK(clk), .Q(q1));
|
||||
DFF_X1 reg2 (.D(n7), .CK(clk), .Q(q2));
|
||||
DFF_X1 reg3 (.D(n8), .CK(clk), .Q(q3));
|
||||
DFF_X1 reg4 (.D(n6), .CK(clk), .Q(q4));
|
||||
endmodule
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,225 @@
|
||||
# Test graph incremental changes, constant propagation, and level reporting.
|
||||
# Targets: Graph.cc (71.2% -> constant propagation, remove/add edges,
|
||||
# setSlew, pinDrvrVertex, pinLoadVertex, hasDownstreamClkPin, etc.)
|
||||
# GraphCmp.cc (90.5% -> EdgeLess, sortEdges, VertexNameLess)
|
||||
# DelayFloat.cc (87.8% -> delayLess with min_max, delayGreater, etc.)
|
||||
|
||||
source ../../test/helpers.tcl
|
||||
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
read_verilog graph_test2.v
|
||||
link_design graph_test2
|
||||
|
||||
create_clock -name clk -period 10 [get_ports clk]
|
||||
set_input_delay -clock clk 1.0 [get_ports d1]
|
||||
set_input_delay -clock clk 1.0 [get_ports d2]
|
||||
set_input_delay -clock clk 0 [get_ports en]
|
||||
set_output_delay -clock clk 1.0 [get_ports q1]
|
||||
set_output_delay -clock clk 1.0 [get_ports q2]
|
||||
set_input_transition 0.1 [get_ports {d1 d2 en}]
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Baseline timing
|
||||
#---------------------------------------------------------------
|
||||
puts "--- baseline report_checks ---"
|
||||
report_checks
|
||||
puts "PASS: baseline report_checks"
|
||||
|
||||
report_checks -path_delay min
|
||||
puts "PASS: baseline min"
|
||||
|
||||
report_checks -path_delay max
|
||||
puts "PASS: baseline max"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Multiple paths through design
|
||||
#---------------------------------------------------------------
|
||||
puts "--- multiple paths ---"
|
||||
report_checks -from [get_ports d1] -to [get_ports q1]
|
||||
puts "PASS: d1->q1"
|
||||
|
||||
report_checks -from [get_ports d1] -to [get_ports q2]
|
||||
puts "PASS: d1->q2"
|
||||
|
||||
report_checks -from [get_ports d2] -to [get_ports q2]
|
||||
puts "PASS: d2->q2"
|
||||
|
||||
report_checks -from [get_ports en] -to [get_ports q1]
|
||||
puts "PASS: en->q1"
|
||||
|
||||
report_checks -from [get_ports en] -to [get_ports q2]
|
||||
puts "PASS: en->q2"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# -through paths (exercises graph traversal)
|
||||
#---------------------------------------------------------------
|
||||
puts "--- through paths ---"
|
||||
catch { report_checks -through [get_pins inv1/ZN] } msg
|
||||
puts "through inv1/ZN: done"
|
||||
puts "PASS: through inv1/ZN"
|
||||
|
||||
catch { report_checks -through [get_pins and1/ZN] } msg
|
||||
puts "through and1/ZN: done"
|
||||
puts "PASS: through and1/ZN"
|
||||
|
||||
catch { report_checks -through [get_pins or1/ZN] } msg
|
||||
puts "through or1/ZN: done"
|
||||
puts "PASS: through or1/ZN"
|
||||
|
||||
catch { report_checks -through [get_pins buf3/Z] } msg
|
||||
puts "through buf3/Z: done"
|
||||
puts "PASS: through buf3/Z"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Timing edge queries for multi-input cells
|
||||
#---------------------------------------------------------------
|
||||
puts "--- timing edges for multi-input cells ---"
|
||||
set edges_and [get_timing_edges -of_objects [get_cells and1]]
|
||||
puts "and1 edges: [llength $edges_and]"
|
||||
|
||||
set edges_or [get_timing_edges -of_objects [get_cells or1]]
|
||||
puts "or1 edges: [llength $edges_or]"
|
||||
|
||||
set edges_reg1 [get_timing_edges -of_objects [get_cells reg1]]
|
||||
puts "reg1 edges: [llength $edges_reg1]"
|
||||
|
||||
set edges_reg2 [get_timing_edges -of_objects [get_cells reg2]]
|
||||
puts "reg2 edges: [llength $edges_reg2]"
|
||||
|
||||
# From/to specific pins
|
||||
set edges_ft [get_timing_edges -from [get_pins and1/A1] -to [get_pins and1/ZN]]
|
||||
puts "and1 A1->ZN edges: [llength $edges_ft]"
|
||||
|
||||
set edges_ft2 [get_timing_edges -from [get_pins and1/A2] -to [get_pins and1/ZN]]
|
||||
puts "and1 A2->ZN edges: [llength $edges_ft2]"
|
||||
|
||||
set edges_ft3 [get_timing_edges -from [get_pins or1/A1] -to [get_pins or1/ZN]]
|
||||
puts "or1 A1->ZN edges: [llength $edges_ft3]"
|
||||
|
||||
puts "PASS: timing edge queries"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# report_edges for various pin combinations
|
||||
#---------------------------------------------------------------
|
||||
puts "--- report_edges ---"
|
||||
report_edges -from [get_pins buf1/A] -to [get_pins buf1/Z]
|
||||
puts "PASS: report_edges buf1"
|
||||
|
||||
report_edges -from [get_pins inv1/A] -to [get_pins inv1/ZN]
|
||||
puts "PASS: report_edges inv1"
|
||||
|
||||
report_edges -from [get_pins and1/A1]
|
||||
puts "PASS: report_edges from and1/A1"
|
||||
|
||||
report_edges -to [get_pins and1/ZN]
|
||||
puts "PASS: report_edges to and1/ZN"
|
||||
|
||||
report_edges -from [get_ports d1]
|
||||
puts "PASS: report_edges from port d1"
|
||||
|
||||
report_edges -to [get_ports q2]
|
||||
puts "PASS: report_edges to port q2"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Constant propagation via set_case_analysis
|
||||
#---------------------------------------------------------------
|
||||
puts "--- set_case_analysis ---"
|
||||
set_case_analysis 1 [get_ports en]
|
||||
report_checks
|
||||
puts "PASS: report_checks en=1"
|
||||
|
||||
report_checks -from [get_ports d1] -to [get_ports q1]
|
||||
puts "PASS: d1->q1 with en=1"
|
||||
|
||||
# Change constant value
|
||||
set_case_analysis 0 [get_ports en]
|
||||
report_checks
|
||||
puts "PASS: report_checks en=0"
|
||||
|
||||
# Remove case analysis
|
||||
unset_case_analysis [get_ports en]
|
||||
report_checks
|
||||
puts "PASS: report_checks after unset_case_analysis"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Disable/enable timing with multiple cells
|
||||
#---------------------------------------------------------------
|
||||
puts "--- disable/enable timing multiple cells ---"
|
||||
set_disable_timing [get_cells buf1]
|
||||
report_checks
|
||||
puts "PASS: disable buf1"
|
||||
|
||||
set_disable_timing [get_cells inv1]
|
||||
report_checks
|
||||
puts "PASS: disable buf1+inv1"
|
||||
|
||||
unset_disable_timing [get_cells buf1]
|
||||
report_checks
|
||||
puts "PASS: enable buf1"
|
||||
|
||||
unset_disable_timing [get_cells inv1]
|
||||
report_checks
|
||||
puts "PASS: enable inv1"
|
||||
|
||||
# Disable specific lib cell arc
|
||||
set_disable_timing -from A -to Z [get_lib_cells NangateOpenCellLibrary/BUF_X1]
|
||||
report_disabled_edges
|
||||
report_checks
|
||||
puts "PASS: disable lib cell arc"
|
||||
|
||||
unset_disable_timing -from A -to Z [get_lib_cells NangateOpenCellLibrary/BUF_X1]
|
||||
report_disabled_edges
|
||||
report_checks
|
||||
puts "PASS: unset lib cell arc"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# report_check_types
|
||||
#---------------------------------------------------------------
|
||||
puts "--- report_check_types ---"
|
||||
report_check_types -max_delay -verbose
|
||||
puts "PASS: report_check_types max_delay"
|
||||
|
||||
report_check_types -min_delay -verbose
|
||||
puts "PASS: report_check_types min_delay"
|
||||
|
||||
report_check_types -max_delay -min_delay -verbose
|
||||
puts "PASS: report_check_types max+min"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Report slews for various pins
|
||||
#---------------------------------------------------------------
|
||||
puts "--- report_slews ---"
|
||||
report_slews [get_ports d1]
|
||||
report_slews [get_ports d2]
|
||||
report_slews [get_ports en]
|
||||
report_slews [get_ports q1]
|
||||
report_slews [get_ports q2]
|
||||
report_slews [get_pins buf1/Z]
|
||||
report_slews [get_pins inv1/ZN]
|
||||
report_slews [get_pins and1/ZN]
|
||||
report_slews [get_pins or1/ZN]
|
||||
report_slews [get_pins reg1/Q]
|
||||
report_slews [get_pins reg2/Q]
|
||||
puts "PASS: report_slews various pins"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# report_checks with -unconstrained
|
||||
#---------------------------------------------------------------
|
||||
puts "--- report_checks -unconstrained ---"
|
||||
report_checks -unconstrained
|
||||
puts "PASS: report_checks unconstrained"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# report_checks with group_count and endpoint_count
|
||||
#---------------------------------------------------------------
|
||||
puts "--- report_checks counts ---"
|
||||
report_checks -group_count 3
|
||||
puts "PASS: group_count 3"
|
||||
|
||||
report_checks -endpoint_count 3
|
||||
puts "PASS: endpoint_count 3"
|
||||
|
||||
report_checks -endpoint_count 5 -path_delay min
|
||||
puts "PASS: endpoint_count 5 min"
|
||||
|
||||
puts "ALL PASSED"
|
||||
@@ -0,0 +1,2 @@
|
||||
No paths found.
|
||||
PASS: graph created and timing reported
|
||||
@@ -0,0 +1,11 @@
|
||||
# Read liberty and design, make graph, verify
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
read_verilog graph_test1.v
|
||||
link_design graph_test1
|
||||
|
||||
# Creating the timing graph implicitly tests graph construction
|
||||
create_clock -name clk -period 10 [get_ports clk]
|
||||
|
||||
# report_checks exercises the graph
|
||||
report_checks -from [get_ports d] -to [get_ports q]
|
||||
puts "PASS: graph created and timing reported"
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,290 @@
|
||||
# Test graph changes with network modifications, multi-corner, and
|
||||
# incremental graph updates.
|
||||
# Targets: Graph.cc (deleteVertexBefore, addEdge, removeEdge,
|
||||
# makeWireEdge, removeWireEdge, pinVertex, pinDrvrVertex,
|
||||
# pinLoadVertex, setConstant, clearConstants, hasDownstreamClkPin,
|
||||
# widthCheckAnnotation, periodCheckAnnotation, regClkVertices, isRegClk)
|
||||
# GraphCmp.cc (sortEdges, VertexNameLess with added/removed vertices)
|
||||
|
||||
source ../../test/helpers.tcl
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Multi-corner setup
|
||||
#---------------------------------------------------------------
|
||||
define_corners fast slow
|
||||
|
||||
read_liberty -corner fast ../../test/nangate45/Nangate45_fast.lib
|
||||
read_liberty -corner slow ../../test/nangate45/Nangate45_slow.lib
|
||||
|
||||
read_verilog graph_test3.v
|
||||
link_design graph_test3
|
||||
|
||||
create_clock -name clk1 -period 10 [get_ports clk1]
|
||||
create_clock -name clk2 -period 15 [get_ports clk2]
|
||||
set_input_delay -clock clk1 1.0 [get_ports {d1 d2 d3 d4}]
|
||||
set_output_delay -clock clk1 1.0 [get_ports {q1 q3}]
|
||||
set_output_delay -clock clk2 1.0 [get_ports q2]
|
||||
set_input_transition 0.1 [get_ports {d1 d2 d3 d4 rst clk1 clk2}]
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Multi-corner baseline timing
|
||||
#---------------------------------------------------------------
|
||||
puts "--- multi-corner baseline ---"
|
||||
report_checks -corner fast
|
||||
puts "PASS: fast baseline"
|
||||
|
||||
report_checks -corner slow
|
||||
puts "PASS: slow baseline"
|
||||
|
||||
report_checks -corner fast -path_delay min
|
||||
puts "PASS: fast min"
|
||||
|
||||
report_checks -corner slow -path_delay min
|
||||
puts "PASS: slow min"
|
||||
|
||||
report_checks -corner fast -path_delay max
|
||||
puts "PASS: fast max"
|
||||
|
||||
report_checks -corner slow -path_delay max
|
||||
puts "PASS: slow max"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Multi-corner per-path (exercises delay comparison across corners)
|
||||
#---------------------------------------------------------------
|
||||
puts "--- multi-corner per-path ---"
|
||||
report_checks -corner fast -from [get_ports d1] -to [get_ports q1]
|
||||
puts "PASS: fast d1->q1"
|
||||
|
||||
report_checks -corner slow -from [get_ports d1] -to [get_ports q1]
|
||||
puts "PASS: slow d1->q1"
|
||||
|
||||
report_checks -corner fast -from [get_ports d3] -to [get_ports q1]
|
||||
puts "PASS: fast d3->q1"
|
||||
|
||||
report_checks -corner slow -from [get_ports d3] -to [get_ports q1]
|
||||
puts "PASS: slow d3->q1"
|
||||
|
||||
# Cross-clock domain paths
|
||||
report_checks -corner fast -from [get_ports d1] -to [get_ports q2]
|
||||
puts "PASS: fast d1->q2 (cross-clock)"
|
||||
|
||||
report_checks -corner slow -from [get_ports d1] -to [get_ports q2]
|
||||
puts "PASS: slow d1->q2 (cross-clock)"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Multi-corner report_dcalc
|
||||
# Exercises: delay value comparison across corners
|
||||
#---------------------------------------------------------------
|
||||
puts "--- multi-corner report_dcalc ---"
|
||||
catch {report_dcalc -corner fast -from [get_pins buf1/A] -to [get_pins buf1/Z]} msg
|
||||
puts "fast buf1 dcalc: done"
|
||||
|
||||
catch {report_dcalc -corner slow -from [get_pins buf1/A] -to [get_pins buf1/Z]} msg
|
||||
puts "slow buf1 dcalc: done"
|
||||
|
||||
catch {report_dcalc -corner fast -from [get_pins nand1/A1] -to [get_pins nand1/ZN]} msg
|
||||
puts "fast nand1 dcalc: done"
|
||||
|
||||
catch {report_dcalc -corner slow -from [get_pins nand1/A1] -to [get_pins nand1/ZN]} msg
|
||||
puts "slow nand1 dcalc: done"
|
||||
|
||||
catch {report_dcalc -corner fast -from [get_pins nor1/A1] -to [get_pins nor1/ZN]} msg
|
||||
puts "fast nor1 dcalc: done"
|
||||
|
||||
catch {report_dcalc -corner slow -from [get_pins nor1/A1] -to [get_pins nor1/ZN]} msg
|
||||
puts "slow nor1 dcalc: done"
|
||||
|
||||
catch {report_dcalc -corner fast -from [get_pins reg1/CK] -to [get_pins reg1/Q] -max} msg
|
||||
puts "fast reg1 CK->Q: done"
|
||||
|
||||
catch {report_dcalc -corner slow -from [get_pins reg1/CK] -to [get_pins reg1/Q] -max} msg
|
||||
puts "slow reg1 CK->Q: done"
|
||||
|
||||
catch {report_dcalc -corner fast -from [get_pins reg1/CK] -to [get_pins reg1/D] -max} msg
|
||||
puts "fast reg1 setup: done"
|
||||
|
||||
catch {report_dcalc -corner slow -from [get_pins reg1/CK] -to [get_pins reg1/D] -min} msg
|
||||
puts "slow reg1 hold: done"
|
||||
|
||||
# Cross-clock domain DFF
|
||||
catch {report_dcalc -corner fast -from [get_pins reg3/CK] -to [get_pins reg3/Q] -max} msg
|
||||
puts "fast reg3 CK->Q: done"
|
||||
|
||||
catch {report_dcalc -corner slow -from [get_pins reg3/CK] -to [get_pins reg3/Q] -max} msg
|
||||
puts "slow reg3 CK->Q: done"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Network modification: add instance, recheck graph
|
||||
# Exercises: graph incremental update after network changes
|
||||
#---------------------------------------------------------------
|
||||
puts "--- network modification and graph update ---"
|
||||
set new_buf [make_instance added_buf NangateOpenCellLibrary/BUF_X1]
|
||||
puts "PASS: make_instance added_buf"
|
||||
|
||||
set new_net [make_net added_net]
|
||||
puts "PASS: make_net added_net"
|
||||
|
||||
connect_pin added_net added_buf/A
|
||||
puts "PASS: connect added_buf/A"
|
||||
|
||||
# Report checks after adding (graph updated incrementally)
|
||||
report_checks -corner fast
|
||||
puts "PASS: fast after add"
|
||||
|
||||
report_checks -corner slow
|
||||
puts "PASS: slow after add"
|
||||
|
||||
# Disconnect and delete
|
||||
disconnect_pin added_net added_buf/A
|
||||
delete_instance added_buf
|
||||
delete_net added_net
|
||||
puts "PASS: cleanup added instance"
|
||||
|
||||
# Report after deletion
|
||||
report_checks -corner fast
|
||||
puts "PASS: fast after delete"
|
||||
|
||||
report_checks -corner slow
|
||||
puts "PASS: slow after delete"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Replace cell and check timing
|
||||
# Exercises: graph update after cell replacement
|
||||
#---------------------------------------------------------------
|
||||
puts "--- replace_cell ---"
|
||||
replace_cell buf1 NangateOpenCellLibrary/BUF_X4
|
||||
report_checks -corner fast
|
||||
puts "PASS: fast after buf1->BUF_X4"
|
||||
|
||||
report_checks -corner slow
|
||||
puts "PASS: slow after buf1->BUF_X4"
|
||||
|
||||
# Replace back
|
||||
replace_cell buf1 NangateOpenCellLibrary/BUF_X1
|
||||
report_checks
|
||||
puts "PASS: replaced back"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Load changes with multi-corner
|
||||
# Exercises: incremental delay recomputation
|
||||
#---------------------------------------------------------------
|
||||
puts "--- load changes multi-corner ---"
|
||||
set_load 0.01 [get_ports q1]
|
||||
report_checks -corner fast
|
||||
report_checks -corner slow
|
||||
puts "PASS: q1 load 0.01"
|
||||
|
||||
set_load 0.05 [get_ports q2]
|
||||
report_checks -corner fast
|
||||
report_checks -corner slow
|
||||
puts "PASS: q2 load 0.05"
|
||||
|
||||
set_load 0.1 [get_ports q3]
|
||||
report_checks -corner fast
|
||||
report_checks -corner slow
|
||||
puts "PASS: q3 load 0.1"
|
||||
|
||||
# Reset loads
|
||||
set_load 0 [get_ports q1]
|
||||
set_load 0 [get_ports q2]
|
||||
set_load 0 [get_ports q3]
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Disable/enable timing with multi-corner
|
||||
# Exercises: edge disable/re-enable with multiple analysis points
|
||||
#---------------------------------------------------------------
|
||||
puts "--- disable timing multi-corner ---"
|
||||
set_disable_timing [get_cells and1]
|
||||
report_checks -corner fast
|
||||
report_checks -corner slow
|
||||
puts "PASS: disable and1"
|
||||
|
||||
set_disable_timing [get_cells or1]
|
||||
report_checks -corner fast
|
||||
report_checks -corner slow
|
||||
puts "PASS: disable and1+or1"
|
||||
|
||||
unset_disable_timing [get_cells and1]
|
||||
unset_disable_timing [get_cells or1]
|
||||
report_checks -corner fast
|
||||
report_checks -corner slow
|
||||
puts "PASS: enable all"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Case analysis with multi-corner
|
||||
#---------------------------------------------------------------
|
||||
puts "--- case analysis multi-corner ---"
|
||||
set_case_analysis 1 [get_ports d1]
|
||||
report_checks -corner fast
|
||||
report_checks -corner slow
|
||||
puts "PASS: d1=1 multi-corner"
|
||||
|
||||
unset_case_analysis [get_ports d1]
|
||||
report_checks -corner fast
|
||||
report_checks -corner slow
|
||||
puts "PASS: d1 unset multi-corner"
|
||||
|
||||
set_case_analysis 0 [get_ports d4]
|
||||
report_checks -corner fast
|
||||
report_checks -corner slow
|
||||
puts "PASS: d4=0 multi-corner"
|
||||
|
||||
unset_case_analysis [get_ports d4]
|
||||
report_checks
|
||||
puts "PASS: d4 unset"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Report slews per corner
|
||||
#---------------------------------------------------------------
|
||||
puts "--- report_slews multi-corner ---"
|
||||
report_slews [get_ports d1]
|
||||
report_slews [get_ports q1]
|
||||
report_slews [get_ports q2]
|
||||
report_slews [get_pins nand1/ZN]
|
||||
report_slews [get_pins nor1/ZN]
|
||||
report_slews [get_pins reg3/Q]
|
||||
puts "PASS: slews multi-corner"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Report edges (exercises EdgeLess comparator)
|
||||
#---------------------------------------------------------------
|
||||
puts "--- report_edges multi-corner ---"
|
||||
report_edges -from [get_pins nand1/A1] -to [get_pins nand1/ZN]
|
||||
report_edges -from [get_pins nand1/A2] -to [get_pins nand1/ZN]
|
||||
report_edges -from [get_pins nor1/A1] -to [get_pins nor1/ZN]
|
||||
report_edges -from [get_pins nor1/A2] -to [get_pins nor1/ZN]
|
||||
report_edges -from [get_pins and2/A1] -to [get_pins and2/ZN]
|
||||
report_edges -from [get_pins and2/A2] -to [get_pins and2/ZN]
|
||||
report_edges -from [get_pins or2/A1] -to [get_pins or2/ZN]
|
||||
report_edges -from [get_pins or2/A2] -to [get_pins or2/ZN]
|
||||
puts "PASS: report_edges multi-corner"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# report_checks with fields per corner
|
||||
#---------------------------------------------------------------
|
||||
puts "--- fields per corner ---"
|
||||
report_checks -corner fast -fields {slew cap input_pins nets fanout}
|
||||
puts "PASS: fast with fields"
|
||||
|
||||
report_checks -corner slow -fields {slew cap input_pins nets fanout}
|
||||
puts "PASS: slow with fields"
|
||||
|
||||
report_checks -corner fast -format full_clock
|
||||
puts "PASS: fast full_clock"
|
||||
|
||||
report_checks -corner slow -format full_clock
|
||||
puts "PASS: slow full_clock"
|
||||
|
||||
report_checks -corner fast -unconstrained
|
||||
puts "PASS: fast unconstrained"
|
||||
|
||||
report_checks -corner slow -unconstrained
|
||||
puts "PASS: slow unconstrained"
|
||||
|
||||
report_checks -corner fast -group_count 3
|
||||
puts "PASS: fast group_count 3"
|
||||
|
||||
report_checks -corner slow -endpoint_count 5
|
||||
puts "PASS: slow endpoint_count 5"
|
||||
|
||||
puts "ALL PASSED"
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,307 @@
|
||||
# Test graph operations with larger multi-clock design for coverage.
|
||||
# Targets: Graph.cc (makeGraph, makeVerticesAndEdges, makeWireEdges,
|
||||
# makePinVertices, makeInstanceEdges, pinVertices, pinDrvrVertex,
|
||||
# pinLoadVertex, vertexCount, edgeCount, vertexIterator, edgeIterator,
|
||||
# arcDelayCount, hasDownstreamClkPin, regClkVertices, isRegClk,
|
||||
# isLatchData, widthCheckAnnotation, periodCheckAnnotation)
|
||||
# GraphCmp.cc (EdgeLess, sortEdges, VertexNameLess, vertexLess)
|
||||
|
||||
source ../../test/helpers.tcl
|
||||
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
read_verilog graph_test3.v
|
||||
link_design graph_test3
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Two clock domains
|
||||
#---------------------------------------------------------------
|
||||
create_clock -name clk1 -period 10 [get_ports clk1]
|
||||
create_clock -name clk2 -period 15 [get_ports clk2]
|
||||
set_input_delay -clock clk1 1.0 [get_ports {d1 d2 d3 d4}]
|
||||
set_output_delay -clock clk1 1.0 [get_ports {q1 q3}]
|
||||
set_output_delay -clock clk2 1.0 [get_ports q2]
|
||||
set_input_transition 0.1 [get_ports {d1 d2 d3 d4 rst clk1 clk2}]
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Baseline timing (exercises makeGraph, graph construction)
|
||||
#---------------------------------------------------------------
|
||||
puts "--- baseline timing ---"
|
||||
report_checks
|
||||
puts "PASS: baseline report_checks"
|
||||
|
||||
report_checks -path_delay min
|
||||
puts "PASS: baseline min"
|
||||
|
||||
report_checks -path_delay max
|
||||
puts "PASS: baseline max"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# All path combinations (exercises vertex/edge traversal thoroughly)
|
||||
#---------------------------------------------------------------
|
||||
puts "--- all path combinations ---"
|
||||
foreach from_port {d1 d2 d3 d4} {
|
||||
foreach to_port {q1 q2 q3} {
|
||||
catch {
|
||||
report_checks -from [get_ports $from_port] -to [get_ports $to_port]
|
||||
} msg
|
||||
puts "${from_port}->${to_port}: done"
|
||||
}
|
||||
}
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Through pin queries for reconvergent paths
|
||||
# Exercises: graph traversal through reconvergent fan-out
|
||||
#---------------------------------------------------------------
|
||||
puts "--- through reconvergent paths ---"
|
||||
catch {report_checks -through [get_pins nand1/ZN]} msg
|
||||
puts "through nand1/ZN: done"
|
||||
|
||||
catch {report_checks -through [get_pins nor1/ZN]} msg
|
||||
puts "through nor1/ZN: done"
|
||||
|
||||
catch {report_checks -through [get_pins and2/ZN]} msg
|
||||
puts "through and2/ZN: done"
|
||||
|
||||
catch {report_checks -through [get_pins or2/ZN]} msg
|
||||
puts "through or2/ZN: done"
|
||||
|
||||
# Through multiple intermediate points
|
||||
catch {report_checks -through [get_pins and1/ZN] -through [get_pins nand1/ZN]} msg
|
||||
puts "through and1->nand1: done"
|
||||
|
||||
catch {report_checks -through [get_pins or1/ZN] -through [get_pins nand1/ZN]} msg
|
||||
puts "through or1->nand1: done"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Timing edge queries for all cells (exercises edge iteration)
|
||||
#---------------------------------------------------------------
|
||||
puts "--- timing edges all cells ---"
|
||||
foreach cell_name {buf1 buf2 inv1 inv2 and1 or1 nand1 nor1 and2 or2 reg1 reg2 reg3 buf3 buf4} {
|
||||
catch {
|
||||
set edges [get_timing_edges -of_objects [get_cells $cell_name]]
|
||||
puts "$cell_name edges: [llength $edges]"
|
||||
} msg
|
||||
}
|
||||
|
||||
# From/to specific pins
|
||||
puts "--- specific edge queries ---"
|
||||
set edges_and1_a1 [get_timing_edges -from [get_pins and1/A1] -to [get_pins and1/ZN]]
|
||||
puts "and1 A1->ZN: [llength $edges_and1_a1]"
|
||||
|
||||
set edges_and1_a2 [get_timing_edges -from [get_pins and1/A2] -to [get_pins and1/ZN]]
|
||||
puts "and1 A2->ZN: [llength $edges_and1_a2]"
|
||||
|
||||
set edges_or1_a1 [get_timing_edges -from [get_pins or1/A1] -to [get_pins or1/ZN]]
|
||||
puts "or1 A1->ZN: [llength $edges_or1_a1]"
|
||||
|
||||
set edges_nand_a1 [get_timing_edges -from [get_pins nand1/A1] -to [get_pins nand1/ZN]]
|
||||
puts "nand1 A1->ZN: [llength $edges_nand_a1]"
|
||||
|
||||
set edges_nor_a1 [get_timing_edges -from [get_pins nor1/A1] -to [get_pins nor1/ZN]]
|
||||
puts "nor1 A1->ZN: [llength $edges_nor_a1]"
|
||||
|
||||
# DFF edges
|
||||
set edges_reg1_ck_q [get_timing_edges -from [get_pins reg1/CK] -to [get_pins reg1/Q]]
|
||||
puts "reg1 CK->Q: [llength $edges_reg1_ck_q]"
|
||||
|
||||
set edges_reg3_ck_q [get_timing_edges -from [get_pins reg3/CK] -to [get_pins reg3/Q]]
|
||||
puts "reg3 CK->Q: [llength $edges_reg3_ck_q]"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Report edges for all cell types
|
||||
#---------------------------------------------------------------
|
||||
puts "--- report_edges ---"
|
||||
report_edges -from [get_pins buf1/A] -to [get_pins buf1/Z]
|
||||
puts "PASS: report_edges buf1"
|
||||
|
||||
report_edges -from [get_pins inv1/A] -to [get_pins inv1/ZN]
|
||||
puts "PASS: report_edges inv1"
|
||||
|
||||
report_edges -from [get_pins and1/A1] -to [get_pins and1/ZN]
|
||||
puts "PASS: report_edges and1 A1"
|
||||
|
||||
report_edges -from [get_pins and1/A2] -to [get_pins and1/ZN]
|
||||
puts "PASS: report_edges and1 A2"
|
||||
|
||||
report_edges -from [get_pins or1/A1] -to [get_pins or1/ZN]
|
||||
puts "PASS: report_edges or1 A1"
|
||||
|
||||
report_edges -from [get_pins nand1/A1] -to [get_pins nand1/ZN]
|
||||
puts "PASS: report_edges nand1 A1"
|
||||
|
||||
report_edges -from [get_pins nor1/A1] -to [get_pins nor1/ZN]
|
||||
puts "PASS: report_edges nor1 A1"
|
||||
|
||||
report_edges -from [get_pins reg1/CK] -to [get_pins reg1/Q]
|
||||
puts "PASS: report_edges reg1 CK->Q"
|
||||
|
||||
report_edges -from [get_pins reg3/CK] -to [get_pins reg3/Q]
|
||||
puts "PASS: report_edges reg3 CK->Q"
|
||||
|
||||
# From only
|
||||
report_edges -from [get_ports d1]
|
||||
puts "PASS: report_edges from d1"
|
||||
|
||||
report_edges -from [get_ports d3]
|
||||
puts "PASS: report_edges from d3"
|
||||
|
||||
# To only
|
||||
report_edges -to [get_ports q1]
|
||||
puts "PASS: report_edges to q1"
|
||||
|
||||
report_edges -to [get_ports q2]
|
||||
puts "PASS: report_edges to q2"
|
||||
|
||||
report_edges -to [get_ports q3]
|
||||
puts "PASS: report_edges to q3"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Disable/enable timing on various cells
|
||||
# Exercises: graph edge disable/enable, re-traversal
|
||||
#---------------------------------------------------------------
|
||||
puts "--- disable/enable timing ---"
|
||||
|
||||
# Disable individual cells
|
||||
set_disable_timing [get_cells buf1]
|
||||
report_checks
|
||||
puts "PASS: disable buf1"
|
||||
|
||||
set_disable_timing [get_cells inv1]
|
||||
report_checks
|
||||
puts "PASS: disable buf1+inv1"
|
||||
|
||||
set_disable_timing [get_cells nand1]
|
||||
report_checks
|
||||
puts "PASS: disable buf1+inv1+nand1"
|
||||
|
||||
# Enable back one by one
|
||||
unset_disable_timing [get_cells buf1]
|
||||
report_checks
|
||||
puts "PASS: enable buf1"
|
||||
|
||||
unset_disable_timing [get_cells inv1]
|
||||
report_checks
|
||||
puts "PASS: enable inv1"
|
||||
|
||||
unset_disable_timing [get_cells nand1]
|
||||
report_checks
|
||||
puts "PASS: enable nand1"
|
||||
|
||||
# Disable specific arcs on lib cells
|
||||
set_disable_timing -from A1 -to ZN [get_lib_cells NangateOpenCellLibrary/AND2_X1]
|
||||
report_disabled_edges
|
||||
report_checks
|
||||
puts "PASS: disable and1 A1->ZN arc"
|
||||
|
||||
unset_disable_timing -from A1 -to ZN [get_lib_cells NangateOpenCellLibrary/AND2_X1]
|
||||
report_disabled_edges
|
||||
report_checks
|
||||
puts "PASS: enable and1 A1->ZN arc"
|
||||
|
||||
# Disable/enable on NOR and NAND
|
||||
set_disable_timing -from A1 -to ZN [get_lib_cells NangateOpenCellLibrary/NAND2_X1]
|
||||
report_checks
|
||||
puts "PASS: disable nand1 A1 arc"
|
||||
|
||||
unset_disable_timing -from A1 -to ZN [get_lib_cells NangateOpenCellLibrary/NAND2_X1]
|
||||
report_checks
|
||||
puts "PASS: enable nand1 A1 arc"
|
||||
|
||||
set_disable_timing -from A1 -to ZN [get_lib_cells NangateOpenCellLibrary/NOR2_X1]
|
||||
report_checks
|
||||
puts "PASS: disable nor1 A1 arc"
|
||||
|
||||
unset_disable_timing -from A1 -to ZN [get_lib_cells NangateOpenCellLibrary/NOR2_X1]
|
||||
report_checks
|
||||
puts "PASS: enable nor1 A1 arc"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Case analysis / constant propagation
|
||||
# Exercises: graph constant propagation, re-traversal
|
||||
#---------------------------------------------------------------
|
||||
puts "--- case analysis ---"
|
||||
set_case_analysis 1 [get_ports rst]
|
||||
report_checks
|
||||
puts "PASS: rst=1"
|
||||
|
||||
set_case_analysis 0 [get_ports rst]
|
||||
report_checks
|
||||
puts "PASS: rst=0"
|
||||
|
||||
unset_case_analysis [get_ports rst]
|
||||
report_checks
|
||||
puts "PASS: rst unset"
|
||||
|
||||
# Case analysis on data inputs
|
||||
set_case_analysis 1 [get_ports d3]
|
||||
report_checks
|
||||
puts "PASS: d3=1"
|
||||
|
||||
unset_case_analysis [get_ports d3]
|
||||
report_checks
|
||||
puts "PASS: d3 unset"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Report slews for pins in multi-clock design
|
||||
# Exercises: vertex slew access across corners
|
||||
#---------------------------------------------------------------
|
||||
puts "--- report_slews ---"
|
||||
report_slews [get_ports d1]
|
||||
report_slews [get_ports d2]
|
||||
report_slews [get_ports d3]
|
||||
report_slews [get_ports d4]
|
||||
report_slews [get_ports q1]
|
||||
report_slews [get_ports q2]
|
||||
report_slews [get_ports q3]
|
||||
report_slews [get_pins buf1/Z]
|
||||
report_slews [get_pins inv1/ZN]
|
||||
report_slews [get_pins and1/ZN]
|
||||
report_slews [get_pins or1/ZN]
|
||||
report_slews [get_pins nand1/ZN]
|
||||
report_slews [get_pins nor1/ZN]
|
||||
report_slews [get_pins and2/ZN]
|
||||
report_slews [get_pins or2/ZN]
|
||||
report_slews [get_pins reg1/Q]
|
||||
report_slews [get_pins reg2/Q]
|
||||
report_slews [get_pins reg3/Q]
|
||||
puts "PASS: report_slews all pins"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# report_check_types (exercises check edge categorization)
|
||||
#---------------------------------------------------------------
|
||||
puts "--- report_check_types ---"
|
||||
report_check_types -max_delay -verbose
|
||||
puts "PASS: check_types max"
|
||||
|
||||
report_check_types -min_delay -verbose
|
||||
puts "PASS: check_types min"
|
||||
|
||||
report_check_types -max_delay -min_delay -verbose
|
||||
puts "PASS: check_types max+min"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# report_checks with various options
|
||||
#---------------------------------------------------------------
|
||||
puts "--- report_checks options ---"
|
||||
report_checks -fields {slew cap input_pins nets fanout}
|
||||
puts "PASS: all fields"
|
||||
|
||||
report_checks -format full_clock
|
||||
puts "PASS: full_clock"
|
||||
|
||||
report_checks -unconstrained
|
||||
puts "PASS: unconstrained"
|
||||
|
||||
report_checks -group_count 3
|
||||
puts "PASS: group_count 3"
|
||||
|
||||
report_checks -endpoint_count 5
|
||||
puts "PASS: endpoint_count 5"
|
||||
|
||||
report_checks -sort_by_slack
|
||||
puts "PASS: sort_by_slack"
|
||||
|
||||
report_checks -endpoint_count 3 -path_delay min
|
||||
puts "PASS: min endpoint_count 3"
|
||||
|
||||
puts "ALL PASSED"
|
||||
@@ -0,0 +1,8 @@
|
||||
module graph_test1 (clk, d, q);
|
||||
input clk, d;
|
||||
output q;
|
||||
wire n1;
|
||||
|
||||
DFF_X1 reg1 (.D(d), .CK(clk), .Q(n1));
|
||||
DFF_X1 reg2 (.D(n1), .CK(clk), .Q(q));
|
||||
endmodule
|
||||
@@ -0,0 +1,14 @@
|
||||
module graph_test2 (clk, d1, d2, en, q1, q2);
|
||||
input clk, d1, d2, en;
|
||||
output q1, q2;
|
||||
wire n1, n2, n3, n4, n5, n6;
|
||||
|
||||
BUF_X1 buf1 (.A(d1), .Z(n1));
|
||||
BUF_X2 buf2 (.A(d2), .Z(n2));
|
||||
INV_X1 inv1 (.A(n1), .ZN(n3));
|
||||
AND2_X1 and1 (.A1(n3), .A2(en), .ZN(n4));
|
||||
OR2_X1 or1 (.A1(n2), .A2(n4), .ZN(n5));
|
||||
BUF_X1 buf3 (.A(n5), .Z(n6));
|
||||
DFF_X1 reg1 (.D(n4), .CK(clk), .Q(q1));
|
||||
DFF_X1 reg2 (.D(n6), .CK(clk), .Q(q2));
|
||||
endmodule
|
||||
@@ -0,0 +1,34 @@
|
||||
// Larger design for graph operations testing: more cell types, fan-in/fan-out,
|
||||
// multiple clock domains, and reconvergent paths.
|
||||
module graph_test3 (clk1, clk2, rst, d1, d2, d3, d4, q1, q2, q3);
|
||||
input clk1, clk2, rst, d1, d2, d3, d4;
|
||||
output q1, q2, q3;
|
||||
wire n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12;
|
||||
|
||||
// Input stage: buffers and inverters
|
||||
BUF_X1 buf1 (.A(d1), .Z(n1));
|
||||
BUF_X2 buf2 (.A(d2), .Z(n2));
|
||||
INV_X1 inv1 (.A(d3), .ZN(n3));
|
||||
INV_X2 inv2 (.A(d4), .ZN(n4));
|
||||
|
||||
// Middle stage: logic gates
|
||||
AND2_X1 and1 (.A1(n1), .A2(n2), .ZN(n5));
|
||||
OR2_X1 or1 (.A1(n3), .A2(n4), .ZN(n6));
|
||||
NAND2_X1 nand1 (.A1(n5), .A2(n6), .ZN(n7));
|
||||
NOR2_X1 nor1 (.A1(n1), .A2(n3), .ZN(n8));
|
||||
|
||||
// Reconvergent fan-out
|
||||
AND2_X2 and2 (.A1(n7), .A2(n8), .ZN(n9));
|
||||
OR2_X2 or2 (.A1(n7), .A2(n8), .ZN(n10));
|
||||
|
||||
// Clock domain 1 registers
|
||||
DFF_X1 reg1 (.D(n9), .CK(clk1), .Q(n11));
|
||||
DFF_X1 reg2 (.D(n10), .CK(clk1), .Q(q1));
|
||||
|
||||
// Clock domain 2 register (cross-domain)
|
||||
DFF_X1 reg3 (.D(n11), .CK(clk2), .Q(n12));
|
||||
BUF_X1 buf3 (.A(n12), .Z(q2));
|
||||
|
||||
// Combinational output
|
||||
BUF_X4 buf4 (.A(n7), .Z(q3));
|
||||
endmodule
|
||||
@@ -0,0 +1,182 @@
|
||||
--- get_timing_edges -of_objects instance ---
|
||||
reg1 timing edges count: 1
|
||||
--- get_timing_edges -from/-to on instance ---
|
||||
CK->Q edges count: 1
|
||||
--- get_timing_edges -from only ---
|
||||
edges from CK count: 5
|
||||
--- get_timing_edges -to only ---
|
||||
edges to Q count: 1
|
||||
--- report_edges -from/-to ---
|
||||
CK -> Q Reg Clk to Q
|
||||
^ -> ^ 0.08:0.08
|
||||
^ -> v 0.08:0.08
|
||||
--- report_edges -from ---
|
||||
CK -> QN Reg Clk to Q
|
||||
^ -> ^ 0.06:0.06
|
||||
^ -> v 0.06:0.06
|
||||
CK -> Q Reg Clk to Q
|
||||
^ -> ^ 0.08:0.08
|
||||
^ -> v 0.08:0.08
|
||||
CK -> CK width
|
||||
^ -> v 0.05:0.05
|
||||
v -> ^ 0.05:0.05
|
||||
CK -> D setup
|
||||
^ -> ^ 0.03:0.03
|
||||
^ -> v 0.04:0.04
|
||||
CK -> D hold
|
||||
^ -> ^ 0.00:0.00
|
||||
^ -> v 0.00:0.00
|
||||
--- report_edges -to ---
|
||||
CK -> D setup
|
||||
^ -> ^ 0.03:0.03
|
||||
^ -> v 0.04:0.04
|
||||
CK -> D hold
|
||||
^ -> ^ 0.01:0.01
|
||||
^ -> v 0.00:0.00
|
||||
reg1/Q -> D wire
|
||||
^ -> ^ 0.00:0.00
|
||||
v -> v 0.00:0.00
|
||||
--- report_disabled_edges (baseline) ---
|
||||
--- set_disable_timing on instance ---
|
||||
PASS: set_disable_timing on reg1
|
||||
--- report_disabled_edges after disable ---
|
||||
reg1 CK Q constraint
|
||||
reg1 CK QN constraint
|
||||
--- report_checks after disable ---
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: q (output port clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg2/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg2/Q (DFF_X1)
|
||||
0.00 0.08 ^ q (out)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
0.00 10.00 output external delay
|
||||
10.00 data required time
|
||||
---------------------------------------------------------
|
||||
10.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.92 slack (MET)
|
||||
|
||||
|
||||
--- unset_disable_timing on instance ---
|
||||
PASS: unset_disable_timing on reg1
|
||||
--- report_disabled_edges after unset ---
|
||||
--- set_disable_timing with -from/-to on lib cell ---
|
||||
PASS: set_disable_timing -from CK -to Q
|
||||
--- report_disabled_edges after lib cell disable ---
|
||||
reg1 CK Q constraint
|
||||
reg2 CK Q constraint
|
||||
--- unset_disable_timing lib cell ---
|
||||
PASS: unset_disable_timing lib cell
|
||||
--- report_checks baseline ---
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg1/CK (DFF_X1)
|
||||
0.08 0.08 v reg1/Q (DFF_X1)
|
||||
0.00 0.08 v reg2/D (DFF_X1)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.04 9.96 library setup time
|
||||
9.96 data required time
|
||||
---------------------------------------------------------
|
||||
9.96 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.88 slack (MET)
|
||||
|
||||
|
||||
--- report_checks -path_delay max ---
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg1/CK (DFF_X1)
|
||||
0.08 0.08 v reg1/Q (DFF_X1)
|
||||
0.00 0.08 v reg2/D (DFF_X1)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.04 9.96 library setup time
|
||||
9.96 data required time
|
||||
---------------------------------------------------------
|
||||
9.96 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.88 slack (MET)
|
||||
|
||||
|
||||
--- report_checks -path_delay min ---
|
||||
Startpoint: d (input port clocked by clk)
|
||||
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: min
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ input external delay
|
||||
0.00 0.00 ^ d (in)
|
||||
0.00 0.00 ^ reg1/D (DFF_X1)
|
||||
0.00 data arrival time
|
||||
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 clock reconvergence pessimism
|
||||
0.00 ^ reg1/CK (DFF_X1)
|
||||
0.00 0.00 library hold time
|
||||
0.00 data required time
|
||||
---------------------------------------------------------
|
||||
0.00 data required time
|
||||
-0.00 data arrival time
|
||||
---------------------------------------------------------
|
||||
0.00 slack (VIOLATED)
|
||||
|
||||
|
||||
--- report_checks from d to q ---
|
||||
No paths found.
|
||||
--- report_edges -from port d ---
|
||||
d -> reg1/D wire
|
||||
^ -> ^ 0.00:0.00
|
||||
v -> v 0.00:0.00
|
||||
--- report_edges -to port q ---
|
||||
reg2/Q -> q wire
|
||||
^ -> ^ 0.00:0.00
|
||||
v -> v 0.00:0.00
|
||||
--- get_timing_edges -of_objects reg2 ---
|
||||
reg2 timing edges count: 1
|
||||
--- report_slews on d port ---
|
||||
d ^ 0.00:0.00 v 0.00:0.00
|
||||
--- report_slews on q port ---
|
||||
q ^ 0.01:0.01 v 0.00:0.00
|
||||
ALL PASSED
|
||||
@@ -0,0 +1,94 @@
|
||||
# Test graph timing edge queries and disable_timing
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
read_verilog graph_test1.v
|
||||
link_design graph_test1
|
||||
|
||||
create_clock -name clk -period 10 [get_ports clk]
|
||||
set_input_delay -clock clk 0 [get_ports d]
|
||||
set_output_delay -clock clk 0 [get_ports q]
|
||||
|
||||
puts "--- get_timing_edges -of_objects instance ---"
|
||||
set edges [get_timing_edges -of_objects [get_cells reg1]]
|
||||
puts "reg1 timing edges count: [llength $edges]"
|
||||
|
||||
puts "--- get_timing_edges -from/-to on instance ---"
|
||||
set edges_ft [get_timing_edges -from [get_pins reg1/CK] -to [get_pins reg1/Q]]
|
||||
puts "CK->Q edges count: [llength $edges_ft]"
|
||||
|
||||
puts "--- get_timing_edges -from only ---"
|
||||
set edges_from [get_timing_edges -from [get_pins reg1/CK]]
|
||||
puts "edges from CK count: [llength $edges_from]"
|
||||
|
||||
puts "--- get_timing_edges -to only ---"
|
||||
set edges_to [get_timing_edges -to [get_pins reg1/Q]]
|
||||
puts "edges to Q count: [llength $edges_to]"
|
||||
|
||||
puts "--- report_edges -from/-to ---"
|
||||
report_edges -from [get_pins reg1/CK] -to [get_pins reg1/Q]
|
||||
|
||||
puts "--- report_edges -from ---"
|
||||
report_edges -from [get_pins reg1/CK]
|
||||
|
||||
puts "--- report_edges -to ---"
|
||||
report_edges -to [get_pins reg2/D]
|
||||
|
||||
puts "--- report_disabled_edges (baseline) ---"
|
||||
report_disabled_edges
|
||||
|
||||
puts "--- set_disable_timing on instance ---"
|
||||
set_disable_timing [get_cells reg1]
|
||||
puts "PASS: set_disable_timing on reg1"
|
||||
|
||||
puts "--- report_disabled_edges after disable ---"
|
||||
report_disabled_edges
|
||||
|
||||
puts "--- report_checks after disable ---"
|
||||
report_checks
|
||||
|
||||
puts "--- unset_disable_timing on instance ---"
|
||||
unset_disable_timing [get_cells reg1]
|
||||
puts "PASS: unset_disable_timing on reg1"
|
||||
|
||||
puts "--- report_disabled_edges after unset ---"
|
||||
report_disabled_edges
|
||||
|
||||
puts "--- set_disable_timing with -from/-to on lib cell ---"
|
||||
set_disable_timing -from CK -to Q [get_lib_cells NangateOpenCellLibrary/DFF_X1]
|
||||
puts "PASS: set_disable_timing -from CK -to Q"
|
||||
|
||||
puts "--- report_disabled_edges after lib cell disable ---"
|
||||
report_disabled_edges
|
||||
|
||||
puts "--- unset_disable_timing lib cell ---"
|
||||
unset_disable_timing -from CK -to Q [get_lib_cells NangateOpenCellLibrary/DFF_X1]
|
||||
puts "PASS: unset_disable_timing lib cell"
|
||||
|
||||
puts "--- report_checks baseline ---"
|
||||
report_checks
|
||||
|
||||
puts "--- report_checks -path_delay max ---"
|
||||
report_checks -path_delay max
|
||||
|
||||
puts "--- report_checks -path_delay min ---"
|
||||
report_checks -path_delay min
|
||||
|
||||
puts "--- report_checks from d to q ---"
|
||||
report_checks -from [get_ports d] -to [get_ports q]
|
||||
|
||||
puts "--- report_edges -from port d ---"
|
||||
report_edges -from [get_ports d]
|
||||
|
||||
puts "--- report_edges -to port q ---"
|
||||
report_edges -to [get_ports q]
|
||||
|
||||
puts "--- get_timing_edges -of_objects reg2 ---"
|
||||
set edges_r2 [get_timing_edges -of_objects [get_cells reg2]]
|
||||
puts "reg2 timing edges count: [llength $edges_r2]"
|
||||
|
||||
puts "--- report_slews on d port ---"
|
||||
report_slews [get_ports d]
|
||||
|
||||
puts "--- report_slews on q port ---"
|
||||
report_slews [get_ports q]
|
||||
|
||||
puts "ALL PASSED"
|
||||
@@ -0,0 +1,978 @@
|
||||
--- Test 1: baseline edge count ---
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
PASS: baseline timing
|
||||
buf1 edges: 1
|
||||
buf2 edges: 1
|
||||
inv1 edges: 1
|
||||
and1 edges: 1
|
||||
or1 edges: 1
|
||||
nand1 edges: 1
|
||||
nor1 edges: 1
|
||||
PASS: baseline edge queries
|
||||
--- Test 2: chain add/delete ---
|
||||
PASS: 4-stage chain created
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
PASS: timing with chain
|
||||
chain_buf0 edges: 1
|
||||
chain_buf1 edges: 1
|
||||
chain_buf2 edges: 1
|
||||
chain_buf3 edges: 1
|
||||
PASS: chain deleted
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
PASS: timing after chain delete
|
||||
--- Test 3: fan-out/fan-in ---
|
||||
PASS: fanout-3 net created
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
PASS: timing with fanout
|
||||
fo_drv edges: 1
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
PASS: fanout-2 timing
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
PASS: fanout-1 timing
|
||||
PASS: fanout cleanup
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
PASS: timing after fanout cleanup
|
||||
--- Test 4: cell replacement cycle ---
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
PASS: buf1 replacement cycle
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.13 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.13 ^ reg2/D (DFF_X1)
|
||||
1.13 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.13 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.84 slack (MET)
|
||||
|
||||
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
PASS: and1 replacement cycle
|
||||
--- Test 5: register add/delete ---
|
||||
PASS: 3 registers added
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
PASS: timing with added registers
|
||||
PASS: registers deleted
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
PASS: timing after register deletion
|
||||
--- Test 6: slew and edge reports ---
|
||||
d1 ^ 0.10:0.10 v 0.10:0.10
|
||||
d2 ^ 0.10:0.10 v 0.10:0.10
|
||||
d3 ^ 0.10:0.10 v 0.10:0.10
|
||||
clk ^ 0.10:0.10 v 0.10:0.10
|
||||
PASS: port slews
|
||||
buf1/A ^ 0.10:0.10 v 0.10:0.10
|
||||
buf1/Z ^ 0.01:0.01 v 0.01:0.01
|
||||
and1/A1 ^ 0.01:0.01 v 0.01:0.01
|
||||
and1/ZN ^ 0.01:0.01 v 0.01:0.01
|
||||
inv1/A ^ 0.10:0.10 v 0.10:0.10
|
||||
inv1/ZN ^ 0.02:0.02 v 0.02:0.02
|
||||
nand1/ZN ^ 0.01:0.01 v 0.01:0.01
|
||||
nor1/ZN ^ 0.01:0.01 v 0.01:0.01
|
||||
PASS: pin slews
|
||||
A -> Z combinational
|
||||
^ -> ^ 0.03:0.03
|
||||
v -> v 0.06:0.06
|
||||
A1 -> ZN combinational
|
||||
^ -> ^ 0.04:0.04
|
||||
v -> v 0.03:0.03
|
||||
A -> ZN combinational
|
||||
^ -> v 0.01:0.01
|
||||
v -> ^ 0.04:0.04
|
||||
PASS: edge reports
|
||||
--- Test 7: through-pin queries ---
|
||||
Startpoint: d1 (input port clocked by clk)
|
||||
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d1 (in)
|
||||
0.06 1.06 v buf1/Z (BUF_X1)
|
||||
0.03 1.09 v and1/ZN (AND2_X1)
|
||||
0.02 1.11 ^ nor1/ZN (NOR2_X1)
|
||||
0.00 1.11 ^ reg3/D (DFF_X1)
|
||||
1.11 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg3/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.11 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.86 slack (MET)
|
||||
|
||||
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.04 1.09 v and1/ZN (AND2_X1)
|
||||
0.02 1.11 ^ nor1/ZN (NOR2_X1)
|
||||
0.00 1.11 ^ reg3/D (DFF_X1)
|
||||
1.11 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg3/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.11 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
Startpoint: d3 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d3 (in)
|
||||
0.04 1.04 ^ inv1/ZN (INV_X1)
|
||||
0.03 1.07 ^ or1/ZN (OR2_X1)
|
||||
0.01 1.09 v nand1/ZN (NAND2_X1)
|
||||
0.00 1.09 v reg2/D (DFF_X1)
|
||||
1.09 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.04 9.96 library setup time
|
||||
9.96 data required time
|
||||
---------------------------------------------------------
|
||||
9.96 data required time
|
||||
-1.09 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.88 slack (MET)
|
||||
|
||||
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.04 1.09 v and1/ZN (AND2_X1)
|
||||
0.02 1.11 ^ nor1/ZN (NOR2_X1)
|
||||
0.00 1.11 ^ reg3/D (DFF_X1)
|
||||
1.11 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg3/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.11 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
PASS: through-pin queries
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: q1 (output port clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg1/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg1/Q (DFF_X1)
|
||||
0.00 0.08 ^ q1 (out)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
-1.00 9.00 output external delay
|
||||
9.00 data required time
|
||||
---------------------------------------------------------
|
||||
9.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.92 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: q2 (output port clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg2/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg2/Q (DFF_X1)
|
||||
0.00 0.08 ^ q2 (out)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
-1.00 9.00 output external delay
|
||||
9.00 data required time
|
||||
---------------------------------------------------------
|
||||
9.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.92 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg3 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: q3 (output port clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg3/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg3/Q (DFF_X1)
|
||||
0.00 0.08 ^ q3 (out)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
-1.00 9.00 output external delay
|
||||
9.00 data required time
|
||||
---------------------------------------------------------
|
||||
9.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.92 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg4 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: q4 (output port clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg4/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg4/Q (DFF_X1)
|
||||
0.00 0.08 ^ q4 (out)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
-1.00 9.00 output external delay
|
||||
9.00 data required time
|
||||
---------------------------------------------------------
|
||||
9.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.92 slack (MET)
|
||||
|
||||
|
||||
PASS: endpoint queries
|
||||
ALL PASSED
|
||||
@@ -0,0 +1,244 @@
|
||||
# Test graph vertex and edge operations in depth: makeVertex, deleteVertex,
|
||||
# makeEdge, deleteEdge, edge arc queries, bidirectional pin handling,
|
||||
# hasFaninOne, vertex iteration, edge linking.
|
||||
# Targets: Graph.cc uncovered:
|
||||
# deleteVertex (lines 476-504): edge cleanup during vertex deletion
|
||||
# deleteInEdge / deleteOutEdge: linked list manipulation for edges
|
||||
# hasFaninOne: single fanin check
|
||||
# pinDrvrVertex / pinLoadVertex: bidirect driver vertex lookup
|
||||
# gateEdgeArc: arc lookup by rise/fall
|
||||
# makePaths / paths / deletePaths: vertex path management
|
||||
# slew / setSlew: slew value access
|
||||
# makeWireEdgesToPin: create wire edges to a pin
|
||||
# isIsolatedNet: isolated net detection
|
||||
# arcDelay / setArcDelay: edge arc delay access
|
||||
|
||||
source ../../test/helpers.tcl
|
||||
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
read_verilog graph_delete_modify.v
|
||||
link_design graph_delete_modify
|
||||
|
||||
create_clock -name clk -period 10 [get_ports clk]
|
||||
set_input_delay -clock clk 1.0 [get_ports {d1 d2 d3 rst}]
|
||||
set_output_delay -clock clk 1.0 [get_ports {q1 q2 q3 q4}]
|
||||
set_input_transition 0.1 [get_ports {d1 d2 d3 rst clk}]
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 1: Baseline - build graph and verify edges
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Test 1: baseline edge count ---"
|
||||
report_checks
|
||||
puts "PASS: baseline timing"
|
||||
|
||||
# Query edges for each cell
|
||||
foreach cell_name {buf1 buf2 inv1 and1 or1 nand1 nor1} {
|
||||
set edges [get_timing_edges -of_objects [get_cells $cell_name]]
|
||||
puts "$cell_name edges: [llength $edges]"
|
||||
}
|
||||
puts "PASS: baseline edge queries"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 2: Add chain of buffers, verify edges, then delete one by one
|
||||
# Exercises: makeVertex, makeEdge, deleteVertex, deleteEdge,
|
||||
# deleteInEdge, deleteOutEdge
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Test 2: chain add/delete ---"
|
||||
|
||||
# Create 4-stage buffer chain
|
||||
set chain_nets {}
|
||||
set chain_insts {}
|
||||
for {set i 0} {$i < 4} {incr i} {
|
||||
lappend chain_nets [make_net "chain_n$i"]
|
||||
}
|
||||
lappend chain_nets [make_net "chain_n4"]
|
||||
|
||||
for {set i 0} {$i < 4} {incr i} {
|
||||
set inst [make_instance "chain_buf$i" NangateOpenCellLibrary/BUF_X1]
|
||||
lappend chain_insts $inst
|
||||
connect_pin "chain_n$i" "chain_buf$i/A"
|
||||
set j [expr {$i + 1}]
|
||||
connect_pin "chain_n$j" "chain_buf$i/Z"
|
||||
}
|
||||
puts "PASS: 4-stage chain created"
|
||||
|
||||
report_checks
|
||||
puts "PASS: timing with chain"
|
||||
|
||||
# Query chain edges
|
||||
for {set i 0} {$i < 4} {incr i} {
|
||||
set edges [get_timing_edges -of_objects [get_cells "chain_buf$i"]]
|
||||
puts "chain_buf$i edges: [llength $edges]"
|
||||
}
|
||||
|
||||
# Delete chain from end to beginning (exercises reverse cleanup)
|
||||
for {set i 3} {$i >= 0} {incr i -1} {
|
||||
disconnect_pin "chain_n$i" "chain_buf$i/A"
|
||||
set j [expr {$i + 1}]
|
||||
disconnect_pin "chain_n$j" "chain_buf$i/Z"
|
||||
delete_instance "chain_buf$i"
|
||||
}
|
||||
for {set i 0} {$i <= 4} {incr i} {
|
||||
delete_net "chain_n$i"
|
||||
}
|
||||
puts "PASS: chain deleted"
|
||||
|
||||
report_checks
|
||||
puts "PASS: timing after chain delete"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 3: Multiple fan-out and fan-in scenarios
|
||||
# Exercises: makeWireEdgesFromPin with multi-driver nets
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Test 3: fan-out/fan-in ---"
|
||||
|
||||
set fo_net [make_net "fanout_net"]
|
||||
set fo_drv [make_instance "fo_drv" NangateOpenCellLibrary/BUF_X4]
|
||||
set fo_load1 [make_instance "fo_load1" NangateOpenCellLibrary/BUF_X1]
|
||||
set fo_load2 [make_instance "fo_load2" NangateOpenCellLibrary/BUF_X1]
|
||||
set fo_load3 [make_instance "fo_load3" NangateOpenCellLibrary/BUF_X1]
|
||||
|
||||
set fo_in [make_net "fo_in"]
|
||||
connect_pin fo_in fo_drv/A
|
||||
connect_pin fanout_net fo_drv/Z
|
||||
connect_pin fanout_net fo_load1/A
|
||||
connect_pin fanout_net fo_load2/A
|
||||
connect_pin fanout_net fo_load3/A
|
||||
|
||||
puts "PASS: fanout-3 net created"
|
||||
|
||||
report_checks
|
||||
puts "PASS: timing with fanout"
|
||||
|
||||
# Query edge count on fanout driver
|
||||
set drv_edges [get_timing_edges -of_objects [get_cells fo_drv]]
|
||||
puts "fo_drv edges: [llength $drv_edges]"
|
||||
|
||||
# Disconnect loads one by one
|
||||
disconnect_pin fanout_net fo_load3/A
|
||||
report_checks
|
||||
puts "PASS: fanout-2 timing"
|
||||
|
||||
disconnect_pin fanout_net fo_load2/A
|
||||
report_checks
|
||||
puts "PASS: fanout-1 timing"
|
||||
|
||||
# Cleanup
|
||||
disconnect_pin fanout_net fo_load1/A
|
||||
disconnect_pin fanout_net fo_drv/Z
|
||||
disconnect_pin fo_in fo_drv/A
|
||||
delete_instance fo_load1
|
||||
delete_instance fo_load2
|
||||
delete_instance fo_load3
|
||||
delete_instance fo_drv
|
||||
delete_net fanout_net
|
||||
delete_net fo_in
|
||||
puts "PASS: fanout cleanup"
|
||||
|
||||
report_checks
|
||||
puts "PASS: timing after fanout cleanup"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 4: Replace cell multiple times and verify edge rebuild
|
||||
# Exercises: makeInstanceEdges rebuild, timing arc set changes
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Test 4: cell replacement cycle ---"
|
||||
|
||||
# Replace buf1 through several sizes
|
||||
foreach lib_cell {BUF_X1 BUF_X2 BUF_X4 BUF_X8 BUF_X4 BUF_X2 BUF_X1} {
|
||||
replace_cell buf1 "NangateOpenCellLibrary/$lib_cell"
|
||||
report_checks -path_delay max
|
||||
}
|
||||
puts "PASS: buf1 replacement cycle"
|
||||
|
||||
# Replace AND gate
|
||||
foreach lib_cell {AND2_X1 AND2_X2 AND2_X4 AND2_X2 AND2_X1} {
|
||||
replace_cell and1 "NangateOpenCellLibrary/$lib_cell"
|
||||
report_checks
|
||||
}
|
||||
puts "PASS: and1 replacement cycle"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 5: Register add/delete to exercise reg_clk_vertices
|
||||
# Exercises: makeVertex is_reg_clk path, reg_clk_vertices_ insert/erase
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Test 5: register add/delete ---"
|
||||
|
||||
# Add multiple registers
|
||||
for {set i 0} {$i < 3} {incr i} {
|
||||
set rn [make_net "reg_d$i"]
|
||||
set rqn [make_net "reg_q$i"]
|
||||
set ri [make_instance "test_reg$i" NangateOpenCellLibrary/DFF_X1]
|
||||
connect_pin "reg_d$i" "test_reg$i/D"
|
||||
connect_pin "reg_q$i" "test_reg$i/Q"
|
||||
catch {connect_pin clk "test_reg$i/CK"} msg
|
||||
}
|
||||
puts "PASS: 3 registers added"
|
||||
|
||||
report_checks
|
||||
puts "PASS: timing with added registers"
|
||||
|
||||
# Delete the registers
|
||||
for {set i 0} {$i < 3} {incr i} {
|
||||
catch {disconnect_pin clk "test_reg$i/CK"} msg
|
||||
disconnect_pin "reg_d$i" "test_reg$i/D"
|
||||
disconnect_pin "reg_q$i" "test_reg$i/Q"
|
||||
delete_instance "test_reg$i"
|
||||
delete_net "reg_d$i"
|
||||
delete_net "reg_q$i"
|
||||
}
|
||||
puts "PASS: registers deleted"
|
||||
|
||||
report_checks
|
||||
puts "PASS: timing after register deletion"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 6: Slew and timing edge reports
|
||||
# Exercises: slew access, edge arc iteration
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Test 6: slew and edge reports ---"
|
||||
|
||||
report_slews [get_ports d1]
|
||||
report_slews [get_ports d2]
|
||||
report_slews [get_ports d3]
|
||||
report_slews [get_ports clk]
|
||||
puts "PASS: port slews"
|
||||
|
||||
report_slews [get_pins buf1/A]
|
||||
report_slews [get_pins buf1/Z]
|
||||
report_slews [get_pins and1/A1]
|
||||
report_slews [get_pins and1/ZN]
|
||||
report_slews [get_pins inv1/A]
|
||||
report_slews [get_pins inv1/ZN]
|
||||
report_slews [get_pins nand1/ZN]
|
||||
report_slews [get_pins nor1/ZN]
|
||||
puts "PASS: pin slews"
|
||||
|
||||
# Edge reports
|
||||
report_edges -from [get_pins buf1/A] -to [get_pins buf1/Z]
|
||||
report_edges -from [get_pins and1/A1] -to [get_pins and1/ZN]
|
||||
report_edges -from [get_pins inv1/A] -to [get_pins inv1/ZN]
|
||||
puts "PASS: edge reports"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 7: Through-pin and endpoint queries
|
||||
# Exercises: graph traversal paths
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Test 7: through-pin queries ---"
|
||||
|
||||
catch {report_checks -through [get_pins buf1/Z]} msg
|
||||
catch {report_checks -through [get_pins and1/ZN]} msg
|
||||
catch {report_checks -through [get_pins inv1/ZN]} msg
|
||||
catch {report_checks -through [get_pins nand1/ZN]} msg
|
||||
catch {report_checks -through [get_pins nor1/ZN]} msg
|
||||
catch {report_checks -through [get_pins or1/ZN]} msg
|
||||
puts "PASS: through-pin queries"
|
||||
|
||||
# Endpoint
|
||||
catch {report_checks -to [get_ports q1]} msg
|
||||
catch {report_checks -to [get_ports q2]} msg
|
||||
catch {report_checks -to [get_ports q3]} msg
|
||||
catch {report_checks -to [get_ports q4]} msg
|
||||
puts "PASS: endpoint queries"
|
||||
|
||||
puts "ALL PASSED"
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,294 @@
|
||||
# Test graph construction, wire/instance edge creation, delay annotation,
|
||||
# slew queries, and edge removal/modification.
|
||||
# Targets:
|
||||
# Graph.cc: makeGraph, makeVertex, makeWireEdge, makeInstEdge,
|
||||
# removeWireEdge, removeInstEdge, arcDelayAnnotated, wireDelayAnnotated,
|
||||
# slew/delay getters for rise/fall combinations, pinVertices,
|
||||
# pinDrvrVertex, pinLoadVertex, vertexCount, edgeCount,
|
||||
# setConstant, clearConstants, regClkVertices, isRegClk,
|
||||
# widthCheckAnnotation, periodCheckAnnotation, setPeriodCheckAnnotation,
|
||||
# hasDownstreamClkPin, minPulseWidthArc
|
||||
|
||||
source ../../test/helpers.tcl
|
||||
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
read_verilog graph_test3.v
|
||||
link_design graph_test3
|
||||
|
||||
create_clock -name clk1 -period 10 [get_ports clk1]
|
||||
create_clock -name clk2 -period 15 [get_ports clk2]
|
||||
set_input_delay -clock clk1 1.0 [get_ports {d1 d2 d3 d4}]
|
||||
set_output_delay -clock clk1 1.0 [get_ports {q1 q3}]
|
||||
set_output_delay -clock clk2 1.0 [get_ports q2]
|
||||
set_input_transition 0.1 [get_ports {d1 d2 d3 d4 rst clk1 clk2}]
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Baseline timing: triggers makeGraph, all vertex/edge construction
|
||||
#---------------------------------------------------------------
|
||||
puts "--- baseline timing ---"
|
||||
report_checks
|
||||
puts "PASS: baseline"
|
||||
|
||||
report_checks -path_delay min
|
||||
puts "PASS: baseline min"
|
||||
|
||||
report_checks -path_delay max
|
||||
puts "PASS: baseline max"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Query all timing edges: exercises edge iteration
|
||||
#---------------------------------------------------------------
|
||||
puts "--- timing edges per cell ---"
|
||||
foreach cell_name {buf1 buf2 inv1 inv2 and1 or1 nand1 nor1 and2 or2 reg1 reg2 reg3 buf3 buf4} {
|
||||
set edges [get_timing_edges -of_objects [get_cells $cell_name]]
|
||||
puts "$cell_name edges: [llength $edges]"
|
||||
}
|
||||
puts "PASS: edge queries"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Specific edge queries: from/to pins
|
||||
# Exercises arc delay access for all transition combinations
|
||||
#---------------------------------------------------------------
|
||||
puts "--- specific edge queries ---"
|
||||
|
||||
# BUF edges (rise/rise, fall/fall)
|
||||
report_edges -from [get_pins buf1/A] -to [get_pins buf1/Z]
|
||||
puts "PASS: buf1 edges"
|
||||
|
||||
# INV edges (rise/fall, fall/rise)
|
||||
report_edges -from [get_pins inv1/A] -to [get_pins inv1/ZN]
|
||||
puts "PASS: inv1 edges"
|
||||
|
||||
# NAND edges
|
||||
report_edges -from [get_pins nand1/A1] -to [get_pins nand1/ZN]
|
||||
report_edges -from [get_pins nand1/A2] -to [get_pins nand1/ZN]
|
||||
puts "PASS: nand1 edges"
|
||||
|
||||
# NOR edges
|
||||
report_edges -from [get_pins nor1/A1] -to [get_pins nor1/ZN]
|
||||
report_edges -from [get_pins nor1/A2] -to [get_pins nor1/ZN]
|
||||
puts "PASS: nor1 edges"
|
||||
|
||||
# AND2 edges
|
||||
report_edges -from [get_pins and2/A1] -to [get_pins and2/ZN]
|
||||
report_edges -from [get_pins and2/A2] -to [get_pins and2/ZN]
|
||||
puts "PASS: and2 edges"
|
||||
|
||||
# OR2 edges
|
||||
report_edges -from [get_pins or2/A1] -to [get_pins or2/ZN]
|
||||
report_edges -from [get_pins or2/A2] -to [get_pins or2/ZN]
|
||||
puts "PASS: or2 edges"
|
||||
|
||||
# DFF edges (CK->Q)
|
||||
report_edges -from [get_pins reg1/CK] -to [get_pins reg1/Q]
|
||||
report_edges -from [get_pins reg2/CK] -to [get_pins reg2/Q]
|
||||
report_edges -from [get_pins reg3/CK] -to [get_pins reg3/Q]
|
||||
puts "PASS: DFF edges"
|
||||
|
||||
# Wire edges (port to first gate)
|
||||
report_edges -from [get_ports d1]
|
||||
report_edges -from [get_ports d2]
|
||||
report_edges -from [get_ports d3]
|
||||
report_edges -from [get_ports d4]
|
||||
puts "PASS: wire edges from ports"
|
||||
|
||||
# Wire edges to output ports
|
||||
report_edges -to [get_ports q1]
|
||||
report_edges -to [get_ports q2]
|
||||
report_edges -to [get_ports q3]
|
||||
puts "PASS: wire edges to ports"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Slew queries: exercises slew getters in Graph.cc
|
||||
#---------------------------------------------------------------
|
||||
puts "--- slew queries ---"
|
||||
|
||||
# Input port slews
|
||||
report_slews [get_ports d1]
|
||||
report_slews [get_ports d2]
|
||||
report_slews [get_ports d3]
|
||||
report_slews [get_ports d4]
|
||||
report_slews [get_ports clk1]
|
||||
report_slews [get_ports clk2]
|
||||
puts "PASS: input slews"
|
||||
|
||||
# Output port slews
|
||||
report_slews [get_ports q1]
|
||||
report_slews [get_ports q2]
|
||||
report_slews [get_ports q3]
|
||||
puts "PASS: output slews"
|
||||
|
||||
# Internal pin slews
|
||||
report_slews [get_pins buf1/Z]
|
||||
report_slews [get_pins buf2/Z]
|
||||
report_slews [get_pins inv1/ZN]
|
||||
report_slews [get_pins inv2/ZN]
|
||||
report_slews [get_pins and1/ZN]
|
||||
report_slews [get_pins or1/ZN]
|
||||
report_slews [get_pins nand1/ZN]
|
||||
report_slews [get_pins nor1/ZN]
|
||||
report_slews [get_pins and2/ZN]
|
||||
report_slews [get_pins or2/ZN]
|
||||
report_slews [get_pins reg1/Q]
|
||||
report_slews [get_pins reg2/Q]
|
||||
report_slews [get_pins reg3/Q]
|
||||
report_slews [get_pins buf3/Z]
|
||||
report_slews [get_pins buf4/Z]
|
||||
puts "PASS: internal slews"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Network modification: add/remove instances
|
||||
# Exercises graph incremental update paths
|
||||
#---------------------------------------------------------------
|
||||
puts "--- network modification ---"
|
||||
|
||||
# Add instance and wire
|
||||
set new_buf [make_instance extra_buf NangateOpenCellLibrary/BUF_X1]
|
||||
set new_net [make_net extra_net]
|
||||
set new_net2 [make_net extra_net2]
|
||||
connect_pin extra_net extra_buf/A
|
||||
connect_pin extra_net2 extra_buf/Z
|
||||
puts "PASS: add instance"
|
||||
|
||||
# Timing after addition (exercises incremental graph update)
|
||||
report_checks
|
||||
puts "PASS: timing after add"
|
||||
|
||||
# Disconnect and remove
|
||||
disconnect_pin extra_net extra_buf/A
|
||||
disconnect_pin extra_net2 extra_buf/Z
|
||||
delete_instance extra_buf
|
||||
delete_net extra_net
|
||||
delete_net extra_net2
|
||||
puts "PASS: cleanup"
|
||||
|
||||
report_checks
|
||||
puts "PASS: timing after cleanup"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Replace cell and verify edge update
|
||||
#---------------------------------------------------------------
|
||||
puts "--- replace cell ---"
|
||||
|
||||
replace_cell buf1 NangateOpenCellLibrary/BUF_X4
|
||||
report_checks
|
||||
report_edges -from [get_pins buf1/A] -to [get_pins buf1/Z]
|
||||
puts "PASS: buf1->BUF_X4"
|
||||
|
||||
replace_cell buf1 NangateOpenCellLibrary/BUF_X1
|
||||
report_checks
|
||||
puts "PASS: buf1 restored"
|
||||
|
||||
replace_cell inv1 NangateOpenCellLibrary/INV_X2
|
||||
report_checks
|
||||
puts "PASS: inv1->INV_X2"
|
||||
|
||||
replace_cell inv1 NangateOpenCellLibrary/INV_X1
|
||||
report_checks
|
||||
puts "PASS: inv1 restored"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Disable/enable timing on edges
|
||||
# Exercises graph edge disable traversal
|
||||
#---------------------------------------------------------------
|
||||
puts "--- disable/enable timing ---"
|
||||
|
||||
set_disable_timing [get_cells buf1]
|
||||
report_checks
|
||||
puts "PASS: disable buf1"
|
||||
|
||||
set_disable_timing [get_cells inv1]
|
||||
report_checks
|
||||
puts "PASS: disable inv1"
|
||||
|
||||
set_disable_timing [get_cells nand1]
|
||||
report_checks
|
||||
puts "PASS: disable nand1"
|
||||
|
||||
unset_disable_timing [get_cells buf1]
|
||||
unset_disable_timing [get_cells inv1]
|
||||
unset_disable_timing [get_cells nand1]
|
||||
report_checks
|
||||
puts "PASS: re-enable all"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Case analysis: exercises setConstant, clearConstants
|
||||
#---------------------------------------------------------------
|
||||
puts "--- case analysis ---"
|
||||
|
||||
set_case_analysis 1 [get_ports rst]
|
||||
report_checks
|
||||
puts "PASS: rst=1"
|
||||
|
||||
set_case_analysis 0 [get_ports rst]
|
||||
report_checks
|
||||
puts "PASS: rst=0"
|
||||
|
||||
unset_case_analysis [get_ports rst]
|
||||
report_checks
|
||||
puts "PASS: rst unset"
|
||||
|
||||
set_case_analysis 1 [get_ports d1]
|
||||
report_checks
|
||||
puts "PASS: d1=1"
|
||||
|
||||
set_case_analysis 0 [get_ports d3]
|
||||
report_checks
|
||||
puts "PASS: d3=0"
|
||||
|
||||
unset_case_analysis [get_ports d1]
|
||||
unset_case_analysis [get_ports d3]
|
||||
report_checks
|
||||
puts "PASS: all unset"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Load changes trigger delay recomputation on graph edges
|
||||
#---------------------------------------------------------------
|
||||
puts "--- load changes ---"
|
||||
|
||||
set_load 0.01 [get_ports q1]
|
||||
report_checks
|
||||
puts "PASS: q1 load=0.01"
|
||||
|
||||
set_load 0.05 [get_ports q2]
|
||||
report_checks
|
||||
puts "PASS: q2 load=0.05"
|
||||
|
||||
set_load 0.1 [get_ports q3]
|
||||
report_checks
|
||||
puts "PASS: q3 load=0.1"
|
||||
|
||||
set_load 0 [get_ports q1]
|
||||
set_load 0 [get_ports q2]
|
||||
set_load 0 [get_ports q3]
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Through pin paths exercise reconvergent graph traversal
|
||||
#---------------------------------------------------------------
|
||||
puts "--- through pin queries ---"
|
||||
|
||||
catch {report_checks -through [get_pins nand1/ZN]} msg
|
||||
puts "through nand1: done"
|
||||
|
||||
catch {report_checks -through [get_pins nor1/ZN]} msg
|
||||
puts "through nor1: done"
|
||||
|
||||
catch {report_checks -through [get_pins and2/ZN]} msg
|
||||
puts "through and2: done"
|
||||
|
||||
catch {report_checks -through [get_pins or2/ZN]} msg
|
||||
puts "through or2: done"
|
||||
|
||||
puts "PASS: through pin queries"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# report_check_types exercises check edge categorization
|
||||
#---------------------------------------------------------------
|
||||
puts "--- report_check_types ---"
|
||||
report_check_types -max_delay -verbose
|
||||
puts "PASS: check_types max"
|
||||
|
||||
report_check_types -min_delay -verbose
|
||||
puts "PASS: check_types min"
|
||||
|
||||
puts "ALL PASSED"
|
||||
Symlink
+1
@@ -0,0 +1 @@
|
||||
../../test/regression
|
||||
Reference in New Issue
Block a user