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OpenSTA
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Renamed tests to match prlx repo, updated test to repro error without my fix 

Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>
This commit is contained in:
dsengupta0628 2026-02-25 20:33:15 +00:00
parent db46579a39
commit cd6f564caf
5 changed files with 11 additions and 13 deletions
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8
network/VerilogNamespace.cc
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@ -91,8 +91,8 @@ staToVerilog(const char *sta_name)
escaped = true; escaped = true;
char next_ch = s[1]; char next_ch = s[1];
if (next_ch == verilog_escape) { if (next_ch == verilog_escape) {
escaped_name += next_ch; escaped_name += next_ch;
s++; s++;
} }
} }
else { else {
@ -126,8 +126,8 @@ staToVerilog2(const char *sta_name)
escaped = true; escaped = true;
char next_ch = s[1]; char next_ch = s[1];
if (next_ch == verilog_escape) { if (next_ch == verilog_escape) {
escaped_name += next_ch; escaped_name += next_ch;
s++; s++;
} }
} }
else { else {

2
test/regression_vars.tcl
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@ -163,9 +163,9 @@ record_public_tests {
report_json1 report_json1
report_json2 report_json2
suppress_msg suppress_msg
test_write_verilog_escape
verilog_attribute verilog_attribute
verilog_specify verilog_specify
verilog_write_escape
} }
define_test_group fast [group_tests all] define_test_group fast [group_tests all]

0
test/test_write_verilog_escape.ok → test/verilog_write_escape.ok
View File

12
test/test_write_verilog_escape.tcl → test/verilog_write_escape.tcl
View File

@ -1,14 +1,14 @@
# Check if "h1\x" and \Y[2:1] are correctly processed from input to output of Verilog # Check if "h1\x" and \Y[2:1] are correctly processed from input to output of Verilog
read_liberty gf180mcu_sram.lib.gz read_liberty gf180mcu_sram.lib.gz
read_liberty asap7_small.lib.gz read_liberty asap7_small.lib.gz
read_verilog test_write_verilog_escape.v read_verilog verilog_write_escape.v
link_design multi_sink link_design multi_sink
write_verilog test_write_verilog_escape_out.v set output_file "verilog_write_escape_out.v"
set input_file "test_write_verilog_escape_out.v" write_verilog $output_file
set fp [open $input_file r] set fp [open $output_file r]
while {[gets $fp line] >= 0} { while {[gets $fp line] >= 0} {
puts $line puts $line
} }
close $fp close $fp
file delete "test_write_verilog_escape_out.v" read_verilog $output_file
file delete $output_file

2
test/test_write_verilog_escape.v → test/verilog_write_escape.v
View File

@ -1,4 +1,3 @@
module \multi_sink (clk); module \multi_sink (clk);
input clk; input clk;
wire \alu_adder_result_ex[0] ; wire \alu_adder_result_ex[0] ;
@ -12,4 +11,3 @@ module \hier_block (childclk, \Y[2:1] );
BUFx2_ASAP7_75t_R \abuf_$100 (.A(childclk)); BUFx2_ASAP7_75t_R \abuf_$100 (.A(childclk));
BUFx2_ASAP7_75t_R \ff0/name (.A(childclk)); BUFx2_ASAP7_75t_R \ff0/name (.A(childclk));
endmodule // hier_block1 endmodule // hier_block1