From cc1bd6b5ab91fc9547baac75f1b619497433ebdc Mon Sep 17 00:00:00 2001 From: James Cherry Date: Mon, 11 Nov 2019 15:30:19 -0700 Subject: [PATCH] TransRiseFall -> RiseFall --- dcalc/ArcDelayCalc.hh | 4 +- dcalc/ArnoldiDelayCalc.cc | 28 +- dcalc/ArnoldiReduce.cc | 8 +- dcalc/ArnoldiReduce.hh | 4 +- dcalc/DelayCalc.tcl | 6 +- dcalc/DmpCeff.cc | 38 +-- dcalc/DmpCeff.hh | 2 +- dcalc/DmpDelayCalc.cc | 28 +- dcalc/GraphDelayCalc.cc | 10 +- dcalc/GraphDelayCalc.hh | 10 +- dcalc/GraphDelayCalc1.cc | 272 +++++++++---------- dcalc/GraphDelayCalc1.hh | 26 +- dcalc/LumpedCapDelayCalc.cc | 30 +-- dcalc/LumpedCapDelayCalc.hh | 6 +- dcalc/RCDelayCalc.cc | 10 +- dcalc/RCDelayCalc.hh | 2 +- dcalc/SimpleRCDelayCalc.cc | 10 +- dcalc/SimpleRCDelayCalc.hh | 2 +- dcalc/UnitDelayCalc.cc | 4 +- dcalc/UnitDelayCalc.hh | 4 +- doc/ApiChanges.txt | 3 + graph/Graph.cc | 54 ++-- graph/Graph.hh | 26 +- graph/GraphClass.hh | 2 +- liberty/InternalPower.cc | 16 +- liberty/InternalPower.hh | 10 +- liberty/Liberty.cc | 190 +++++++------- liberty/Liberty.hh | 94 +++---- liberty/LibertyBuilder.cc | 204 +++++++-------- liberty/LibertyBuilder.hh | 14 +- liberty/LibertyClass.hh | 4 +- liberty/LibertyReader.cc | 376 +++++++++++++------------- liberty/LibertyReaderPvt.hh | 82 +++--- liberty/TableModel.cc | 4 +- liberty/TableModel.hh | 4 +- liberty/TimingArc.cc | 78 +++--- liberty/TimingArc.hh | 28 +- liberty/Transition.cc | 136 +++++----- liberty/Transition.hh | 94 +++---- parasitics/ConcreteParasitics.cc | 88 +++---- parasitics/ConcreteParasitics.hh | 12 +- parasitics/ConcreteParasiticsPvt.hh | 4 +- parasitics/EstimateParasitics.cc | 22 +- parasitics/EstimateParasitics.hh | 8 +- parasitics/NullParasitics.cc | 10 +- parasitics/NullParasitics.hh | 10 +- parasitics/Parasitics.hh | 10 +- parasitics/Parasitics.i | 18 +- parasitics/ReduceParasitics.cc | 38 +-- parasitics/SpefReader.cc | 4 +- sdc/Clock.cc | 96 +++---- sdc/Clock.hh | 40 +-- sdc/ClockInsertion.cc | 16 +- sdc/ClockInsertion.hh | 8 +- sdc/ClockLatency.cc | 16 +- sdc/ClockLatency.hh | 8 +- sdc/DataCheck.cc | 28 +- sdc/DataCheck.hh | 14 +- sdc/DeratingFactors.cc | 24 +- sdc/DeratingFactors.hh | 12 +- sdc/ExceptionPath.cc | 142 +++++----- sdc/ExceptionPath.hh | 39 +-- sdc/InputDrive.cc | 60 ++--- sdc/InputDrive.hh | 24 +- sdc/PortDelay.cc | 4 +- sdc/PortDelay.hh | 2 +- sdc/PortExtCap.cc | 16 +- sdc/PortExtCap.hh | 8 +- sdc/RiseFallMinMax.cc | 114 ++++---- sdc/RiseFallMinMax.hh | 22 +- sdc/RiseFallValues.cc | 44 ++-- sdc/RiseFallValues.hh | 14 +- sdc/Sdc.cc | 392 ++++++++++++++-------------- sdc/Sdc.hh | 172 ++++++------ sdc/WriteSdc.cc | 182 ++++++------- sdc/WriteSdcPvt.hh | 10 +- sdf/ReportAnnotation.cc | 4 +- sdf/SdfReader.cc | 6 +- sdf/SdfWriter.cc | 98 +++---- search/CheckMaxSkews.cc | 8 +- search/CheckMinPulseWidths.cc | 20 +- search/CheckMinPulseWidths.hh | 4 +- search/CheckSlewLimits.cc | 56 ++-- search/CheckSlewLimits.hh | 12 +- search/ClkInfo.cc | 6 +- search/ClkInfo.hh | 6 +- search/ClkSkew.cc | 30 +-- search/ClkSkew.hh | 6 +- search/FindRegister.cc | 88 +++---- search/FindRegister.hh | 10 +- search/GatedClk.cc | 14 +- search/GatedClk.hh | 2 +- search/Genclks.cc | 46 ++-- search/Genclks.hh | 10 +- search/Latches.cc | 44 ++-- search/Latches.hh | 4 +- search/Path.cc | 6 +- search/Path.hh | 4 +- search/PathEnd.cc | 26 +- search/PathEnd.hh | 6 +- search/PathEnum.cc | 18 +- search/PathEnumed.cc | 2 +- search/PathEnumed.hh | 2 +- search/PathRef.cc | 8 +- search/PathRef.hh | 4 +- search/PathVertex.cc | 32 +-- search/PathVertex.hh | 10 +- search/Power.cc | 12 +- search/Property.cc | 84 +++--- search/ReportPath.cc | 250 +++++++++--------- search/ReportPath.hh | 46 ++-- search/Search.cc | 302 ++++++++++----------- search/Search.hh | 56 ++-- search/SearchPred.cc | 39 +-- search/SearchPred.hh | 4 +- search/Sta.cc | 330 +++++++++++------------ search/Sta.hh | 148 +++++------ search/Tag.cc | 12 +- search/Tag.hh | 6 +- search/TagGroup.cc | 2 +- search/VisitPathEnds.cc | 106 ++++---- search/VisitPathEnds.hh | 24 +- search/VisitPathGroupVertices.cc | 10 +- search/WritePathSpice.cc | 328 +++++++++++------------ tcl/Cmds.tcl | 88 +++---- tcl/Sdc.tcl | 72 ++--- tcl/Search.tcl | 18 +- tcl/Sta.tcl | 12 +- tcl/StaTcl.i | 314 +++++++++++----------- 129 files changed, 3258 insertions(+), 3251 deletions(-) diff --git a/dcalc/ArcDelayCalc.hh b/dcalc/ArcDelayCalc.hh index e9997a01..5113cedd 100644 --- a/dcalc/ArcDelayCalc.hh +++ b/dcalc/ArcDelayCalc.hh @@ -53,14 +53,14 @@ public: // Find the parasitic for drvr_pin that is acceptable to the delay // calculator by probing parasitics_. virtual Parasitic *findParasitic(const Pin *drvr_pin, - const TransRiseFall *tr, + const RiseFall *rf, const DcalcAnalysisPt *dcalc_ap) = 0; // Find the wire delays and slews for an input port without a driving cell. // This call primarily initializes the load delay/slew iterator. virtual void inputPortDelay(const Pin *port_pin, float in_slew, - const TransRiseFall *tr, + const RiseFall *rf, Parasitic *parasitic, const DcalcAnalysisPt *dcalc_ap) = 0; diff --git a/dcalc/ArnoldiDelayCalc.cc b/dcalc/ArnoldiDelayCalc.cc index a8ab1868..7b12749b 100644 --- a/dcalc/ArnoldiDelayCalc.cc +++ b/dcalc/ArnoldiDelayCalc.cc @@ -114,7 +114,7 @@ public: virtual ~ArnoldiDelayCalc(); virtual ArcDelayCalc *copy(); virtual Parasitic *findParasitic(const Pin *drvr_pin, - const TransRiseFall *tr, + const RiseFall *rf, const DcalcAnalysisPt *dcalc_ap); virtual void gateDelay(const LibertyCell *drvr_cell, TimingArc *arc, @@ -134,7 +134,7 @@ public: Slew &load_slew); virtual void inputPortDelay(const Pin *port_pin, float in_slew, - const TransRiseFall *tr, + const RiseFall *rf, Parasitic *parasitic, const DcalcAnalysisPt *dcalc_ap); virtual void reportGateDelay(const LibertyCell *drvr_cell, @@ -260,7 +260,7 @@ ArnoldiDelayCalc::~ArnoldiDelayCalc() Parasitic * ArnoldiDelayCalc::findParasitic(const Pin *drvr_pin, - const TransRiseFall *drvr_tr, + const RiseFall *drvr_rf, const DcalcAnalysisPt *dcalc_ap) { // set_load has precidence over parasitics. @@ -278,7 +278,7 @@ ArnoldiDelayCalc::findParasitic(const Pin *drvr_pin, if (wireload) { float pin_cap, wire_cap, fanout; bool has_wire_cap; - graph_delay_calc_->netCaps(drvr_pin, drvr_tr, dcalc_ap, + graph_delay_calc_->netCaps(drvr_pin, drvr_rf, dcalc_ap, pin_cap, wire_cap, fanout, has_wire_cap); parasitic_network = parasitics_->makeWireloadNetwork(drvr_pin, wireload, fanout, op_cond, @@ -292,7 +292,7 @@ ArnoldiDelayCalc::findParasitic(const Pin *drvr_pin, reduce_->reduceToArnoldi(parasitic_network, drvr_pin, parasitic_ap->couplingCapFactor(), - drvr_tr, op_cond, corner, + drvr_rf, op_cond, corner, cnst_min_max, parasitic_ap); if (delete_parasitic_network) { Net *net = network_->net(drvr_pin); @@ -308,11 +308,11 @@ ArnoldiDelayCalc::findParasitic(const Pin *drvr_pin, void ArnoldiDelayCalc::inputPortDelay(const Pin *drvr_pin, float in_slew, - const TransRiseFall *tr, + const RiseFall *rf, Parasitic *parasitic, const DcalcAnalysisPt *dcalc_ap) { - RCDelayCalc::inputPortDelay(drvr_pin, in_slew, tr, parasitic, dcalc_ap); + RCDelayCalc::inputPortDelay(drvr_pin, in_slew, rf, parasitic, dcalc_ap); rcmodel_ = nullptr; _delayV[0] = 0.0; _slewV[0] = in_slew; @@ -332,9 +332,9 @@ ArnoldiDelayCalc::inputPortDelay(const Pin *drvr_pin, pin_n_ = rcmodel_->n; double slew_derate = drvr_library_->slewDerateFromLibrary(); - double lo_thresh = drvr_library_->slewLowerThreshold(drvr_tr_); - double hi_thresh = drvr_library_->slewUpperThreshold(drvr_tr_); - bool rising = (drvr_tr_ == TransRiseFall::rise()); + double lo_thresh = drvr_library_->slewLowerThreshold(drvr_rf_); + double hi_thresh = drvr_library_->slewUpperThreshold(drvr_rf_); + bool rising = (drvr_rf_ == RiseFall::rise()); delay_work_set_thresholds(delay_work_, lo_thresh, hi_thresh, rising, slew_derate); delay_c *c = delay_work_->c; @@ -362,7 +362,7 @@ ArnoldiDelayCalc::gateDelay(const LibertyCell *drvr_cell, Slew &drvr_slew) { input_port_ = false; - drvr_tr_ = arc->toTrans()->asRiseFall(); + drvr_rf_ = arc->toTrans()->asRiseFall(); drvr_library_ = drvr_cell->libertyLibrary(); drvr_parasitic_ = drvr_parasitic; ConcreteParasitic *drvr_cparasitic = @@ -403,9 +403,9 @@ ArnoldiDelayCalc::gateDelaySlew(const LibertyCell *drvr_cell, pin_n_ = rcmodel_->n; if (table_model) { double slew_derate = drvr_library_->slewDerateFromLibrary(); - double lo_thresh = drvr_library_->slewLowerThreshold(drvr_tr_); - double hi_thresh = drvr_library_->slewUpperThreshold(drvr_tr_); - bool rising = (drvr_tr_ == TransRiseFall::rise()); + double lo_thresh = drvr_library_->slewLowerThreshold(drvr_rf_); + double hi_thresh = drvr_library_->slewUpperThreshold(drvr_rf_); + bool rising = (drvr_rf_ == RiseFall::rise()); delay_work_set_thresholds(delay_work_, lo_thresh, hi_thresh, rising, slew_derate); if (rcmodel_->order > 0) { diff --git a/dcalc/ArnoldiReduce.cc b/dcalc/ArnoldiReduce.cc index d018afc9..a3a21289 100644 --- a/dcalc/ArnoldiReduce.cc +++ b/dcalc/ArnoldiReduce.cc @@ -139,7 +139,7 @@ Parasitic * ArnoldiReduce::reduceToArnoldi(Parasitic *parasitic, const Pin *drvr_pin, float coupling_cap_factor, - const TransRiseFall *tr, + const RiseFall *rf, const OperatingConditions *op_cond, const Corner *corner, const MinMax *cnst_min_max, @@ -148,7 +148,7 @@ ArnoldiReduce::reduceToArnoldi(Parasitic *parasitic, parasitic_network_ = reinterpret_cast(parasitic); drvr_pin_ = drvr_pin; coupling_cap_factor_ = coupling_cap_factor; - tr_ = tr; + rf_ = rf; op_cond_ = op_cond; corner_ = corner; cnst_min_max_ = cnst_min_max; @@ -449,9 +449,9 @@ ArnoldiReduce::pinCapacitance(ParasiticNode *node) Port *port = network_->port(pin); LibertyPort *lib_port = network_->libertyPort(port); if (lib_port) - pin_cap = sdc_->pinCapacitance(pin,tr_, op_cond_, corner_, cnst_min_max_); + pin_cap = sdc_->pinCapacitance(pin,rf_, op_cond_, corner_, cnst_min_max_); else if (network_->isTopLevelPort(pin)) - pin_cap = sdc_->portExtCap(port, tr_, cnst_min_max_); + pin_cap = sdc_->portExtCap(port, rf_, cnst_min_max_); } return pin_cap; } diff --git a/dcalc/ArnoldiReduce.hh b/dcalc/ArnoldiReduce.hh index 8b286716..9c86d59c 100644 --- a/dcalc/ArnoldiReduce.hh +++ b/dcalc/ArnoldiReduce.hh @@ -44,7 +44,7 @@ public: Parasitic *reduceToArnoldi(Parasitic *parasitic, const Pin *drvr_pin, float coupling_cap_factor, - const TransRiseFall *tr, + const RiseFall *rf, const OperatingConditions *op_cond, const Corner *corner, const MinMax *cnst_min_max, @@ -66,7 +66,7 @@ protected: ConcreteParasiticNetwork *parasitic_network_; const Pin *drvr_pin_; float coupling_cap_factor_; - const TransRiseFall *tr_; + const RiseFall *rf_; const OperatingConditions *op_cond_; const Corner *corner_; const MinMax *cnst_min_max_; diff --git a/dcalc/DelayCalc.tcl b/dcalc/DelayCalc.tcl index beaca5bc..7cc5c51a 100644 --- a/dcalc/DelayCalc.tcl +++ b/dcalc/DelayCalc.tcl @@ -91,10 +91,10 @@ proc report_edge_dcalc { edge corner min_max digits } { while {[$arc_iter has_next]} { set arc [$arc_iter next] set from [get_name [$from_pin port]] - set from_tr [$arc from_trans] + set from_rf [$arc from_trans] set to [get_name [$to_pin port]] - set to_tr [$arc to_trans] - puts "$from $from_tr -> $to $to_tr" + set to_rf [$arc to_trans] + puts "$from $from_rf -> $to $to_rf" puts -nonewline [report_delay_calc_cmd $edge $arc $corner $min_max $digits] if { [$edge delay_annotated $arc $corner $min_max] } { set delay [$edge arc_delay $arc $corner $min_max] diff --git a/dcalc/DmpCeff.cc b/dcalc/DmpCeff.cc index 7ca8acf8..d293e6fd 100644 --- a/dcalc/DmpCeff.cc +++ b/dcalc/DmpCeff.cc @@ -135,7 +135,7 @@ public: const LibertyCell *drvr_cell, const Pvt *pvt, const GateTableModel *gate_model, - const TransRiseFall *tr, + const RiseFall *rf, double rd, double in_slew, float related_out_cap, @@ -166,7 +166,7 @@ protected: const LibertyCell *drvr_cell, const Pvt *pvt, const GateTableModel *gate_model, - const TransRiseFall *tr, + const RiseFall *rf, double rd, double in_slew, float related_out_cap); @@ -302,7 +302,7 @@ DmpAlg::init(const LibertyLibrary *drvr_library, const LibertyCell *drvr_cell, const Pvt *pvt, const GateTableModel *gate_model, - const TransRiseFall *tr, + const RiseFall *rf, double rd, double in_slew, float related_out_cap) @@ -315,9 +315,9 @@ DmpAlg::init(const LibertyLibrary *drvr_library, in_slew_ = in_slew; related_out_cap_ = related_out_cap; driver_valid_ = false; - vth_ = drvr_library->outputThreshold(tr); - vl_ = drvr_library->slewLowerThreshold(tr); - vh_ = drvr_library->slewUpperThreshold(tr); + vth_ = drvr_library->outputThreshold(rf); + vl_ = drvr_library->slewLowerThreshold(rf); + vh_ = drvr_library->slewUpperThreshold(rf); slew_derate_ = drvr_library->slewDerateFromLibrary(); } @@ -698,7 +698,7 @@ public: const LibertyCell *drvr_cell, const Pvt *pvt, const GateTableModel *gate_model, - const TransRiseFall *tr, + const RiseFall *rf, double rd, double in_slew, float related_out_cap, @@ -731,7 +731,7 @@ DmpCap::init(const LibertyLibrary *drvr_library, const LibertyCell *drvr_cell, const Pvt *pvt, const GateTableModel *gate_model, - const TransRiseFall *tr, + const RiseFall *rf, double rd, double in_slew, float related_out_cap, @@ -740,7 +740,7 @@ DmpCap::init(const LibertyLibrary *drvr_library, double c1) { debugPrint0(debug_, "delay_calc", 3, "Using DMP cap\n"); - DmpAlg::init(drvr_library, drvr_cell, pvt, gate_model, tr, + DmpAlg::init(drvr_library, drvr_cell, pvt, gate_model, rf, rd, in_slew, related_out_cap); ceff_ = c1 + c2; } @@ -813,7 +813,7 @@ public: const LibertyCell *drvr_cell, const Pvt *pvt, const GateTableModel *gate_model, - const TransRiseFall *tr, + const RiseFall *rf, double rd, double in_slew, float related_out_cap, @@ -880,7 +880,7 @@ DmpPi::init(const LibertyLibrary *drvr_library, const LibertyCell *drvr_cell, const Pvt *pvt, const GateTableModel *gate_model, - const TransRiseFall *tr, + const RiseFall *rf, double rd, double in_slew, float related_out_cap, @@ -889,7 +889,7 @@ DmpPi::init(const LibertyLibrary *drvr_library, double c1) { debugPrint0(debug_, "delay_calc", 3, "Using DMP Pi\n"); - DmpAlg::init(drvr_library, drvr_cell, pvt, gate_model, tr, rd, + DmpAlg::init(drvr_library, drvr_cell, pvt, gate_model, rf, rd, in_slew, related_out_cap); c1_ = c1; c2_ = c2; @@ -1143,7 +1143,7 @@ public: const LibertyCell *drvr_cell, const Pvt *pvt, const GateTableModel *gate_model, - const TransRiseFall *tr, + const RiseFall *rf, double rd, double in_slew, float related_out_cap, @@ -1190,7 +1190,7 @@ DmpZeroC2::init(const LibertyLibrary *drvr_library, const LibertyCell *drvr_cell, const Pvt *pvt, const GateTableModel *gate_model, - const TransRiseFall *tr, + const RiseFall *rf, double rd, double in_slew, float related_out_cap, @@ -1199,7 +1199,7 @@ DmpZeroC2::init(const LibertyLibrary *drvr_library, double c1) { debugPrint0(debug_, "delay_calc", 3, "Using DMP C2=0\n"); - DmpAlg::init(drvr_library, drvr_cell, pvt, gate_model, tr, rd, + DmpAlg::init(drvr_library, drvr_cell, pvt, gate_model, rf, rd, in_slew, related_out_cap); ceff_ = c1_ = c1; rpi_ = rpi; @@ -1566,13 +1566,13 @@ DmpCeffDelayCalc::~DmpCeffDelayCalc() void DmpCeffDelayCalc::inputPortDelay(const Pin *port_pin, float in_slew, - const TransRiseFall *tr, + const RiseFall *rf, Parasitic *parasitic, const DcalcAnalysisPt *dcalc_ap) { dmp_alg_ = nullptr; input_port_ = true; - RCDelayCalc::inputPortDelay(port_pin, in_slew, tr, parasitic, dcalc_ap); + RCDelayCalc::inputPortDelay(port_pin, in_slew, rf, parasitic, dcalc_ap); } void @@ -1589,7 +1589,7 @@ DmpCeffDelayCalc::gateDelay(const LibertyCell *drvr_cell, Slew &drvr_slew) { input_port_ = false; - drvr_tr_ = arc->toTrans()->asRiseFall(); + drvr_rf_ = arc->toTrans()->asRiseFall(); drvr_library_ = drvr_cell->libertyLibrary(); drvr_parasitic_ = drvr_parasitic; GateTimingModel *model = gateModel(arc, dcalc_ap); @@ -1649,7 +1649,7 @@ DmpCeffDelayCalc::setCeffAlgorithm(const LibertyLibrary *drvr_library, // The full monty. dmp_alg_ = dmp_pi_; dmp_alg_->init(drvr_library, drvr_cell, pvt, gate_model, - drvr_tr_, rd, in_slew, related_out_cap, c2, rpi, c1); + drvr_rf_, rd, in_slew, related_out_cap, c2, rpi, c1); debugPrint6(debug_, "delay_calc", 3, " DMP in_slew = %s c2 = %s rpi = %s c1 = %s Rd = %s (%s alg)\n", units_->timeUnit()->asString(in_slew), diff --git a/dcalc/DmpCeff.hh b/dcalc/DmpCeff.hh index 95062d48..71a8b77a 100644 --- a/dcalc/DmpCeff.hh +++ b/dcalc/DmpCeff.hh @@ -36,7 +36,7 @@ public: virtual ~DmpCeffDelayCalc(); virtual void inputPortDelay(const Pin *port_pin, float in_slew, - const TransRiseFall *tr, + const RiseFall *rf, Parasitic *parasitic, const DcalcAnalysisPt *dcalc_ap); virtual void gateDelay(const LibertyCell *drvr_cell, diff --git a/dcalc/DmpDelayCalc.cc b/dcalc/DmpDelayCalc.cc index dcb85183..b7c1deb4 100644 --- a/dcalc/DmpDelayCalc.cc +++ b/dcalc/DmpDelayCalc.cc @@ -127,11 +127,11 @@ public: DmpCeffTwoPoleDelayCalc(StaState *sta); virtual ArcDelayCalc *copy(); virtual Parasitic *findParasitic(const Pin *drvr_pin, - const TransRiseFall *tr, + const RiseFall *rf, const DcalcAnalysisPt *dcalc_ap); virtual void inputPortDelay(const Pin *port_pin, float in_slew, - const TransRiseFall *tr, + const RiseFall *rf, Parasitic *parasitic, const DcalcAnalysisPt *dcalc_ap); virtual void gateDelay(const LibertyCell *drvr_cell, @@ -197,7 +197,7 @@ DmpCeffTwoPoleDelayCalc::copy() Parasitic * DmpCeffTwoPoleDelayCalc::findParasitic(const Pin *drvr_pin, - const TransRiseFall *tr, + const RiseFall *rf, const DcalcAnalysisPt *dcalc_ap) { // set_load has precidence over parasitics. @@ -206,12 +206,12 @@ DmpCeffTwoPoleDelayCalc::findParasitic(const Pin *drvr_pin, const ParasiticAnalysisPt *parasitic_ap = dcalc_ap->parasiticAnalysisPt(); if (parasitics_->haveParasitics()) { // Prefer PiPoleResidue. - parasitic = parasitics_->findPiPoleResidue(drvr_pin, tr, + parasitic = parasitics_->findPiPoleResidue(drvr_pin, rf, parasitic_ap); if (parasitic) return parasitic; - parasitic = parasitics_->findPiElmore(drvr_pin, tr, parasitic_ap); + parasitic = parasitics_->findPiElmore(drvr_pin, rf, parasitic_ap); if (parasitic) return parasitic; @@ -223,7 +223,7 @@ DmpCeffTwoPoleDelayCalc::findParasitic(const Pin *drvr_pin, dcalc_ap->corner(), dcalc_ap->constraintMinMax(), parasitic_ap); - parasitic = parasitics_->findPiPoleResidue(drvr_pin, tr, parasitic_ap); + parasitic = parasitics_->findPiPoleResidue(drvr_pin, rf, parasitic_ap); reduced_parasitic_drvrs_.push_back(drvr_pin); return parasitic; } @@ -234,9 +234,9 @@ DmpCeffTwoPoleDelayCalc::findParasitic(const Pin *drvr_pin, if (wireload) { float pin_cap, wire_cap, fanout; bool has_wire_cap; - graph_delay_calc_->netCaps(drvr_pin, tr, dcalc_ap, + graph_delay_calc_->netCaps(drvr_pin, rf, dcalc_ap, pin_cap, wire_cap, fanout, has_wire_cap); - parasitic = parasitics_->estimatePiElmore(drvr_pin, tr, wireload, + parasitic = parasitics_->estimatePiElmore(drvr_pin, rf, wireload, fanout, pin_cap, dcalc_ap->operatingConditions(), dcalc_ap->corner(), @@ -254,12 +254,12 @@ DmpCeffTwoPoleDelayCalc::findParasitic(const Pin *drvr_pin, void DmpCeffTwoPoleDelayCalc::inputPortDelay(const Pin *port_pin, float in_slew, - const TransRiseFall *tr, + const RiseFall *rf, Parasitic *parasitic, const DcalcAnalysisPt *dcalc_ap) { parasitic_is_pole_residue_ = parasitics_->isPiPoleResidue(parasitic); - DmpCeffDelayCalc::inputPortDelay(port_pin, in_slew, tr, parasitic, dcalc_ap); + DmpCeffDelayCalc::inputPortDelay(port_pin, in_slew, rf, parasitic, dcalc_ap); } void @@ -277,10 +277,10 @@ DmpCeffTwoPoleDelayCalc::gateDelay(const LibertyCell *drvr_cell, { parasitic_is_pole_residue_ = parasitics_->isPiPoleResidue(drvr_parasitic); const LibertyLibrary *drvr_library = drvr_cell->libertyLibrary(); - const TransRiseFall *tr = arc->toTrans()->asRiseFall(); - vth_ = drvr_library->outputThreshold(tr); - vl_ = drvr_library->slewLowerThreshold(tr); - vh_ = drvr_library->slewUpperThreshold(tr); + const RiseFall *rf = arc->toTrans()->asRiseFall(); + vth_ = drvr_library->outputThreshold(rf); + vl_ = drvr_library->slewLowerThreshold(rf); + vh_ = drvr_library->slewUpperThreshold(rf); slew_derate_ = drvr_library->slewDerateFromLibrary(); DmpCeffDelayCalc::gateDelay(drvr_cell, arc, in_slew, load_cap, drvr_parasitic, diff --git a/dcalc/GraphDelayCalc.cc b/dcalc/GraphDelayCalc.cc index f446a4e3..a89d6e3a 100644 --- a/dcalc/GraphDelayCalc.cc +++ b/dcalc/GraphDelayCalc.cc @@ -61,7 +61,7 @@ GraphDelayCalc::incrementalDelayTolerance() void GraphDelayCalc::loadCap(const Pin *, Parasitic *, - const TransRiseFall *, + const RiseFall *, const DcalcAnalysisPt *, // Return values. float &pin_cap, @@ -72,7 +72,7 @@ GraphDelayCalc::loadCap(const Pin *, float GraphDelayCalc::loadCap(const Pin *, - const TransRiseFall *, + const RiseFall *, const DcalcAnalysisPt *) const { return 0.0F; @@ -81,7 +81,7 @@ GraphDelayCalc::loadCap(const Pin *, float GraphDelayCalc::loadCap(const Pin *, Parasitic *, - const TransRiseFall *, + const RiseFall *, const DcalcAnalysisPt *) const { return 0.0F; @@ -96,7 +96,7 @@ GraphDelayCalc::loadCap(const Pin *, void GraphDelayCalc::netCaps(const Pin *, - const TransRiseFall *, + const RiseFall *, const DcalcAnalysisPt *, // Return values. float &pin_cap, @@ -118,7 +118,7 @@ GraphDelayCalc::ceff(Edge *, void GraphDelayCalc::minPulseWidth(const Pin *pin, - const TransRiseFall *hi_low, + const RiseFall *hi_low, DcalcAPIndex ap_index, const MinMax *min_max, // Return values. diff --git a/dcalc/GraphDelayCalc.hh b/dcalc/GraphDelayCalc.hh index 103a93b0..173476c5 100644 --- a/dcalc/GraphDelayCalc.hh +++ b/dcalc/GraphDelayCalc.hh @@ -74,14 +74,14 @@ public: // wire_cap = annotated net capacitance + port external wire capacitance. virtual void loadCap(const Pin *drvr_pin, Parasitic *drvr_parasitic, - const TransRiseFall *tr, + const RiseFall *rf, const DcalcAnalysisPt *dcalc_ap, // Return values. float &pin_cap, float &wire_cap) const; // Load pin_cap + wire_cap including parasitic. virtual float loadCap(const Pin *drvr_pin, - const TransRiseFall *to_tr, + const RiseFall *to_rf, const DcalcAnalysisPt *dcalc_ap) const; // Load pin_cap + wire_cap including parasitic min/max for rise/fall. virtual float loadCap(const Pin *drvr_pin, @@ -89,10 +89,10 @@ public: // Load pin_cap + wire_cap. virtual float loadCap(const Pin *drvr_pin, Parasitic *drvr_parasitic, - const TransRiseFall *tr, + const RiseFall *rf, const DcalcAnalysisPt *dcalc_ap) const; virtual void netCaps(const Pin *drvr_pin, - const TransRiseFall *tr, + const RiseFall *rf, const DcalcAnalysisPt *dcalc_ap, // Return values. float &pin_cap, @@ -107,7 +107,7 @@ public: // Liberty library // (ignores set_min_pulse_width constraint) void minPulseWidth(const Pin *pin, - const TransRiseFall *hi_low, + const RiseFall *hi_low, DcalcAPIndex ap_index, const MinMax *min_max, // Return values. diff --git a/dcalc/GraphDelayCalc1.cc b/dcalc/GraphDelayCalc1.cc index c817e0f8..d4c24d47 100644 --- a/dcalc/GraphDelayCalc1.cc +++ b/dcalc/GraphDelayCalc1.cc @@ -59,14 +59,14 @@ public: VertexSet *drvrs() { return drvrs_; } Vertex *dcalcDrvr() const { return dcalc_drvr_; } void setDcalcDrvr(Vertex *drvr); - void parallelDelaySlew(const TransRiseFall *drvr_tr, + void parallelDelaySlew(const RiseFall *drvr_rf, const DcalcAnalysisPt *dcalc_ap, ArcDelayCalc *arc_delay_calc, GraphDelayCalc1 *dcalc, // Return values. ArcDelay ¶llel_delay, Slew ¶llel_slew); - void netCaps(const TransRiseFall *tr, + void netCaps(const RiseFall *rf, const DcalcAnalysisPt *dcalc_ap, // Return values. float &pin_cap, @@ -83,11 +83,11 @@ private: // Driver that triggers delay calculation for all the drivers on the net. Vertex *dcalc_drvr_; VertexSet *drvrs_; - // [drvr_tr->index][dcalc_ap->index] + // [drvr_rf->index][dcalc_ap->index] ArcDelay *parallel_delays_; - // [drvr_tr->index][dcalc_ap->index] + // [drvr_rf->index][dcalc_ap->index] Slew *parallel_slews_; - // [drvr_tr->index][dcalc_ap->index] + // [drvr_rf->index][dcalc_ap->index] NetCaps *net_caps_; bool delays_valid_:1; }; @@ -113,7 +113,7 @@ MultiDrvrNet::~MultiDrvrNet() } void -MultiDrvrNet::parallelDelaySlew(const TransRiseFall *drvr_tr, +MultiDrvrNet::parallelDelaySlew(const RiseFall *drvr_rf, const DcalcAnalysisPt *dcalc_ap, ArcDelayCalc *arc_delay_calc, GraphDelayCalc1 *dcalc, @@ -126,8 +126,8 @@ MultiDrvrNet::parallelDelaySlew(const TransRiseFall *drvr_tr, delays_valid_ = true; } - int index = dcalc_ap->index() * TransRiseFall::index_count - + drvr_tr->index(); + int index = dcalc_ap->index() * RiseFall::index_count + + drvr_rf->index(); parallel_delay = parallel_delays_[index]; parallel_slew = parallel_slews_[index]; } @@ -137,16 +137,16 @@ MultiDrvrNet::findDelaysSlews(ArcDelayCalc *arc_delay_calc, GraphDelayCalc1 *dcalc) { Corners *corners = dcalc->corners(); - int count = TransRiseFall::index_count * corners->dcalcAnalysisPtCount(); + int count = RiseFall::index_count * corners->dcalcAnalysisPtCount(); parallel_delays_ = new ArcDelay[count]; parallel_slews_ = new Slew[count]; for (auto dcalc_ap : corners->dcalcAnalysisPts()) { DcalcAPIndex ap_index = dcalc_ap->index(); const Pvt *pvt = dcalc_ap->operatingConditions(); - for (auto drvr_tr : TransRiseFall::range()) { - int drvr_tr_index = drvr_tr->index(); - int index = ap_index*TransRiseFall::index_count+drvr_tr_index; - dcalc->findMultiDrvrGateDelay(this, drvr_tr, pvt, dcalc_ap, + for (auto drvr_rf : RiseFall::range()) { + int drvr_rf_index = drvr_rf->index(); + int index = ap_index*RiseFall::index_count+drvr_rf_index; + dcalc->findMultiDrvrGateDelay(this, drvr_rf, pvt, dcalc_ap, arc_delay_calc, parallel_delays_[index], parallel_slews_[index]); @@ -155,7 +155,7 @@ MultiDrvrNet::findDelaysSlews(ArcDelayCalc *arc_delay_calc, } void -MultiDrvrNet::netCaps(const TransRiseFall *drvr_tr, +MultiDrvrNet::netCaps(const RiseFall *drvr_rf, const DcalcAnalysisPt *dcalc_ap, // Return values. float &pin_cap, @@ -163,8 +163,8 @@ MultiDrvrNet::netCaps(const TransRiseFall *drvr_tr, float &fanout, bool &has_set_load) { - int index = dcalc_ap->index() * TransRiseFall::index_count - + drvr_tr->index(); + int index = dcalc_ap->index() * RiseFall::index_count + + drvr_rf->index(); NetCaps &net_caps = net_caps_[index]; pin_cap = net_caps.pinCap(); wire_cap = net_caps.wireCap(); @@ -177,7 +177,7 @@ MultiDrvrNet::findCaps(const GraphDelayCalc1 *dcalc, const Sdc *sdc) { Corners *corners = dcalc->corners(); - int count = TransRiseFall::index_count * corners->dcalcAnalysisPtCount(); + int count = RiseFall::index_count * corners->dcalcAnalysisPtCount(); net_caps_ = new NetCaps[count]; const Pin *drvr_pin = dcalc_drvr_->pin(); for (auto dcalc_ap : corners->dcalcAnalysisPts()) { @@ -185,14 +185,14 @@ MultiDrvrNet::findCaps(const GraphDelayCalc1 *dcalc, const Corner *corner = dcalc_ap->corner(); const OperatingConditions *op_cond = dcalc_ap->operatingConditions(); const MinMax *min_max = dcalc_ap->constraintMinMax(); - for (auto drvr_tr : TransRiseFall::range()) { - int drvr_tr_index = drvr_tr->index(); - int index = ap_index * TransRiseFall::index_count + drvr_tr_index; + for (auto drvr_rf : RiseFall::range()) { + int drvr_rf_index = drvr_rf->index(); + int index = ap_index * RiseFall::index_count + drvr_rf_index; NetCaps &net_caps = net_caps_[index]; float pin_cap, wire_cap, fanout; bool has_set_load; // Find pin and external pin/wire capacitance. - sdc->connectedCap(drvr_pin, drvr_tr, op_cond, corner, min_max, + sdc->connectedCap(drvr_pin, drvr_rf, op_cond, corner, min_max, pin_cap, wire_cap, fanout, has_set_load); net_caps.init(pin_cap, wire_cap, fanout, has_set_load); } @@ -602,7 +602,7 @@ GraphDelayCalc1::seedDrvrSlew(Vertex *drvr_vertex, Port *port = network_->port(drvr_pin); drive = sdc_->findInputDrive(port); } - for (auto tr : TransRiseFall::range()) { + for (auto tr : RiseFall::range()) { for (auto dcalc_ap : corners_->dcalcAnalysisPts()) { if (drive) { const MinMax *cnst_min_max = dcalc_ap->constraintMinMax(); @@ -630,7 +630,7 @@ GraphDelayCalc1::seedDrvrSlew(Vertex *drvr_vertex, void GraphDelayCalc1::seedNoDrvrCellSlew(Vertex *drvr_vertex, const Pin *drvr_pin, - const TransRiseFall *tr, + const RiseFall *rf, InputDrive *drive, DcalcAnalysisPt *dcalc_ap, ArcDelayCalc *arc_delay_calc) @@ -640,7 +640,7 @@ GraphDelayCalc1::seedNoDrvrCellSlew(Vertex *drvr_vertex, Slew slew = default_slew; float drive_slew; bool exists; - drive->slew(tr, cnst_min_max, drive_slew, exists); + drive->slew(rf, cnst_min_max, drive_slew, exists); if (exists) slew = drive_slew; else { @@ -648,31 +648,31 @@ GraphDelayCalc1::seedNoDrvrCellSlew(Vertex *drvr_vertex, // bidirect instance paths are disabled. if (sdc_->bidirectDrvrSlewFromLoad(drvr_pin)) { Vertex *load_vertex = graph_->pinLoadVertex(drvr_pin); - slew = graph_->slew(load_vertex, tr, ap_index); + slew = graph_->slew(load_vertex, rf, ap_index); } } Delay drive_delay = delay_zero; float drive_res; - drive->driveResistance(tr, cnst_min_max, drive_res, exists); - Parasitic *parasitic = arc_delay_calc->findParasitic(drvr_pin, tr, dcalc_ap); + drive->driveResistance(rf, cnst_min_max, drive_res, exists); + Parasitic *parasitic = arc_delay_calc->findParasitic(drvr_pin, rf, dcalc_ap); if (exists) { - float cap = loadCap(drvr_pin, parasitic, tr, dcalc_ap); + float cap = loadCap(drvr_pin, parasitic, rf, dcalc_ap); drive_delay = cap * drive_res; slew = cap * drive_res; } const MinMax *slew_min_max = dcalc_ap->slewMinMax(); - if (!drvr_vertex->slewAnnotated(tr, slew_min_max)) - graph_->setSlew(drvr_vertex, tr, ap_index, slew); - arc_delay_calc->inputPortDelay(drvr_pin, delayAsFloat(slew), tr, + if (!drvr_vertex->slewAnnotated(rf, slew_min_max)) + graph_->setSlew(drvr_vertex, rf, ap_index, slew); + arc_delay_calc->inputPortDelay(drvr_pin, delayAsFloat(slew), rf, parasitic, dcalc_ap); - annotateLoadDelays(drvr_vertex, tr, drive_delay, false, dcalc_ap, + annotateLoadDelays(drvr_vertex, rf, drive_delay, false, dcalc_ap, arc_delay_calc); } void GraphDelayCalc1::seedNoDrvrSlew(Vertex *drvr_vertex, const Pin *drvr_pin, - const TransRiseFall *tr, + const RiseFall *rf, DcalcAnalysisPt *dcalc_ap, ArcDelayCalc *arc_delay_calc) { @@ -683,14 +683,14 @@ GraphDelayCalc1::seedNoDrvrSlew(Vertex *drvr_vertex, // bidirect instance paths are disabled. if (sdc_->bidirectDrvrSlewFromLoad(drvr_pin)) { Vertex *load_vertex = graph_->pinLoadVertex(drvr_pin); - slew = graph_->slew(load_vertex, tr, ap_index); + slew = graph_->slew(load_vertex, rf, ap_index); } - if (!drvr_vertex->slewAnnotated(tr, slew_min_max)) - graph_->setSlew(drvr_vertex, tr, ap_index, slew); - Parasitic *parasitic = arc_delay_calc->findParasitic(drvr_pin, tr, dcalc_ap); - arc_delay_calc->inputPortDelay(drvr_pin, delayAsFloat(slew), tr, + if (!drvr_vertex->slewAnnotated(rf, slew_min_max)) + graph_->setSlew(drvr_vertex, rf, ap_index, slew); + Parasitic *parasitic = arc_delay_calc->findParasitic(drvr_pin, rf, dcalc_ap); + arc_delay_calc->inputPortDelay(drvr_pin, delayAsFloat(slew), rf, parasitic, dcalc_ap); - annotateLoadDelays(drvr_vertex, tr, delay_zero, false, dcalc_ap, + annotateLoadDelays(drvr_vertex, rf, delay_zero, false, dcalc_ap, arc_delay_calc); } @@ -702,7 +702,7 @@ GraphDelayCalc1::seedLoadSlew(Vertex *vertex) vertex->name(sdc_network_)); ClockSet *clks = sdc_->findLeafPinClocks(pin); initSlew(vertex); - for (auto tr : TransRiseFall::range()) { + for (auto tr : RiseFall::range()) { for (auto dcalc_ap : corners_->dcalcAnalysisPts()) { const MinMax *slew_min_max = dcalc_ap->slewMinMax(); if (!vertex->slewAnnotated(tr, slew_min_max)) { @@ -770,7 +770,7 @@ void GraphDelayCalc1::findInputDriverDelay(LibertyCell *drvr_cell, const Pin *drvr_pin, Vertex *drvr_vertex, - const TransRiseFall *tr, + const RiseFall *rf, LibertyPort *from_port, float *from_slews, LibertyPort *to_port, @@ -778,7 +778,7 @@ GraphDelayCalc1::findInputDriverDelay(LibertyCell *drvr_cell, { debugPrint2(debug_, "delay_calc", 2, " driver cell %s %s\n", drvr_cell->name(), - tr->asString()); + rf->asString()); LibertyCellTimingArcSetIterator set_iter(drvr_cell); while (set_iter.hasNext()) { TimingArcSet *arc_set = set_iter.next(); @@ -787,7 +787,7 @@ GraphDelayCalc1::findInputDriverDelay(LibertyCell *drvr_cell, TimingArcSetArcIterator arc_iter(arc_set); while (arc_iter.hasNext()) { TimingArc *arc = arc_iter.next(); - if (arc->toTrans()->asRiseFall() == tr) { + if (arc->toTrans()->asRiseFall() == rf) { float from_slew = from_slews[arc->fromTrans()->index()]; findInputArcDelay(drvr_cell, drvr_pin, drvr_vertex, arc, from_slew, dcalc_ap); @@ -814,13 +814,13 @@ GraphDelayCalc1::findInputArcDelay(LibertyCell *drvr_cell, arc->to()->name(), arc->toTrans()->asString(), arc->role()->asString()); - TransRiseFall *drvr_tr = arc->toTrans()->asRiseFall(); - if (drvr_tr) { + RiseFall *drvr_rf = arc->toTrans()->asRiseFall(); + if (drvr_rf) { DcalcAPIndex ap_index = dcalc_ap->index(); const Pvt *pvt = dcalc_ap->operatingConditions(); - Parasitic *drvr_parasitic = arc_delay_calc_->findParasitic(drvr_pin, drvr_tr, + Parasitic *drvr_parasitic = arc_delay_calc_->findParasitic(drvr_pin, drvr_rf, dcalc_ap); - float load_cap = loadCap(drvr_pin, drvr_parasitic, drvr_tr, dcalc_ap); + float load_cap = loadCap(drvr_pin, drvr_parasitic, drvr_rf, dcalc_ap); ArcDelay intrinsic_delay; Slew intrinsic_slew; @@ -841,8 +841,8 @@ GraphDelayCalc1::findInputArcDelay(LibertyCell *drvr_cell, delayAsString(gate_delay, this), delayAsString(intrinsic_delay, this), delayAsString(gate_slew, this)); - graph_->setSlew(drvr_vertex, drvr_tr, ap_index, gate_slew); - annotateLoadDelays(drvr_vertex, drvr_tr, load_delay, false, dcalc_ap, + graph_->setSlew(drvr_vertex, drvr_rf, ap_index, gate_slew); + annotateLoadDelays(drvr_vertex, drvr_rf, load_delay, false, dcalc_ap, arc_delay_calc_); } } @@ -960,7 +960,7 @@ GraphDelayCalc1::initRootSlews(Vertex *vertex) for (auto dcalc_ap : corners_->dcalcAnalysisPts()) { const MinMax *slew_min_max = dcalc_ap->slewMinMax(); DcalcAPIndex ap_index = dcalc_ap->index(); - for (auto tr : TransRiseFall::range()) { + for (auto tr : RiseFall::range()) { if (!vertex->slewAnnotated(tr, slew_min_max)) graph_->setSlew(vertex, tr, ap_index, default_slew); } @@ -990,16 +990,16 @@ GraphDelayCalc1::findDriverEdgeDelays(LibertyCell *drvr_cell, TimingArcSetArcIterator arc_iter(arc_set); while (arc_iter.hasNext()) { TimingArc *arc = arc_iter.next(); - const TransRiseFall *tr = arc->toTrans()->asRiseFall(); - Parasitic *parasitic = arc_delay_calc->findParasitic(drvr_pin, tr, + const RiseFall *rf = arc->toTrans()->asRiseFall(); + Parasitic *parasitic = arc_delay_calc->findParasitic(drvr_pin, rf, dcalc_ap); float related_out_cap = 0.0; if (related_out_pin) { Parasitic *related_out_parasitic = - arc_delay_calc->findParasitic(related_out_pin, tr, dcalc_ap); + arc_delay_calc->findParasitic(related_out_pin, rf, dcalc_ap); related_out_cap = loadCap(related_out_pin, related_out_parasitic, - tr, dcalc_ap); + rf, dcalc_ap); } delay_changed |= findArcDelay(drvr_cell, drvr_pin, drvr_vertex, multi_drvr, arc, parasitic, @@ -1022,10 +1022,10 @@ GraphDelayCalc1::loadCap(const Pin *drvr_pin, { const MinMax *min_max = dcalc_ap->constraintMinMax(); float load_cap = 0.0; - for (auto drvr_tr : TransRiseFall::range()) { - Parasitic *drvr_parasitic = arc_delay_calc_->findParasitic(drvr_pin, drvr_tr, + for (auto drvr_rf : RiseFall::range()) { + Parasitic *drvr_parasitic = arc_delay_calc_->findParasitic(drvr_pin, drvr_rf, dcalc_ap); - float cap = loadCap(drvr_pin, nullptr, drvr_parasitic, drvr_tr, dcalc_ap); + float cap = loadCap(drvr_pin, nullptr, drvr_parasitic, drvr_rf, dcalc_ap); if (min_max->compare(cap, load_cap)) load_cap = cap; } @@ -1034,39 +1034,39 @@ GraphDelayCalc1::loadCap(const Pin *drvr_pin, float GraphDelayCalc1::loadCap(const Pin *drvr_pin, - const TransRiseFall *drvr_tr, + const RiseFall *drvr_rf, const DcalcAnalysisPt *dcalc_ap) const { - Parasitic *drvr_parasitic = arc_delay_calc_->findParasitic(drvr_pin, drvr_tr, + Parasitic *drvr_parasitic = arc_delay_calc_->findParasitic(drvr_pin, drvr_rf, dcalc_ap); - float cap = loadCap(drvr_pin, nullptr, drvr_parasitic, drvr_tr, dcalc_ap); + float cap = loadCap(drvr_pin, nullptr, drvr_parasitic, drvr_rf, dcalc_ap); return cap; } float GraphDelayCalc1::loadCap(const Pin *drvr_pin, Parasitic *drvr_parasitic, - const TransRiseFall *tr, + const RiseFall *rf, const DcalcAnalysisPt *dcalc_ap) const { - return loadCap(drvr_pin, nullptr, drvr_parasitic, tr, dcalc_ap); + return loadCap(drvr_pin, nullptr, drvr_parasitic, rf, dcalc_ap); } float GraphDelayCalc1::loadCap(const Pin *drvr_pin, MultiDrvrNet *multi_drvr, Parasitic *drvr_parasitic, - const TransRiseFall *tr, + const RiseFall *rf, const DcalcAnalysisPt *dcalc_ap) const { float pin_cap, wire_cap; bool has_set_load; float fanout; if (multi_drvr) - multi_drvr->netCaps(tr, dcalc_ap, + multi_drvr->netCaps(rf, dcalc_ap, pin_cap, wire_cap, fanout, has_set_load); else - netCaps(drvr_pin, tr, dcalc_ap, + netCaps(drvr_pin, rf, dcalc_ap, pin_cap, wire_cap, fanout, has_set_load); loadCap(drvr_parasitic, has_set_load, pin_cap, wire_cap); return wire_cap + pin_cap; @@ -1075,7 +1075,7 @@ GraphDelayCalc1::loadCap(const Pin *drvr_pin, void GraphDelayCalc1::loadCap(const Pin *drvr_pin, Parasitic *drvr_parasitic, - const TransRiseFall *tr, + const RiseFall *rf, const DcalcAnalysisPt *dcalc_ap, // Return values. float &pin_cap, @@ -1084,7 +1084,7 @@ GraphDelayCalc1::loadCap(const Pin *drvr_pin, bool has_set_load; float fanout; // Find pin and external pin/wire capacitance. - netCaps(drvr_pin, tr, dcalc_ap, + netCaps(drvr_pin, rf, dcalc_ap, pin_cap, wire_cap, fanout, has_set_load); loadCap(drvr_parasitic, has_set_load, pin_cap, wire_cap); } @@ -1115,7 +1115,7 @@ GraphDelayCalc1::loadCap(Parasitic *drvr_parasitic, void GraphDelayCalc1::netCaps(const Pin *drvr_pin, - const TransRiseFall *tr, + const RiseFall *rf, const DcalcAnalysisPt *dcalc_ap, // Return values. float &pin_cap, @@ -1129,14 +1129,14 @@ GraphDelayCalc1::netCaps(const Pin *drvr_pin, multi_drvr = multiDrvrNet(drvr_vertex); } if (multi_drvr) - multi_drvr->netCaps(tr, dcalc_ap, + multi_drvr->netCaps(rf, dcalc_ap, pin_cap, wire_cap, fanout, has_set_load); else { const OperatingConditions *op_cond = dcalc_ap->operatingConditions(); const Corner *corner = dcalc_ap->corner(); const MinMax *min_max = dcalc_ap->constraintMinMax(); // Find pin and external pin/wire capacitance. - sdc_->connectedCap(drvr_pin, tr, op_cond, corner, min_max, + sdc_->connectedCap(drvr_pin, rf, op_cond, corner, min_max, pin_cap, wire_cap, fanout, has_set_load); } } @@ -1144,7 +1144,7 @@ GraphDelayCalc1::netCaps(const Pin *drvr_pin, void GraphDelayCalc1::initSlew(Vertex *vertex) { - for (auto tr : TransRiseFall::range()) { + for (auto tr : RiseFall::range()) { for (auto dcalc_ap : corners_->dcalcAnalysisPts()) { const MinMax *slew_min_max = dcalc_ap->slewMinMax(); if (!vertex->slewAnnotated(tr, slew_min_max)) { @@ -1171,7 +1171,7 @@ GraphDelayCalc1::initWireDelays(Vertex *drvr_vertex, Delay delay_init_value(delay_min_max->initValue()); Slew slew_init_value(slew_min_max->initValue()); DcalcAPIndex ap_index = dcalc_ap->index(); - for (auto tr : TransRiseFall::range()) { + for (auto tr : RiseFall::range()) { if (!graph_->wireDelayAnnotated(wire_edge, tr, ap_index)) graph_->setWireArcDelay(wire_edge, tr, ap_index, delay_init_value); // Init load vertex slew. @@ -1203,9 +1203,9 @@ GraphDelayCalc1::findArcDelay(LibertyCell *drvr_cell, ArcDelayCalc *arc_delay_calc) { bool delay_changed = false; - TransRiseFall *from_tr = arc->fromTrans()->asRiseFall(); - TransRiseFall *drvr_tr = arc->toTrans()->asRiseFall(); - if (from_tr && drvr_tr) { + RiseFall *from_rf = arc->fromTrans()->asRiseFall(); + RiseFall *drvr_rf = arc->toTrans()->asRiseFall(); + if (from_rf && drvr_rf) { DcalcAPIndex ap_index = dcalc_ap->index(); debugPrint6(debug_, "delay_calc", 3, " %s %s -> %s %s (%s) %s\n", @@ -1217,7 +1217,7 @@ GraphDelayCalc1::findArcDelay(LibertyCell *drvr_cell, dcalc_ap->corner()->name()); // Delay calculation is done even when the gate delays/slews are // annotated because the wire delays may not be annotated. - const Slew from_slew = edgeFromSlew(from_vertex, from_tr, edge, dcalc_ap); + const Slew from_slew = edgeFromSlew(from_vertex, from_rf, edge, dcalc_ap); ArcDelay gate_delay; Slew gate_slew; if (multi_drvr @@ -1229,7 +1229,7 @@ GraphDelayCalc1::findArcDelay(LibertyCell *drvr_cell, gate_delay, gate_slew); else { float load_cap = loadCap(drvr_pin, multi_drvr, drvr_parasitic, - drvr_tr, dcalc_ap); + drvr_rf, dcalc_ap); arc_delay_calc->gateDelay(drvr_cell, arc, from_slew, load_cap, drvr_parasitic, related_out_cap, pvt, dcalc_ap, @@ -1240,11 +1240,11 @@ GraphDelayCalc1::findArcDelay(LibertyCell *drvr_cell, delayAsString(gate_delay, this), delayAsString(gate_slew, this)); // Merge slews. - const Slew &drvr_slew = graph_->slew(drvr_vertex, drvr_tr, ap_index); + const Slew &drvr_slew = graph_->slew(drvr_vertex, drvr_rf, ap_index); const MinMax *slew_min_max = dcalc_ap->slewMinMax(); if (fuzzyGreater(gate_slew, drvr_slew, dcalc_ap->slewMinMax()) - && !drvr_vertex->slewAnnotated(drvr_tr, slew_min_max)) - graph_->setSlew(drvr_vertex, drvr_tr, ap_index, gate_slew); + && !drvr_vertex->slewAnnotated(drvr_rf, slew_min_max)) + graph_->setSlew(drvr_vertex, drvr_rf, ap_index, gate_slew); if (!graph_->arcDelayAnnotated(edge, arc, ap_index)) { const ArcDelay &prev_gate_delay = graph_->arcDelay(edge,arc,ap_index); float gate_delay1 = delayAsFloat(gate_delay); @@ -1255,7 +1255,7 @@ GraphDelayCalc1::findArcDelay(LibertyCell *drvr_cell, delay_changed = true; graph_->setArcDelay(edge, arc, ap_index, gate_delay); } - annotateLoadDelays(drvr_vertex, drvr_tr, delay_zero, true, dcalc_ap, + annotateLoadDelays(drvr_vertex, drvr_rf, delay_zero, true, dcalc_ap, arc_delay_calc); } return delay_changed; @@ -1283,15 +1283,15 @@ GraphDelayCalc1::multiDrvrGateDelay(MultiDrvrNet *multi_drvr, intrinsic_delay, intrinsic_slew); ArcDelay parallel_delay; Slew parallel_slew; - const TransRiseFall *drvr_tr = arc->toTrans()->asRiseFall(); - multi_drvr->parallelDelaySlew(drvr_tr, dcalc_ap, arc_delay_calc, this, + const RiseFall *drvr_rf = arc->toTrans()->asRiseFall(); + multi_drvr->parallelDelaySlew(drvr_rf, dcalc_ap, arc_delay_calc, this, parallel_delay, parallel_slew); gate_delay = parallel_delay + intrinsic_delay; gate_slew = parallel_slew; float load_cap = loadCap(drvr_pin, multi_drvr, drvr_parasitic, - drvr_tr, dcalc_ap); + drvr_rf, dcalc_ap); Delay gate_delay1; Slew gate_slew1; arc_delay_calc->gateDelay(drvr_cell, arc, @@ -1304,7 +1304,7 @@ GraphDelayCalc1::multiDrvrGateDelay(MultiDrvrNet *multi_drvr, void GraphDelayCalc1::findMultiDrvrGateDelay(MultiDrvrNet *multi_drvr, - const TransRiseFall *drvr_tr, + const RiseFall *drvr_rf, const Pvt *pvt, const DcalcAnalysisPt *dcalc_ap, ArcDelayCalc *arc_delay_calc, @@ -1329,18 +1329,18 @@ GraphDelayCalc1::findMultiDrvrGateDelay(MultiDrvrNet *multi_drvr, TimingArcSetArcIterator arc_iter(arc_set1); while (arc_iter.hasNext()) { TimingArc *arc1 = arc_iter.next(); - TransRiseFall *drvr_tr1 = arc1->toTrans()->asRiseFall(); - if (drvr_tr1 == drvr_tr) { + RiseFall *drvr_rf1 = arc1->toTrans()->asRiseFall(); + if (drvr_rf1 == drvr_rf) { Vertex *from_vertex1 = edge1->from(graph_); - TransRiseFall *from_tr1 = arc1->fromTrans()->asRiseFall(); - Slew from_slew1 = edgeFromSlew(from_vertex1, from_tr1, edge1, dcalc_ap); + RiseFall *from_rf1 = arc1->fromTrans()->asRiseFall(); + Slew from_slew1 = edgeFromSlew(from_vertex1, from_rf1, edge1, dcalc_ap); ArcDelay intrinsic_delay1; Slew intrinsic_slew1; arc_delay_calc->gateDelay(drvr_cell1, arc1, from_slew1, 0.0, 0, 0.0, pvt, dcalc_ap, intrinsic_delay1, intrinsic_slew1); Parasitic *parasitic1 = - arc_delay_calc->findParasitic(drvr_pin1, drvr_tr1, dcalc_ap); + arc_delay_calc->findParasitic(drvr_pin1, drvr_rf1, dcalc_ap); const Pin *related_out_pin1 = 0; float related_out_cap1 = 0.0; if (related_out_port) { @@ -1348,15 +1348,15 @@ GraphDelayCalc1::findMultiDrvrGateDelay(MultiDrvrNet *multi_drvr, related_out_pin1 = network_->findPin(inst1, related_out_port); if (related_out_pin1) { Parasitic *related_out_parasitic1 = - arc_delay_calc->findParasitic(related_out_pin1, drvr_tr, + arc_delay_calc->findParasitic(related_out_pin1, drvr_rf, dcalc_ap); related_out_cap1 = loadCap(related_out_pin1, related_out_parasitic1, - drvr_tr, dcalc_ap); + drvr_rf, dcalc_ap); } } float load_cap1 = loadCap(drvr_pin1, parasitic1, - drvr_tr, dcalc_ap); + drvr_rf, dcalc_ap); ArcDelay gate_delay1; Slew gate_slew1; arc_delay_calc->gateDelay(drvr_cell1, arc1, @@ -1377,21 +1377,21 @@ GraphDelayCalc1::findMultiDrvrGateDelay(MultiDrvrNet *multi_drvr, // Use clock slew for register/latch clk->q edges. Slew GraphDelayCalc1::edgeFromSlew(const Vertex *from_vertex, - const TransRiseFall *from_tr, + const RiseFall *from_rf, const Edge *edge, const DcalcAnalysisPt *dcalc_ap) { const TimingRole *role = edge->role(); if (role->genericRole() == TimingRole::regClkToQ() && isIdealClk(from_vertex)) - return idealClkSlew(from_vertex, from_tr, dcalc_ap->slewMinMax()); + return idealClkSlew(from_vertex, from_rf, dcalc_ap->slewMinMax()); else - return graph_->slew(from_vertex, from_tr, dcalc_ap->index()); + return graph_->slew(from_vertex, from_rf, dcalc_ap->index()); } Slew GraphDelayCalc1::idealClkSlew(const Vertex *vertex, - const TransRiseFall *tr, + const RiseFall *rf, const MinMax *min_max) { float slew = min_max->initValue(); @@ -1399,7 +1399,7 @@ GraphDelayCalc1::idealClkSlew(const Vertex *vertex, ClockSet::ConstIterator clk_iter(clks); while (clk_iter.hasNext()) { Clock *clk = clk_iter.next(); - float clk_slew = clk->slew(tr, min_max); + float clk_slew = clk->slew(rf, min_max); if (min_max->compare(clk_slew, slew)) slew = clk_slew; } @@ -1411,7 +1411,7 @@ GraphDelayCalc1::idealClkSlew(const Vertex *vertex, // by the delay calculator. void GraphDelayCalc1::annotateLoadDelays(Vertex *drvr_vertex, - const TransRiseFall *drvr_tr, + const RiseFall *drvr_rf, const ArcDelay &extra_delay, bool merge, const DcalcAnalysisPt *dcalc_ap, @@ -1433,30 +1433,30 @@ GraphDelayCalc1::annotateLoadDelays(Vertex *drvr_vertex, load_vertex->name(sdc_network_), delayAsString(wire_delay, this), delayAsString(load_slew, this)); - if (!load_vertex->slewAnnotated(drvr_tr, slew_min_max)) { - if (drvr_vertex->slewAnnotated(drvr_tr, slew_min_max)) { + if (!load_vertex->slewAnnotated(drvr_rf, slew_min_max)) { + if (drvr_vertex->slewAnnotated(drvr_rf, slew_min_max)) { // Copy the driver slew to the load if it is annotated. - const Slew &drvr_slew = graph_->slew(drvr_vertex,drvr_tr,ap_index); - graph_->setSlew(load_vertex, drvr_tr, ap_index, drvr_slew); + const Slew &drvr_slew = graph_->slew(drvr_vertex,drvr_rf,ap_index); + graph_->setSlew(load_vertex, drvr_rf, ap_index, drvr_slew); } else { - const Slew &slew = graph_->slew(load_vertex, drvr_tr, ap_index); + const Slew &slew = graph_->slew(load_vertex, drvr_rf, ap_index); if (!merge || fuzzyGreater(load_slew, slew, slew_min_max)) - graph_->setSlew(load_vertex, drvr_tr, ap_index, load_slew); + graph_->setSlew(load_vertex, drvr_rf, ap_index, load_slew); } } - if (!graph_->wireDelayAnnotated(wire_edge, drvr_tr, ap_index)) { + if (!graph_->wireDelayAnnotated(wire_edge, drvr_rf, ap_index)) { // Multiple timing arcs with the same output transition // annotate the same wire edges so they must be combined // rather than set. - const ArcDelay &delay = graph_->wireArcDelay(wire_edge, drvr_tr, + const ArcDelay &delay = graph_->wireArcDelay(wire_edge, drvr_rf, ap_index); Delay wire_delay_extra = extra_delay + wire_delay; const MinMax *delay_min_max = dcalc_ap->delayMinMax(); if (!merge || fuzzyGreater(wire_delay_extra, delay, delay_min_max)) { - graph_->setWireArcDelay(wire_edge, drvr_tr, ap_index, + graph_->setWireArcDelay(wire_edge, drvr_rf, ap_index, wire_delay_extra); if (observer_) observer_->delayChangedTo(load_vertex); @@ -1519,9 +1519,9 @@ GraphDelayCalc1::findCheckEdgeDelays(Edge *edge, TimingArcSetArcIterator arc_iter(arc_set); while (arc_iter.hasNext()) { TimingArc *arc = arc_iter.next(); - TransRiseFall *from_tr = arc->fromTrans()->asRiseFall(); - TransRiseFall *to_tr = arc->toTrans()->asRiseFall(); - if (from_tr && to_tr) { + RiseFall *from_rf = arc->fromTrans()->asRiseFall(); + RiseFall *to_rf = arc->toTrans()->asRiseFall(); + if (from_rf && to_rf) { const LibertyPort *related_out_port = arc_set->relatedOut(); const Pin *related_out_pin = 0; if (related_out_port) @@ -1532,10 +1532,10 @@ GraphDelayCalc1::findCheckEdgeDelays(Edge *edge, const Pvt *pvt = sdc_->pvt(inst,dcalc_ap->constraintMinMax()); if (pvt == nullptr) pvt = dcalc_ap->operatingConditions(); - const Slew &from_slew = checkEdgeClkSlew(from_vertex, from_tr, + const Slew &from_slew = checkEdgeClkSlew(from_vertex, from_rf, dcalc_ap); int slew_index = dcalc_ap->checkDataSlewIndex(); - const Slew &to_slew = graph_->slew(to_vertex, to_tr, slew_index); + const Slew &to_slew = graph_->slew(to_vertex, to_rf, slew_index); debugPrint5(debug_, "delay_calc", 3, " %s %s -> %s %s (%s)\n", arc_set->from()->name(), @@ -1550,10 +1550,10 @@ GraphDelayCalc1::findCheckEdgeDelays(Edge *edge, float related_out_cap = 0.0; if (related_out_pin) { Parasitic *related_out_parasitic = - arc_delay_calc->findParasitic(related_out_pin, to_tr, dcalc_ap); + arc_delay_calc->findParasitic(related_out_pin, to_rf, dcalc_ap); related_out_cap = loadCap(related_out_pin, related_out_parasitic, - to_tr, dcalc_ap); + to_rf, dcalc_ap); } ArcDelay check_delay; arc_delay_calc->checkDelay(cell, arc, @@ -1578,13 +1578,13 @@ GraphDelayCalc1::findCheckEdgeDelays(Edge *edge, // Use clock slew for timing check clock edges. Slew GraphDelayCalc1::checkEdgeClkSlew(const Vertex *from_vertex, - const TransRiseFall *from_tr, + const RiseFall *from_rf, const DcalcAnalysisPt *dcalc_ap) { if (isIdealClk(from_vertex)) - return idealClkSlew(from_vertex, from_tr, dcalc_ap->checkClkSlewMinMax()); + return idealClkSlew(from_vertex, from_rf, dcalc_ap->checkClkSlewMinMax()); else - return graph_->slew(from_vertex, from_tr, dcalc_ap->checkClkSlewIndex()); + return graph_->slew(from_vertex, from_rf, dcalc_ap->checkClkSlewIndex()); } //////////////////////////////////////////////////////////////// @@ -1696,9 +1696,9 @@ GraphDelayCalc1::ceff(Edge *edge, const Pvt *pvt = sdc_->pvt(inst, dcalc_ap->constraintMinMax()); if (pvt == nullptr) pvt = dcalc_ap->operatingConditions(); - TransRiseFall *from_tr = arc->fromTrans()->asRiseFall(); - TransRiseFall *to_tr = arc->toTrans()->asRiseFall(); - if (from_tr && to_tr) { + RiseFall *from_rf = arc->fromTrans()->asRiseFall(); + RiseFall *to_rf = arc->toTrans()->asRiseFall(); + if (from_rf && to_rf) { const LibertyPort *related_out_port = arc_set->relatedOut(); const Pin *related_out_pin = 0; if (related_out_port) @@ -1706,14 +1706,14 @@ GraphDelayCalc1::ceff(Edge *edge, float related_out_cap = 0.0; if (related_out_pin) { Parasitic *related_out_parasitic = - arc_delay_calc_->findParasitic(related_out_pin, to_tr, dcalc_ap); + arc_delay_calc_->findParasitic(related_out_pin, to_rf, dcalc_ap); related_out_cap = loadCap(related_out_pin, related_out_parasitic, - to_tr, dcalc_ap); + to_rf, dcalc_ap); } - Parasitic *to_parasitic = arc_delay_calc_->findParasitic(to_pin, to_tr, + Parasitic *to_parasitic = arc_delay_calc_->findParasitic(to_pin, to_rf, dcalc_ap); - const Slew &from_slew = edgeFromSlew(from_vertex, from_tr, edge, dcalc_ap); - float load_cap = loadCap(to_pin, to_parasitic, to_tr, dcalc_ap); + const Slew &from_slew = edgeFromSlew(from_vertex, from_rf, edge, dcalc_ap); + float load_cap = loadCap(to_pin, to_parasitic, to_rf, dcalc_ap); ceff = arc_delay_calc_->ceff(cell, arc, from_slew, load_cap, to_parasitic, related_out_cap, pvt, dcalc_ap); @@ -1743,9 +1743,9 @@ GraphDelayCalc1::reportDelayCalc(Edge *edge, const Pvt *pvt = sdc_->pvt(inst, dcalc_ap->constraintMinMax()); if (pvt == nullptr) pvt = dcalc_ap->operatingConditions(); - TransRiseFall *from_tr = arc->fromTrans()->asRiseFall(); - TransRiseFall *to_tr = arc->toTrans()->asRiseFall(); - if (from_tr && to_tr) { + RiseFall *from_rf = arc->fromTrans()->asRiseFall(); + RiseFall *to_rf = arc->toTrans()->asRiseFall(); + if (from_rf && to_rf) { const LibertyPort *related_out_port = arc_set->relatedOut(); const Pin *related_out_pin = 0; if (related_out_port) @@ -1753,14 +1753,14 @@ GraphDelayCalc1::reportDelayCalc(Edge *edge, float related_out_cap = 0.0; if (related_out_pin) { Parasitic *related_out_parasitic = - arc_delay_calc_->findParasitic(related_out_pin, to_tr, dcalc_ap); + arc_delay_calc_->findParasitic(related_out_pin, to_rf, dcalc_ap); related_out_cap = loadCap(related_out_pin, related_out_parasitic, - to_tr, dcalc_ap); + to_rf, dcalc_ap); } if (role->isTimingCheck()) { - const Slew &from_slew = checkEdgeClkSlew(from_vertex, from_tr, dcalc_ap); + const Slew &from_slew = checkEdgeClkSlew(from_vertex, from_rf, dcalc_ap); int slew_index = dcalc_ap->checkDataSlewIndex(); - const Slew &to_slew = graph_->slew(to_vertex, to_tr, slew_index); + const Slew &to_slew = graph_->slew(to_vertex, to_rf, slew_index); bool from_ideal_clk = isIdealClk(from_vertex); const char *from_slew_annotation = from_ideal_clk ? " (ideal clock)" : nullptr; arc_delay_calc_->reportCheckDelay(cell, arc, from_slew, from_slew_annotation, @@ -1769,9 +1769,9 @@ GraphDelayCalc1::reportDelayCalc(Edge *edge, } else { Parasitic *to_parasitic = - arc_delay_calc_->findParasitic(to_pin, to_tr, dcalc_ap); - const Slew &from_slew = edgeFromSlew(from_vertex, from_tr, edge, dcalc_ap); - float load_cap = loadCap(to_pin, to_parasitic, to_tr, dcalc_ap); + arc_delay_calc_->findParasitic(to_pin, to_rf, dcalc_ap); + const Slew &from_slew = edgeFromSlew(from_vertex, from_rf, edge, dcalc_ap); + float load_cap = loadCap(to_pin, to_parasitic, to_rf, dcalc_ap); arc_delay_calc_->reportGateDelay(cell, arc, from_slew, load_cap, to_parasitic, related_out_cap, pvt, dcalc_ap, diff --git a/dcalc/GraphDelayCalc1.hh b/dcalc/GraphDelayCalc1.hh index 6a323bc8..3d1d9dc1 100644 --- a/dcalc/GraphDelayCalc1.hh +++ b/dcalc/GraphDelayCalc1.hh @@ -53,23 +53,23 @@ public: virtual void setObserver(DelayCalcObserver *observer); // Load pin_cap + wire_cap. virtual float loadCap(const Pin *drvr_pin, - const TransRiseFall *drvr_tr, + const RiseFall *drvr_rf, const DcalcAnalysisPt *dcalc_ap) const; virtual float loadCap(const Pin *drvr_pin, const DcalcAnalysisPt *dcalc_ap) const; virtual void loadCap(const Pin *drvr_pin, Parasitic *drvr_parasitic, - const TransRiseFall *tr, + const RiseFall *rf, const DcalcAnalysisPt *dcalc_ap, // Return values. float &pin_cap, float &wire_cap) const; virtual float loadCap(const Pin *drvr_pin, Parasitic *drvr_parasitic, - const TransRiseFall *tr, + const RiseFall *rf, const DcalcAnalysisPt *dcalc_ap) const; virtual void netCaps(const Pin *drvr_pin, - const TransRiseFall *tr, + const RiseFall *rf, const DcalcAnalysisPt *dcalc_ap, // Return values. float &pin_cap, @@ -92,12 +92,12 @@ protected: ArcDelayCalc *arc_delay_calc); void seedNoDrvrSlew(Vertex *drvr_vertex, const Pin *drvr_pin, - const TransRiseFall *tr, + const RiseFall *rf, DcalcAnalysisPt *dcalc_ap, ArcDelayCalc *arc_delay_calc); void seedNoDrvrCellSlew(Vertex *drvr_vertex, const Pin *drvr_pin, - const TransRiseFall *tr, + const RiseFall *rf, InputDrive *drive, DcalcAnalysisPt *dcalc_ap, ArcDelayCalc *arc_delay_calc); @@ -106,7 +106,7 @@ protected: void findInputDriverDelay(LibertyCell *drvr_cell, const Pin *drvr_pin, Vertex *drvr_vertex, - const TransRiseFall *tr, + const RiseFall *rf, LibertyPort *from_port, float *from_slews, LibertyPort *to_port, @@ -155,7 +155,7 @@ protected: const DcalcAnalysisPt *dcalc_ap, ArcDelayCalc *arc_delay_calc); void annotateLoadDelays(Vertex *drvr_vertex, - const TransRiseFall *drvr_tr, + const RiseFall *drvr_rf, const ArcDelay &extra_delay, bool merge, const DcalcAnalysisPt *dcalc_ap, @@ -165,7 +165,7 @@ protected: void findCheckEdgeDelays(Edge *edge, ArcDelayCalc *arc_delay_calc); void findMultiDrvrGateDelay(MultiDrvrNet *multi_drvr, - const TransRiseFall *drvr_tr, + const RiseFall *drvr_rf, const Pvt *pvt, const DcalcAnalysisPt *dcalc_ap, ArcDelayCalc *arc_delay_calc, @@ -187,11 +187,11 @@ protected: Slew &gate_slew); void deleteMultiDrvrNets(); Slew edgeFromSlew(const Vertex *from_vertex, - const TransRiseFall *from_tr, + const RiseFall *from_rf, const Edge *edge, const DcalcAnalysisPt *dcalc_ap); Slew checkEdgeClkSlew(const Vertex *from_vertex, - const TransRiseFall *from_tr, + const RiseFall *from_rf, const DcalcAnalysisPt *dcalc_ap); bool bidirectDrvrSlewFromLoad(const Vertex *vertex) const; void clearIdealClkMap(); @@ -200,7 +200,7 @@ protected: ClockSet *idealClks(const Vertex *vertex); bool isIdealClk(const Vertex *vertex); Slew idealClkSlew(const Vertex *vertex, - const TransRiseFall *tr, + const RiseFall *rf, const MinMax *min_max); MultiDrvrNet *multiDrvrNet(const Vertex *drvr_vertex) const; void loadCap(Parasitic *drvr_parasitic, @@ -211,7 +211,7 @@ protected: float loadCap(const Pin *drvr_pin, MultiDrvrNet *multi_drvr, Parasitic *drvr_parasitic, - const TransRiseFall *tr, + const RiseFall *rf, const DcalcAnalysisPt *dcalc_ap) const; void mergeIdealClks(); diff --git a/dcalc/LumpedCapDelayCalc.cc b/dcalc/LumpedCapDelayCalc.cc index 73e258b6..726053d1 100644 --- a/dcalc/LumpedCapDelayCalc.cc +++ b/dcalc/LumpedCapDelayCalc.cc @@ -48,7 +48,7 @@ LumpedCapDelayCalc::copy() Parasitic * LumpedCapDelayCalc::findParasitic(const Pin *drvr_pin, - const TransRiseFall *tr, + const RiseFall *rf, const DcalcAnalysisPt *dcalc_ap) { // set_load has precidence over parasitics. @@ -57,7 +57,7 @@ LumpedCapDelayCalc::findParasitic(const Pin *drvr_pin, const ParasiticAnalysisPt *parasitic_ap = dcalc_ap->parasiticAnalysisPt(); if (parasitics_->haveParasitics()) { // Prefer PiElmore. - parasitic = parasitics_->findPiElmore(drvr_pin, tr,parasitic_ap); + parasitic = parasitics_->findPiElmore(drvr_pin, rf, parasitic_ap); if (parasitic) return parasitic; @@ -69,7 +69,7 @@ LumpedCapDelayCalc::findParasitic(const Pin *drvr_pin, dcalc_ap->corner(), dcalc_ap->constraintMinMax(), parasitic_ap); - parasitic = parasitics_->findPiElmore(drvr_pin, tr,parasitic_ap); + parasitic = parasitics_->findPiElmore(drvr_pin, rf, parasitic_ap); reduced_parasitic_drvrs_.push_back(drvr_pin); return parasitic; } @@ -80,9 +80,9 @@ LumpedCapDelayCalc::findParasitic(const Pin *drvr_pin, if (wireload) { float pin_cap, wire_cap, fanout; bool has_wire_cap; - graph_delay_calc_->netCaps(drvr_pin, tr, dcalc_ap, + graph_delay_calc_->netCaps(drvr_pin, rf, dcalc_ap, pin_cap, wire_cap, fanout, has_wire_cap); - parasitic = parasitics_->estimatePiElmore(drvr_pin, tr, wireload, + parasitic = parasitics_->estimatePiElmore(drvr_pin, rf, wireload, fanout, pin_cap, dcalc_ap->operatingConditions(), dcalc_ap->corner(), @@ -110,12 +110,12 @@ LumpedCapDelayCalc::finishDrvrPin() void LumpedCapDelayCalc::inputPortDelay(const Pin *, float in_slew, - const TransRiseFall *tr, + const RiseFall *rf, Parasitic *, const DcalcAnalysisPt *) { drvr_slew_ = in_slew; - drvr_tr_ = tr; + drvr_rf_ = rf; drvr_library_ = network_->defaultLibertyLibrary(); multi_drvr_slew_factor_ = 1.0F; } @@ -167,7 +167,7 @@ LumpedCapDelayCalc::gateDelay(const LibertyCell *drvr_cell, drvr_slew = delay_zero; drvr_slew_ = 0.0; } - drvr_tr_ = arc->toTrans()->asRiseFall(); + drvr_rf_ = arc->toTrans()->asRiseFall(); drvr_library_ = drvr_cell->libertyLibrary(); multi_drvr_slew_factor_ = 1.0F; } @@ -193,17 +193,17 @@ LumpedCapDelayCalc::thresholdAdjust(const Pin *load_pin, if (load_library && drvr_library_ && load_library != drvr_library_) { - float drvr_vth = drvr_library_->outputThreshold(drvr_tr_); - float load_vth = load_library->inputThreshold(drvr_tr_); - float drvr_slew_delta = drvr_library_->slewUpperThreshold(drvr_tr_) - - drvr_library_->slewLowerThreshold(drvr_tr_); + float drvr_vth = drvr_library_->outputThreshold(drvr_rf_); + float load_vth = load_library->inputThreshold(drvr_rf_); + float drvr_slew_delta = drvr_library_->slewUpperThreshold(drvr_rf_) + - drvr_library_->slewLowerThreshold(drvr_rf_); float load_delay_delta = delayAsFloat(load_slew) * ((load_vth - drvr_vth) / drvr_slew_delta); - load_delay += (drvr_tr_ == TransRiseFall::rise()) + load_delay += (drvr_rf_ == RiseFall::rise()) ? load_delay_delta : -load_delay_delta; - float load_slew_delta = load_library->slewUpperThreshold(drvr_tr_) - - load_library->slewLowerThreshold(drvr_tr_); + float load_slew_delta = load_library->slewUpperThreshold(drvr_rf_) + - load_library->slewLowerThreshold(drvr_rf_); float drvr_slew_derate = drvr_library_->slewDerateFromLibrary(); float load_slew_derate = load_library->slewDerateFromLibrary(); load_slew = load_slew * ((load_slew_delta / load_slew_derate) diff --git a/dcalc/LumpedCapDelayCalc.hh b/dcalc/LumpedCapDelayCalc.hh index d849877c..3ff8e0b8 100644 --- a/dcalc/LumpedCapDelayCalc.hh +++ b/dcalc/LumpedCapDelayCalc.hh @@ -29,11 +29,11 @@ public: LumpedCapDelayCalc(StaState *sta); virtual ArcDelayCalc *copy(); virtual Parasitic *findParasitic(const Pin *drvr_pin, - const TransRiseFall *tr, + const RiseFall *rf, const DcalcAnalysisPt *dcalc_ap); virtual void inputPortDelay(const Pin *port_pin, float in_slew, - const TransRiseFall *tr, + const RiseFall *rf, Parasitic *parasitic, const DcalcAnalysisPt *dcalc_ap); virtual void gateDelay(const LibertyCell *drvr_cell, @@ -102,7 +102,7 @@ protected: Slew drvr_slew_; float multi_drvr_slew_factor_; const LibertyLibrary *drvr_library_; - const TransRiseFall *drvr_tr_; + const RiseFall *drvr_rf_; // Parasitics returned by findParasitic that are reduced or estimated // that can be deleted after delay calculation for the driver pin // is finished. diff --git a/dcalc/RCDelayCalc.cc b/dcalc/RCDelayCalc.cc index 94f42989..70ad72ef 100644 --- a/dcalc/RCDelayCalc.cc +++ b/dcalc/RCDelayCalc.cc @@ -38,13 +38,13 @@ RCDelayCalc::copy() void RCDelayCalc::inputPortDelay(const Pin *, float in_slew, - const TransRiseFall *tr, + const RiseFall *rf, Parasitic *parasitic, const DcalcAnalysisPt *) { drvr_parasitic_ = parasitic; drvr_slew_ = in_slew; - drvr_tr_ = tr; + drvr_rf_ = rf; drvr_cell_ = nullptr; drvr_library_ = network_->defaultLibertyLibrary(); multi_drvr_slew_factor_ = 1.0F; @@ -66,9 +66,9 @@ RCDelayCalc::dspfWireDelaySlew(const Pin *, float vh = .8; float slew_derate = 1.0; if (drvr_library_) { - vth = drvr_library_->inputThreshold(drvr_tr_); - vl = drvr_library_->slewLowerThreshold(drvr_tr_); - vh = drvr_library_->slewUpperThreshold(drvr_tr_); + vth = drvr_library_->inputThreshold(drvr_rf_); + vl = drvr_library_->slewLowerThreshold(drvr_rf_); + vh = drvr_library_->slewUpperThreshold(drvr_rf_); slew_derate = drvr_library_->slewDerateFromLibrary(); } wire_delay = static_cast(-elmore * log(1.0 - vth)); diff --git a/dcalc/RCDelayCalc.hh b/dcalc/RCDelayCalc.hh index 666ce453..dce78e81 100644 --- a/dcalc/RCDelayCalc.hh +++ b/dcalc/RCDelayCalc.hh @@ -29,7 +29,7 @@ public: virtual ArcDelayCalc *copy(); virtual void inputPortDelay(const Pin *port_pin, float in_slew, - const TransRiseFall *tr, + const RiseFall *rf, Parasitic *parasitic, const DcalcAnalysisPt *dcalc_ap); diff --git a/dcalc/SimpleRCDelayCalc.cc b/dcalc/SimpleRCDelayCalc.cc index 94e6efcc..4b3717a7 100644 --- a/dcalc/SimpleRCDelayCalc.cc +++ b/dcalc/SimpleRCDelayCalc.cc @@ -45,12 +45,12 @@ SimpleRCDelayCalc::copy() void SimpleRCDelayCalc::inputPortDelay(const Pin *port_pin, float in_slew, - const TransRiseFall *tr, + const RiseFall *rf, Parasitic *parasitic, const DcalcAnalysisPt *dcalc_ap) { pvt_ = dcalc_ap->operatingConditions(); - RCDelayCalc::inputPortDelay(port_pin, in_slew, tr, parasitic, dcalc_ap); + RCDelayCalc::inputPortDelay(port_pin, in_slew, rf, parasitic, dcalc_ap); } void @@ -67,7 +67,7 @@ SimpleRCDelayCalc::gateDelay(const LibertyCell *drvr_cell, Slew &drvr_slew) { drvr_parasitic_ = drvr_parasitic; - drvr_tr_ = arc->toTrans()->asRiseFall(); + drvr_rf_ = arc->toTrans()->asRiseFall(); drvr_cell_ = drvr_cell; drvr_library_ = drvr_cell->libertyLibrary(); pvt_ = pvt; @@ -89,9 +89,9 @@ SimpleRCDelayCalc::loadDelay(const Pin *load_pin, if (drvr_parasitic_) parasitics_->findElmore(drvr_parasitic_, load_pin, elmore, elmore_exists); if (elmore_exists) { - if (drvr_library_ && drvr_library_->wireSlewDegradationTable(drvr_tr_)) { + if (drvr_library_ && drvr_library_->wireSlewDegradationTable(drvr_rf_)) { wire_delay1 = elmore; - load_slew1 = drvr_library_->degradeWireSlew(drvr_cell_, drvr_tr_, + load_slew1 = drvr_library_->degradeWireSlew(drvr_cell_, drvr_rf_, pvt_, delayAsFloat(drvr_slew_), delayAsFloat(wire_delay1)); diff --git a/dcalc/SimpleRCDelayCalc.hh b/dcalc/SimpleRCDelayCalc.hh index 4e74482e..ff472d01 100644 --- a/dcalc/SimpleRCDelayCalc.hh +++ b/dcalc/SimpleRCDelayCalc.hh @@ -33,7 +33,7 @@ public: virtual ArcDelayCalc *copy(); virtual void inputPortDelay(const Pin *port_pin, float in_slew, - const TransRiseFall *tr, + const RiseFall *rf, Parasitic *parasitic, const DcalcAnalysisPt *dcalc_ap); virtual void gateDelay(const LibertyCell *drvr_cell, diff --git a/dcalc/UnitDelayCalc.cc b/dcalc/UnitDelayCalc.cc index e8b56a05..4b7aec4e 100644 --- a/dcalc/UnitDelayCalc.cc +++ b/dcalc/UnitDelayCalc.cc @@ -39,7 +39,7 @@ UnitDelayCalc::copy() Parasitic * UnitDelayCalc::findParasitic(const Pin *, - const TransRiseFall *, + const RiseFall *, const DcalcAnalysisPt *) { return nullptr; @@ -48,7 +48,7 @@ UnitDelayCalc::findParasitic(const Pin *, void UnitDelayCalc::inputPortDelay(const Pin *, float, - const TransRiseFall *, + const RiseFall *, Parasitic *, const DcalcAnalysisPt *) { diff --git a/dcalc/UnitDelayCalc.hh b/dcalc/UnitDelayCalc.hh index e3721aa1..834b6325 100644 --- a/dcalc/UnitDelayCalc.hh +++ b/dcalc/UnitDelayCalc.hh @@ -28,7 +28,7 @@ public: UnitDelayCalc(StaState *sta); virtual ArcDelayCalc *copy(); virtual Parasitic *findParasitic(const Pin *drvr_pin, - const TransRiseFall *tr, + const RiseFall *rf, const DcalcAnalysisPt *dcalc_ap); virtual void gateDelay(const LibertyCell *drvr_cell, TimingArc *arc, @@ -56,7 +56,7 @@ public: const DcalcAnalysisPt *dcalc_ap); virtual void inputPortDelay(const Pin *port_pin, float in_slew, - const TransRiseFall *tr, + const RiseFall *rf, Parasitic *parasitic, const DcalcAnalysisPt *dcalc_ap); virtual void checkDelay(const LibertyCell *cell, diff --git a/doc/ApiChanges.txt b/doc/ApiChanges.txt index d7546dfd..aa20adff 100644 --- a/doc/ApiChanges.txt +++ b/doc/ApiChanges.txt @@ -22,6 +22,9 @@ Release 2.0.17 2019/11/11 Network::setVertexIndex renamed to setVertexId Network::vertexIndex renamed to vertexId +TransRiseFall renamed to RiseFall +TransRiseFallBoth renamed to RiseFallBoth + Release 2.0.0 2018/06/11 ------------------------- diff --git a/graph/Graph.cc b/graph/Graph.cc index b6665999..b2443696 100644 --- a/graph/Graph.cc +++ b/graph/Graph.cc @@ -38,14 +38,14 @@ namespace sta { //////////////////////////////////////////////////////////////// Graph::Graph(StaState *sta, - int slew_tr_count, + int slew_rf_count, bool have_arc_delays, DcalcAPIndex ap_count) : StaState(sta), vertices_(nullptr), edges_(nullptr), arc_count_(0), - slew_tr_count_(slew_tr_count), + slew_rf_count_(slew_rf_count), have_arc_delays_(have_arc_delays), ap_count_(ap_count), width_check_annotations_(nullptr), @@ -553,12 +553,12 @@ Graph::clearPrevPaths() const Slew & Graph::slew(const Vertex *vertex, - const TransRiseFall *tr, + const RiseFall *rf, DcalcAPIndex ap_index) { - if (slew_tr_count_) { + if (slew_rf_count_) { int table_index = - (slew_tr_count_ == 1) ? ap_index : ap_index*slew_tr_count_+tr->index(); + (slew_rf_count_ == 1) ? ap_index : ap_index*slew_rf_count_+rf->index(); DelayTable *table = slew_tables_[table_index]; VertexId vertex_id = id(vertex); return table->ref(vertex_id); @@ -571,13 +571,13 @@ Graph::slew(const Vertex *vertex, void Graph::setSlew(Vertex *vertex, - const TransRiseFall *tr, + const RiseFall *rf, DcalcAPIndex ap_index, const Slew &slew) { - if (slew_tr_count_) { + if (slew_rf_count_) { int table_index = - (slew_tr_count_ == 1) ? ap_index : ap_index*slew_tr_count_+tr->index(); + (slew_rf_count_ == 1) ? ap_index : ap_index*slew_rf_count_+rf->index(); DelayTable *table = slew_tables_[table_index]; VertexId vertex_id = id(vertex); Slew &vertex_slew = table->ref(vertex_id); @@ -707,13 +707,13 @@ Graph::setArcDelay(Edge *edge, const ArcDelay & Graph::wireArcDelay(const Edge *edge, - const TransRiseFall *tr, + const RiseFall *rf, DcalcAPIndex ap_index) { if (have_arc_delays_) { DelayTable *table = arc_delays_[ap_index]; ArcDelay *arc_delays = table->pointer(edge->arcDelays()); - return arc_delays[tr->index()]; + return arc_delays[rf->index()]; } else return delay_zero; @@ -721,14 +721,14 @@ Graph::wireArcDelay(const Edge *edge, void Graph::setWireArcDelay(Edge *edge, - const TransRiseFall *tr, + const RiseFall *rf, DcalcAPIndex ap_index, const ArcDelay &delay) { if (have_arc_delays_) { DelayTable *table = arc_delays_[ap_index]; ArcDelay *arc_delays = table->pointer(edge->arcDelays()); - arc_delays[tr->index()] = delay; + arc_delays[rf->index()] = delay; } } @@ -761,10 +761,10 @@ Graph::setArcDelayAnnotated(Edge *edge, bool Graph::wireDelayAnnotated(Edge *edge, - const TransRiseFall *tr, + const RiseFall *rf, DcalcAPIndex ap_index) const { - size_t index = (edge->arcDelays() + TimingArcSet::wireArcIndex(tr)) * ap_count_ + size_t index = (edge->arcDelays() + TimingArcSet::wireArcIndex(rf)) * ap_count_ + ap_index; if (index >= arc_delay_annotated_.size()) internalError("arc_delay_annotated array bounds exceeded"); @@ -773,11 +773,11 @@ Graph::wireDelayAnnotated(Edge *edge, void Graph::setWireDelayAnnotated(Edge *edge, - const TransRiseFall *tr, + const RiseFall *rf, DcalcAPIndex ap_index, bool annotated) { - size_t index = (edge->arcDelays() + TimingArcSet::wireArcIndex(tr)) * ap_count_ + size_t index = (edge->arcDelays() + TimingArcSet::wireArcIndex(rf)) * ap_count_ + ap_index; if (index >= arc_delay_annotated_.size()) internalError("arc_delay_annotated array bounds exceeded"); @@ -850,7 +850,7 @@ Graph::delayAnnotated(Edge *edge) void Graph::makeSlewTables(DcalcAPIndex ap_count) { - DcalcAPIndex tr_ap_count = slew_tr_count_ * ap_count; + DcalcAPIndex tr_ap_count = slew_rf_count_ * ap_count; slew_tables_.resize(tr_ap_count); for (DcalcAPIndex i = 0; i < tr_ap_count; i++) { DelayTable *table = new DelayTable; @@ -867,7 +867,7 @@ Graph::deleteSlewTables() void Graph::makeVertexSlews(Vertex *vertex) { - DcalcAPIndex tr_ap_count = slew_tr_count_ * ap_count_; + DcalcAPIndex tr_ap_count = slew_rf_count_ * ap_count_; for (DcalcAPIndex i = 0; i < tr_ap_count; i++) { DelayTable *table = slew_tables_[i]; // Slews are 1:1 with vertices and use the same object id. @@ -880,7 +880,7 @@ Graph::makeVertexSlews(Vertex *vertex) void Graph::widthCheckAnnotation(const Pin *pin, - const TransRiseFall *tr, + const RiseFall *rf, DcalcAPIndex ap_index, // Return values. float &width, @@ -890,7 +890,7 @@ Graph::widthCheckAnnotation(const Pin *pin, if (width_check_annotations_) { float *widths = width_check_annotations_->findKey(pin); if (widths) { - int index = ap_index * TransRiseFall::index_count + tr->index(); + int index = ap_index * RiseFall::index_count + rf->index(); width = widths[index]; if (width >= 0.0) exists = true; @@ -900,7 +900,7 @@ Graph::widthCheckAnnotation(const Pin *pin, void Graph::setWidthCheckAnnotation(const Pin *pin, - const TransRiseFall *tr, + const RiseFall *rf, DcalcAPIndex ap_index, float width) { @@ -908,14 +908,14 @@ Graph::setWidthCheckAnnotation(const Pin *pin, width_check_annotations_ = new WidthCheckAnnotations; float *widths = width_check_annotations_->findKey(pin); if (widths == nullptr) { - int width_count = TransRiseFall::index_count * ap_count_; + int width_count = RiseFall::index_count * ap_count_; widths = new float[width_count]; // Use negative (illegal) width values to indicate unannotated checks. for (int i = 0; i < width_count; i++) widths[i] = -1; (*width_check_annotations_)[pin] = widths; } - int index = ap_index * TransRiseFall::index_count + tr->index(); + int index = ap_index * RiseFall::index_count + rf->index(); widths[index] = width; } @@ -1091,10 +1091,10 @@ Vertex::setColor(LevelColor color) } bool -Vertex::slewAnnotated(const TransRiseFall *tr, +Vertex::slewAnnotated(const RiseFall *rf, const MinMax *min_max) const { - int index = min_max->index() * transitionCount() + tr->index(); + int index = min_max->index() * transitionCount() + rf->index(); return ((1 << index) & slew_annotated_) != 0; } @@ -1106,14 +1106,14 @@ Vertex::slewAnnotated() const void Vertex::setSlewAnnotated(bool annotated, - const TransRiseFall *tr, + const RiseFall *rf, DcalcAPIndex ap_index) { // Track rise/fall/min/max annotations separately, but after that // only rise/fall. if (ap_index > 1) ap_index = 0; - int index = ap_index * transitionCount() + tr->index(); + int index = ap_index * transitionCount() + rf->index(); if (annotated) slew_annotated_ |= (1 << index); else diff --git a/graph/Graph.hh b/graph/Graph.hh index 6f2ec6e4..31015dc7 100644 --- a/graph/Graph.hh +++ b/graph/Graph.hh @@ -64,13 +64,13 @@ static constexpr ObjectIdx prev_path_null = object_id_null; class Graph : public StaState { public: - // slew_tr_count is + // slew_rf_count is // 0 no slews // 1 one slew for rise/fall // 2 rise/fall slews // ap_count is the dcalc analysis point count. Graph(StaState *sta, - int slew_tr_count, + int slew_rf_count, bool have_arc_delays, DcalcAPIndex ap_count); void makeGraph(); @@ -112,10 +112,10 @@ public: // reported_slews = measured_slews / slew_derate_from_library // Measured slews are between slew_lower_threshold and slew_upper_threshold. virtual const Slew &slew(const Vertex *vertex, - const TransRiseFall *tr, + const RiseFall *rf, DcalcAPIndex ap_index); virtual void setSlew(Vertex *vertex, - const TransRiseFall *tr, + const RiseFall *rf, DcalcAPIndex ap_index, const Slew &slew); @@ -142,10 +142,10 @@ public: ArcDelay delay); // Alias for arcDelays using library wire arcs. virtual const ArcDelay &wireArcDelay(const Edge *edge, - const TransRiseFall *tr, + const RiseFall *rf, DcalcAPIndex ap_index); virtual void setWireArcDelay(Edge *edge, - const TransRiseFall *tr, + const RiseFall *rf, DcalcAPIndex ap_index, const ArcDelay &delay); // Is timing arc delay annotated. @@ -157,10 +157,10 @@ public: DcalcAPIndex ap_index, bool annotated); bool wireDelayAnnotated(Edge *edge, - const TransRiseFall *tr, + const RiseFall *rf, DcalcAPIndex ap_index) const; void setWireDelayAnnotated(Edge *edge, - const TransRiseFall *tr, + const RiseFall *rf, DcalcAPIndex ap_index, bool annotated); // True if any edge arc is annotated. @@ -170,13 +170,13 @@ public: // Sdf width check annotation. void widthCheckAnnotation(const Pin *pin, - const TransRiseFall *tr, + const RiseFall *rf, DcalcAPIndex ap_index, // Return values. float &width, bool &exists); void setWidthCheckAnnotation(const Pin *pin, - const TransRiseFall *tr, + const RiseFall *rf, DcalcAPIndex ap_index, float width); @@ -237,7 +237,7 @@ protected: PrevPathsTable prev_paths_; std::mutex prev_paths_lock_; Vector arc_delay_annotated_; - int slew_tr_count_; + int slew_rf_count_; bool have_arc_delays_; DcalcAPIndex ap_count_; DelayTableSeq slew_tables_; // [ap_index][tr_index][vertex_id] @@ -285,12 +285,12 @@ public: TagGroupIndex tagGroupIndex() const; void setTagGroupIndex(TagGroupIndex tag_index); // Slew is annotated by sdc set_annotated_transition cmd. - bool slewAnnotated(const TransRiseFall *tr, + bool slewAnnotated(const RiseFall *rf, const MinMax *min_max) const; // True if any rise/fall analysis pt slew is annotated. bool slewAnnotated() const; void setSlewAnnotated(bool annotated, - const TransRiseFall *tr, + const RiseFall *rf, DcalcAPIndex ap_index); void removeSlewAnnotated(); // Constant zero/one from simulation. diff --git a/graph/GraphClass.hh b/graph/GraphClass.hh index 1040671d..e84b0f19 100644 --- a/graph/GraphClass.hh +++ b/graph/GraphClass.hh @@ -49,7 +49,7 @@ typedef Vector GraphLoopSeq; // 16,777,215 tags static const int tag_group_index_bits = 24; static const TagGroupIndex tag_group_index_max = (1<index()]; + return models_[rf->index()]; } void -InternalPowerAttrs::setModel(TransRiseFall *tr, +InternalPowerAttrs::setModel(RiseFall *rf, InternalPowerModel *model) { - models_[tr->index()] = model; + models_[rf->index()] = model; } void @@ -77,7 +77,7 @@ InternalPower::InternalPower(LibertyCell *cell, when_(attrs->when()), related_pg_pin_(attrs->relatedPgPin()) { - for (auto tr : TransRiseFall::range()) { + for (auto tr : RiseFall::range()) { int tr_index = tr->index(); models_[tr_index] = attrs->model(tr); } @@ -96,12 +96,12 @@ InternalPower::libertyCell() const } float -InternalPower::power(TransRiseFall *tr, +InternalPower::power(RiseFall *rf, const Pvt *pvt, float in_slew, float load_cap) { - InternalPowerModel *model = models_[tr->index()]; + InternalPowerModel *model = models_[rf->index()]; if (model) return model->power(libertyCell(), pvt, in_slew, load_cap); else diff --git a/liberty/InternalPower.hh b/liberty/InternalPower.hh index 13ccc1f1..38f81240 100644 --- a/liberty/InternalPower.hh +++ b/liberty/InternalPower.hh @@ -34,15 +34,15 @@ public: void deleteContents(); FuncExpr *when() const { return when_; } FuncExpr *&whenRef() { return when_; } - void setModel(TransRiseFall *tr, + void setModel(RiseFall *rf, InternalPowerModel *model); - InternalPowerModel *model(TransRiseFall *tr) const; + InternalPowerModel *model(RiseFall *rf) const; const char *relatedPgPin() const { return related_pg_pin_; } void setRelatedPgPin(const char *related_pg_pin); protected: FuncExpr *when_; - InternalPowerModel *models_[TransRiseFall::index_count]; + InternalPowerModel *models_[RiseFall::index_count]; const char *related_pg_pin_; private: @@ -62,7 +62,7 @@ public: LibertyPort *relatedPort() const { return related_port_; } FuncExpr *when() const { return when_; } const char *relatedPgPin() const { return related_pg_pin_; } - float power(TransRiseFall *tr, + float power(RiseFall *rf, const Pvt *pvt, float in_slew, float load_cap); @@ -72,7 +72,7 @@ protected: LibertyPort *related_port_; FuncExpr *when_; const char *related_pg_pin_; - InternalPowerModel *models_[TransRiseFall::index_count]; + InternalPowerModel *models_[RiseFall::index_count]; private: DISALLOW_COPY_AND_ASSIGN(InternalPower); diff --git a/liberty/Liberty.cc b/liberty/Liberty.cc index cb4abe77..7d022dac 100644 --- a/liberty/Liberty.cc +++ b/liberty/Liberty.cc @@ -94,7 +94,7 @@ LibertyLibrary::LibertyLibrary(const char *name, addTableTemplate(scalar_template, type); } - for (auto tr_index : TransRiseFall::rangeIndex()) { + for (auto tr_index : RiseFall::rangeIndex()) { wire_slew_degradation_tbls_[tr_index] = nullptr; input_threshold_[tr_index] = input_threshold_default_; output_threshold_[tr_index] = output_threshold_default_; @@ -111,7 +111,7 @@ LibertyLibrary::~LibertyLibrary() scale_factors_map_.deleteContents(); delete scale_factors_; - for (auto tr_index : TransRiseFall::rangeIndex()) { + for (auto tr_index : RiseFall::rangeIndex()) { TableModel *model = wire_slew_degradation_tbls_[tr_index]; delete model; } @@ -278,28 +278,28 @@ LibertyLibrary::scaleFactor(ScaleFactorType type, void LibertyLibrary::setWireSlewDegradationTable(TableModel *model, - TransRiseFall *tr) + RiseFall *rf) { - int tr_index = tr->index(); + int tr_index = rf->index(); if (wire_slew_degradation_tbls_[tr_index]) delete wire_slew_degradation_tbls_[tr_index]; wire_slew_degradation_tbls_[tr_index] = model; } TableModel * -LibertyLibrary::wireSlewDegradationTable(const TransRiseFall *tr) const +LibertyLibrary::wireSlewDegradationTable(const RiseFall *rf) const { - return wire_slew_degradation_tbls_[tr->index()]; + return wire_slew_degradation_tbls_[rf->index()]; } float LibertyLibrary::degradeWireSlew(const LibertyCell *cell, - const TransRiseFall *tr, + const RiseFall *rf, const Pvt *pvt, float in_slew, float wire_delay) const { - const TableModel *model = wireSlewDegradationTable(tr); + const TableModel *model = wireSlewDegradationTable(rf); if (model) return degradeWireSlew(cell, pvt, model, in_slew, wire_delay); else @@ -450,64 +450,64 @@ LibertyLibrary::setDefaultOutputPinCap(float cap) } void -LibertyLibrary::defaultIntrinsic(const TransRiseFall *tr, +LibertyLibrary::defaultIntrinsic(const RiseFall *rf, // Return values. float &intrinsic, bool &exists) const { - default_intrinsic_.value(tr, intrinsic, exists); + default_intrinsic_.value(rf, intrinsic, exists); } void -LibertyLibrary::setDefaultIntrinsic(const TransRiseFall *tr, +LibertyLibrary::setDefaultIntrinsic(const RiseFall *rf, float value) { - default_intrinsic_.setValue(tr, value); + default_intrinsic_.setValue(rf, value); } void -LibertyLibrary::defaultPinResistance(const TransRiseFall *tr, +LibertyLibrary::defaultPinResistance(const RiseFall *rf, const PortDirection *dir, // Return values. float &res, bool &exists) const { if (dir->isAnyTristate()) - defaultBidirectPinRes(tr, res, exists); + defaultBidirectPinRes(rf, res, exists); else - defaultOutputPinRes(tr, res, exists); + defaultOutputPinRes(rf, res, exists); } void -LibertyLibrary::defaultBidirectPinRes(const TransRiseFall *tr, +LibertyLibrary::defaultBidirectPinRes(const RiseFall *rf, // Return values. float &res, bool &exists) const { - return default_inout_pin_res_.value(tr, res, exists); + return default_inout_pin_res_.value(rf, res, exists); } void -LibertyLibrary::setDefaultBidirectPinRes(const TransRiseFall *tr, +LibertyLibrary::setDefaultBidirectPinRes(const RiseFall *rf, float value) { - default_inout_pin_res_.setValue(tr, value); + default_inout_pin_res_.setValue(rf, value); } void -LibertyLibrary::defaultOutputPinRes(const TransRiseFall *tr, +LibertyLibrary::defaultOutputPinRes(const RiseFall *rf, // Return values. float &res, bool &exists) const { - default_output_pin_res_.value(tr, res, exists); + default_output_pin_res_.value(rf, res, exists); } void -LibertyLibrary::setDefaultOutputPinRes(const TransRiseFall *tr, +LibertyLibrary::setDefaultOutputPinRes(const RiseFall *rf, float value) { - default_output_pin_res_.setValue(tr, value); + default_output_pin_res_.setValue(rf, value); } void @@ -595,55 +595,55 @@ LibertyLibrary::setDefaultOperatingConditions(OperatingConditions *op_cond) } float -LibertyLibrary::inputThreshold(const TransRiseFall *tr) const +LibertyLibrary::inputThreshold(const RiseFall *rf) const { - return input_threshold_[tr->index()]; + return input_threshold_[rf->index()]; } void -LibertyLibrary::setInputThreshold(const TransRiseFall *tr, +LibertyLibrary::setInputThreshold(const RiseFall *rf, float th) { - input_threshold_[tr->index()] = th; + input_threshold_[rf->index()] = th; } float -LibertyLibrary::outputThreshold(const TransRiseFall *tr) const +LibertyLibrary::outputThreshold(const RiseFall *rf) const { - return output_threshold_[tr->index()]; + return output_threshold_[rf->index()]; } void -LibertyLibrary::setOutputThreshold(const TransRiseFall *tr, +LibertyLibrary::setOutputThreshold(const RiseFall *rf, float th) { - output_threshold_[tr->index()] = th; + output_threshold_[rf->index()] = th; } float -LibertyLibrary::slewLowerThreshold(const TransRiseFall *tr) const +LibertyLibrary::slewLowerThreshold(const RiseFall *rf) const { - return slew_lower_threshold_[tr->index()]; + return slew_lower_threshold_[rf->index()]; } void -LibertyLibrary::setSlewLowerThreshold(const TransRiseFall *tr, +LibertyLibrary::setSlewLowerThreshold(const RiseFall *rf, float th) { - slew_lower_threshold_[tr->index()] = th; + slew_lower_threshold_[rf->index()] = th; } float -LibertyLibrary::slewUpperThreshold(const TransRiseFall *tr) const +LibertyLibrary::slewUpperThreshold(const RiseFall *rf) const { - return slew_upper_threshold_[tr->index()]; + return slew_upper_threshold_[rf->index()]; } void -LibertyLibrary::setSlewUpperThreshold(const TransRiseFall *tr, +LibertyLibrary::setSlewUpperThreshold(const RiseFall *rf, float th) { - slew_upper_threshold_[tr->index()] = th; + slew_upper_threshold_[rf->index()] = th; } float @@ -1507,7 +1507,7 @@ class LatchEnable public: LatchEnable(LibertyPort *data, LibertyPort *enable, - TransRiseFall *enable_tr, + RiseFall *enable_rf, FuncExpr *enable_func, LibertyPort *output, TimingArcSet *d_to_q, @@ -1517,7 +1517,7 @@ public: LibertyPort *output() const { return output_; } LibertyPort *enable() const { return enable_; } FuncExpr *enableFunc() const { return enable_func_; } - TransRiseFall *enableTransition() const { return enable_tr_; } + RiseFall *enableTransition() const { return enable_rf_; } TimingArcSet *dToQ() const { return d_to_q_; } TimingArcSet *enToQ() const { return en_to_q_; } TimingArcSet *setupCheck() const { return setup_check_; } @@ -1527,7 +1527,7 @@ private: LibertyPort *data_; LibertyPort *enable_; - TransRiseFall *enable_tr_; + RiseFall *enable_rf_; FuncExpr *enable_func_; LibertyPort *output_; TimingArcSet *d_to_q_; @@ -1537,7 +1537,7 @@ private: LatchEnable::LatchEnable(LibertyPort *data, LibertyPort *enable, - TransRiseFall *enable_tr, + RiseFall *enable_rf, FuncExpr *enable_func, LibertyPort *output, TimingArcSet *d_to_q, @@ -1545,7 +1545,7 @@ LatchEnable::LatchEnable(LibertyPort *data, TimingArcSet *setup_check) : data_(data), enable_(enable), - enable_tr_(enable_tr), + enable_rf_(enable_rf), enable_func_(enable_func), output_(output), d_to_q_(d_to_q), @@ -1583,38 +1583,38 @@ LibertyCell::makeLatchEnables(Report *report, TimingArcSetArcIterator check_arc_iter(setup_check); if (check_arc_iter.hasNext()) { TimingArc *check_arc = check_arc_iter.next(); - TransRiseFall *en_tr = latch_enable->enableTransition(); - TransRiseFall *check_tr = check_arc->fromTrans()->asRiseFall(); - if (check_tr == en_tr) { + RiseFall *en_rf = latch_enable->enableTransition(); + RiseFall *check_rf = check_arc->fromTrans()->asRiseFall(); + if (check_rf == en_rf) { report->warn("cell %s/%s %s -> %s latch enable %s_edge timing arc is inconsistent with %s -> %s setup_%s check.\n", library_->name(), name_, en->name(), q->name(), - en_tr == TransRiseFall::rise()?"rising":"falling", + en_rf == RiseFall::rise()?"rising":"falling", en->name(), d->name(), - check_tr==TransRiseFall::rise()?"rising":"falling"); + check_rf==RiseFall::rise()?"rising":"falling"); } FuncExpr *en_func = latch_enable->enableFunc(); if (en_func) { TimingSense en_sense = en_func->portTimingSense(en); if (en_sense == TimingSense::positive_unate - && en_tr != TransRiseFall::rise()) + && en_rf != RiseFall::rise()) report->warn("cell %s/%s %s -> %s latch enable %s_edge is inconsistent with latch group enable function positive sense.\n", library_->name(), name_, en->name(), q->name(), - en_tr == TransRiseFall::rise()?"rising":"falling"); + en_rf == RiseFall::rise()?"rising":"falling"); else if (en_sense == TimingSense::negative_unate - && en_tr != TransRiseFall::fall()) + && en_rf != RiseFall::fall()) report->warn("cell %s/%s %s -> %s latch enable %s_edge is inconsistent with latch group enable function negative sense.\n", library_->name(), name_, en->name(), q->name(), - en_tr == TransRiseFall::rise()?"rising":"falling"); + en_rf == RiseFall::rise()?"rising":"falling"); } break; } @@ -1651,9 +1651,9 @@ LibertyCell::makeLatchEnable(LibertyPort *d, TimingArcSet *setup_check, Debug *debug) { - TransRiseFall *en_tr = en_to_q->isRisingFallingEdge(); + RiseFall *en_rf = en_to_q->isRisingFallingEdge(); FuncExpr *en_func = findLatchEnableFunc(d, en); - LatchEnable *latch_enable = new LatchEnable(d, en, en_tr, en_func, q, + LatchEnable *latch_enable = new LatchEnable(d, en, en_rf, en_func, q, d_to_q, en_to_q, setup_check); // Multiple enables for D->Q pairs are not supported. if (latch_d_to_q_map_[d_to_q]) @@ -1720,18 +1720,18 @@ LibertyCell::latchEnable(TimingArcSet *d_to_q_set, // Return values. LibertyPort *&enable_port, FuncExpr *&enable_func, - TransRiseFall *&enable_tr) const + RiseFall *&enable_rf) const { enable_port = nullptr; LatchEnable *latch_enable = latch_d_to_q_map_.findKey(d_to_q_set); if (latch_enable) { enable_port = latch_enable->enable(); enable_func = latch_enable->enableFunc(); - enable_tr = latch_enable->enableTransition(); + enable_rf = latch_enable->enableTransition(); } } -TransRiseFall * +RiseFall * LibertyCell::latchCheckEnableTrans(TimingArcSet *check_set) { LatchEnable *latch_enable = latch_check_map_.findKey(check_set); @@ -1817,8 +1817,8 @@ LibertyPort::LibertyPort(LibertyCell *cell, is_disabled_constraint_(false) { liberty_port_ = this; - min_pulse_width_[TransRiseFall::riseIndex()] = 0.0; - min_pulse_width_[TransRiseFall::fallIndex()] = 0.0; + min_pulse_width_[RiseFall::riseIndex()] = 0.0; + min_pulse_width_[RiseFall::fallIndex()] = 0.0; } LibertyPort::~LibertyPort() @@ -1855,34 +1855,34 @@ LibertyPort::findLibertyBusBit(int index) const void LibertyPort::setCapacitance(float cap) { - setCapacitance(TransRiseFall::rise(), MinMax::min(), cap); - setCapacitance(TransRiseFall::fall(), MinMax::min(), cap); - setCapacitance(TransRiseFall::rise(), MinMax::max(), cap); - setCapacitance(TransRiseFall::fall(), MinMax::max(), cap); + setCapacitance(RiseFall::rise(), MinMax::min(), cap); + setCapacitance(RiseFall::fall(), MinMax::min(), cap); + setCapacitance(RiseFall::rise(), MinMax::max(), cap); + setCapacitance(RiseFall::fall(), MinMax::max(), cap); } void -LibertyPort::setCapacitance(const TransRiseFall *tr, +LibertyPort::setCapacitance(const RiseFall *rf, const MinMax *min_max, float cap) { - capacitance_.setValue(tr, min_max, cap); + capacitance_.setValue(rf, min_max, cap); if (hasMembers()) { LibertyPortMemberIterator member_iter(this); while (member_iter.hasNext()) { LibertyPort *port_bit = member_iter.next(); - port_bit->setCapacitance(tr, min_max, cap); + port_bit->setCapacitance(rf, min_max, cap); } } } float -LibertyPort::capacitance(const TransRiseFall *tr, +LibertyPort::capacitance(const RiseFall *rf, const MinMax *min_max) const { float cap; bool exists; - capacitance_.value(tr, min_max, cap, exists); + capacitance_.value(rf, min_max, cap, exists); if (exists) return cap; else @@ -1890,17 +1890,17 @@ LibertyPort::capacitance(const TransRiseFall *tr, } void -LibertyPort::capacitance(const TransRiseFall *tr, +LibertyPort::capacitance(const RiseFall *rf, const MinMax *min_max, // Return values. float &cap, bool &exists) const { - capacitance_.value(tr, min_max, cap, exists); + capacitance_.value(rf, min_max, cap, exists); } float -LibertyPort::capacitance(const TransRiseFall *tr, +LibertyPort::capacitance(const RiseFall *rf, const MinMax *min_max, const OperatingConditions *op_cond, const Pvt *pvt) const @@ -1910,10 +1910,10 @@ LibertyPort::capacitance(const TransRiseFall *tr, // Scaled capacitance is not derated because scale factors are wrt // nominal pvt. if (scaled_port) - return scaled_port->capacitance(tr, min_max); + return scaled_port->capacitance(rf, min_max); } LibertyLibrary *lib = liberty_cell_->libertyLibrary(); - float cap = capacitance(tr, min_max); + float cap = capacitance(rf, min_max); return cap * lib->scaleFactor(ScaleFactorType::pin_cap, liberty_cell_, pvt); } @@ -1927,7 +1927,7 @@ LibertyPort::capacitanceIsOneValue() const // Use the min/max "drive" for all the timing arcs in the cell. float -LibertyPort::driveResistance(const TransRiseFall *tr, +LibertyPort::driveResistance(const RiseFall *rf, const MinMax *min_max) const { float max_drive = min_max->initValue(); @@ -1939,8 +1939,8 @@ LibertyPort::driveResistance(const TransRiseFall *tr, TimingArcSetArcIterator arc_iter(set); while (arc_iter.hasNext()) { TimingArc *arc = arc_iter.next(); - if (tr == nullptr - || arc->toTrans()->asRiseFall() == tr) { + if (rf == nullptr + || arc->toTrans()->asRiseFall() == rf) { GateTimingModel *model = dynamic_cast(arc->model()); if (model) { float drive = model->driveResistance(liberty_cell_, nullptr); @@ -2077,7 +2077,7 @@ LibertyPort::setMinPeriod(float min_period) } void -LibertyPort::minPulseWidth(const TransRiseFall *hi_low, +LibertyPort::minPulseWidth(const RiseFall *hi_low, const OperatingConditions *op_cond, const Pvt *pvt, float &min_width, @@ -2099,7 +2099,7 @@ LibertyPort::minPulseWidth(const TransRiseFall *hi_low, } void -LibertyPort::minPulseWidth(const TransRiseFall *hi_low, +LibertyPort::minPulseWidth(const RiseFall *hi_low, float &min_width, bool &exists) const { @@ -2109,7 +2109,7 @@ LibertyPort::minPulseWidth(const TransRiseFall *hi_low, } void -LibertyPort::setMinPulseWidth(TransRiseFall *hi_low, +LibertyPort::setMinPulseWidth(RiseFall *hi_low, float min_width) { int hi_low_index = hi_low->index(); @@ -2202,8 +2202,8 @@ LibertyPort::setIsPllFeedbackPin(bool is_pll_feedback_pin) } void -LibertyPort::setPulseClk(TransRiseFall *trigger, - TransRiseFall *sense) +LibertyPort::setPulseClk(RiseFall *trigger, + RiseFall *sense) { pulse_clk_trigger_ = trigger; pulse_clk_sense_ = sense; @@ -2575,7 +2575,7 @@ ScaleFactors::ScaleFactors(const char *name) : { for (int type = 0; type < scale_factor_type_count; type++) { for (int pvt = 0; pvt < int(ScaleFactorPvt::count); pvt++) { - for (auto tr_index : TransRiseFall::rangeIndex()) { + for (auto tr_index : RiseFall::rangeIndex()) { scales_[type][pvt][tr_index] = 0.0; } } @@ -2590,10 +2590,10 @@ ScaleFactors::~ScaleFactors() void ScaleFactors::setScale(ScaleFactorType type, ScaleFactorPvt pvt, - TransRiseFall *tr, + RiseFall *rf, float scale) { - scales_[int(type)][int(pvt)][tr->index()] = scale; + scales_[int(type)][int(pvt)][rf->index()] = scale; } void @@ -2607,9 +2607,9 @@ ScaleFactors::setScale(ScaleFactorType type, float ScaleFactors::scale(ScaleFactorType type, ScaleFactorPvt pvt, - TransRiseFall *tr) + RiseFall *rf) { - return scales_[int(type)][int(pvt)][tr->index()]; + return scales_[int(type)][int(pvt)][rf->index()]; } float @@ -2644,8 +2644,8 @@ ScaleFactors::print() || scaleFactorTypeRiseFallPrefix(type) || scaleFactorTypeLowHighSuffix(type)) { printf(" %.3f,%.3f", - scales_[type_index][pvt_index][TransRiseFall::riseIndex()], - scales_[type_index][pvt_index][TransRiseFall::fallIndex()]); + scales_[type_index][pvt_index][RiseFall::riseIndex()], + scales_[type_index][pvt_index][RiseFall::fallIndex()]); } else { printf(" %.3f", @@ -2714,7 +2714,7 @@ OcvDerate::OcvDerate(const char *name) : name_(name) { for (auto el_index : EarlyLate::rangeIndex()) { - for (auto tr_index : TransRiseFall::rangeIndex()) { + for (auto tr_index : RiseFall::rangeIndex()) { derate_[tr_index][el_index][int(PathType::clk)] = nullptr; derate_[tr_index][el_index][int(PathType::data)] = nullptr; } @@ -2728,7 +2728,7 @@ OcvDerate::~OcvDerate() // Collect them in a set to avoid duplicate deletes. Set models; for (auto el_index : EarlyLate::rangeIndex()) { - for (auto tr_index : TransRiseFall::rangeIndex()) { + for (auto tr_index : RiseFall::rangeIndex()) { Table *derate; derate = derate_[tr_index][el_index][int(PathType::clk)]; if (derate) @@ -2746,20 +2746,20 @@ OcvDerate::~OcvDerate() } Table * -OcvDerate::derateTable(const TransRiseFall *tr, +OcvDerate::derateTable(const RiseFall *rf, const EarlyLate *early_late, PathType path_type) { - return derate_[tr->index()][early_late->index()][int(path_type)]; + return derate_[rf->index()][early_late->index()][int(path_type)]; } void -OcvDerate::setDerateTable(const TransRiseFall *tr, +OcvDerate::setDerateTable(const RiseFall *rf, const EarlyLate *early_late, const PathType path_type, Table *derate) { - derate_[tr->index()][early_late->index()][int(path_type)] = derate; + derate_[rf->index()][early_late->index()][int(path_type)] = derate; } //////////////////////////////////////////////////////////////// diff --git a/liberty/Liberty.hh b/liberty/Liberty.hh index 2bc16329..d74a5da0 100644 --- a/liberty/Liberty.hh +++ b/liberty/Liberty.hh @@ -150,10 +150,10 @@ public: const LibertyCell *cell, const Pvt *pvt) const; void setWireSlewDegradationTable(TableModel *model, - TransRiseFall *tr); - TableModel *wireSlewDegradationTable(const TransRiseFall *tr) const; + RiseFall *rf); + TableModel *wireSlewDegradationTable(const RiseFall *rf) const; float degradeWireSlew(const LibertyCell *cell, - const TransRiseFall *tr, + const RiseFall *rf, const Pvt *pvt, float in_slew, float wire_delay) const; @@ -168,29 +168,29 @@ public: float defaultBidirectPinCap() const { return default_bidirect_pin_cap_; } void setDefaultBidirectPinCap(float cap); - void defaultIntrinsic(const TransRiseFall *tr, + void defaultIntrinsic(const RiseFall *rf, // Return values. float &intrisic, bool &exists) const; - void setDefaultIntrinsic(const TransRiseFall *tr, + void setDefaultIntrinsic(const RiseFall *rf, float value); // Uses defaultOutputPinRes or defaultBidirectPinRes based on dir. - void defaultPinResistance(const TransRiseFall *tr, + void defaultPinResistance(const RiseFall *rf, const PortDirection *dir, // Return values. float &res, bool &exists) const; - void defaultBidirectPinRes(const TransRiseFall *tr, + void defaultBidirectPinRes(const RiseFall *rf, // Return values. float &res, bool &exists) const; - void setDefaultBidirectPinRes(const TransRiseFall *tr, + void setDefaultBidirectPinRes(const RiseFall *rf, float value); - void defaultOutputPinRes(const TransRiseFall *tr, + void defaultOutputPinRes(const RiseFall *rf, // Return values. float &res, bool &exists) const; - void setDefaultOutputPinRes(const TransRiseFall *tr, + void setDefaultOutputPinRes(const RiseFall *rf, float value); void defaultMaxSlew(float &slew, @@ -206,18 +206,18 @@ public: void setDefaultFanoutLoad(float load); // Logic thresholds. - float inputThreshold(const TransRiseFall *tr) const; - void setInputThreshold(const TransRiseFall *tr, + float inputThreshold(const RiseFall *rf) const; + void setInputThreshold(const RiseFall *rf, float th); - float outputThreshold(const TransRiseFall *tr) const; - void setOutputThreshold(const TransRiseFall *tr, + float outputThreshold(const RiseFall *rf) const; + void setOutputThreshold(const RiseFall *rf, float th); // Slew thresholds (measured). - float slewLowerThreshold(const TransRiseFall *tr) const; - void setSlewLowerThreshold(const TransRiseFall *tr, + float slewLowerThreshold(const RiseFall *rf) const; + void setSlewLowerThreshold(const RiseFall *rf, float th); - float slewUpperThreshold(const TransRiseFall *tr) const; - void setSlewUpperThreshold(const TransRiseFall *tr, + float slewUpperThreshold(const RiseFall *rf) const; + void setSlewUpperThreshold(const RiseFall *rf, float th); // The library and delay calculator use the liberty slew upper/lower // (measured) thresholds for the table axes and value. These slews @@ -299,7 +299,7 @@ protected: float nominal_temperature_; ScaleFactors *scale_factors_; ScaleFactorsMap scale_factors_map_; - TableModel *wire_slew_degradation_tbls_[TransRiseFall::index_count]; + TableModel *wire_slew_degradation_tbls_[RiseFall::index_count]; float default_input_pin_cap_; float default_output_pin_cap_; float default_bidirect_pin_cap_; @@ -313,10 +313,10 @@ protected: bool default_max_fanout_exists_; float default_max_slew_; bool default_max_slew_exists_; - float input_threshold_[TransRiseFall::index_count]; - float output_threshold_[TransRiseFall::index_count]; - float slew_lower_threshold_[TransRiseFall::index_count]; - float slew_upper_threshold_[TransRiseFall::index_count]; + float input_threshold_[RiseFall::index_count]; + float output_threshold_[RiseFall::index_count]; + float slew_lower_threshold_[RiseFall::index_count]; + float slew_upper_threshold_[RiseFall::index_count]; float slew_derate_from_library_; WireloadMap wireloads_; Wireload *default_wire_load_; @@ -442,8 +442,8 @@ public: // Return values. LibertyPort *&enable_port, FuncExpr *&enable_func, - TransRiseFall *&enable_tr) const; - TransRiseFall *latchCheckEnableTrans(TimingArcSet *check_set); + RiseFall *&enable_rf) const; + RiseFall *latchCheckEnableTrans(TimingArcSet *check_set); bool isDisabledConstraint() const { return is_disabled_constraint_; } LibertyCell *cornerCell(int ap_index); @@ -638,25 +638,25 @@ public: LibertyCell *libertyCell() const { return liberty_cell_; } LibertyPort *findLibertyMember(int index) const; LibertyPort *findLibertyBusBit(int index) const; - float capacitance(const TransRiseFall *tr, + float capacitance(const RiseFall *rf, const MinMax *min_max) const; - void capacitance(const TransRiseFall *tr, + void capacitance(const RiseFall *rf, const MinMax *min_max, // Return values. float &cap, bool &exists) const; // Capacitance at op_cond derated by library/cell scale factors // using pvt. - float capacitance(const TransRiseFall *tr, + float capacitance(const RiseFall *rf, const MinMax *min_max, const OperatingConditions *op_cond, const Pvt *pvt) const; bool capacitanceIsOneValue() const; void setCapacitance(float cap); - void setCapacitance(const TransRiseFall *tr, + void setCapacitance(const RiseFall *rf, const MinMax *min_max, float cap); - float driveResistance(const TransRiseFall *tr, + float driveResistance(const RiseFall *rf, const MinMax *min_max) const; // Max of rise/fall. float driveResistance() const; @@ -694,16 +694,16 @@ public: bool &exists) const; void setMinPeriod(float min_period); // high = rise, low = fall - void minPulseWidth(const TransRiseFall *hi_low, + void minPulseWidth(const RiseFall *hi_low, const OperatingConditions *op_cond, const Pvt *pvt, float &min_width, bool &exists) const; // Unscaled value. - void minPulseWidth(const TransRiseFall *hi_low, + void minPulseWidth(const RiseFall *hi_low, float &min_width, bool &exists) const; - void setMinPulseWidth(TransRiseFall *hi_low, + void setMinPulseWidth(RiseFall *hi_low, float min_width); bool isClock() const; void setIsClock(bool is_clk); @@ -721,11 +721,11 @@ public: // Is the clock for timing checks. bool isCheckClk() const { return is_check_clk_; } void setIsCheckClk(bool is_clk); - TransRiseFall *pulseClkTrigger() const { return pulse_clk_trigger_; } + RiseFall *pulseClkTrigger() const { return pulse_clk_trigger_; } // Rise for high, fall for low. - TransRiseFall *pulseClkSense() const { return pulse_clk_sense_; } - void setPulseClk(TransRiseFall *trigger, - TransRiseFall *sense); + RiseFall *pulseClkSense() const { return pulse_clk_sense_; } + void setPulseClk(RiseFall *rfigger, + RiseFall *sense); bool isDisabledConstraint() const { return is_disabled_constraint_; } void setIsDisabledConstraint(bool is_disabled); LibertyPort *cornerPort(int ap_index); @@ -765,14 +765,14 @@ protected: MinMaxFloatValues cap_limit_; // outputs MinMaxFloatValues fanout_limit_; // outputs float min_period_; - float min_pulse_width_[TransRiseFall::index_count]; - TransRiseFall *pulse_clk_trigger_; - TransRiseFall *pulse_clk_sense_; + float min_pulse_width_[RiseFall::index_count]; + RiseFall *pulse_clk_trigger_; + RiseFall *pulse_clk_sense_; const char *related_ground_pin_; const char *related_power_pin_; Vector corner_ports_; - unsigned int min_pulse_width_exists_:TransRiseFall::index_count; + unsigned int min_pulse_width_exists_:RiseFall::index_count; bool min_period_exists_:1; bool is_clk_:1; bool is_reg_clk_:1; @@ -864,7 +864,7 @@ public: const char *name() const { return name_; } float scale(ScaleFactorType type, ScaleFactorPvt pvt, - TransRiseFall *tr); + RiseFall *rf); float scale(ScaleFactorType type, ScaleFactorPvt pvt, int tr_index); @@ -872,7 +872,7 @@ public: ScaleFactorPvt pvt); void setScale(ScaleFactorType type, ScaleFactorPvt pvt, - TransRiseFall *tr, + RiseFall *rf, float scale); void setScale(ScaleFactorType type, ScaleFactorPvt pvt, @@ -881,7 +881,7 @@ public: protected: const char *name_; - float scales_[scale_factor_type_count][int(ScaleFactorPvt::count)][TransRiseFall::index_count]; + float scales_[scale_factor_type_count][int(ScaleFactorPvt::count)][RiseFall::index_count]; private: DISALLOW_COPY_AND_ASSIGN(ScaleFactors); @@ -1024,10 +1024,10 @@ public: OcvDerate(const char *name); ~OcvDerate(); const char *name() const { return name_; } - Table *derateTable(const TransRiseFall *tr, + Table *derateTable(const RiseFall *rf, const EarlyLate *early_late, PathType path_type); - void setDerateTable(const TransRiseFall *tr, + void setDerateTable(const RiseFall *rf, const EarlyLate *early_late, PathType path_type, Table *derate); @@ -1035,7 +1035,7 @@ public: private: const char *name_; // [rf_type][derate_type][path_type] - Table *derate_[TransRiseFall::index_count][EarlyLate::index_count][path_type_count]; + Table *derate_[RiseFall::index_count][EarlyLate::index_count][path_type_count]; }; // Power/ground port. diff --git a/liberty/LibertyBuilder.cc b/liberty/LibertyBuilder.cc index ad38c95d..0423d5f9 100644 --- a/liberty/LibertyBuilder.cc +++ b/liberty/LibertyBuilder.cc @@ -143,47 +143,47 @@ LibertyBuilder::makeTimingArcs(LibertyCell *cell, true, false, attrs); case TimingType::setup_rising: return makeFromTransitionArcs(cell, from_port, to_port, related_out, - TransRiseFall::rise(), TimingRole::setup(), + RiseFall::rise(), TimingRole::setup(), attrs); case TimingType::setup_falling: return makeFromTransitionArcs(cell, from_port, to_port, related_out, - TransRiseFall::fall(), TimingRole::setup(), + RiseFall::fall(), TimingRole::setup(), attrs); case TimingType::hold_rising: return makeFromTransitionArcs(cell, from_port, to_port, related_out, - TransRiseFall::rise(), TimingRole::hold(), + RiseFall::rise(), TimingRole::hold(), attrs); case TimingType::hold_falling: return makeFromTransitionArcs(cell, from_port, to_port, related_out, - TransRiseFall::fall(), TimingRole::hold(), + RiseFall::fall(), TimingRole::hold(), attrs); case TimingType::rising_edge: return makeRegLatchArcs(cell, from_port, to_port, related_out, - TransRiseFall::rise(), attrs); + RiseFall::rise(), attrs); case TimingType::falling_edge: return makeRegLatchArcs(cell, from_port, to_port, related_out, - TransRiseFall::fall(), attrs); + RiseFall::fall(), attrs); case TimingType::preset: return makePresetClrArcs(cell, from_port, to_port, related_out, - TransRiseFall::rise(), attrs); + RiseFall::rise(), attrs); case TimingType::clear: return makePresetClrArcs(cell, from_port, to_port, related_out, - TransRiseFall::fall(), attrs); + RiseFall::fall(), attrs); case TimingType::recovery_rising: return makeFromTransitionArcs(cell, from_port, to_port, related_out, - TransRiseFall::rise(),TimingRole::recovery(), + RiseFall::rise(),TimingRole::recovery(), attrs); case TimingType::recovery_falling: return makeFromTransitionArcs(cell, from_port, to_port, related_out, - TransRiseFall::fall(),TimingRole::recovery(), + RiseFall::fall(),TimingRole::recovery(), attrs); case TimingType::removal_rising: return makeFromTransitionArcs(cell, from_port, to_port, related_out, - TransRiseFall::rise(), TimingRole::removal(), + RiseFall::rise(), TimingRole::removal(), attrs); case TimingType::removal_falling: return makeFromTransitionArcs(cell, from_port, to_port, related_out, - TransRiseFall::fall(), TimingRole::removal(), + RiseFall::fall(), TimingRole::removal(), attrs); case TimingType::three_state_disable: return makeTristateDisableArcs(cell, from_port, to_port, related_out, @@ -205,28 +205,28 @@ LibertyBuilder::makeTimingArcs(LibertyCell *cell, true, false, attrs); case TimingType::skew_falling: return makeFromTransitionArcs(cell, from_port, to_port, related_out, - TransRiseFall::fall(), TimingRole::skew(), + RiseFall::fall(), TimingRole::skew(), attrs); case TimingType::skew_rising: return makeFromTransitionArcs(cell, from_port, to_port, related_out, - TransRiseFall::rise(), TimingRole::skew(), + RiseFall::rise(), TimingRole::skew(), attrs); case TimingType::non_seq_setup_rising: return makeFromTransitionArcs(cell, from_port, to_port, related_out, - TransRiseFall::rise(), + RiseFall::rise(), TimingRole::nonSeqSetup(), attrs); case TimingType::non_seq_setup_falling: return makeFromTransitionArcs(cell, from_port, to_port, related_out, - TransRiseFall::fall(), + RiseFall::fall(), TimingRole::nonSeqSetup(), attrs); case TimingType::non_seq_hold_rising: return makeFromTransitionArcs(cell, from_port, to_port, related_out, - TransRiseFall::rise(), + RiseFall::rise(), TimingRole::nonSeqHold(), attrs); case TimingType::non_seq_hold_falling: return makeFromTransitionArcs(cell, from_port, to_port, related_out, - TransRiseFall::fall(), + RiseFall::fall(), TimingRole::nonSeqHold(), attrs); case TimingType::min_pulse_width: @@ -270,34 +270,34 @@ LibertyBuilder::makeCombinationalArcs(LibertyCell *cell, } } TimingModel *model; - TransRiseFall *to_tr; + RiseFall *to_rf; switch (sense) { case TimingSense::positive_unate: if (to_rise) { - to_tr = TransRiseFall::rise(); - model = attrs->model(to_tr); + to_rf = RiseFall::rise(); + model = attrs->model(to_rf); if (model) - makeTimingArc(arc_set, TransRiseFall::rise(), to_tr, model); + makeTimingArc(arc_set, RiseFall::rise(), to_rf, model); } if (to_fall) { - to_tr = TransRiseFall::fall(); - model = attrs->model(to_tr); + to_rf = RiseFall::fall(); + model = attrs->model(to_rf); if (model) - makeTimingArc(arc_set, TransRiseFall::fall(), to_tr, model); + makeTimingArc(arc_set, RiseFall::fall(), to_rf, model); } break; case TimingSense::negative_unate: if (to_fall) { - to_tr = TransRiseFall::fall(); - model = attrs->model(to_tr); + to_rf = RiseFall::fall(); + model = attrs->model(to_rf); if (model) - makeTimingArc(arc_set, TransRiseFall::rise(), to_tr, model); + makeTimingArc(arc_set, RiseFall::rise(), to_rf, model); } if (to_rise) { - to_tr = TransRiseFall::rise(); - model = attrs->model(to_tr); + to_rf = RiseFall::rise(); + model = attrs->model(to_rf); if (model) - makeTimingArc(arc_set, TransRiseFall::fall(), to_tr, model); + makeTimingArc(arc_set, RiseFall::fall(), to_rf, model); } break; case TimingSense::non_unate: @@ -307,19 +307,19 @@ LibertyBuilder::makeCombinationalArcs(LibertyCell *cell, // as in fpga lut cells. case TimingSense::none: if (to_fall) { - to_tr = TransRiseFall::fall(); - model = attrs->model(to_tr); + to_rf = RiseFall::fall(); + model = attrs->model(to_rf); if (model) { - makeTimingArc(arc_set, TransRiseFall::fall(), to_tr, model); - makeTimingArc(arc_set, TransRiseFall::rise(), to_tr, model); + makeTimingArc(arc_set, RiseFall::fall(), to_rf, model); + makeTimingArc(arc_set, RiseFall::rise(), to_rf, model); } } if (to_rise) { - to_tr = TransRiseFall::rise(); - model = attrs->model(to_tr); + to_rf = RiseFall::rise(); + model = attrs->model(to_rf); if (model) { - makeTimingArc(arc_set, TransRiseFall::rise(), to_tr, model); - makeTimingArc(arc_set, TransRiseFall::fall(), to_tr, model); + makeTimingArc(arc_set, RiseFall::rise(), to_rf, model); + makeTimingArc(arc_set, RiseFall::fall(), to_rf, model); } } break; @@ -338,20 +338,20 @@ LibertyBuilder::makeLatchDtoQArcs(LibertyCell *cell, related_out, TimingRole::latchDtoQ(), attrs); TimingModel *model; - TransRiseFall *to_tr = TransRiseFall::rise(); - model = attrs->model(to_tr); + RiseFall *to_rf = RiseFall::rise(); + model = attrs->model(to_rf); TimingSense sense = attrs->timingSense(); if (model) { - TransRiseFall *from_tr = (sense == TimingSense::negative_unate) ? - to_tr->opposite() : to_tr; - makeTimingArc(arc_set, from_tr, to_tr, model); + RiseFall *from_rf = (sense == TimingSense::negative_unate) ? + to_rf->opposite() : to_rf; + makeTimingArc(arc_set, from_rf, to_rf, model); } - to_tr = TransRiseFall::fall(); - model = attrs->model(to_tr); + to_rf = RiseFall::fall(); + model = attrs->model(to_rf); if (model) { - TransRiseFall *from_tr = (sense == TimingSense::negative_unate) ? - to_tr->opposite() : to_tr; - makeTimingArc(arc_set, from_tr, to_tr, model); + RiseFall *from_rf = (sense == TimingSense::negative_unate) ? + to_rf->opposite() : to_rf; + makeTimingArc(arc_set, from_rf, to_rf, model); } return arc_set; } @@ -361,7 +361,7 @@ LibertyBuilder::makeRegLatchArcs(LibertyCell *cell, LibertyPort *from_port, LibertyPort *to_port, LibertyPort *related_out, - TransRiseFall *from_tr, + RiseFall *from_rf, TimingArcAttrs *attrs) { FuncExpr *to_func = to_port->function(); @@ -374,23 +374,23 @@ LibertyBuilder::makeRegLatchArcs(LibertyCell *cell, TimingRole *role = seq->isRegister() ? TimingRole::regClkToQ() : TimingRole::latchEnToQ(); return makeFromTransitionArcs(cell, from_port, to_port, related_out, - from_tr, role, attrs); + from_rf, role, attrs); } else if (seq->isLatch() && seq->data() && seq->data()->hasPort(from_port)) return makeFromTransitionArcs(cell, from_port, to_port, related_out, - from_tr, TimingRole::latchDtoQ(), attrs); + from_rf, TimingRole::latchDtoQ(), attrs); else if ((seq->clear() && seq->clear()->hasPort(from_port)) || (seq->preset() && seq->preset()->hasPort(from_port))) return makeFromTransitionArcs(cell, from_port, to_port, related_out, - from_tr, TimingRole::regSetClr(), attrs); + from_rf, TimingRole::regSetClr(), attrs); } } // No associated ff/latch - assume register clk->q. cell->setHasInferedRegTimingArcs(true); return makeFromTransitionArcs(cell, from_port, to_port, related_out, - from_tr, TimingRole::regClkToQ(), attrs); + from_rf, TimingRole::regClkToQ(), attrs); } TimingArcSet * @@ -398,22 +398,22 @@ LibertyBuilder::makeFromTransitionArcs(LibertyCell *cell, LibertyPort *from_port, LibertyPort *to_port, LibertyPort *related_out, - TransRiseFall *from_tr, + RiseFall *from_rf, TimingRole *role, TimingArcAttrs *attrs) { TimingArcSet *arc_set = makeTimingArcSet(cell, from_port, to_port, related_out, role, attrs); TimingModel *model; - TransRiseFall *to_tr; - to_tr = TransRiseFall::rise(); - model = attrs->model(to_tr); + RiseFall *to_rf; + to_rf = RiseFall::rise(); + model = attrs->model(to_rf); if (model) - makeTimingArc(arc_set, from_tr, to_tr, model); - to_tr = TransRiseFall::fall(); - model = attrs->model(to_tr); + makeTimingArc(arc_set, from_rf, to_rf, model); + to_rf = RiseFall::fall(); + model = attrs->model(to_rf); if (model) - makeTimingArc(arc_set, from_tr, to_tr, model); + makeTimingArc(arc_set, from_rf, to_rf, model); return arc_set; } @@ -422,26 +422,26 @@ LibertyBuilder::makePresetClrArcs(LibertyCell *cell, LibertyPort *from_port, LibertyPort *to_port, LibertyPort *related_out, - TransRiseFall *to_tr, + RiseFall *to_rf, TimingArcAttrs *attrs) { TimingArcSet *arc_set = nullptr; - TimingModel *model = attrs->model(to_tr); + TimingModel *model = attrs->model(to_rf); if (model) { arc_set = makeTimingArcSet(cell, from_port, to_port, related_out, TimingRole::regSetClr(), attrs); - TransRiseFall *opp_tr = to_tr->opposite(); + RiseFall *opp_rf = to_rf->opposite(); switch (attrs->timingSense()) { case TimingSense::positive_unate: - makeTimingArc(arc_set, to_tr, to_tr, model); + makeTimingArc(arc_set, to_rf, to_rf, model); break; case TimingSense::negative_unate: - makeTimingArc(arc_set, opp_tr, to_tr, model); + makeTimingArc(arc_set, opp_rf, to_rf, model); break; case TimingSense::non_unate: case TimingSense::unknown: - makeTimingArc(arc_set, to_tr, to_tr, model); - makeTimingArc(arc_set, opp_tr, to_tr, model); + makeTimingArc(arc_set, to_rf, to_rf, model); + makeTimingArc(arc_set, opp_rf, to_rf, model); break; case TimingSense::none: break; @@ -469,32 +469,32 @@ LibertyBuilder::makeTristateEnableArcs(LibertyCell *cell, if (sense == TimingSense::unknown && tristate_enable) sense = tristate_enable->portTimingSense(from_port); TimingModel *model; - TransRiseFall *to_tr; + RiseFall *to_rf; switch (sense) { case TimingSense::positive_unate: if (to_rise) { - to_tr = TransRiseFall::rise(); - model = attrs->model(to_tr); + to_rf = RiseFall::rise(); + model = attrs->model(to_rf); if (model) makeTimingArc(arc_set, Transition::rise(), Transition::trZ1(), model); } if (to_fall) { - to_tr = TransRiseFall::fall(); - model = attrs->model(to_tr); + to_rf = RiseFall::fall(); + model = attrs->model(to_rf); if (model) makeTimingArc(arc_set, Transition::rise(), Transition::trZ0(), model); } break; case TimingSense::negative_unate: if (to_rise) { - to_tr = TransRiseFall::rise(); - model = attrs->model(to_tr); + to_rf = RiseFall::rise(); + model = attrs->model(to_rf); if (model) makeTimingArc(arc_set, Transition::fall(), Transition::trZ1(), model); } if (to_fall) { - to_tr = TransRiseFall::fall(); - model = attrs->model(to_tr); + to_rf = RiseFall::fall(); + model = attrs->model(to_rf); if (model) makeTimingArc(arc_set, Transition::fall(), Transition::trZ0(), model); } @@ -502,16 +502,16 @@ LibertyBuilder::makeTristateEnableArcs(LibertyCell *cell, case TimingSense::non_unate: case TimingSense::unknown: if (to_rise) { - to_tr = TransRiseFall::rise(); - model = attrs->model(to_tr); + to_rf = RiseFall::rise(); + model = attrs->model(to_rf); if (model) { makeTimingArc(arc_set, Transition::rise(), Transition::trZ1(), model); makeTimingArc(arc_set, Transition::fall(), Transition::trZ1(), model); } } if (to_fall) { - to_tr = TransRiseFall::fall(); - model = attrs->model(to_tr); + to_rf = RiseFall::fall(); + model = attrs->model(to_rf); if (model) { makeTimingArc(arc_set, Transition::rise(), Transition::trZ0(), model); makeTimingArc(arc_set, Transition::fall(), Transition::trZ0(), model); @@ -542,32 +542,32 @@ LibertyBuilder::makeTristateDisableArcs(LibertyCell *cell, if (sense == TimingSense::unknown && tristate_enable) sense = timingSenseOpposite(tristate_enable->portTimingSense(from_port)); TimingModel *model; - TransRiseFall *to_tr; + RiseFall *to_rf; switch (sense) { case TimingSense::positive_unate: if (to_rise) { - to_tr = TransRiseFall::rise(); - model = attrs->model(to_tr); + to_rf = RiseFall::rise(); + model = attrs->model(to_rf); if (model) makeTimingArc(arc_set, Transition::rise(), Transition::tr0Z(), model); } if (to_fall) { - to_tr = TransRiseFall::fall(); - model = attrs->model(to_tr); + to_rf = RiseFall::fall(); + model = attrs->model(to_rf); if (model) makeTimingArc(arc_set, Transition::rise(), Transition::tr1Z(), model); } break; case TimingSense::negative_unate: if (to_rise) { - to_tr = TransRiseFall::rise(); - model = attrs->model(to_tr); + to_rf = RiseFall::rise(); + model = attrs->model(to_rf); if (model) makeTimingArc(arc_set, Transition::fall(), Transition::tr0Z(), model); } if (to_fall) { - to_tr = TransRiseFall::fall(); - model = attrs->model(to_tr); + to_rf = RiseFall::fall(); + model = attrs->model(to_rf); if (model) makeTimingArc(arc_set, Transition::fall(), Transition::tr1Z(), model); } @@ -575,16 +575,16 @@ LibertyBuilder::makeTristateDisableArcs(LibertyCell *cell, case TimingSense::non_unate: case TimingSense::unknown: if (to_rise) { - to_tr = TransRiseFall::rise(); - model = attrs->model(to_tr); + to_rf = RiseFall::rise(); + model = attrs->model(to_rf); if (model) { makeTimingArc(arc_set, Transition::fall(), Transition::tr0Z(), model); makeTimingArc(arc_set, Transition::rise(), Transition::tr0Z(), model); } } if (to_fall) { - to_tr = TransRiseFall::fall(); - model = attrs->model(to_tr); + to_rf = RiseFall::fall(); + model = attrs->model(to_rf); if (model) { makeTimingArc(arc_set, Transition::fall(), Transition::tr1Z(), model); makeTimingArc(arc_set, Transition::rise(), Transition::tr1Z(), model); @@ -610,21 +610,21 @@ LibertyBuilder::makeTimingArcSet(LibertyCell *cell, TimingArc * LibertyBuilder::makeTimingArc(TimingArcSet *set, - TransRiseFall *from_tr, - TransRiseFall *to_tr, + RiseFall *from_rf, + RiseFall *to_rf, TimingModel *model) { - return new TimingArc(set, from_tr->asTransition(), - to_tr->asTransition(), model); + return new TimingArc(set, from_rf->asTransition(), + to_rf->asTransition(), model); } TimingArc * LibertyBuilder::makeTimingArc(TimingArcSet *set, - Transition *from_tr, - Transition *to_tr, + Transition *from_rf, + Transition *to_rf, TimingModel *model) { - return new TimingArc(set, from_tr, to_tr, model); + return new TimingArc(set, from_rf, to_rf, model); } //////////////////////////////////////////////////////////////// diff --git a/liberty/LibertyBuilder.hh b/liberty/LibertyBuilder.hh index 53bd3b61..6d26a342 100644 --- a/liberty/LibertyBuilder.hh +++ b/liberty/LibertyBuilder.hh @@ -83,12 +83,12 @@ protected: TimingRole *role, TimingArcAttrs *attrs); virtual TimingArc *makeTimingArc(TimingArcSet *set, - Transition *from_tr, - Transition *to_tr, + Transition *from_rf, + Transition *to_rf, TimingModel *model); TimingArc *makeTimingArc(TimingArcSet *set, - TransRiseFall *from_tr, - TransRiseFall *to_tr, + RiseFall *from_rf, + RiseFall *to_rf, TimingModel *model); TimingArcSet *makeCombinationalArcs(LibertyCell *cell, LibertyPort *from_port, @@ -106,20 +106,20 @@ protected: LibertyPort *from_port, LibertyPort *to_port, LibertyPort *related_out, - TransRiseFall *from_tr, + RiseFall *from_rf, TimingArcAttrs *attrs); TimingArcSet *makeFromTransitionArcs(LibertyCell *cell, LibertyPort *from_port, LibertyPort *to_port, LibertyPort *related_out, - TransRiseFall *from_tr, + RiseFall *from_rf, TimingRole *role, TimingArcAttrs *attrs); TimingArcSet *makePresetClrArcs(LibertyCell *cell, LibertyPort *from_port, LibertyPort *to_port, LibertyPort *related_out, - TransRiseFall *to_tr, + RiseFall *to_rf, TimingArcAttrs *attrs); TimingArcSet *makeTristateEnableArcs(LibertyCell *cell, LibertyPort *from_port, diff --git a/liberty/LibertyClass.hh b/liberty/LibertyClass.hh index 12c3941d..a4e7be9e 100644 --- a/liberty/LibertyClass.hh +++ b/liberty/LibertyClass.hh @@ -53,8 +53,8 @@ class FuncExpr; class TimingModel; class TimingRole; class Transition; -class TransRiseFall; -class TransRiseFallBoth; +class RiseFall; +class RiseFallBoth; class LibertyCellSequentialIterator; typedef Vector LibertyLibrarySeq; diff --git a/liberty/LibertyReader.cc b/liberty/LibertyReader.cc index 156255ad..93ce2e4e 100644 --- a/liberty/LibertyReader.cc +++ b/liberty/LibertyReader.cc @@ -129,11 +129,11 @@ LibertyReader::readLibertyFile(const char *filename, pg_port_ = nullptr; have_resistance_unit_ = false; - for (auto tr_index : TransRiseFall::rangeIndex()) { - have_input_threshold_[tr_index] = false; - have_output_threshold_[tr_index] = false; - have_slew_lower_threshold_[tr_index] = false; - have_slew_upper_threshold_[tr_index] = false; + for (auto rf_index : RiseFall::rangeIndex()) { + have_input_threshold_[rf_index] = false; + have_output_threshold_[rf_index] = false; + have_slew_lower_threshold_[rf_index] = false; + have_slew_upper_threshold_[rf_index] = false; } parseLibertyFile(filename, this, report_); @@ -457,8 +457,8 @@ LibertyReader::defineScalingFactorVisitors() ScaleFactorPvt pvt = static_cast(pvt_index); const char *pvt_name = scaleFactorPvtName(pvt); if (scaleFactorTypeRiseFallSuffix(type)) { - for (auto tr : TransRiseFall::range()) { - const char *tr_name = (tr == TransRiseFall::rise()) ? "rise":"fall"; + for (auto tr : RiseFall::range()) { + const char *tr_name = (tr == RiseFall::rise()) ? "rise":"fall"; const char *attr_name = stringPrintTmp("k_%s_%s_%s", pvt_name, type_name, @@ -467,8 +467,8 @@ LibertyReader::defineScalingFactorVisitors() } } else if (scaleFactorTypeRiseFallPrefix(type)) { - for (auto tr : TransRiseFall::range()) { - const char *tr_name = (tr == TransRiseFall::rise()) ? "rise":"fall"; + for (auto tr : RiseFall::range()) { + const char *tr_name = (tr == RiseFall::rise()) ? "rise":"fall"; const char *attr_name = stringPrintTmp("k_%s_%s_%s", pvt_name, tr_name, @@ -477,8 +477,8 @@ LibertyReader::defineScalingFactorVisitors() } } else if (scaleFactorTypeLowHighSuffix(type)) { - for (auto tr : TransRiseFall::range()) { - const char *tr_name = (tr == TransRiseFall::rise()) ? "high":"low"; + for (auto tr : RiseFall::range()) { + const char *tr_name = (tr == RiseFall::rise()) ? "high":"low"; const char *attr_name = stringPrintTmp("k_%s_%s_%s", pvt_name, tr_name, @@ -609,7 +609,7 @@ LibertyReader::endLibraryAttrs(LibertyGroup *group) } bool missing_threshold = false; - for (auto tr : TransRiseFall::range()) { + for (auto tr : RiseFall::range()) { int tr_index = tr->index(); if (!have_input_threshold_[tr_index]) { libWarn(group, "input_threshold_pct_%s not found.\n", tr->name()); @@ -969,75 +969,75 @@ LibertyReader::visitDefaultMaxFanout(LibertyAttr *attr) void LibertyReader::visitDefaultIntrinsicRise(LibertyAttr *attr) { - visitDefaultIntrinsic(attr, TransRiseFall::rise()); + visitDefaultIntrinsic(attr, RiseFall::rise()); } void LibertyReader::visitDefaultIntrinsicFall(LibertyAttr *attr) { - visitDefaultIntrinsic(attr, TransRiseFall::fall()); + visitDefaultIntrinsic(attr, RiseFall::fall()); } void LibertyReader::visitDefaultIntrinsic(LibertyAttr *attr, - TransRiseFall *tr) + RiseFall *rf) { if (library_) { float value; bool exists; getAttrFloat(attr, value, exists); if (exists) - library_->setDefaultIntrinsic(tr, value * time_scale_); + library_->setDefaultIntrinsic(rf, value * time_scale_); } } void LibertyReader::visitDefaultInoutPinRiseRes(LibertyAttr *attr) { - visitDefaultInoutPinRes(attr, TransRiseFall::rise()); + visitDefaultInoutPinRes(attr, RiseFall::rise()); } void LibertyReader::visitDefaultInoutPinFallRes(LibertyAttr *attr) { - visitDefaultInoutPinRes(attr, TransRiseFall::fall()); + visitDefaultInoutPinRes(attr, RiseFall::fall()); } void LibertyReader::visitDefaultInoutPinRes(LibertyAttr *attr, - TransRiseFall *tr) + RiseFall *rf) { if (library_) { float value; bool exists; getAttrFloat(attr, value, exists); if (exists) - library_->setDefaultBidirectPinRes(tr, value * res_scale_); + library_->setDefaultBidirectPinRes(rf, value * res_scale_); } } void LibertyReader::visitDefaultOutputPinRiseRes(LibertyAttr *attr) { - visitDefaultOutputPinRes(attr, TransRiseFall::rise()); + visitDefaultOutputPinRes(attr, RiseFall::rise()); } void LibertyReader::visitDefaultOutputPinFallRes(LibertyAttr *attr) { - visitDefaultOutputPinRes(attr, TransRiseFall::fall()); + visitDefaultOutputPinRes(attr, RiseFall::fall()); } void LibertyReader::visitDefaultOutputPinRes(LibertyAttr *attr, - TransRiseFall *tr) + RiseFall *rf) { if (library_) { float value; bool exists; getAttrFloat(attr, value, exists); if (exists) - library_->setDefaultOutputPinRes(tr, value * res_scale_); + library_->setDefaultOutputPinRes(rf, value * res_scale_); } } @@ -1107,105 +1107,105 @@ LibertyReader::visitDefaultOperatingConditions(LibertyAttr *attr) void LibertyReader::visitInputThresholdPctFall(LibertyAttr *attr) { - visitInputThresholdPct(attr, TransRiseFall::fall()); + visitInputThresholdPct(attr, RiseFall::fall()); } void LibertyReader::visitInputThresholdPctRise(LibertyAttr *attr) { - visitInputThresholdPct(attr, TransRiseFall::rise()); + visitInputThresholdPct(attr, RiseFall::rise()); } void LibertyReader::visitInputThresholdPct(LibertyAttr *attr, - TransRiseFall *tr) + RiseFall *rf) { if (library_) { float value; bool exists; getAttrFloat(attr, value, exists); if (exists) - library_->setInputThreshold(tr, value / 100.0F); + library_->setInputThreshold(rf, value / 100.0F); } - have_input_threshold_[tr->index()] = true; + have_input_threshold_[rf->index()] = true; } void LibertyReader::visitOutputThresholdPctFall(LibertyAttr *attr) { - visitOutputThresholdPct(attr, TransRiseFall::fall()); + visitOutputThresholdPct(attr, RiseFall::fall()); } void LibertyReader::visitOutputThresholdPctRise(LibertyAttr *attr) { - visitOutputThresholdPct(attr, TransRiseFall::rise()); + visitOutputThresholdPct(attr, RiseFall::rise()); } void LibertyReader::visitOutputThresholdPct(LibertyAttr *attr, - TransRiseFall *tr) + RiseFall *rf) { if (library_) { float value; bool exists; getAttrFloat(attr, value, exists); if (exists) - library_->setOutputThreshold(tr, value / 100.0F); + library_->setOutputThreshold(rf, value / 100.0F); } - have_output_threshold_[tr->index()] = true; + have_output_threshold_[rf->index()] = true; } void LibertyReader::visitSlewLowerThresholdPctFall(LibertyAttr *attr) { - visitSlewLowerThresholdPct(attr, TransRiseFall::fall()); + visitSlewLowerThresholdPct(attr, RiseFall::fall()); } void LibertyReader::visitSlewLowerThresholdPctRise(LibertyAttr *attr) { - visitSlewLowerThresholdPct(attr, TransRiseFall::rise()); + visitSlewLowerThresholdPct(attr, RiseFall::rise()); } void LibertyReader::visitSlewLowerThresholdPct(LibertyAttr *attr, - TransRiseFall *tr) + RiseFall *rf) { if (library_) { float value; bool exists; getAttrFloat(attr, value, exists); if (exists) - library_->setSlewLowerThreshold(tr, value / 100.0F); + library_->setSlewLowerThreshold(rf, value / 100.0F); } - have_slew_lower_threshold_[tr->index()] = true; + have_slew_lower_threshold_[rf->index()] = true; } void LibertyReader::visitSlewUpperThresholdPctFall(LibertyAttr *attr) { - visitSlewUpperThresholdPct(attr, TransRiseFall::fall()); + visitSlewUpperThresholdPct(attr, RiseFall::fall()); } void LibertyReader::visitSlewUpperThresholdPctRise(LibertyAttr *attr) { - visitSlewUpperThresholdPct(attr, TransRiseFall::rise()); + visitSlewUpperThresholdPct(attr, RiseFall::rise()); } void LibertyReader::visitSlewUpperThresholdPct(LibertyAttr *attr, - TransRiseFall *tr) + RiseFall *rf) { if (library_) { float value; bool exists; getAttrFloat(attr, value, exists); if (exists) - library_->setSlewUpperThreshold(tr, value / 100.0F); + library_->setSlewUpperThreshold(rf, value / 100.0F); } - have_slew_upper_threshold_[tr->index()] = true; + have_slew_upper_threshold_[rf->index()] = true; } void @@ -1440,7 +1440,7 @@ LibertyReader::visitScaleFactorSuffix(LibertyAttr *attr) if (scale_factors_) { ScaleFactorPvt pvt = ScaleFactorPvt::unknown; ScaleFactorType type = ScaleFactorType::unknown; - TransRiseFall *tr = nullptr; + RiseFall *rf = nullptr; // Parse the attribute name. TokenParser parser(attr->name(), "_"); if (parser.hasNext()) @@ -1456,18 +1456,18 @@ LibertyReader::visitScaleFactorSuffix(LibertyAttr *attr) if (parser.hasNext()) { const char *tr_name = parser.next(); if (stringEq(tr_name, "rise")) - tr = TransRiseFall::rise(); + rf = RiseFall::rise(); else if (stringEq(tr_name, "fall")) - tr = TransRiseFall::fall(); + rf = RiseFall::fall(); } if (pvt != ScaleFactorPvt::unknown && type != ScaleFactorType::unknown - && tr) { + && rf) { float value; bool exists; getAttrFloat(attr, value, exists); if (exists) - scale_factors_->setScale(type, pvt, tr, value); + scale_factors_->setScale(type, pvt, rf, value); } } } @@ -1478,7 +1478,7 @@ LibertyReader::visitScaleFactorPrefix(LibertyAttr *attr) if (scale_factors_) { ScaleFactorPvt pvt = ScaleFactorPvt::unknown; ScaleFactorType type = ScaleFactorType::unknown; - TransRiseFall *tr = nullptr; + RiseFall *rf = nullptr; // Parse the attribute name. TokenParser parser(attr->name(), "_"); if (parser.hasNext()) @@ -1490,9 +1490,9 @@ LibertyReader::visitScaleFactorPrefix(LibertyAttr *attr) if (parser.hasNext()) { const char *tr_name = parser.next(); if (stringEq(tr_name, "rise")) - tr = TransRiseFall::rise(); + rf = RiseFall::rise(); else if (stringEq(tr_name, "fall")) - tr = TransRiseFall::fall(); + rf = RiseFall::fall(); } if (parser.hasNext()) { const char *type_name = parser.next(); @@ -1500,12 +1500,12 @@ LibertyReader::visitScaleFactorPrefix(LibertyAttr *attr) } if (pvt != ScaleFactorPvt::unknown && type != ScaleFactorType::unknown - && tr) { + && rf) { float value; bool exists; getAttrFloat(attr, value, exists); if (exists) - scale_factors_->setScale(type, pvt, tr, value); + scale_factors_->setScale(type, pvt, rf, value); } } } @@ -1516,7 +1516,7 @@ LibertyReader::visitScaleFactorHiLow(LibertyAttr *attr) if (scale_factors_) { ScaleFactorPvt pvt = ScaleFactorPvt::unknown; ScaleFactorType type = ScaleFactorType::unknown; - TransRiseFall *tr = nullptr; + RiseFall *rf = nullptr; const char *pvt_name = nullptr; const char *type_name = nullptr; const char *tr_name = nullptr; @@ -1535,18 +1535,18 @@ LibertyReader::visitScaleFactorHiLow(LibertyAttr *attr) if (parser.hasNext()) { tr_name = parser.next(); if (stringEq(tr_name, "high")) - tr = TransRiseFall::rise(); + rf = RiseFall::rise(); else if (stringEq(tr_name, "low")) - tr = TransRiseFall::fall(); + rf = RiseFall::fall(); } if (pvt != ScaleFactorPvt::unknown && type != ScaleFactorType::unknown - && tr) { + && rf) { float value; bool exists; getAttrFloat(attr, value, exists); if (exists) - scale_factors_->setScale(type, pvt, tr, value); + scale_factors_->setScale(type, pvt, rf, value); } } } @@ -2158,7 +2158,7 @@ TimingGroup::makeTimingModels(LibertyLibrary *library, void TimingGroup::makeLinearModels(LibertyLibrary *library) { - for (auto tr : TransRiseFall::range()) { + for (auto tr : RiseFall::range()) { int tr_index = tr->index(); float intr = intrinsic_[tr_index]; bool intr_exists = intrinsic_exists_[tr_index]; @@ -2187,7 +2187,7 @@ TimingGroup::makeLinearModels(LibertyLibrary *library) void TimingGroup::makeTableModels(LibertyReader *visitor) { - for (auto tr : TransRiseFall::range()) { + for (auto tr : RiseFall::range()) { int tr_index = tr->index(); TableModel *cell = cell_[tr_index]; TableModel *constraint = constraint_[tr_index]; @@ -2614,7 +2614,7 @@ void LibertyReader::setPortCapDefault(LibertyPort *port) { for (auto min_max : MinMax::range()) { - for (auto tr : TransRiseFall::range()) { + for (auto tr : RiseFall::range()) { float cap; bool exists; port->capacitance(tr, min_max, cap, exists); @@ -2891,8 +2891,8 @@ LibertyReader::visitRiseCap(LibertyAttr *attr) LibertyPortSeq::Iterator port_iter(ports_); while (port_iter.hasNext()) { LibertyPort *port = port_iter.next(); - port->setCapacitance(TransRiseFall::rise(), MinMax::min(), cap); - port->setCapacitance(TransRiseFall::rise(), MinMax::max(), cap); + port->setCapacitance(RiseFall::rise(), MinMax::min(), cap); + port->setCapacitance(RiseFall::rise(), MinMax::max(), cap); } } } @@ -2910,8 +2910,8 @@ LibertyReader::visitFallCap(LibertyAttr *attr) LibertyPortSeq::Iterator port_iter(ports_); while (port_iter.hasNext()) { LibertyPort *port = port_iter.next(); - port->setCapacitance(TransRiseFall::fall(), MinMax::min(), cap); - port->setCapacitance(TransRiseFall::fall(), MinMax::max(), cap); + port->setCapacitance(RiseFall::fall(), MinMax::min(), cap); + port->setCapacitance(RiseFall::fall(), MinMax::max(), cap); } } } @@ -2930,8 +2930,8 @@ LibertyReader::visitRiseCapRange(LibertyAttr *attr) LibertyPortSeq::Iterator port_iter(ports_); while (port_iter.hasNext()) { LibertyPort *port = port_iter.next(); - port->setCapacitance(TransRiseFall::rise(), MinMax::min(), min); - port->setCapacitance(TransRiseFall::rise(), MinMax::max(), max); + port->setCapacitance(RiseFall::rise(), MinMax::min(), min); + port->setCapacitance(RiseFall::rise(), MinMax::max(), max); } } } @@ -2950,8 +2950,8 @@ LibertyReader::visitFallCapRange(LibertyAttr *attr) LibertyPortSeq::Iterator port_iter(ports_); while (port_iter.hasNext()) { LibertyPort *port = port_iter.next(); - port->setCapacitance(TransRiseFall::fall(), MinMax::min(), min); - port->setCapacitance(TransRiseFall::fall(), MinMax::max(), max); + port->setCapacitance(RiseFall::fall(), MinMax::min(), min); + port->setCapacitance(RiseFall::fall(), MinMax::max(), max); } } } @@ -3083,18 +3083,18 @@ LibertyReader::visitMinPeriod(LibertyAttr *attr) void LibertyReader::visitMinPulseWidthLow(LibertyAttr *attr) { - visitMinPulseWidth(attr, TransRiseFall::fall()); + visitMinPulseWidth(attr, RiseFall::fall()); } void LibertyReader::visitMinPulseWidthHigh(LibertyAttr *attr) { - visitMinPulseWidth(attr, TransRiseFall::rise()); + visitMinPulseWidth(attr, RiseFall::rise()); } void LibertyReader::visitMinPulseWidth(LibertyAttr *attr, - TransRiseFall *tr) + RiseFall *rf) { if (cell_) { float value; @@ -3105,7 +3105,7 @@ LibertyReader::visitMinPulseWidth(LibertyAttr *attr, LibertyPortSeq::Iterator port_iter(ports_); while (port_iter.hasNext()) { LibertyPort *port = port_iter.next(); - port->setMinPulseWidth(tr, value); + port->setMinPulseWidth(rf, value); } } } @@ -3117,23 +3117,23 @@ LibertyReader::visitPulseClock(LibertyAttr *attr) if (cell_) { const char *pulse_clk = getAttrString(attr); if (pulse_clk) { - TransRiseFall *trigger = nullptr; - TransRiseFall *sense = nullptr; + RiseFall *trigger = nullptr; + RiseFall *sense = nullptr; if (stringEq(pulse_clk, "rise_triggered_high_pulse")) { - trigger = TransRiseFall::rise(); - sense = TransRiseFall::rise(); + trigger = RiseFall::rise(); + sense = RiseFall::rise(); } else if (stringEq(pulse_clk, "rise_triggered_low_pulse")) { - trigger = TransRiseFall::rise(); - sense = TransRiseFall::fall(); + trigger = RiseFall::rise(); + sense = RiseFall::fall(); } else if (stringEq(pulse_clk, "fall_triggered_high_pulse")) { - trigger = TransRiseFall::fall(); - sense = TransRiseFall::rise(); + trigger = RiseFall::fall(); + sense = RiseFall::rise(); } else if (stringEq(pulse_clk, "fall_triggered_low_pulse")) { - trigger = TransRiseFall::fall(); - sense = TransRiseFall::fall(); + trigger = RiseFall::fall(); + sense = RiseFall::fall(); } else libWarn(attr, "pulse_latch unknown pulse type.\n"); @@ -3427,7 +3427,7 @@ LibertyReader::endTiming(LibertyGroup *) { if (timing_) { // Set scale factor type in constraint tables. - for (auto tr : TransRiseFall::range()) { + for (auto tr : RiseFall::range()) { TableModel *model = timing_->constraint(tr); if (model) { ScaleFactorType type=timingTypeScaleFactorType(timing_->timingType()); @@ -3592,63 +3592,63 @@ LibertyReader::visitMode(LibertyAttr *attr) void LibertyReader::visitIntrinsicRise(LibertyAttr *attr) { - visitIntrinsic(attr, TransRiseFall::rise()); + visitIntrinsic(attr, RiseFall::rise()); } void LibertyReader::visitIntrinsicFall(LibertyAttr *attr) { - visitIntrinsic(attr, TransRiseFall::fall()); + visitIntrinsic(attr, RiseFall::fall()); } void LibertyReader::visitIntrinsic(LibertyAttr *attr, - TransRiseFall *tr) + RiseFall *rf) { if (timing_) { float value; bool exists; getAttrFloat(attr, value, exists); if (exists) - timing_->setIntrinsic(tr, value * time_scale_); + timing_->setIntrinsic(rf, value * time_scale_); } } void LibertyReader::visitRiseResistance(LibertyAttr *attr) { - visitRiseFallResistance(attr, TransRiseFall::rise()); + visitRiseFallResistance(attr, RiseFall::rise()); } void LibertyReader::visitFallResistance(LibertyAttr *attr) { - visitRiseFallResistance(attr, TransRiseFall::fall()); + visitRiseFallResistance(attr, RiseFall::fall()); } void LibertyReader::visitRiseFallResistance(LibertyAttr *attr, - TransRiseFall *tr) + RiseFall *rf) { if (timing_) { float value; bool exists; getAttrFloat(attr, value, exists); if (exists) - timing_->setResistance(tr, value * res_scale_); + timing_->setResistance(rf, value * res_scale_); } } void LibertyReader::beginCellRise(LibertyGroup *group) { - beginTimingTableModel(group, TransRiseFall::rise(), ScaleFactorType::cell); + beginTimingTableModel(group, RiseFall::rise(), ScaleFactorType::cell); } void LibertyReader::beginCellFall(LibertyGroup *group) { - beginTimingTableModel(group, TransRiseFall::fall(), ScaleFactorType::cell); + beginTimingTableModel(group, RiseFall::fall(), ScaleFactorType::cell); } void @@ -3656,8 +3656,8 @@ LibertyReader::endCellRiseFall(LibertyGroup *group) { if (table_) { if (GateTableModel::checkAxes(table_)) { - TableModel *table_model = new TableModel(table_, scale_factor_type_, tr_); - timing_->setCell(tr_, table_model); + TableModel *table_model = new TableModel(table_, scale_factor_type_, rf_); + timing_->setCell(rf_, table_model); } else { libWarn(group, "unsupported model axis.\n"); @@ -3670,13 +3670,13 @@ LibertyReader::endCellRiseFall(LibertyGroup *group) void LibertyReader::beginRiseTransition(LibertyGroup *group) { - beginTimingTableModel(group, TransRiseFall::rise(), ScaleFactorType::transition); + beginTimingTableModel(group, RiseFall::rise(), ScaleFactorType::transition); } void LibertyReader::beginFallTransition(LibertyGroup *group) { - beginTimingTableModel(group, TransRiseFall::fall(), ScaleFactorType::transition); + beginTimingTableModel(group, RiseFall::fall(), ScaleFactorType::transition); } void @@ -3684,8 +3684,8 @@ LibertyReader::endRiseFallTransition(LibertyGroup *group) { if (table_) { if (GateTableModel::checkAxes(table_)) { - TableModel *table_model = new TableModel(table_, scale_factor_type_, tr_); - timing_->setTransition(tr_, table_model); + TableModel *table_model = new TableModel(table_, scale_factor_type_, rf_); + timing_->setTransition(rf_, table_model); } else { libWarn(group, "unsupported model axis.\n"); @@ -3699,14 +3699,14 @@ void LibertyReader::beginRiseConstraint(LibertyGroup *group) { // Scale factor depends on timing_type, which may follow this stmt. - beginTimingTableModel(group, TransRiseFall::rise(), ScaleFactorType::unknown); + beginTimingTableModel(group, RiseFall::rise(), ScaleFactorType::unknown); } void LibertyReader::beginFallConstraint(LibertyGroup *group) { // Scale factor depends on timing_type, which may follow this stmt. - beginTimingTableModel(group, TransRiseFall::fall(), ScaleFactorType::unknown); + beginTimingTableModel(group, RiseFall::fall(), ScaleFactorType::unknown); } void @@ -3714,8 +3714,8 @@ LibertyReader::endRiseFallConstraint(LibertyGroup *group) { if (table_) { if (CheckTableModel::checkAxes(table_)) { - TableModel *table_model = new TableModel(table_, scale_factor_type_, tr_); - timing_->setConstraint(tr_, table_model); + TableModel *table_model = new TableModel(table_, scale_factor_type_, rf_); + timing_->setConstraint(rf_, table_model); } else { libWarn(group, "unsupported model axis.\n"); @@ -3732,7 +3732,7 @@ LibertyReader::beginRiseTransitionDegredation(LibertyGroup *group) { if (library_) beginTableModel(group, TableTemplateType::delay, - TransRiseFall::rise(), time_scale_, + RiseFall::rise(), time_scale_, ScaleFactorType::transition); } @@ -3741,7 +3741,7 @@ LibertyReader::beginFallTransitionDegredation(LibertyGroup *group) { if (library_) beginTableModel(group, TableTemplateType::delay, - TransRiseFall::fall(), time_scale_, + RiseFall::fall(), time_scale_, ScaleFactorType::transition); } @@ -3750,8 +3750,8 @@ LibertyReader::endRiseFallTransitionDegredation(LibertyGroup *group) { if (table_) { if (LibertyLibrary::checkSlewDegradationAxes(table_)) { - TableModel *table_model = new TableModel(table_, scale_factor_type_, tr_); - library_->setWireSlewDegradationTable(table_model, tr_); + TableModel *table_model = new TableModel(table_, scale_factor_type_, rf_); + library_->setWireSlewDegradationTable(table_model, rf_); } else { libWarn(group, "unsupported model axis.\n"); @@ -3765,23 +3765,23 @@ LibertyReader::endRiseFallTransitionDegredation(LibertyGroup *group) void LibertyReader::beginTimingTableModel(LibertyGroup *group, - TransRiseFall *tr, + RiseFall *rf, ScaleFactorType scale_factor_type) { if (timing_) - beginTableModel(group, TableTemplateType::delay, tr, + beginTableModel(group, TableTemplateType::delay, rf, time_scale_, scale_factor_type); } void LibertyReader::beginTableModel(LibertyGroup *group, TableTemplateType type, - TransRiseFall *tr, + RiseFall *rf, float scale, ScaleFactorType scale_factor_type) { beginTable(group, type, scale); - tr_ = tr; + rf_ = rf; scale_factor_type_ = scale_factor_type; sigma_type_ = EarlyLateAll::all(); } @@ -4455,7 +4455,7 @@ LibertyReader::beginFallPower(LibertyGroup *group) { if (internal_power_) beginTableModel(group, TableTemplateType::power, - TransRiseFall::fall(), energy_scale_, + RiseFall::fall(), energy_scale_, ScaleFactorType::internal_power); } @@ -4464,7 +4464,7 @@ LibertyReader::beginRisePower(LibertyGroup *group) { if (internal_power_) beginTableModel(group, TableTemplateType::power, - TransRiseFall::rise(), energy_scale_, + RiseFall::rise(), energy_scale_, ScaleFactorType::internal_power); } @@ -4472,8 +4472,8 @@ void LibertyReader::endRiseFallPower(LibertyGroup *) { if (table_) { - TableModel *table_model = new TableModel(table_, scale_factor_type_, tr_); - internal_power_->setModel(tr_, new InternalPowerModel(table_model)); + TableModel *table_model = new TableModel(table_, scale_factor_type_, rf_); + internal_power_->setModel(rf_, new InternalPowerModel(table_model)); } endTableModel(); } @@ -4576,7 +4576,7 @@ void LibertyReader::beginOcvDerateFactors(LibertyGroup *group) { if (ocv_derate_) { - rf_type_ = TransRiseFallBoth::riseFall(); + rf_type_ = RiseFallBoth::riseFall(); derate_type_ = EarlyLateAll::all(); path_type_ = PathType::clk_and_data; beginTable(group, TableTemplateType::ocv, 1.0); @@ -4604,13 +4604,13 @@ LibertyReader::endOcvDerateFactors(LibertyGroup *) void LibertyReader::visitRfType(LibertyAttr *attr) { - const char *tr_name = getAttrString(attr); - if (stringEq(tr_name, "rise")) - rf_type_ = TransRiseFallBoth::rise(); - else if (stringEq(tr_name, "fall")) - rf_type_ = TransRiseFallBoth::fall(); - else if (stringEq(tr_name, "rise_and_fall")) - rf_type_ = TransRiseFallBoth::riseFall(); + const char *rf_name = getAttrString(attr); + if (stringEq(rf_name, "rise")) + rf_type_ = RiseFallBoth::rise(); + else if (stringEq(rf_name, "fall")) + rf_type_ = RiseFallBoth::fall(); + else if (stringEq(rf_name, "rise_and_fall")) + rf_type_ = RiseFallBoth::riseFall(); else libError(attr, "unknown rf_type.\n"); } @@ -4640,13 +4640,13 @@ LibertyReader::visitPathType(LibertyAttr *attr) void LibertyReader::beginOcvSigmaCellRise(LibertyGroup *group) { - beginTimingTableModel(group, TransRiseFall::rise(), ScaleFactorType::unknown); + beginTimingTableModel(group, RiseFall::rise(), ScaleFactorType::unknown); } void LibertyReader::beginOcvSigmaCellFall(LibertyGroup *group) { - beginTimingTableModel(group, TransRiseFall::fall(), ScaleFactorType::unknown); + beginTimingTableModel(group, RiseFall::fall(), ScaleFactorType::unknown); } void @@ -4654,13 +4654,13 @@ LibertyReader::endOcvSigmaCell(LibertyGroup *group) { if (table_) { if (GateTableModel::checkAxes(table_)) { - TableModel *table_model = new TableModel(table_, scale_factor_type_, tr_); + TableModel *table_model = new TableModel(table_, scale_factor_type_, rf_); if (sigma_type_ == EarlyLateAll::all()) { - timing_->setDelaySigma(tr_, EarlyLate::min(), table_model); - timing_->setDelaySigma(tr_, EarlyLate::max(), table_model); + timing_->setDelaySigma(rf_, EarlyLate::min(), table_model); + timing_->setDelaySigma(rf_, EarlyLate::max(), table_model); } else - timing_->setDelaySigma(tr_, sigma_type_->asMinMax(), table_model); + timing_->setDelaySigma(rf_, sigma_type_->asMinMax(), table_model); } else { libWarn(group, "unsupported model axis.\n"); @@ -4673,13 +4673,13 @@ LibertyReader::endOcvSigmaCell(LibertyGroup *group) void LibertyReader::beginOcvSigmaRiseTransition(LibertyGroup *group) { - beginTimingTableModel(group, TransRiseFall::rise(), ScaleFactorType::unknown); + beginTimingTableModel(group, RiseFall::rise(), ScaleFactorType::unknown); } void LibertyReader::beginOcvSigmaFallTransition(LibertyGroup *group) { - beginTimingTableModel(group, TransRiseFall::fall(), ScaleFactorType::unknown); + beginTimingTableModel(group, RiseFall::fall(), ScaleFactorType::unknown); } void @@ -4687,13 +4687,13 @@ LibertyReader::endOcvSigmaTransition(LibertyGroup *group) { if (table_) { if (GateTableModel::checkAxes(table_)) { - TableModel *table_model = new TableModel(table_, scale_factor_type_, tr_); + TableModel *table_model = new TableModel(table_, scale_factor_type_, rf_); if (sigma_type_ == EarlyLateAll::all()) { - timing_->setSlewSigma(tr_, EarlyLate::min(), table_model); - timing_->setSlewSigma(tr_, EarlyLate::max(), table_model); + timing_->setSlewSigma(rf_, EarlyLate::min(), table_model); + timing_->setSlewSigma(rf_, EarlyLate::max(), table_model); } else - timing_->setSlewSigma(tr_, sigma_type_->asMinMax(), table_model); + timing_->setSlewSigma(rf_, sigma_type_->asMinMax(), table_model); } else { libWarn(group, "unsupported model axis.\n"); @@ -4706,13 +4706,13 @@ LibertyReader::endOcvSigmaTransition(LibertyGroup *group) void LibertyReader::beginOcvSigmaRiseConstraint(LibertyGroup *group) { - beginTimingTableModel(group, TransRiseFall::rise(), ScaleFactorType::unknown); + beginTimingTableModel(group, RiseFall::rise(), ScaleFactorType::unknown); } void LibertyReader::beginOcvSigmaFallConstraint(LibertyGroup *group) { - beginTimingTableModel(group, TransRiseFall::fall(), ScaleFactorType::unknown); + beginTimingTableModel(group, RiseFall::fall(), ScaleFactorType::unknown); } void @@ -4720,13 +4720,13 @@ LibertyReader::endOcvSigmaConstraint(LibertyGroup *group) { if (table_) { if (CheckTableModel::checkAxes(table_)) { - TableModel *table_model = new TableModel(table_, scale_factor_type_, tr_); + TableModel *table_model = new TableModel(table_, scale_factor_type_, rf_); if (sigma_type_ == EarlyLateAll::all()) { - timing_->setConstraintSigma(tr_, EarlyLate::min(), table_model); - timing_->setConstraintSigma(tr_, EarlyLate::max(), table_model); + timing_->setConstraintSigma(rf_, EarlyLate::min(), table_model); + timing_->setConstraintSigma(rf_, EarlyLate::max(), table_model); } else - timing_->setConstraintSigma(tr_, sigma_type_->asMinMax(), table_model); + timing_->setConstraintSigma(rf_, sigma_type_->asMinMax(), table_model); } else { libWarn(group, "unsupported model axis.\n"); @@ -4971,19 +4971,19 @@ TimingGroup::TimingGroup(int line) : RelatedPortGroup(line), related_output_port_name_(nullptr) { - for (auto tr_index : TransRiseFall::rangeIndex()) { - cell_[tr_index] = nullptr; - constraint_[tr_index] = nullptr; - transition_[tr_index] = nullptr; - intrinsic_[tr_index] = 0.0F; - intrinsic_exists_[tr_index] = false; - resistance_[tr_index] = 0.0F; - resistance_exists_[tr_index] = false; + for (auto rf_index : RiseFall::rangeIndex()) { + cell_[rf_index] = nullptr; + constraint_[rf_index] = nullptr; + transition_[rf_index] = nullptr; + intrinsic_[rf_index] = 0.0F; + intrinsic_exists_[rf_index] = false; + resistance_[rf_index] = 0.0F; + resistance_exists_[rf_index] = false; for (auto el_index : EarlyLate::rangeIndex()) { - delay_sigma_[tr_index][el_index] = nullptr; - slew_sigma_[tr_index][el_index] = nullptr; - constraint_sigma_[tr_index][el_index] = nullptr; + delay_sigma_[rf_index][el_index] = nullptr; + slew_sigma_[rf_index][el_index] = nullptr; + constraint_sigma_[rf_index][el_index] = nullptr; } } } @@ -5003,106 +5003,106 @@ TimingGroup::setRelatedOutputPortName(const char *name) } void -TimingGroup::setIntrinsic(TransRiseFall *tr, +TimingGroup::setIntrinsic(RiseFall *rf, float value) { - int tr_index = tr->index(); - intrinsic_[tr_index] = value; - intrinsic_exists_[tr_index] = true; + int rf_index = rf->index(); + intrinsic_[rf_index] = value; + intrinsic_exists_[rf_index] = true; } void -TimingGroup::intrinsic(TransRiseFall *tr, +TimingGroup::intrinsic(RiseFall *rf, // Return values. float &value, bool &exists) { - int tr_index = tr->index(); - value = intrinsic_[tr_index]; - exists = intrinsic_exists_[tr_index]; + int rf_index = rf->index(); + value = intrinsic_[rf_index]; + exists = intrinsic_exists_[rf_index]; } void -TimingGroup::setResistance(TransRiseFall *tr, +TimingGroup::setResistance(RiseFall *rf, float value) { - int tr_index = tr->index(); - resistance_[tr_index] = value; - resistance_exists_[tr_index] = true; + int rf_index = rf->index(); + resistance_[rf_index] = value; + resistance_exists_[rf_index] = true; } void -TimingGroup::resistance(TransRiseFall *tr, +TimingGroup::resistance(RiseFall *rf, // Return values. float &value, bool &exists) { - int tr_index = tr->index(); - value = resistance_[tr_index]; - exists = resistance_exists_[tr_index]; + int rf_index = rf->index(); + value = resistance_[rf_index]; + exists = resistance_exists_[rf_index]; } TableModel * -TimingGroup::cell(TransRiseFall *tr) +TimingGroup::cell(RiseFall *rf) { - return cell_[tr->index()]; + return cell_[rf->index()]; } void -TimingGroup::setCell(TransRiseFall *tr, +TimingGroup::setCell(RiseFall *rf, TableModel *model) { - cell_[tr->index()] = model; + cell_[rf->index()] = model; } TableModel * -TimingGroup::constraint(TransRiseFall *tr) +TimingGroup::constraint(RiseFall *rf) { - return constraint_[tr->index()]; + return constraint_[rf->index()]; } void -TimingGroup::setConstraint(TransRiseFall *tr, +TimingGroup::setConstraint(RiseFall *rf, TableModel *model) { - constraint_[tr->index()] = model; + constraint_[rf->index()] = model; } TableModel * -TimingGroup::transition(TransRiseFall *tr) +TimingGroup::transition(RiseFall *rf) { - return transition_[tr->index()]; + return transition_[rf->index()]; } void -TimingGroup::setTransition(TransRiseFall *tr, +TimingGroup::setTransition(RiseFall *rf, TableModel *model) { - transition_[tr->index()] = model; + transition_[rf->index()] = model; } void -TimingGroup::setDelaySigma(TransRiseFall *tr, +TimingGroup::setDelaySigma(RiseFall *rf, EarlyLate *early_late, TableModel *model) { - delay_sigma_[tr->index()][early_late->index()] = model; + delay_sigma_[rf->index()][early_late->index()] = model; } void -TimingGroup::setSlewSigma(TransRiseFall *tr, +TimingGroup::setSlewSigma(RiseFall *rf, EarlyLate *early_late, TableModel *model) { - slew_sigma_[tr->index()][early_late->index()] = model; + slew_sigma_[rf->index()][early_late->index()] = model; } void -TimingGroup::setConstraintSigma(TransRiseFall *tr, +TimingGroup::setConstraintSigma(RiseFall *rf, EarlyLate *early_late, TableModel *model) { - constraint_sigma_[tr->index()][early_late->index()] = model; + constraint_sigma_[rf->index()][early_late->index()] = model; } //////////////////////////////////////////////////////////////// diff --git a/liberty/LibertyReaderPvt.hh b/liberty/LibertyReaderPvt.hh index b13cf050..0c91a646 100644 --- a/liberty/LibertyReaderPvt.hh +++ b/liberty/LibertyReaderPvt.hh @@ -100,15 +100,15 @@ public: virtual void visitDefaultIntrinsicRise(LibertyAttr *attr); virtual void visitDefaultIntrinsicFall(LibertyAttr *attr); virtual void visitDefaultIntrinsic(LibertyAttr *attr, - TransRiseFall *tr); + RiseFall *rf); virtual void visitDefaultInoutPinRiseRes(LibertyAttr *attr); virtual void visitDefaultInoutPinFallRes(LibertyAttr *attr); virtual void visitDefaultInoutPinRes(LibertyAttr *attr, - TransRiseFall *tr); + RiseFall *rf); virtual void visitDefaultOutputPinRiseRes(LibertyAttr *attr); virtual void visitDefaultOutputPinFallRes(LibertyAttr *attr); virtual void visitDefaultOutputPinRes(LibertyAttr *attr, - TransRiseFall *tr); + RiseFall *rf); virtual void visitDefaultFanoutLoad(LibertyAttr *attr); virtual void visitDefaultWireLoad(LibertyAttr *attr); virtual void visitDefaultWireLoadMode(LibertyAttr *attr); @@ -117,19 +117,19 @@ public: virtual void visitInputThresholdPctFall(LibertyAttr *attr); virtual void visitInputThresholdPctRise(LibertyAttr *attr); virtual void visitInputThresholdPct(LibertyAttr *attr, - TransRiseFall *tr); + RiseFall *rf); virtual void visitOutputThresholdPctFall(LibertyAttr *attr); virtual void visitOutputThresholdPctRise(LibertyAttr *attr); virtual void visitOutputThresholdPct(LibertyAttr *attr, - TransRiseFall *tr); + RiseFall *rf); virtual void visitSlewLowerThresholdPctFall(LibertyAttr *attr); virtual void visitSlewLowerThresholdPctRise(LibertyAttr *attr); virtual void visitSlewLowerThresholdPct(LibertyAttr *attr, - TransRiseFall *tr); + RiseFall *rf); virtual void visitSlewUpperThresholdPctFall(LibertyAttr *attr); virtual void visitSlewUpperThresholdPctRise(LibertyAttr *attr); virtual void visitSlewUpperThresholdPct(LibertyAttr *attr, - TransRiseFall *tr); + RiseFall *rf); virtual void visitSlewDerateFromLibrary(LibertyAttr *attr); virtual void beginTableTemplateDelay(LibertyGroup *group); @@ -222,7 +222,7 @@ public: virtual void visitMinPulseWidthLow(LibertyAttr *attr); virtual void visitMinPulseWidthHigh(LibertyAttr *attr); virtual void visitMinPulseWidth(LibertyAttr *attr, - TransRiseFall *tr); + RiseFall *rf); virtual void visitPulseClock(LibertyAttr *attr); virtual void visitClockGateClockPin(LibertyAttr *attr); virtual void visitClockGateEnablePin(LibertyAttr *attr); @@ -300,11 +300,11 @@ public: virtual void visitIntrinsicRise(LibertyAttr *attr); virtual void visitIntrinsicFall(LibertyAttr *attr); virtual void visitIntrinsic(LibertyAttr *attr, - TransRiseFall *tr); + RiseFall *rf); virtual void visitRiseResistance(LibertyAttr *attr); virtual void visitFallResistance(LibertyAttr *attr); virtual void visitRiseFallResistance(LibertyAttr *attr, - TransRiseFall *tr); + RiseFall *rf); virtual void visitValue(LibertyAttr *attr); virtual void visitValues(LibertyAttr *attr); virtual void beginCellRise(LibertyGroup *group); @@ -323,12 +323,12 @@ public: virtual void beginTableModel(LibertyGroup *group, TableTemplateType type, - TransRiseFall *tr, + RiseFall *rf, float scale, ScaleFactorType scale_factor_type); virtual void endTableModel(); virtual void beginTimingTableModel(LibertyGroup *group, - TransRiseFall *tr, + RiseFall *rf, ScaleFactorType scale_factor_type); virtual void beginTable(LibertyGroup *group, TableTemplateType type, @@ -517,10 +517,10 @@ protected: const char *default_wireload_selection_; ScaleFactors *scale_factors_; ScaleFactors *save_scale_factors_; - bool have_input_threshold_[TransRiseFall::index_count]; - bool have_output_threshold_[TransRiseFall::index_count]; - bool have_slew_lower_threshold_[TransRiseFall::index_count]; - bool have_slew_upper_threshold_[TransRiseFall::index_count]; + bool have_input_threshold_[RiseFall::index_count]; + bool have_output_threshold_[RiseFall::index_count]; + bool have_slew_lower_threshold_[RiseFall::index_count]; + bool have_slew_upper_threshold_[RiseFall::index_count]; TableTemplate *tbl_template_; LibertyCell *cell_; LibertyCell *save_cell_; @@ -549,9 +549,9 @@ protected: InternalPowerGroup *internal_power_; LeakagePowerGroup *leakage_power_; LeakagePowerGroupSeq leakage_powers_; - TransRiseFall *tr_; + RiseFall *rf_; OcvDerate *ocv_derate_; - TransRiseFallBoth *rf_type_; + RiseFallBoth *rf_type_; EarlyLateAll *derate_type_; EarlyLateAll *sigma_type_; PathType path_type_; @@ -710,36 +710,36 @@ public: virtual ~TimingGroup(); const char *relatedOutputPortName()const {return related_output_port_name_;} void setRelatedOutputPortName(const char *name); - void intrinsic(TransRiseFall *tr, + void intrinsic(RiseFall *rf, // Return values. float &value, bool &exists); - void setIntrinsic(TransRiseFall *tr, + void setIntrinsic(RiseFall *rf, float value); - void resistance(TransRiseFall *tr, + void resistance(RiseFall *rf, // Return values. float &value, bool &exists); - void setResistance(TransRiseFall *tr, + void setResistance(RiseFall *rf, float value); - TableModel *cell(TransRiseFall *tr); - void setCell(TransRiseFall *tr, + TableModel *cell(RiseFall *rf); + void setCell(RiseFall *rf, TableModel *model); - TableModel *constraint(TransRiseFall *tr); - void setConstraint(TransRiseFall *tr, + TableModel *constraint(RiseFall *rf); + void setConstraint(RiseFall *rf, TableModel *model); - TableModel *transition(TransRiseFall *tr); - void setTransition(TransRiseFall *tr, + TableModel *transition(RiseFall *rf); + void setTransition(RiseFall *rf, TableModel *model); void makeTimingModels(LibertyLibrary *library, LibertyReader *visitor); - void setDelaySigma(TransRiseFall *tr, + void setDelaySigma(RiseFall *rf, EarlyLate *early_late, TableModel *model); - void setSlewSigma(TransRiseFall *tr, + void setSlewSigma(RiseFall *rf, EarlyLate *early_late, TableModel *model); - void setConstraintSigma(TransRiseFall *tr, + void setConstraintSigma(RiseFall *rf, EarlyLate *early_late, TableModel *model); @@ -748,16 +748,16 @@ protected: void makeTableModels(LibertyReader *visitor); const char *related_output_port_name_; - float intrinsic_[TransRiseFall::index_count]; - bool intrinsic_exists_[TransRiseFall::index_count]; - float resistance_[TransRiseFall::index_count]; - bool resistance_exists_[TransRiseFall::index_count]; - TableModel *cell_[TransRiseFall::index_count]; - TableModel *constraint_[TransRiseFall::index_count]; - TableModel *constraint_sigma_[TransRiseFall::index_count][EarlyLate::index_count]; - TableModel *transition_[TransRiseFall::index_count]; - TableModel *delay_sigma_[TransRiseFall::index_count][EarlyLate::index_count]; - TableModel *slew_sigma_[TransRiseFall::index_count][EarlyLate::index_count]; + float intrinsic_[RiseFall::index_count]; + bool intrinsic_exists_[RiseFall::index_count]; + float resistance_[RiseFall::index_count]; + bool resistance_exists_[RiseFall::index_count]; + TableModel *cell_[RiseFall::index_count]; + TableModel *constraint_[RiseFall::index_count]; + TableModel *constraint_sigma_[RiseFall::index_count][EarlyLate::index_count]; + TableModel *transition_[RiseFall::index_count]; + TableModel *delay_sigma_[RiseFall::index_count][EarlyLate::index_count]; + TableModel *slew_sigma_[RiseFall::index_count][EarlyLate::index_count]; private: DISALLOW_COPY_AND_ASSIGN(TimingGroup); diff --git a/liberty/TableModel.cc b/liberty/TableModel.cc index 4b912947..43962117 100644 --- a/liberty/TableModel.cc +++ b/liberty/TableModel.cc @@ -551,10 +551,10 @@ CheckTableModel::checkAxis(TableAxis *axis) TableModel::TableModel(Table *table, ScaleFactorType scale_factor_type, - TransRiseFall *tr) : + RiseFall *rf) : table_(table), scale_factor_type_(int(scale_factor_type)), - tr_index_(tr->index()), + tr_index_(rf->index()), is_scaled_(false) { } diff --git a/liberty/TableModel.hh b/liberty/TableModel.hh index 764f1f03..bf9e805d 100644 --- a/liberty/TableModel.hh +++ b/liberty/TableModel.hh @@ -197,7 +197,7 @@ class TableModel public: TableModel(Table *table, ScaleFactorType scale_factor_type, - TransRiseFall *tr); + RiseFall *rf); ~TableModel(); void setScaleFactorType(ScaleFactorType type); int order() const; @@ -242,7 +242,7 @@ protected: Table *table_; // ScaleFactorType gcc barfs if this is dcl'd. unsigned scale_factor_type_:scale_factor_bits; - unsigned tr_index_:TransRiseFall::index_bit_count; + unsigned tr_index_:RiseFall::index_bit_count; bool is_scaled_:1; private: diff --git a/liberty/TimingArc.cc b/liberty/TimingArc.cc index 9e61ad03..382771f4 100644 --- a/liberty/TimingArc.cc +++ b/liberty/TimingArc.cc @@ -64,8 +64,8 @@ TimingArcAttrs::deleteContents() stringDelete(sdf_cond_end_); stringDelete(mode_name_); stringDelete(mode_value_); - delete models_[TransRiseFall::riseIndex()]; - delete models_[TransRiseFall::fallIndex()]; + delete models_[RiseFall::riseIndex()]; + delete models_[RiseFall::fallIndex()]; } void @@ -116,16 +116,16 @@ TimingArcAttrs::setModeValue(const char *value) } TimingModel * -TimingArcAttrs::model(TransRiseFall *tr) const +TimingArcAttrs::model(RiseFall *rf) const { - return models_[tr->index()]; + return models_[rf->index()]; } void -TimingArcAttrs::setModel(TransRiseFall *tr, +TimingArcAttrs::setModel(RiseFall *rf, TimingModel *model) { - models_[tr->index()] = model; + models_[rf->index()] = model; } void @@ -188,7 +188,7 @@ TimingArcSet::init(LibertyCell *cell) if (cell) index_ = cell->addTimingArcSet(this); - for (auto tr_index : TransRiseFall::rangeIndex()) { + for (auto tr_index : RiseFall::rangeIndex()) { from_arc1_[tr_index] = nullptr; from_arc2_[tr_index] = nullptr; } @@ -223,11 +223,11 @@ TimingArcSet::addTimingArc(TimingArc *arc) internalError("timing arc max index exceeded\n"); arcs_.push_back(arc); - int from_tr_index = arc->fromTrans()->asRiseFall()->index(); - if (from_arc1_[from_tr_index] == nullptr) - from_arc1_[from_tr_index] = arc; - else if (from_arc2_[from_tr_index] == nullptr) - from_arc2_[from_tr_index] = arc; + int from_rf_index = arc->fromTrans()->asRiseFall()->index(); + if (from_arc1_[from_rf_index] == nullptr) + from_arc1_[from_rf_index] = arc; + else if (from_arc2_[from_rf_index] == nullptr) + from_arc2_[from_rf_index] = arc; return arc_index; } @@ -243,13 +243,13 @@ TimingArcSet::deleteTimingArc(TimingArc *arc) arcs_[arc->index()] = last_arc; arcs_.pop_back(); } - int from_tr_index = arc->fromTrans()->asRiseFall()->index(); - if (from_arc1_[from_tr_index] == arc) { - from_arc1_[from_tr_index] = from_arc2_[from_tr_index]; - from_arc2_[from_tr_index] = nullptr; + int from_rf_index = arc->fromTrans()->asRiseFall()->index(); + if (from_arc1_[from_rf_index] == arc) { + from_arc1_[from_rf_index] = from_arc2_[from_rf_index]; + from_arc2_[from_rf_index] = nullptr; } - else if (from_arc2_[from_tr_index] == arc) - from_arc2_[from_tr_index] = nullptr; + else if (from_arc2_[from_rf_index] == arc) + from_arc2_[from_rf_index] = nullptr; delete arc; } @@ -272,12 +272,12 @@ TimingArcSet::setIsCondDefault(bool is_default) } void -TimingArcSet::arcsFrom(const TransRiseFall *from_tr, +TimingArcSet::arcsFrom(const RiseFall *from_rf, // Return values. TimingArc *&arc1, TimingArc *&arc2) { - int tr_index = from_tr->index(); + int tr_index = from_rf->index(); arc1 = from_arc1_[tr_index]; arc2 = from_arc2_[tr_index]; } @@ -293,15 +293,15 @@ TimingArcSet::sense() const return TimingSense::non_unate; } -TransRiseFall * +RiseFall * TimingArcSet::isRisingFallingEdge() const { int arc_count = arcs_.size(); if (arc_count == 2) { - TransRiseFall *from_tr1 = arcs_[0]->fromTrans()->asRiseFall(); - TransRiseFall *from_tr2 = arcs_[1]->fromTrans()->asRiseFall(); - if (from_tr1 == from_tr2) - return from_tr1; + RiseFall *from_rf1 = arcs_[0]->fromTrans()->asRiseFall(); + RiseFall *from_rf2 = arcs_[1]->fromTrans()->asRiseFall(); + if (from_rf1 == from_rf2) + return from_rf1; } if (arcs_.size() == 1) return arcs_[0]->fromTrans()->asRiseFall(); @@ -463,9 +463,9 @@ timingArcsLess(const TimingArcSet *set1, //////////////////////////////////////////////////////////////// int -TimingArcSet::wireArcIndex(const TransRiseFall *tr) +TimingArcSet::wireArcIndex(const RiseFall *rf) { - return tr->index(); + return rf->index(); } void @@ -495,12 +495,12 @@ TimingArcSetArcIterator::TimingArcSetArcIterator(const TimingArcSet *set) : //////////////////////////////////////////////////////////////// TimingArc::TimingArc(TimingArcSet *set, - Transition *from_tr, - Transition *to_tr, + Transition *from_rf, + Transition *to_rf, TimingModel *model) : set_(set), - from_tr_(from_tr), - to_tr_(to_tr), + from_rf_(from_rf), + to_rf_(to_rf), model_(model), scaled_models_(nullptr) { @@ -576,15 +576,15 @@ TimingArc::setCornerArc(TimingArc *corner_arc, TimingSense TimingArc::sense() const { - if ((from_tr_ == Transition::rise() - && to_tr_ == Transition::rise()) - || (from_tr_ == Transition::fall() - && to_tr_ == Transition::fall())) + if ((from_rf_ == Transition::rise() + && to_rf_ == Transition::rise()) + || (from_rf_ == Transition::fall() + && to_rf_ == Transition::fall())) return TimingSense::positive_unate; - else if ((from_tr_ == Transition::rise() - && to_tr_ == Transition::fall()) - || (from_tr_ == Transition::fall() - && to_tr_ == Transition::rise())) + else if ((from_rf_ == Transition::rise() + && to_rf_ == Transition::fall()) + || (from_rf_ == Transition::fall() + && to_rf_ == Transition::rise())) return TimingSense::negative_unate; else return TimingSense::non_unate; diff --git a/liberty/TimingArc.hh b/liberty/TimingArc.hh index a6507e71..7bf129a7 100644 --- a/liberty/TimingArc.hh +++ b/liberty/TimingArc.hh @@ -106,8 +106,8 @@ public: void setModeName(const char *name); const char *modeValue() const { return mode_value_; } void setModeValue(const char *value); - TimingModel *model(TransRiseFall *tr) const; - void setModel(TransRiseFall *tr, + TimingModel *model(RiseFall *rf) const; + void setModel(RiseFall *rf, TimingModel *model); float ocvArcDepth() const { return ocv_arc_depth_; } void setOcvArcDepth(float depth); @@ -122,7 +122,7 @@ protected: const char *mode_name_; const char *mode_value_; float ocv_arc_depth_; - TimingModel *models_[TransRiseFall::index_count]; + TimingModel *models_[RiseFall::index_count]; private: DISALLOW_COPY_AND_ASSIGN(TimingArcAttrs); @@ -150,11 +150,11 @@ public: TimingRole *role() const { return role_; }; TimingSense sense() const; // Rise/fall if the arc set is rising_edge or falling_edge. - TransRiseFall *isRisingFallingEdge() const; + RiseFall *isRisingFallingEdge() const; size_t arcCount() const { return arcs_.size(); } TimingArcSeq &arcs() { return arcs_; } // Return 1 or 2 arcs matching from transition. - void arcsFrom(const TransRiseFall *from_tr, + void arcsFrom(const RiseFall *from_rf, // Return values. TimingArc *&arc1, TimingArc *&arc2); @@ -194,7 +194,7 @@ public: // Psuedo definition for wire arcs. static TimingArcSet *wireTimingArcSet() { return wire_timing_arc_set_; } - static int wireArcIndex(const TransRiseFall *tr); + static int wireArcIndex(const RiseFall *rf); static int wireArcCount() { return 2; } protected: @@ -215,8 +215,8 @@ protected: float ocv_arc_depth_; unsigned index_; bool is_disabled_constraint_; - TimingArc *from_arc1_[TransRiseFall::index_count]; - TimingArc *from_arc2_[TransRiseFall::index_count]; + TimingArc *from_arc1_[RiseFall::index_count]; + TimingArc *from_arc2_[RiseFall::index_count]; static TimingArcSet *wire_timing_arc_set_; @@ -239,14 +239,14 @@ class TimingArc { public: TimingArc(TimingArcSet *set, - Transition *from_tr, - Transition *to_tr, + Transition *from_rf, + Transition *to_rf, TimingModel *model); ~TimingArc(); LibertyPort *from() const { return set_->from(); } LibertyPort *to() const { return set_->to(); } - Transition *fromTrans() const { return from_tr_; } - Transition *toTrans() const { return to_tr_; } + Transition *fromTrans() const { return from_rf_; } + Transition *toTrans() const { return to_rf_; } TimingRole *role() const { return set_->role(); } TimingArcSet *set() const { return set_; } TimingSense sense() const; @@ -267,8 +267,8 @@ protected: TimingModel *scaled_model); TimingArcSet *set_; - Transition *from_tr_; - Transition *to_tr_; + Transition *from_rf_; + Transition *to_rf_; unsigned index_; TimingModel *model_; ScaledTimingModelMap *scaled_models_; diff --git a/liberty/Transition.cc b/liberty/Transition.cc index 3e4ef971..0ce910b3 100644 --- a/liberty/Transition.cc +++ b/liberty/Transition.cc @@ -21,12 +21,12 @@ namespace sta { using std::max; -TransRiseFall TransRiseFall::rise_("rise", "^", 0); -TransRiseFall TransRiseFall::fall_("fall", "v", 1); -const std::array TransRiseFall::range_{&rise_, &fall_}; -const std::array TransRiseFall::range_index_{rise_.index(), fall_.index()}; +RiseFall RiseFall::rise_("rise", "^", 0); +RiseFall RiseFall::fall_("fall", "v", 1); +const std::array RiseFall::range_{&rise_, &fall_}; +const std::array RiseFall::range_index_{rise_.index(), fall_.index()}; -TransRiseFall::TransRiseFall(const char *name, +RiseFall::RiseFall(const char *name, const char *short_name, int sdf_triple_index) : name_(name), @@ -35,20 +35,20 @@ TransRiseFall::TransRiseFall(const char *name, { } -TransRiseFall::~TransRiseFall() +RiseFall::~RiseFall() { stringDelete(short_name_); } void -TransRiseFall::setShortName(const char *short_name) +RiseFall::setShortName(const char *short_name) { stringDelete(short_name_); short_name_ = stringCopy(short_name); } -TransRiseFall * -TransRiseFall::opposite() const +RiseFall * +RiseFall::opposite() const { if (this == &rise_) return &fall_; @@ -56,8 +56,8 @@ TransRiseFall::opposite() const return &rise_; } -TransRiseFall * -TransRiseFall::find(const char *tr_str) +RiseFall * +RiseFall::find(const char *tr_str) { if (stringEq(tr_str, rise_.name())) return &rise_; @@ -67,8 +67,8 @@ TransRiseFall::find(const char *tr_str) return nullptr; } -TransRiseFall * -TransRiseFall::find(int index) +RiseFall * +RiseFall::find(int index) { if (index == rise_.index()) return &rise_; @@ -76,26 +76,26 @@ TransRiseFall::find(int index) return &fall_; } -TransRiseFallBoth * -TransRiseFall::asRiseFallBoth() +RiseFallBoth * +RiseFall::asRiseFallBoth() { if (this == &rise_) - return TransRiseFallBoth::rise(); + return RiseFallBoth::rise(); else - return TransRiseFallBoth::fall(); + return RiseFallBoth::fall(); } -const TransRiseFallBoth * -TransRiseFall::asRiseFallBoth() const +const RiseFallBoth * +RiseFall::asRiseFallBoth() const { if (this == &rise_) - return TransRiseFallBoth::rise(); + return RiseFallBoth::rise(); else - return TransRiseFallBoth::fall(); + return RiseFallBoth::fall(); } Transition * -TransRiseFall::asTransition() const +RiseFall::asTransition() const { if (this == &rise_) return Transition::rise(); @@ -105,26 +105,26 @@ TransRiseFall::asTransition() const //////////////////////////////////////////////////////////////// -TransRiseFallBoth TransRiseFallBoth::rise_("rise", "^", 0, - TransRiseFall::rise(), - {TransRiseFall::rise()}, - {TransRiseFall::riseIndex()}); -TransRiseFallBoth TransRiseFallBoth::fall_("fall", "v", 1, - TransRiseFall::fall(), - {TransRiseFall::fall()}, - {TransRiseFall::fallIndex()}); -TransRiseFallBoth TransRiseFallBoth::rise_fall_("rise_fall", "rf", 2, +RiseFallBoth RiseFallBoth::rise_("rise", "^", 0, + RiseFall::rise(), + {RiseFall::rise()}, + {RiseFall::riseIndex()}); +RiseFallBoth RiseFallBoth::fall_("fall", "v", 1, + RiseFall::fall(), + {RiseFall::fall()}, + {RiseFall::fallIndex()}); +RiseFallBoth RiseFallBoth::rise_fall_("rise_fall", "rf", 2, nullptr, - {TransRiseFall::rise(), - TransRiseFall::fall()}, - {TransRiseFall::riseIndex(), - TransRiseFall::fallIndex()}); + {RiseFall::rise(), + RiseFall::fall()}, + {RiseFall::riseIndex(), + RiseFall::fallIndex()}); -TransRiseFallBoth::TransRiseFallBoth(const char *name, +RiseFallBoth::RiseFallBoth(const char *name, const char *short_name, int sdf_triple_index, - TransRiseFall *as_rise_fall, - std::vector range, + RiseFall *as_rise_fall, + std::vector range, std::vector range_index) : name_(name), short_name_(stringCopy(short_name)), @@ -135,13 +135,13 @@ TransRiseFallBoth::TransRiseFallBoth(const char *name, { } -TransRiseFallBoth::~TransRiseFallBoth() +RiseFallBoth::~RiseFallBoth() { stringDelete(short_name_); } -TransRiseFallBoth * -TransRiseFallBoth::find(const char *tr_str) +RiseFallBoth * +RiseFallBoth::find(const char *tr_str) { if (stringEq(tr_str, rise_.name())) return &rise_; @@ -154,14 +154,14 @@ TransRiseFallBoth::find(const char *tr_str) } bool -TransRiseFallBoth::matches(const TransRiseFall *tr) const +RiseFallBoth::matches(const RiseFall *rf) const { return this == &rise_fall_ - || as_rise_fall_ == tr; + || as_rise_fall_ == rf; } bool -TransRiseFallBoth::matches(const Transition *tr) const +RiseFallBoth::matches(const Transition *tr) const { return this == &rise_fall_ || (this == &rise_ @@ -171,7 +171,7 @@ TransRiseFallBoth::matches(const Transition *tr) const } void -TransRiseFallBoth::setShortName(const char *short_name) +RiseFallBoth::setShortName(const char *short_name) { stringDelete(short_name_); short_name_ = stringCopy(short_name); @@ -183,23 +183,23 @@ TransitionMap Transition::transition_map_; int Transition::max_index_ = 0; // Sdf triple order defined on Sdf 3.0 spec, pg 3-17. -Transition Transition::rise_{ "^", "01", TransRiseFall::rise(), 0}; -Transition Transition::fall_ { "v", "10", TransRiseFall::fall(), 1}; -Transition Transition::tr_0Z_{"0Z", "0Z", TransRiseFall::rise(), 2}; -Transition Transition::tr_Z1_{"Z1", "Z1", TransRiseFall::rise(), 3}; -Transition Transition::tr_1Z_{"1Z", "1Z", TransRiseFall::fall(), 4}; -Transition Transition::tr_Z0_{"Z0", "Z0", TransRiseFall::fall(), 5}; -Transition Transition::tr_0X_{"0X", "0X", TransRiseFall::rise(), 6}; -Transition Transition::tr_X1_{"X1", "X1", TransRiseFall::rise(), 7}; -Transition Transition::tr_1X_{"1X", "1X", TransRiseFall::fall(), 8}; -Transition Transition::tr_X0_{"X0", "X0", TransRiseFall::fall(), 9}; +Transition Transition::rise_{ "^", "01", RiseFall::rise(), 0}; +Transition Transition::fall_ { "v", "10", RiseFall::fall(), 1}; +Transition Transition::tr_0Z_{"0Z", "0Z", RiseFall::rise(), 2}; +Transition Transition::tr_Z1_{"Z1", "Z1", RiseFall::rise(), 3}; +Transition Transition::tr_1Z_{"1Z", "1Z", RiseFall::fall(), 4}; +Transition Transition::tr_Z0_{"Z0", "Z0", RiseFall::fall(), 5}; +Transition Transition::tr_0X_{"0X", "0X", RiseFall::rise(), 6}; +Transition Transition::tr_X1_{"X1", "X1", RiseFall::rise(), 7}; +Transition Transition::tr_1X_{"1X", "1X", RiseFall::fall(), 8}; +Transition Transition::tr_X0_{"X0", "X0", RiseFall::fall(), 9}; Transition Transition::tr_XZ_{"XZ", "XZ", nullptr, 10}; Transition Transition::tr_ZX_{"ZX", "ZX", nullptr, 11}; Transition Transition::rise_fall_{"*", "**", nullptr, -1}; Transition::Transition(const char *name, const char *init_final, - TransRiseFall *as_rise_fall, + RiseFall *as_rise_fall, int sdf_triple_index) : name_(stringCopy(name)), init_final_(init_final), @@ -228,10 +228,10 @@ Transition::find(const char *tr_str) return transition_map_.findKey(tr_str); } -const TransRiseFallBoth * +const RiseFallBoth * Transition::asRiseFallBoth() const { - return reinterpret_cast(as_rise_fall_); + return reinterpret_cast(as_rise_fall_); } void @@ -243,35 +243,35 @@ Transition::setName(const char *name) //////////////////////////////////////////////////////////////// -TransRiseFallIterator::TransRiseFallIterator(const TransRiseFallBoth *tr) +RiseFallIterator::RiseFallIterator(const RiseFallBoth *rf) { - if (tr == TransRiseFallBoth::riseFall()) { + if (rf == RiseFallBoth::riseFall()) { index_ = 0; - index_max_ = TransRiseFall::index_max; + index_max_ = RiseFall::index_max; } else { - index_ = tr->asRiseFall()->index(); + index_ = rf->asRiseFall()->index(); index_max_ = index_; } } void -TransRiseFallIterator::init() +RiseFallIterator::init() { index_ = 0; - index_max_ = TransRiseFall::index_max; + index_max_ = RiseFall::index_max; } bool -TransRiseFallIterator::hasNext() +RiseFallIterator::hasNext() { return index_ <= index_max_; } -TransRiseFall * -TransRiseFallIterator::next() +RiseFall * +RiseFallIterator::next() { - return (index_++ == 0) ? TransRiseFall::rise() : TransRiseFall::fall(); + return (index_++ == 0) ? RiseFall::rise() : RiseFall::fall(); } } // namespace diff --git a/liberty/Transition.hh b/liberty/Transition.hh index 579b3f1d..5e4c6a8a 100644 --- a/liberty/Transition.hh +++ b/liberty/Transition.hh @@ -27,18 +27,18 @@ namespace sta { class Transition; -class TransRiseFall; -class TransRiseFallBoth; +class RiseFall; +class RiseFallBoth; typedef Map TransitionMap; // Rise/fall transition. -class TransRiseFall +class RiseFall { public: // Singleton accessors. - static TransRiseFall *rise() { return &rise_; } - static TransRiseFall *fall() { return &fall_; } + static RiseFall *rise() { return &rise_; } + static RiseFall *fall() { return &fall_; } static int riseIndex() { return rise_.sdf_triple_index_; } static int fallIndex() { return fall_.sdf_triple_index_; } const char *asString() const { return short_name_; } @@ -46,63 +46,63 @@ public: const char *shortName() const { return short_name_; } void setShortName(const char *short_name); int index() const { return sdf_triple_index_; } - TransRiseFallBoth *asRiseFallBoth(); - const TransRiseFallBoth *asRiseFallBoth() const; + RiseFallBoth *asRiseFallBoth(); + const RiseFallBoth *asRiseFallBoth() const; Transition *asTransition() const; // Find transition corresponding to tr_str. - static TransRiseFall *find(const char *tr_str); + static RiseFall *find(const char *tr_str); // Find transition from index. - static TransRiseFall *find(int index); - TransRiseFall *opposite() const; + static RiseFall *find(int index); + RiseFall *opposite() const; // for range support. - // for (auto tr : TransRiseFall::range()) {} - static const std::array &range() { return range_; } - // for (auto tr_index : TransRiseFall::rangeIndex()) {} + // for (auto tr : RiseFall::range()) {} + static const std::array &range() { return range_; } + // for (auto tr_index : RiseFall::rangeIndex()) {} static const std::array &rangeIndex() { return range_index_; } static const int index_count = 2; static const int index_max = (index_count - 1); static const int index_bit_count = 1; protected: - TransRiseFall(const char *name, + RiseFall(const char *name, const char *short_name, int sdf_triple_index); - ~TransRiseFall(); + ~RiseFall(); const char *name_; const char *short_name_; const int sdf_triple_index_; - static TransRiseFall rise_; - static TransRiseFall fall_; - static const std::array range_; + static RiseFall rise_; + static RiseFall fall_; + static const std::array range_; static const std::array range_index_; private: - DISALLOW_COPY_AND_ASSIGN(TransRiseFall); + DISALLOW_COPY_AND_ASSIGN(RiseFall); }; // Rise/fall/risefall transition. -class TransRiseFallBoth +class RiseFallBoth { public: // Singleton accessors. - static TransRiseFallBoth *rise() { return &rise_; } - static TransRiseFallBoth *fall() { return &fall_; } - static TransRiseFallBoth *riseFall() { return &rise_fall_; } + static RiseFallBoth *rise() { return &rise_; } + static RiseFallBoth *fall() { return &fall_; } + static RiseFallBoth *riseFall() { return &rise_fall_; } const char *asString() const { return short_name_; } const char *name() const { return name_; } const char *shortName() const { return short_name_; } void setShortName(const char *short_name); int index() const { return sdf_triple_index_; } - bool matches(const TransRiseFall *tr) const; + bool matches(const RiseFall *rf) const; bool matches(const Transition *tr) const; - TransRiseFall *asRiseFall() const { return as_rise_fall_; } + RiseFall *asRiseFall() const { return as_rise_fall_; } // Find transition corresponding to string. - static TransRiseFallBoth *find(const char *tr_str); + static RiseFallBoth *find(const char *tr_str); // for (auto tr : min_max->range()) {} - const std::vector &range() const { return range_; } + const std::vector &range() const { return range_; } // for (auto tr_index : min_max->rangeIndex()) {} const std::vector &rangeIndex() const { return range_index_; } @@ -111,27 +111,27 @@ public: static const int index_bit_count = 2; protected: - TransRiseFallBoth(const char *name, + RiseFallBoth(const char *name, const char *short_name, int sdf_triple_index, - TransRiseFall *as_rise_fall, - std::vector range, + RiseFall *as_rise_fall, + std::vector range, std::vector range_index); - ~TransRiseFallBoth(); + ~RiseFallBoth(); const char *name_; const char *short_name_; const int sdf_triple_index_; - TransRiseFall *as_rise_fall_; - const std::vector range_; + RiseFall *as_rise_fall_; + const std::vector range_; const std::vector range_index_; - static TransRiseFallBoth rise_; - static TransRiseFallBoth fall_; - static TransRiseFallBoth rise_fall_; + static RiseFallBoth rise_; + static RiseFallBoth fall_; + static RiseFallBoth rise_fall_; private: - DISALLOW_COPY_AND_ASSIGN(TransRiseFallBoth); + DISALLOW_COPY_AND_ASSIGN(RiseFallBoth); }; // General SDF transition. @@ -159,8 +159,8 @@ public: const char *asInitFinalString() const { return init_final_; } int sdfTripleIndex() const { return sdf_triple_index_; } int index() const { return sdf_triple_index_; } - TransRiseFall *asRiseFall() const { return as_rise_fall_; } - const TransRiseFallBoth *asRiseFallBoth() const; + RiseFall *asRiseFall() const { return as_rise_fall_; } + const RiseFallBoth *asRiseFallBoth() const; bool matches(const Transition *tr) const; // Find transition corresponding to string. static Transition *find(const char *tr_str); @@ -169,13 +169,13 @@ public: private: Transition(const char *name, const char *init_final, - TransRiseFall *as_rise_fall, + RiseFall *as_rise_fall, int sdf_triple_index); ~Transition(); const char *name_; const char *init_final_; - TransRiseFall *as_rise_fall_; + RiseFall *as_rise_fall_; const int sdf_triple_index_; static Transition rise_; @@ -203,18 +203,18 @@ private: }; // Obsolete. Use range iteration instead. -// for (auto tr : TransRiseFall::range()) {} -class TransRiseFallIterator : public Iterator +// for (auto tr : RiseFall::range()) {} +class RiseFallIterator : public Iterator { public: - TransRiseFallIterator() : index_(0), index_max_(TransRiseFall::index_max) {} - explicit TransRiseFallIterator(const TransRiseFallBoth *tr); + RiseFallIterator() : index_(0), index_max_(RiseFall::index_max) {} + explicit RiseFallIterator(const RiseFallBoth *rf); void init(); virtual bool hasNext(); - virtual TransRiseFall *next(); + virtual RiseFall *next(); private: - DISALLOW_COPY_AND_ASSIGN(TransRiseFallIterator); + DISALLOW_COPY_AND_ASSIGN(RiseFallIterator); int index_; int index_max_; diff --git a/parasitics/ConcreteParasitics.cc b/parasitics/ConcreteParasitics.cc index 96973c40..231fdd0e 100644 --- a/parasitics/ConcreteParasitics.cc +++ b/parasitics/ConcreteParasitics.cc @@ -290,7 +290,7 @@ ConcretePiElmoreEstimated::ConcretePiElmoreEstimated(float c2, float elmore_res, float elmore_cap, bool elmore_use_load_cap, - const TransRiseFall *tr, + const RiseFall *rf, const OperatingConditions *op, const Corner *corner, const MinMax *min_max, @@ -299,7 +299,7 @@ ConcretePiElmoreEstimated::ConcretePiElmoreEstimated(float c2, elmore_res_(elmore_res), elmore_cap_(elmore_cap), elmore_use_load_cap_(elmore_use_load_cap), - tr_(tr), + rf_(rf), op_cond_(op), corner_(corner), min_max_(min_max), @@ -328,7 +328,7 @@ ConcretePiElmoreEstimated::findElmore(const Pin *load_pin, { float load_cap = 0.0; if (elmore_use_load_cap_) - load_cap = sdc_->pinCapacitance(load_pin, tr_, op_cond_, + load_cap = sdc_->pinCapacitance(load_pin, rf_, op_cond_, corner_, min_max_); elmore = elmore_res_ * (elmore_cap_ + load_cap); exists = true; @@ -875,20 +875,20 @@ ConcreteParasitics::clear() int ConcreteParasitics::parasiticAnalysisPtIndex(const ParasiticAnalysisPt *ap, - const TransRiseFall *tr) const + const RiseFall *rf) const { - return ap->index() * TransRiseFall::index_count + tr->index(); + return ap->index() * RiseFall::index_count + rf->index(); } void ConcreteParasitics::deleteParasitics() { int ap_count = corners_->parasiticAnalysisPtCount(); - int ap_tr_count = ap_count * TransRiseFall::index_count; + int ap_rf_count = ap_count * RiseFall::index_count; for (auto drvr_parasitics : drvr_parasitic_map_) { ConcreteParasitic **parasitics = drvr_parasitics.second; if (parasitics) { - for (int i = 0; i < ap_tr_count; i++) + for (int i = 0; i < ap_rf_count; i++) delete parasitics[i]; delete [] parasitics; } @@ -912,10 +912,10 @@ ConcreteParasitics::deleteParasitics(const Pin *drvr_pin, { ConcreteParasitic **parasitics = drvr_parasitic_map_[drvr_pin]; if (parasitics) { - for (auto tr : TransRiseFall::range()) { - int ap_tr_index = parasiticAnalysisPtIndex(ap, tr); - delete parasitics[ap_tr_index]; - parasitics[ap_tr_index] = nullptr; + for (auto tr : RiseFall::range()) { + int ap_rf_index = parasiticAnalysisPtIndex(ap, tr); + delete parasitics[ap_rf_index]; + parasitics[ap_rf_index] = nullptr; } } } @@ -1017,8 +1017,8 @@ ConcreteParasitics::deleteDrvrReducedParasitics(const Pin *drvr_pin) ConcreteParasitic **parasitics = drvr_parasitic_map_[drvr_pin]; if (parasitics) { int ap_count = corners_->parasiticAnalysisPtCount(); - int ap_tr_count = ap_count * TransRiseFall::index_count; - for (int i = 0; i < ap_tr_count; i++) + int ap_rf_count = ap_count * RiseFall::index_count; + for (int i = 0; i < ap_rf_count; i++) delete parasitics[i]; delete [] parasitics; } @@ -1036,18 +1036,18 @@ ConcreteParasitics::isPiElmore(Parasitic *parasitic) const Parasitic * ConcreteParasitics::findPiElmore(const Pin *drvr_pin, - const TransRiseFall *tr, + const RiseFall *rf, const ParasiticAnalysisPt *ap) const { if (!drvr_parasitic_map_.empty()) { - int ap_tr_index = parasiticAnalysisPtIndex(ap, tr); + int ap_rf_index = parasiticAnalysisPtIndex(ap, rf); UniqueLock lock(lock_); ConcreteParasitic **parasitics = drvr_parasitic_map_.findKey(drvr_pin); if (parasitics) { - ConcreteParasitic *parasitic = parasitics[ap_tr_index]; - if (parasitic == nullptr && tr == TransRiseFall::fall()) { - ap_tr_index = parasiticAnalysisPtIndex(ap, TransRiseFall::rise()); - parasitic = parasitics[ap_tr_index]; + ConcreteParasitic *parasitic = parasitics[ap_rf_index]; + if (parasitic == nullptr && rf == RiseFall::fall()) { + ap_rf_index = parasiticAnalysisPtIndex(ap, RiseFall::rise()); + parasitic = parasitics[ap_rf_index]; } if (parasitic && parasitic->isPiElmore()) return parasitic; @@ -1058,7 +1058,7 @@ ConcreteParasitics::findPiElmore(const Pin *drvr_pin, Parasitic * ConcreteParasitics::makePiElmore(const Pin *drvr_pin, - const TransRiseFall *tr, + const RiseFall *rf, const ParasiticAnalysisPt *ap, float c2, float rpi, @@ -1068,14 +1068,14 @@ ConcreteParasitics::makePiElmore(const Pin *drvr_pin, ConcreteParasitic **parasitics = drvr_parasitic_map_.findKey(drvr_pin); if (parasitics == nullptr) { int ap_count = corners_->parasiticAnalysisPtCount(); - int ap_tr_count = ap_count * TransRiseFall::index_count; - parasitics = new ConcreteParasitic*[ap_tr_count]; - for (int i = 0; i < ap_tr_count; i++) + int ap_rf_count = ap_count * RiseFall::index_count; + parasitics = new ConcreteParasitic*[ap_rf_count]; + for (int i = 0; i < ap_rf_count; i++) parasitics[i] = nullptr; drvr_parasitic_map_[drvr_pin] = parasitics; } - int ap_tr_index = parasiticAnalysisPtIndex(ap, tr); - ConcreteParasitic *parasitic = parasitics[ap_tr_index]; + int ap_rf_index = parasiticAnalysisPtIndex(ap, rf); + ConcreteParasitic *parasitic = parasitics[ap_rf_index]; ConcretePiElmore *pi_elmore = nullptr; if (parasitic) { if (parasitic->isPiElmore()) { @@ -1085,12 +1085,12 @@ ConcreteParasitics::makePiElmore(const Pin *drvr_pin, else { delete parasitic; pi_elmore = new ConcretePiElmore(c2, rpi, c1); - parasitics[ap_tr_index] = pi_elmore; + parasitics[ap_rf_index] = pi_elmore; } } else { pi_elmore = new ConcretePiElmore(c2, rpi, c1); - parasitics[ap_tr_index] = pi_elmore; + parasitics[ap_rf_index] = pi_elmore; } return pi_elmore; } @@ -1156,18 +1156,18 @@ ConcreteParasitics::isPiPoleResidue(Parasitic* parasitic) const Parasitic * ConcreteParasitics::findPiPoleResidue(const Pin *drvr_pin, - const TransRiseFall *tr, + const RiseFall *rf, const ParasiticAnalysisPt *ap) const { if (!drvr_parasitic_map_.empty()) { - int ap_tr_index = parasiticAnalysisPtIndex(ap, tr); + int ap_rf_index = parasiticAnalysisPtIndex(ap, rf); UniqueLock lock(lock_); ConcreteParasitic **parasitics = drvr_parasitic_map_.findKey(drvr_pin); if (parasitics) { - ConcreteParasitic *parasitic = parasitics[ap_tr_index]; - if (parasitic == nullptr && tr == TransRiseFall::fall()) { - ap_tr_index = parasiticAnalysisPtIndex(ap, TransRiseFall::rise()); - parasitic = parasitics[ap_tr_index]; + ConcreteParasitic *parasitic = parasitics[ap_rf_index]; + if (parasitic == nullptr && rf == RiseFall::fall()) { + ap_rf_index = parasiticAnalysisPtIndex(ap, RiseFall::rise()); + parasitic = parasitics[ap_rf_index]; } if (parasitic->isPiPoleResidue()) return parasitic; @@ -1178,7 +1178,7 @@ ConcreteParasitics::findPiPoleResidue(const Pin *drvr_pin, Parasitic * ConcreteParasitics::makePiPoleResidue(const Pin *drvr_pin, - const TransRiseFall *tr, + const RiseFall *rf, const ParasiticAnalysisPt *ap, float c2, float rpi, @@ -1188,14 +1188,14 @@ ConcreteParasitics::makePiPoleResidue(const Pin *drvr_pin, ConcreteParasitic **parasitics = drvr_parasitic_map_.findKey(drvr_pin); if (parasitics == nullptr) { int ap_count = corners_->parasiticAnalysisPtCount(); - int ap_tr_count = ap_count * TransRiseFall::index_count; - parasitics = new ConcreteParasitic*[ap_tr_count]; - for (int i = 0; i < ap_tr_count; i++) + int ap_rf_count = ap_count * RiseFall::index_count; + parasitics = new ConcreteParasitic*[ap_rf_count]; + for (int i = 0; i < ap_rf_count; i++) parasitics[i] = nullptr; drvr_parasitic_map_[drvr_pin] = parasitics; } - int ap_tr_index = parasiticAnalysisPtIndex(ap, tr); - ConcreteParasitic *parasitic = parasitics[ap_tr_index]; + int ap_rf_index = parasiticAnalysisPtIndex(ap, rf); + ConcreteParasitic *parasitic = parasitics[ap_rf_index]; ConcretePiPoleResidue *pi_pole_residue = nullptr; if (parasitic) { if (parasitic->isPiElmore()) { @@ -1205,12 +1205,12 @@ ConcreteParasitics::makePiPoleResidue(const Pin *drvr_pin, else { delete parasitic; pi_pole_residue = new ConcretePiPoleResidue(c2, rpi, c1); - parasitics[ap_tr_index] = pi_pole_residue; + parasitics[ap_rf_index] = pi_pole_residue; } } else { pi_pole_residue = new ConcretePiPoleResidue(c2, rpi, c1); - parasitics[ap_tr_index] = pi_pole_residue; + parasitics[ap_rf_index] = pi_pole_residue; } return pi_pole_residue; } @@ -1652,7 +1652,7 @@ ConcreteParasitics::reduceToPiPoleResidue2(Parasitic *parasitic, Parasitic * ConcreteParasitics::estimatePiElmore(const Pin *drvr_pin, - const TransRiseFall *tr, + const RiseFall *rf, const Wireload *wireload, float fanout, float net_pin_cap, @@ -1663,14 +1663,14 @@ ConcreteParasitics::estimatePiElmore(const Pin *drvr_pin, { float c2, rpi, c1, elmore_res, elmore_cap; bool elmore_use_load_cap; - estimatePiElmore(drvr_pin, tr, wireload, fanout, net_pin_cap, + estimatePiElmore(drvr_pin, rf, wireload, fanout, net_pin_cap, op_cond, corner, min_max, this, c2, rpi, c1, elmore_res, elmore_cap, elmore_use_load_cap); return new ConcretePiElmoreEstimated(c2, rpi, c1, elmore_res, elmore_cap, elmore_use_load_cap, - tr, op_cond, corner, min_max, + rf, op_cond, corner, min_max, sdc_); } diff --git a/parasitics/ConcreteParasitics.hh b/parasitics/ConcreteParasitics.hh index f525acc9..40216046 100644 --- a/parasitics/ConcreteParasitics.hh +++ b/parasitics/ConcreteParasitics.hh @@ -61,10 +61,10 @@ public: virtual bool isPiElmore(Parasitic *parasitic) const; virtual Parasitic *findPiElmore(const Pin *drvr_pin, - const TransRiseFall *tr, + const RiseFall *rf, const ParasiticAnalysisPt *ap) const; virtual Parasitic *makePiElmore(const Pin *drvr_pin, - const TransRiseFall *tr, + const RiseFall *rf, const ParasiticAnalysisPt *ap, float c2, float rpi, float c1); @@ -80,12 +80,12 @@ public: virtual bool isPiPoleResidue(Parasitic* parasitic) const; virtual Parasitic *findPiPoleResidue(const Pin *drvr_pin, - const TransRiseFall *tr, + const RiseFall *rf, const ParasiticAnalysisPt *ap) const; virtual Parasitic *findPoleResidue(const Parasitic *parasitic, const Pin *load_pin) const; virtual Parasitic *makePiPoleResidue(const Pin *drvr_pin, - const TransRiseFall *tr, + const RiseFall *rf, const ParasiticAnalysisPt *ap, float c2, float rpi, float c1); virtual void setPoleResidue(Parasitic *parasitic, const Pin *load_pin, @@ -150,7 +150,7 @@ public: ParasiticNode *node) const; virtual Parasitic *estimatePiElmore(const Pin *drvr_pin, - const TransRiseFall *tr, + const RiseFall *rf, const Wireload *wireload, float fanout, float net_pin_cap, @@ -196,7 +196,7 @@ public: protected: int parasiticAnalysisPtIndex(const ParasiticAnalysisPt *ap, - const TransRiseFall *tr) const; + const RiseFall *rf) const; Parasitic *ensureRspf(const Pin *drvr_pin); void makeAnalysisPtAfter(); void deleteReducedParasitics(const Pin *pin); diff --git a/parasitics/ConcreteParasiticsPvt.hh b/parasitics/ConcreteParasiticsPvt.hh index dafa8863..ed0ced20 100644 --- a/parasitics/ConcreteParasiticsPvt.hh +++ b/parasitics/ConcreteParasiticsPvt.hh @@ -157,7 +157,7 @@ public: float elmore_res, float elmore_cap, bool elmore_use_load_cap, - const TransRiseFall *tr, + const RiseFall *rf, const OperatingConditions *op_cond, const Corner *corner, const MinMax *min_max, @@ -174,7 +174,7 @@ private: float elmore_res_; float elmore_cap_; bool elmore_use_load_cap_; - const TransRiseFall *tr_; + const RiseFall *rf_; const OperatingConditions *op_cond_; const Corner *corner_; const MinMax *min_max_; diff --git a/parasitics/EstimateParasitics.cc b/parasitics/EstimateParasitics.cc index e9931d7f..3c170f8a 100644 --- a/parasitics/EstimateParasitics.cc +++ b/parasitics/EstimateParasitics.cc @@ -28,7 +28,7 @@ namespace sta { // loads when driven by a different pin. void EstimateParasitics::estimatePiElmore(const Pin *drvr_pin, - const TransRiseFall *tr, + const RiseFall *rf, const Wireload *wireload, float fanout, float net_pin_cap, @@ -52,7 +52,7 @@ EstimateParasitics::estimatePiElmore(const Pin *drvr_pin, switch (tree) { case WireloadTree::worst_case: estimatePiElmoreWorst(drvr_pin, wireload_cap, wireload_res, - fanout, net_pin_cap, tr, op_cond, corner, + fanout, net_pin_cap, rf, op_cond, corner, min_max, sta, c2, rpi, c1, elmore_res, elmore_cap, elmore_use_load_cap); @@ -60,13 +60,13 @@ EstimateParasitics::estimatePiElmore(const Pin *drvr_pin, case WireloadTree::balanced: case WireloadTree::unknown: estimatePiElmoreBalanced(drvr_pin, wireload_cap, wireload_res, - fanout, net_pin_cap, tr, op_cond, + fanout, net_pin_cap, rf, op_cond, corner, min_max,sta, c2, rpi, c1, elmore_res, elmore_cap, elmore_use_load_cap); break; case WireloadTree::best_case: - estimatePiElmoreBest(drvr_pin, wireload_cap, net_pin_cap, tr, + estimatePiElmoreBest(drvr_pin, wireload_cap, net_pin_cap, rf, op_cond, corner, min_max, c2, rpi, c1, elmore_res, elmore_cap, elmore_use_load_cap); @@ -79,7 +79,7 @@ void EstimateParasitics::estimatePiElmoreBest(const Pin *, float wireload_cap, float net_pin_cap, - const TransRiseFall *, + const RiseFall *, const OperatingConditions *, const Corner *, const MinMax *, @@ -106,7 +106,7 @@ EstimateParasitics::estimatePiElmoreWorst(const Pin *drvr_pin, float wireload_res, float, float net_pin_cap, - const TransRiseFall *tr, + const RiseFall *rf, const OperatingConditions *op_cond, const Corner *corner, const MinMax *min_max, @@ -120,7 +120,7 @@ EstimateParasitics::estimatePiElmoreWorst(const Pin *drvr_pin, { Sdc *sdc = sta->sdc(); float drvr_pin_cap = 0.0; - drvr_pin_cap = sdc->pinCapacitance(drvr_pin, tr, op_cond, corner, min_max); + drvr_pin_cap = sdc->pinCapacitance(drvr_pin, rf, op_cond, corner, min_max); c2 = drvr_pin_cap; rpi = wireload_res; c1 = net_pin_cap - drvr_pin_cap + wireload_cap; @@ -138,7 +138,7 @@ EstimateParasitics::estimatePiElmoreBalanced(const Pin *drvr_pin, float wireload_res, float fanout, float net_pin_cap, - const TransRiseFall *tr, + const RiseFall *rf, const OperatingConditions *op_cond, const Corner *corner, const MinMax *min_max, @@ -168,7 +168,7 @@ EstimateParasitics::estimatePiElmoreBalanced(const Pin *drvr_pin, double y1 = 0.0; double y2 = 0.0; double y3 = 0.0; - y1 = sdc->pinCapacitance(drvr_pin, tr, op_cond, corner, min_max); + y1 = sdc->pinCapacitance(drvr_pin, rf, op_cond, corner, min_max); PinConnectedPinIterator *load_iter = network->connectedPinIterator(drvr_pin); while (load_iter->hasNext()) { @@ -178,10 +178,10 @@ EstimateParasitics::estimatePiElmoreBalanced(const Pin *drvr_pin, Port *port = network->port(load_pin); double load_cap = 0.0; if (network->isLeaf(load_pin)) - load_cap = sdc->pinCapacitance(load_pin, tr, op_cond, + load_cap = sdc->pinCapacitance(load_pin, rf, op_cond, corner, min_max); else if (network->isTopLevelPort(load_pin)) - load_cap = sdc->portExtCap(port, tr, min_max); + load_cap = sdc->portExtCap(port, rf, min_max); else internalError("load pin not leaf or top level"); double cap = load_cap + cap_fanout; diff --git a/parasitics/EstimateParasitics.hh b/parasitics/EstimateParasitics.hh index d7f6e6aa..5595832c 100644 --- a/parasitics/EstimateParasitics.hh +++ b/parasitics/EstimateParasitics.hh @@ -31,7 +31,7 @@ public: protected: // Helper function for wireload estimation. void estimatePiElmore(const Pin *drvr_pin, - const TransRiseFall *tr, + const RiseFall *rf, const Wireload *wireload, float fanout, float net_pin_cap, @@ -49,7 +49,7 @@ protected: void estimatePiElmoreBest(const Pin *drvr_pin, float net_pin_cap, float wireload_cap, - const TransRiseFall *tr, + const RiseFall *rf, const OperatingConditions *op_cond, const Corner *corner, const MinMax *min_max, @@ -65,7 +65,7 @@ protected: float wireload_res, float fanout, float net_pin_cap, - const TransRiseFall *tr, + const RiseFall *rf, const OperatingConditions *op_cond, const Corner *corner, const MinMax *min_max, @@ -79,7 +79,7 @@ protected: float wireload_res, float fanout, float net_pin_cap, - const TransRiseFall *tr, + const RiseFall *rf, const OperatingConditions *op_cond, const Corner *corner, const MinMax *min_max, diff --git a/parasitics/NullParasitics.cc b/parasitics/NullParasitics.cc index 318bb889..742b76f0 100644 --- a/parasitics/NullParasitics.cc +++ b/parasitics/NullParasitics.cc @@ -74,7 +74,7 @@ NullParasitics::capacitance(Parasitic *) const Parasitic * NullParasitics::findPiElmore(const Pin *, - const TransRiseFall *, + const RiseFall *, const ParasiticAnalysisPt *) const { return nullptr; @@ -82,7 +82,7 @@ NullParasitics::findPiElmore(const Pin *, Parasitic * NullParasitics::makePiElmore(const Pin *, - const TransRiseFall *, + const RiseFall *, const ParasiticAnalysisPt *, float, float, @@ -154,7 +154,7 @@ NullParasitics::isPiPoleResidue(Parasitic* ) const Parasitic * NullParasitics::findPiPoleResidue(const Pin *, - const TransRiseFall *, + const RiseFall *, const ParasiticAnalysisPt *) const { return nullptr; @@ -162,7 +162,7 @@ NullParasitics::findPiPoleResidue(const Pin *, Parasitic * NullParasitics::makePiPoleResidue(const Pin *, - const TransRiseFall *, + const RiseFall *, const ParasiticAnalysisPt *, float, float, @@ -432,7 +432,7 @@ NullParasitics::reduceToPiPoleResidue2(Parasitic *, Parasitic * NullParasitics::estimatePiElmore(const Pin *, - const TransRiseFall *, + const RiseFall *, const Wireload *, float, float, diff --git a/parasitics/NullParasitics.hh b/parasitics/NullParasitics.hh index 406b1eb0..7d8364fa 100644 --- a/parasitics/NullParasitics.hh +++ b/parasitics/NullParasitics.hh @@ -42,10 +42,10 @@ public: virtual Parasitic * findPiElmore(const Pin *drvr_pin, - const TransRiseFall *tr, + const RiseFall *rf, const ParasiticAnalysisPt *ap) const; virtual Parasitic *makePiElmore(const Pin *drvr_pin, - const TransRiseFall *tr, + const RiseFall *rf, const ParasiticAnalysisPt *ap, float c2, float rpi, float c1); virtual bool isPiElmore(Parasitic *parasitic) const; @@ -66,10 +66,10 @@ public: virtual bool isPiPoleResidue(Parasitic* parasitic) const; virtual Parasitic * findPiPoleResidue(const Pin *drvr_pin, - const TransRiseFall *tr, + const RiseFall *rf, const ParasiticAnalysisPt *ap) const; virtual Parasitic *makePiPoleResidue(const Pin *drvr_pin, - const TransRiseFall *tr, + const RiseFall *rf, const ParasiticAnalysisPt *ap, float c2, float rpi, float c1); @@ -173,7 +173,7 @@ public: const ParasiticAnalysisPt *ap); virtual Parasitic * estimatePiElmore(const Pin *drvr_pin, - const TransRiseFall *tr, + const RiseFall *rf, const Wireload *wireload, float fanout, float net_pin_cap, diff --git a/parasitics/Parasitics.hh b/parasitics/Parasitics.hh index 023e5810..209d487f 100644 --- a/parasitics/Parasitics.hh +++ b/parasitics/Parasitics.hh @@ -77,10 +77,10 @@ public: // capacitor on the driver pin. virtual bool isPiElmore(Parasitic *parasitic) const = 0; virtual Parasitic *findPiElmore(const Pin *drvr_pin, - const TransRiseFall *tr, + const RiseFall *rf, const ParasiticAnalysisPt *ap) const = 0; virtual Parasitic *makePiElmore(const Pin *drvr_pin, - const TransRiseFall *tr, + const RiseFall *rf, const ParasiticAnalysisPt *ap, float c2, float rpi, @@ -115,10 +115,10 @@ public: // Pi model driver load with pole/residue interconnect model to load pins. virtual bool isPiPoleResidue(Parasitic* parasitic) const = 0; virtual Parasitic *findPiPoleResidue(const Pin *drvr_pin, - const TransRiseFall *tr, + const RiseFall *rf, const ParasiticAnalysisPt *ap) const=0; virtual Parasitic *makePiPoleResidue(const Pin *drvr_pin, - const TransRiseFall *tr, + const RiseFall *rf, const ParasiticAnalysisPt *ap, float c2, float rpi, @@ -262,7 +262,7 @@ public: // Estimate parasitic as pi elmore using wireload model. virtual Parasitic *estimatePiElmore(const Pin *drvr_pin, - const TransRiseFall *tr, + const RiseFall *rf, const Wireload *wireload, float fanout, float net_pin_cap, diff --git a/parasitics/Parasitics.i b/parasitics/Parasitics.i index 9ecefbc9..232aa63f 100644 --- a/parasitics/Parasitics.i +++ b/parasitics/Parasitics.i @@ -25,7 +25,7 @@ using sta::cmdLinkedNetwork; using sta::Instance; using sta::MinMaxAll; using sta::ReduceParasiticsTo; -using sta::TransRiseFall; +using sta::RiseFall; using sta::Pin; using sta::TmpFloatSeq; @@ -56,12 +56,12 @@ read_spef_cmd(const char *filename, TmpFloatSeq * find_pi_elmore(Pin *drvr_pin, - TransRiseFall *tr, + RiseFall *rf, MinMax *min_max) { float c2, rpi, c1; bool exists; - Sta::sta()->findPiElmore(drvr_pin, tr, min_max, c2, rpi, c1, exists); + Sta::sta()->findPiElmore(drvr_pin, rf, min_max, c2, rpi, c1, exists); TmpFloatSeq *floats = new FloatSeq; if (exists) { floats->push_back(c2); @@ -74,34 +74,34 @@ find_pi_elmore(Pin *drvr_pin, float find_elmore(Pin *drvr_pin, Pin *load_pin, - TransRiseFall *tr, + RiseFall *rf, MinMax *min_max) { float elmore = 0.0; bool exists; - Sta::sta()->findElmore(drvr_pin, load_pin, tr, min_max, elmore, exists); + Sta::sta()->findElmore(drvr_pin, load_pin, rf, min_max, elmore, exists); return elmore; } void set_pi_model_cmd(Pin *drvr_pin, - TransRiseFall *tr, + RiseFall *rf, MinMaxAll *min_max, float c2, float rpi, float c1) { - Sta::sta()->makePiElmore(drvr_pin, tr, min_max, c2, rpi, c1); + Sta::sta()->makePiElmore(drvr_pin, rf, min_max, c2, rpi, c1); } void set_elmore_cmd(Pin *drvr_pin, Pin *load_pin, - TransRiseFall *tr, + RiseFall *rf, MinMaxAll *min_max, float elmore) { - Sta::sta()->setElmore(drvr_pin, load_pin, tr, min_max, elmore); + Sta::sta()->setElmore(drvr_pin, load_pin, rf, min_max, elmore); } %} // inline diff --git a/parasitics/ReduceParasitics.cc b/parasitics/ReduceParasitics.cc index 9ae27e17..e2f25bf3 100644 --- a/parasitics/ReduceParasitics.cc +++ b/parasitics/ReduceParasitics.cc @@ -40,7 +40,7 @@ public: ParasiticNode *drvr_node, bool includes_pin_caps, float coupling_cap_factor, - const TransRiseFall *tr, + const RiseFall *rf, const OperatingConditions *op_cond, const Corner *corner, const MinMax *cnst_min_max, @@ -71,7 +71,7 @@ protected: bool includes_pin_caps_; float coupling_cap_multiplier_; - const TransRiseFall *tr_; + const RiseFall *rf_; const OperatingConditions *op_cond_; const Corner *corner_; const MinMax *cnst_min_max_; @@ -84,7 +84,7 @@ protected: ReduceToPi::ReduceToPi(StaState *sta) : StaState(sta), coupling_cap_multiplier_(1.0), - tr_(nullptr), + rf_(nullptr), op_cond_(nullptr), corner_(nullptr), cnst_min_max_(nullptr), @@ -101,7 +101,7 @@ ReduceToPi::reduceToPi(const Pin *drvr_pin, ParasiticNode *drvr_node, bool includes_pin_caps, float coupling_cap_factor, - const TransRiseFall *tr, + const RiseFall *rf, const OperatingConditions *op_cond, const Corner *corner, const MinMax *cnst_min_max, @@ -112,7 +112,7 @@ ReduceToPi::reduceToPi(const Pin *drvr_pin, { includes_pin_caps_ = includes_pin_caps; coupling_cap_multiplier_ = coupling_cap_factor; - tr_ = tr; + rf_ = rf; op_cond_ = op_cond; corner_ = corner; cnst_min_max_ = cnst_min_max; @@ -212,13 +212,13 @@ ReduceToPi::pinCapacitance(ParasiticNode *node) LibertyPort *lib_port = network_->libertyPort(port); if (lib_port) { if (!includes_pin_caps_) { - pin_cap = sdc_->pinCapacitance(pin, tr_, op_cond_, corner_, + pin_cap = sdc_->pinCapacitance(pin, rf_, op_cond_, corner_, cnst_min_max_); pin_caps_one_value_ &= lib_port->capacitanceIsOneValue(); } } else if (network_->isTopLevelPort(pin)) - pin_cap = sdc_->portExtCap(port, tr_, cnst_min_max_); + pin_cap = sdc_->portExtCap(port, rf_, cnst_min_max_); } return pin_cap; } @@ -276,7 +276,7 @@ public: const Pin *drvr_pin, ParasiticNode *drvr_node, float coupling_cap_factor, - const TransRiseFall *tr, + const RiseFall *rf, const OperatingConditions *op_cond, const Corner *corner, const MinMax *cnst_min_max, @@ -308,11 +308,11 @@ reduceToPiElmore(Parasitic *parasitic_network, sta->network()->pathName(drvr_pin)); ReduceToPiElmore reducer(sta); reducer.makePiElmore(parasitic_network, drvr_pin, drvr_node, - coupling_cap_factor, TransRiseFall::rise(), + coupling_cap_factor, RiseFall::rise(), op_cond, corner, cnst_min_max, ap); if (!reducer.pinCapsOneValue()) reducer.makePiElmore(parasitic_network, drvr_pin, drvr_node, - coupling_cap_factor, TransRiseFall::fall(), + coupling_cap_factor, RiseFall::fall(), op_cond, corner, cnst_min_max, ap); } } @@ -327,7 +327,7 @@ ReduceToPiElmore::makePiElmore(Parasitic *parasitic_network, const Pin *drvr_pin, ParasiticNode *drvr_node, float coupling_cap_factor, - const TransRiseFall *tr, + const RiseFall *rf, const OperatingConditions *op_cond, const Corner *corner, const MinMax *cnst_min_max, @@ -337,9 +337,9 @@ ReduceToPiElmore::makePiElmore(Parasitic *parasitic_network, reduceToPi(drvr_pin, drvr_node, parasitics_->includesPinCaps(parasitic_network), coupling_cap_factor, - tr, op_cond, corner, cnst_min_max, ap, + rf, op_cond, corner, cnst_min_max, ap, c2, rpi, c1); - Parasitic *pi_elmore = parasitics_->makePiElmore(drvr_pin, tr, ap, + Parasitic *pi_elmore = parasitics_->makePiElmore(drvr_pin, rf, ap, c2, rpi, c1); parasitics_->setIsReducedParasiticNetwork(pi_elmore, true); reduceElmoreDfs(drvr_pin, drvr_node, 0, 0.0, pi_elmore, ap); @@ -401,7 +401,7 @@ public: const Pin *drvr_pin, ParasiticNode *drvr_node, float coupling_cap_factor, - const TransRiseFall *tr, + const RiseFall *rf, const OperatingConditions *op_cond, const Corner *corner, const MinMax *cnst_min_max, @@ -475,11 +475,11 @@ reduceToPiPoleResidue2(Parasitic *parasitic_network, sta->network()->pathName(drvr_pin)); ReduceToPiPoleResidue2 reducer(sta); reducer.makePiPoleResidue2(parasitic_network, drvr_pin, drvr_node, - coupling_cap_factor, TransRiseFall::rise(), + coupling_cap_factor, RiseFall::rise(), op_cond, corner, cnst_min_max, ap); if (!reducer.pinCapsOneValue()) reducer.makePiPoleResidue2(parasitic_network, drvr_pin, drvr_node, - coupling_cap_factor, TransRiseFall::fall(), + coupling_cap_factor, RiseFall::fall(), op_cond, corner, cnst_min_max, ap); } } @@ -489,7 +489,7 @@ ReduceToPiPoleResidue2::makePiPoleResidue2(Parasitic *parasitic_network, const Pin *drvr_pin, ParasiticNode *drvr_node, float coupling_cap_factor, - const TransRiseFall *tr, + const RiseFall *rf, const OperatingConditions *op_cond, const Corner *corner, const MinMax *cnst_min_max, @@ -499,10 +499,10 @@ ReduceToPiPoleResidue2::makePiPoleResidue2(Parasitic *parasitic_network, reduceToPi(drvr_pin, drvr_node, parasitics_->includesPinCaps(parasitic_network), coupling_cap_factor, - tr, op_cond, corner, cnst_min_max, ap, + rf, op_cond, corner, cnst_min_max, ap, c2, rpi, c1); Parasitic *pi_pole_residue = parasitics_->makePiPoleResidue(drvr_pin, - tr, ap, + rf, ap, c2, rpi, c1); parasitics_->setIsReducedParasiticNetwork(pi_pole_residue, true); findPolesResidues(parasitic_network, pi_pole_residue, diff --git a/parasitics/SpefReader.cc b/parasitics/SpefReader.cc index e992502c..9a167eb4 100644 --- a/parasitics/SpefReader.cc +++ b/parasitics/SpefReader.cc @@ -408,7 +408,7 @@ SpefReader::rspfDrvrBegin(Pin *drvr_pin, if (drvr_pin) { // Incremental parasitics do not overwrite existing parasitics. if (!(increment_ && - parasitics_->findPiElmore(drvr_pin, TransRiseFall::rise(), ap_))) { + parasitics_->findPiElmore(drvr_pin, RiseFall::rise(), ap_))) { float c2 = pi->c2()->value(triple_index_) * cap_scale_; float rpi = pi->r1()->value(triple_index_) * res_scale_; float c1 = pi->c1()->value(triple_index_) * cap_scale_; @@ -416,7 +416,7 @@ SpefReader::rspfDrvrBegin(Pin *drvr_pin, parasitics_->deleteParasitics(drvr_pin, ap_); // Only one parasitic, save it under rise transition. parasitic_ = parasitics_->makePiElmore(drvr_pin, - TransRiseFall::rise(), + RiseFall::rise(), ap_, c2, rpi, c1); } } diff --git a/sdc/Clock.cc b/sdc/Clock.cc index 4c7ffc14..b3720e65 100644 --- a/sdc/Clock.cc +++ b/sdc/Clock.cc @@ -115,8 +115,8 @@ Clock::setMasterClk(Clock *master) void Clock::makeClkEdges() { - clk_edges_ = new ClockEdge*[TransRiseFall::index_count]; - for (auto tr : TransRiseFall::range()) { + clk_edges_ = new ClockEdge*[RiseFall::index_count]; + for (auto tr : RiseFall::range()) { clk_edges_[tr->index()] = new ClockEdge(this, tr); } } @@ -125,8 +125,8 @@ Clock::~Clock() { stringDelete(name_); if (clk_edges_) { - delete clk_edges_[TransRiseFall::riseIndex()]; - delete clk_edges_[TransRiseFall::fallIndex()]; + delete clk_edges_[RiseFall::riseIndex()]; + delete clk_edges_[RiseFall::fallIndex()]; delete [] clk_edges_; } delete waveform_; @@ -157,15 +157,15 @@ Clock::setAddToPins(bool add_to_pins) void Clock::setClkEdgeTimes() { - setClkEdgeTime(TransRiseFall::rise()); - setClkEdgeTime(TransRiseFall::fall()); + setClkEdgeTime(RiseFall::rise()); + setClkEdgeTime(RiseFall::fall()); } void -Clock::setClkEdgeTime(const TransRiseFall *tr) +Clock::setClkEdgeTime(const RiseFall *rf) { - float time = (tr == TransRiseFall::rise()) ? (*waveform_)[0]:(*waveform_)[1]; - clk_edges_[tr->index()]->setTime(time); + float time = (rf == RiseFall::rise()) ? (*waveform_)[0]:(*waveform_)[1]; + clk_edges_[rf->index()]->setTime(time); } Pin * @@ -179,9 +179,9 @@ Clock::defaultPin() const } ClockEdge * -Clock::edge(const TransRiseFall *tr) const +Clock::edge(const RiseFall *rf) const { - return clk_edges_[tr->index()]; + return clk_edges_[rf->index()]; } void @@ -191,41 +191,41 @@ Clock::setIsPropagated(bool propagated) } void -Clock::slew(const TransRiseFall *tr, +Clock::slew(const RiseFall *rf, const MinMax *min_max, // Return values. float &slew, bool &exists) const { - slews_.value(tr, min_max, slew, exists); + slews_.value(rf, min_max, slew, exists); } float -Clock::slew(const TransRiseFall *tr, +Clock::slew(const RiseFall *rf, const MinMax *min_max) const { float slew; bool exists; - slews_.value(tr, min_max, slew, exists); + slews_.value(rf, min_max, slew, exists); if (!exists) slew = 0.0; return slew; } void -Clock::setSlew(const TransRiseFallBoth *tr, +Clock::setSlew(const RiseFallBoth *rf, const MinMaxAll *min_max, float slew) { - slews_.setValue(tr, min_max, slew); + slews_.setValue(rf, min_max, slew); } void -Clock::setSlew(const TransRiseFall *tr, +Clock::setSlew(const RiseFall *rf, const MinMax *min_max, float slew) { - slews_.setValue(tr, min_max, slew); + slews_.setValue(rf, min_max, slew); } void @@ -235,23 +235,23 @@ Clock::removeSlew() } void -Clock::setSlewLimit(const TransRiseFallBoth *tr, +Clock::setSlewLimit(const RiseFallBoth *rf, const PathClkOrData clk_data, const MinMax *min_max, float slew) { - slew_limits_[int(clk_data)].setValue(tr, min_max, slew); + slew_limits_[int(clk_data)].setValue(rf, min_max, slew); } void -Clock::slewLimit(const TransRiseFall *tr, +Clock::slewLimit(const RiseFall *rf, const PathClkOrData clk_data, const MinMax *min_max, // Return values. float &slew, bool &exists) const { - slew_limits_[int(clk_data)].value(tr, min_max, slew, exists); + slew_limits_[int(clk_data)].value(rf, min_max, slew, exists); } void @@ -482,13 +482,13 @@ isPowerOfTwo(int i) return (i & (i - 1)) == 0; } -const TransRiseFall * -Clock::masterClkEdgeTr(const TransRiseFall *tr) const +const RiseFall * +Clock::masterClkEdgeTr(const RiseFall *rf) const { - int edge_index = (tr == TransRiseFall::rise()) ? 0 : 1; + int edge_index = (rf == RiseFall::rise()) ? 0 : 1; return ((*edges_)[edge_index] - 1) % 2 - ? TransRiseFall::fall() - : TransRiseFall::rise(); + ? RiseFall::fall() + : RiseFall::rise(); } void @@ -529,12 +529,12 @@ Clock::isDivideByOneCombinational() const //////////////////////////////////////////////////////////////// ClockEdge::ClockEdge(Clock *clock, - TransRiseFall *tr) : + RiseFall *rf) : clock_(clock), - tr_(tr), - name_(stringPrint("%s %s", clock_->name(), tr_->asString())), + rf_(rf), + name_(stringPrint("%s %s", clock_->name(), rf_->asString())), time_(0.0), - index_(clock_->index() * TransRiseFall::index_count + tr_->index()) + index_(clock_->index() * RiseFall::index_count + rf_->index()) { } @@ -552,7 +552,7 @@ ClockEdge::setTime(float time) ClockEdge * ClockEdge::opposite() const { - return clock_->edge(tr_->opposite()); + return clock_->edge(rf_->opposite()); } float @@ -630,44 +630,44 @@ InterClockUncertainty::InterClockUncertainty(const Clock *src, bool InterClockUncertainty::empty() const { - return uncertainties_[TransRiseFall::riseIndex()].empty() - && uncertainties_[TransRiseFall::fallIndex()].empty(); + return uncertainties_[RiseFall::riseIndex()].empty() + && uncertainties_[RiseFall::fallIndex()].empty(); } void -InterClockUncertainty::uncertainty(const TransRiseFall *src_tr, - const TransRiseFall *tgt_tr, +InterClockUncertainty::uncertainty(const RiseFall *src_rf, + const RiseFall *tgt_rf, const SetupHold *setup_hold, float &uncertainty, bool &exists) const { - uncertainties_[src_tr->index()].value(tgt_tr, setup_hold, + uncertainties_[src_rf->index()].value(tgt_rf, setup_hold, uncertainty, exists); } void -InterClockUncertainty::setUncertainty(const TransRiseFallBoth *src_tr, - const TransRiseFallBoth *tgt_tr, +InterClockUncertainty::setUncertainty(const RiseFallBoth *src_rf, + const RiseFallBoth *tgt_rf, const SetupHoldAll *setup_hold, float uncertainty) { - for (auto src_tr_index : src_tr->rangeIndex()) - uncertainties_[src_tr_index].setValue(tgt_tr, setup_hold, uncertainty); + for (auto src_rf_index : src_rf->rangeIndex()) + uncertainties_[src_rf_index].setValue(tgt_rf, setup_hold, uncertainty); } void -InterClockUncertainty::removeUncertainty(const TransRiseFallBoth *src_tr, - const TransRiseFallBoth *tgt_tr, +InterClockUncertainty::removeUncertainty(const RiseFallBoth *src_rf, + const RiseFallBoth *tgt_rf, const SetupHoldAll *setup_hold) { - for (auto src_tr_index : src_tr->rangeIndex()) - uncertainties_[src_tr_index].removeValue(tgt_tr, setup_hold); + for (auto src_rf_index : src_rf->rangeIndex()) + uncertainties_[src_rf_index].removeValue(tgt_rf, setup_hold); } const RiseFallMinMax * -InterClockUncertainty::uncertainties(TransRiseFall *src_tr) const +InterClockUncertainty::uncertainties(RiseFall *src_rf) const { - return &uncertainties_[src_tr->index()]; + return &uncertainties_[src_rf->index()]; } bool diff --git a/sdc/Clock.hh b/sdc/Clock.hh index ebbff6dd..eebf9482 100644 --- a/sdc/Clock.hh +++ b/sdc/Clock.hh @@ -51,32 +51,32 @@ public: void setAddToPins(bool add_to_pins); FloatSeq *waveform() { return waveform_; } const FloatSeq *waveform() const { return waveform_; } - ClockEdge *edge(const TransRiseFall *tr) const; + ClockEdge *edge(const RiseFall *rf) const; int index() const { return index_; } bool isPropagated() const { return is_propagated_; } void setIsPropagated(bool propagated); // Ideal clock slew. - void slew(const TransRiseFall *tr, + void slew(const RiseFall *rf, const MinMax *min_max, // Return values. float &slew, bool &exists) const; // Return zero (default) if no slew exists. - float slew(const TransRiseFall *tr, + float slew(const RiseFall *rf, const MinMax *min_max) const; - void setSlew(const TransRiseFall *tr, + void setSlew(const RiseFall *rf, const MinMax *min_max, float slew); - void setSlew(const TransRiseFallBoth *tr, + void setSlew(const RiseFallBoth *rf, const MinMaxAll *min_max, float slew); void removeSlew(); RiseFallMinMax *slews() { return &slews_; } - void setSlewLimit(const TransRiseFallBoth *tr, + void setSlewLimit(const RiseFallBoth *rf, const PathClkOrData clk_data, const MinMax *min_max, float slew); - void slewLimit(const TransRiseFall *tr, + void slewLimit(const RiseFall *rf, const PathClkOrData clk_data, const MinMax *min_max, // Return values. @@ -115,7 +115,7 @@ public: bool invert() const { return invert_; } IntSeq *edges() const { return edges_; } FloatSeq *edgeShifts() const { return edge_shifts_; } - const TransRiseFall *masterClkEdgeTr(const TransRiseFall *tr) const; + const RiseFall *masterClkEdgeTr(const RiseFall *rf) const; bool combinational() const { return combinational_; } bool isDivideByOneCombinational() const; bool generatedUpToDate() const; @@ -157,7 +157,7 @@ protected: void setMasterClk(Clock *master); void makeClkEdges(); void setClkEdgeTimes(); - void setClkEdgeTime(const TransRiseFall *tr); + void setClkEdgeTime(const RiseFall *rf); void generateScaledClk(const Clock *src_clk, float scale); void generateEdgesClk(const Clock *src_clk); @@ -204,7 +204,7 @@ class ClockEdge public: Clock *clock() const { return clock_; } ~ClockEdge(); - TransRiseFall *transition() const { return tr_; } + RiseFall *transition() const { return rf_; } float time() const { return time_; } const char *name() const { return name_; } int index() const { return index_; } @@ -215,11 +215,11 @@ public: friend class Clock; // builder private: DISALLOW_COPY_AND_ASSIGN(ClockEdge); - ClockEdge(Clock *clock, TransRiseFall *tr); + ClockEdge(Clock *clock, RiseFall *rf); void setTime(float time); Clock *clock_; - TransRiseFall *tr_; + RiseFall *rf_; const char *name_; float time_; int index_; @@ -250,20 +250,20 @@ public: const Clock *target); const Clock *src() const { return src_; } const Clock *target() const { return target_; } - void uncertainty(const TransRiseFall *src_tr, - const TransRiseFall *tgt_tr, + void uncertainty(const RiseFall *src_rf, + const RiseFall *tgt_rf, const SetupHold *setup_hold, // Return values. float &uncertainty, bool &exists) const; - void setUncertainty(const TransRiseFallBoth *src_tr, - const TransRiseFallBoth *tgt_tr, + void setUncertainty(const RiseFallBoth *src_rf, + const RiseFallBoth *tgt_rf, const SetupHoldAll *setup_hold, float uncertainty); - void removeUncertainty(const TransRiseFallBoth *src_tr, - const TransRiseFallBoth *tgt_tr, + void removeUncertainty(const RiseFallBoth *src_rf, + const RiseFallBoth *tgt_rf, const SetupHoldAll *setup_hold); - const RiseFallMinMax *uncertainties(TransRiseFall *src_tr) const; + const RiseFallMinMax *uncertainties(RiseFall *src_rf) const; bool empty() const; private: @@ -271,7 +271,7 @@ private: const Clock *src_; const Clock *target_; - RiseFallMinMax uncertainties_[TransRiseFall::index_count]; + RiseFallMinMax uncertainties_[RiseFall::index_count]; }; class InterClockUncertaintyLess diff --git a/sdc/ClockInsertion.cc b/sdc/ClockInsertion.cc index b68a64fb..72682094 100644 --- a/sdc/ClockInsertion.cc +++ b/sdc/ClockInsertion.cc @@ -27,23 +27,23 @@ ClockInsertion::ClockInsertion(const Clock *clk, } void -ClockInsertion::setDelay(const TransRiseFallBoth *tr, +ClockInsertion::setDelay(const RiseFallBoth *rf, const MinMaxAll *min_max, const EarlyLateAll *early_late, float delay) { for (auto el_index : early_late->rangeIndex()) - delays_[el_index].setValue(tr, min_max, delay); + delays_[el_index].setValue(rf, min_max, delay); } float -ClockInsertion::delay(const TransRiseFall *tr, +ClockInsertion::delay(const RiseFall *rf, const MinMax *min_max, const EarlyLate *early_late) { float insertion; bool exists; - delays_[early_late->index()].value(tr, min_max, insertion, exists); + delays_[early_late->index()].value(rf, min_max, insertion, exists); if (exists) return insertion; else @@ -51,7 +51,7 @@ ClockInsertion::delay(const TransRiseFall *tr, } void -ClockInsertion::delay(const TransRiseFall *tr, +ClockInsertion::delay(const RiseFall *rf, const MinMax *min_max, const EarlyLate *early_late, // Return values. @@ -59,18 +59,18 @@ ClockInsertion::delay(const TransRiseFall *tr, bool &exists) { - delays_[early_late->index()].value(tr, min_max, insertion, exists); + delays_[early_late->index()].value(rf, min_max, insertion, exists); if (!exists) insertion = 0.0; } void -ClockInsertion::setDelay(const TransRiseFall *tr, +ClockInsertion::setDelay(const RiseFall *rf, const MinMax *min_max, const EarlyLate *early_late, float delay) { - delays_[early_late->index()].setValue(tr, min_max, delay); + delays_[early_late->index()].setValue(rf, min_max, delay); } void diff --git a/sdc/ClockInsertion.hh b/sdc/ClockInsertion.hh index 196b8570..09b745b3 100644 --- a/sdc/ClockInsertion.hh +++ b/sdc/ClockInsertion.hh @@ -32,16 +32,16 @@ public: ClockInsertion(const Clock *clk, const Pin *pin); const Clock *clock() const { return clk_; } const Pin *pin() const { return pin_; } - float delay(const TransRiseFall *tr, const MinMax *min_max, + float delay(const RiseFall *rf, const MinMax *min_max, const EarlyLate *early_late); - void delay(const TransRiseFall *tr, const MinMax *min_max, + void delay(const RiseFall *rf, const MinMax *min_max, const EarlyLate *early_late, // Return values. float &insertion, bool &exists); RiseFallMinMax *delays(const EarlyLate *early_late); - void setDelay(const TransRiseFall *tr, const MinMax *min_max, + void setDelay(const RiseFall *rf, const MinMax *min_max, const EarlyLate *early_late, float delay); - void setDelay(const TransRiseFallBoth *tr, const MinMaxAll *min_max, + void setDelay(const RiseFallBoth *rf, const MinMaxAll *min_max, const EarlyLateAll *early_late, float delay); void setDelays(RiseFallMinMax *delays); diff --git a/sdc/ClockLatency.cc b/sdc/ClockLatency.cc index 873b93cb..6d5ccb95 100644 --- a/sdc/ClockLatency.cc +++ b/sdc/ClockLatency.cc @@ -27,20 +27,20 @@ ClockLatency::ClockLatency(const Clock *clk, } void -ClockLatency::setDelay(const TransRiseFallBoth *tr, +ClockLatency::setDelay(const RiseFallBoth *rf, const MinMaxAll *min_max, float delay) { - delays_.setValue(tr, min_max, delay); + delays_.setValue(rf, min_max, delay); } float -ClockLatency::delay(const TransRiseFall *tr, +ClockLatency::delay(const RiseFall *rf, const MinMax *min_max) { float latency; bool exists; - delays_.value(tr, min_max, latency, exists); + delays_.value(rf, min_max, latency, exists); if (exists) return latency; else @@ -48,24 +48,24 @@ ClockLatency::delay(const TransRiseFall *tr, } void -ClockLatency::delay(const TransRiseFall *tr, +ClockLatency::delay(const RiseFall *rf, const MinMax *min_max, // Return values. float &latency, bool &exists) { - delays_.value(tr, min_max, latency, exists); + delays_.value(rf, min_max, latency, exists); if (!exists) latency = 0.0; } void -ClockLatency::setDelay(const TransRiseFall *tr, +ClockLatency::setDelay(const RiseFall *rf, const MinMax *min_max, float delay) { - delays_.setValue(tr, min_max, delay); + delays_.setValue(rf, min_max, delay); } void diff --git a/sdc/ClockLatency.hh b/sdc/ClockLatency.hh index 53f21811..c9c097c2 100644 --- a/sdc/ClockLatency.hh +++ b/sdc/ClockLatency.hh @@ -33,18 +33,18 @@ public: const Pin *pin); const Clock *clock() const { return clk_; } const Pin *pin() const { return pin_; } - float delay(const TransRiseFall *tr, + float delay(const RiseFall *rf, const MinMax *min_max); - void delay(const TransRiseFall *tr, + void delay(const RiseFall *rf, const MinMax *min_max, // Return values. float &latency, bool &exists); RiseFallMinMax *delays(); - void setDelay(const TransRiseFall *tr, + void setDelay(const RiseFall *rf, const MinMax *min_max, float delay); - void setDelay(const TransRiseFallBoth *tr, + void setDelay(const RiseFallBoth *rf, const MinMaxAll *min_max, float delay); void setDelays(RiseFallMinMax *delays); diff --git a/sdc/DataCheck.cc b/sdc/DataCheck.cc index 70edf314..08168aec 100644 --- a/sdc/DataCheck.cc +++ b/sdc/DataCheck.cc @@ -30,40 +30,40 @@ DataCheck::DataCheck(Pin *from, } void -DataCheck::margin(const TransRiseFall *from_tr, - const TransRiseFall *to_tr, +DataCheck::margin(const RiseFall *from_rf, + const RiseFall *to_rf, const SetupHold *setup_hold, // Return values. float &margin, bool &exists) const { - return margins_[from_tr->index()].value(to_tr, setup_hold, + return margins_[from_rf->index()].value(to_rf, setup_hold, margin, exists); } void -DataCheck::setMargin(const TransRiseFallBoth *from_tr, - const TransRiseFallBoth *to_tr, +DataCheck::setMargin(const RiseFallBoth *from_rf, + const RiseFallBoth *to_rf, const SetupHoldAll *setup_hold, float margin) { - for (auto from_tr_index : from_tr->rangeIndex()) - margins_[from_tr_index].setValue(to_tr, setup_hold, margin); + for (auto from_rf_index : from_rf->rangeIndex()) + margins_[from_rf_index].setValue(to_rf, setup_hold, margin); } void -DataCheck::removeMargin(const TransRiseFallBoth *from_tr, - const TransRiseFallBoth *to_tr, +DataCheck::removeMargin(const RiseFallBoth *from_rf, + const RiseFallBoth *to_rf, const SetupHoldAll *setup_hold) { - for (auto from_tr_index : from_tr->rangeIndex()) - margins_[from_tr_index].removeValue(to_tr, setup_hold); + for (auto from_rf_index : from_rf->rangeIndex()) + margins_[from_rf_index].removeValue(to_rf, setup_hold); } bool DataCheck::empty() const { - for (auto tr_index : TransRiseFall::rangeIndex()) { + for (auto tr_index : RiseFall::rangeIndex()) { if (!margins_[tr_index].empty()) return false; } @@ -77,8 +77,8 @@ DataCheck::marginIsOneValue(SetupHold *setup_hold, bool &one_value) const { float value1, value2; - if (margins_[TransRiseFall::riseIndex()].isOneValue(setup_hold, value1) - && margins_[TransRiseFall::fallIndex()].isOneValue(setup_hold, value2) + if (margins_[RiseFall::riseIndex()].isOneValue(setup_hold, value1) + && margins_[RiseFall::fallIndex()].isOneValue(setup_hold, value2) && value1 == value2) { value = value1; one_value = true; diff --git a/sdc/DataCheck.hh b/sdc/DataCheck.hh index 2a1574fb..ed199069 100644 --- a/sdc/DataCheck.hh +++ b/sdc/DataCheck.hh @@ -38,18 +38,18 @@ public: Pin *from() const { return from_; } Pin *to() const { return to_; } Clock *clk() const { return clk_; } - void margin(const TransRiseFall *from_tr, - const TransRiseFall *to_tr, + void margin(const RiseFall *from_rf, + const RiseFall *to_rf, const SetupHold *setup_hold, // Return values. float &margin, bool &exists) const; - void setMargin(const TransRiseFallBoth *from_tr, - const TransRiseFallBoth *to_tr, + void setMargin(const RiseFallBoth *from_rf, + const RiseFallBoth *to_rf, const SetupHoldAll *setup_hold, float margin); - void removeMargin(const TransRiseFallBoth *from_tr, - const TransRiseFallBoth *to_tr, + void removeMargin(const RiseFallBoth *from_rf, + const RiseFallBoth *to_rf, const SetupHoldAll *setup_hold); bool empty() const; void marginIsOneValue(SetupHold *setup_hold, @@ -63,7 +63,7 @@ private: Pin *from_; Pin *to_; Clock *clk_; - RiseFallMinMax margins_[TransRiseFall::index_count]; + RiseFallMinMax margins_[RiseFall::index_count]; }; class DataCheckLess diff --git a/sdc/DeratingFactors.cc b/sdc/DeratingFactors.cc index a9259c97..bef239b6 100644 --- a/sdc/DeratingFactors.cc +++ b/sdc/DeratingFactors.cc @@ -32,22 +32,22 @@ DeratingFactors::DeratingFactors() void DeratingFactors::setFactor(PathClkOrData clk_data, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, const EarlyLate *early_late, float factor) { - for (auto tr1 : tr->range()) + for (auto tr1 : rf->range()) factors_[int(clk_data)].setValue(tr1, early_late, factor); } void DeratingFactors::factor(PathClkOrData clk_data, - const TransRiseFall *tr, + const RiseFall *rf, const EarlyLate *early_late, float &factor, bool &exists) const { - factors_[int(clk_data)].value(tr, early_late, factor, exists); + factors_[int(clk_data)].value(rf, early_late, factor, exists); } void @@ -98,22 +98,22 @@ DeratingFactorsGlobal::DeratingFactorsGlobal() void DeratingFactorsGlobal::setFactor(TimingDerateType type, PathClkOrData clk_data, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, const EarlyLate *early_late, float factor) { - factors_[TimingDerateIndex(type)].setFactor(clk_data, tr, early_late, factor); + factors_[TimingDerateIndex(type)].setFactor(clk_data, rf, early_late, factor); } void DeratingFactorsGlobal::factor(TimingDerateType type, PathClkOrData clk_data, - const TransRiseFall *tr, + const RiseFall *rf, const EarlyLate *early_late, float &factor, bool &exists) const { - factors_[TimingDerateIndex(type)].factor(clk_data, tr, early_late, factor, exists); + factors_[TimingDerateIndex(type)].factor(clk_data, rf, early_late, factor, exists); } void @@ -139,22 +139,22 @@ DeratingFactorsCell::DeratingFactorsCell() void DeratingFactorsCell::setFactor(TimingDerateType type, PathClkOrData clk_data, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, const EarlyLate *early_late, float factor) { - factors_[TimingDerateIndex(type)].setFactor(clk_data, tr, early_late, factor); + factors_[TimingDerateIndex(type)].setFactor(clk_data, rf, early_late, factor); } void DeratingFactorsCell::factor(TimingDerateType type, PathClkOrData clk_data, - const TransRiseFall *tr, + const RiseFall *rf, const EarlyLate *early_late, float &factor, bool &exists) const { - factors_[TimingDerateIndex(type)].factor(clk_data, tr, early_late, factor, exists); + factors_[TimingDerateIndex(type)].factor(clk_data, rf, early_late, factor, exists); } void diff --git a/sdc/DeratingFactors.hh b/sdc/DeratingFactors.hh index 16f27035..b3031232 100644 --- a/sdc/DeratingFactors.hh +++ b/sdc/DeratingFactors.hh @@ -30,11 +30,11 @@ class DeratingFactors public: DeratingFactors(); void setFactor(PathClkOrData clk_data, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, const EarlyLate *early_late, float factor); void factor(PathClkOrData clk_data, - const TransRiseFall *tr, + const RiseFall *rf, const EarlyLate *early_late, float &factor, bool &exists) const; @@ -60,12 +60,12 @@ public: DeratingFactorsGlobal(); void setFactor(TimingDerateType type, PathClkOrData clk_data, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, const EarlyLate *early_late, float factor); void factor(TimingDerateType type, PathClkOrData clk_data, - const TransRiseFall *tr, + const RiseFall *rf, const EarlyLate *early_late, float &factor, bool &exists) const; @@ -84,12 +84,12 @@ public: DeratingFactorsCell(); void setFactor(TimingDerateType type, PathClkOrData clk_data, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, const EarlyLate *early_late, float factor); void factor(TimingDerateType type, PathClkOrData clk_data, - const TransRiseFall *tr, + const RiseFall *rf, const EarlyLate *early_late, float &factor, bool &exists) const; diff --git a/sdc/ExceptionPath.cc b/sdc/ExceptionPath.cc index 87037442..41121fb3 100644 --- a/sdc/ExceptionPath.cc +++ b/sdc/ExceptionPath.cc @@ -162,9 +162,9 @@ checkFromThrusTo(ExceptionFrom *from, || (to && (!to->hasObjects() && to->transition() - == TransRiseFallBoth::riseFall() + == RiseFallBoth::riseFall() && (to->endTransition() - == TransRiseFallBoth::riseFall())))); + == RiseFallBoth::riseFall())))); if (thrus) { ExceptionThruSeq::Iterator thru_iter(thrus); while (thru_iter.hasNext()) { @@ -239,11 +239,11 @@ ExceptionPath::firstPt() } bool -ExceptionPath::matchesFirstPt(const TransRiseFall *to_tr, +ExceptionPath::matchesFirstPt(const RiseFall *to_rf, const MinMax *min_max) { ExceptionPt *first_pt = firstPt(); - return first_pt->transition()->matches(to_tr) + return first_pt->transition()->matches(to_rf) && matches(min_max, false); } @@ -932,9 +932,9 @@ GroupPath::overrides(ExceptionPath *exception) const const int ExceptionPt::as_string_max_objects_ = 20; -ExceptionPt::ExceptionPt(const TransRiseFallBoth *tr, +ExceptionPt::ExceptionPt(const RiseFallBoth *rf, bool own_pts) : - tr_(tr), + rf_(rf), own_pts_(own_pts), hash_(0) { @@ -951,9 +951,9 @@ ExceptionPt::hash() const ExceptionFromTo::ExceptionFromTo(PinSet *pins, ClockSet *clks, InstanceSet *insts, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, bool own_pts) : - ExceptionPt(tr, own_pts), + ExceptionPt(rf, own_pts), pins_(pins), clks_(clks), insts_(insts) @@ -1074,7 +1074,7 @@ ExceptionFromTo::equal(ExceptionFromTo *from_to) const return PinSet::equal(from_to->pins_, pins_) && ClockSet::equal(from_to->clks_, clks_) && InstanceSet::equal(from_to->insts_, insts_) - && from_to->transition() == tr_; + && from_to->transition() == rf_; } int @@ -1089,7 +1089,7 @@ ExceptionFromTo::nameCmp(ExceptionPt *pt2, if (clk_cmp == 0) { int inst_cmp = setNameCmp(insts_, pt2->instances(), network); if (inst_cmp == 0) - return tr_->index() - pt2->transition()->index(); + return rf_->index() - pt2->transition()->index(); else return inst_cmp; } @@ -1304,9 +1304,9 @@ ExceptionFromTo::objectCount() const ExceptionFrom::ExceptionFrom(PinSet *pins, ClockSet *clks, InstanceSet *insts, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, bool own_pts) : - ExceptionFromTo(pins, clks, insts, tr, own_pts) + ExceptionFromTo(pins, clks, insts, rf, own_pts) { } @@ -1314,7 +1314,7 @@ void ExceptionFrom::findHash() { ExceptionFromTo::findHash(); - hash_ += tr_->index() * 31 + 29; + hash_ += rf_->index() * 31 + 29; } ExceptionFrom * @@ -1329,13 +1329,13 @@ ExceptionFrom::clone() InstanceSet *insts = nullptr; if (insts_) insts = new InstanceSet(*insts_); - return new ExceptionFrom(pins, clks, insts, tr_, true); + return new ExceptionFrom(pins, clks, insts, rf_, true); } bool ExceptionFrom::intersectsPts(ExceptionFrom *from) const { - return from->transition() == tr_ + return from->transition() == rf_ && ((pins_ && PinSet::intersects(pins_, from->pins())) || (clks_ && ClockSet::intersects(clks_, from->clks())) || (insts_ && InstanceSet::intersects(insts_, from->instances()))); @@ -1344,9 +1344,9 @@ ExceptionFrom::intersectsPts(ExceptionFrom *from) const const char * ExceptionFrom::cmdKeyword() const { - if (tr_ == TransRiseFallBoth::rise()) + if (rf_ == RiseFallBoth::rise()) return "-rise_from"; - else if (tr_ == TransRiseFallBoth::fall()) + else if (rf_ == RiseFallBoth::fall()) return "-fall_from"; else return "-from"; @@ -1357,11 +1357,11 @@ ExceptionFrom::cmdKeyword() const ExceptionTo::ExceptionTo(PinSet *pins, ClockSet *clks, InstanceSet *insts, - const TransRiseFallBoth *tr, - const TransRiseFallBoth *end_tr, + const RiseFallBoth *rf, + const RiseFallBoth *end_rf, bool own_pts) : - ExceptionFromTo(pins, clks, insts, tr, own_pts), - end_tr_(end_tr) + ExceptionFromTo(pins, clks, insts, rf, own_pts), + end_rf_(end_rf) { } @@ -1377,7 +1377,7 @@ ExceptionTo::clone() InstanceSet *insts = nullptr; if (insts_) insts = new InstanceSet(*insts_); - return new ExceptionTo(pins, clks, insts, tr_, end_tr_, true); + return new ExceptionTo(pins, clks, insts, rf_, end_rf_, true); } const char * @@ -1387,8 +1387,8 @@ ExceptionTo::asString(const Network *network) const if (hasObjects()) str += ExceptionFromTo::asString(network); - if (end_tr_ != TransRiseFallBoth::riseFall()) - str += (end_tr_ == TransRiseFallBoth::rise()) ? " -rise" : " -fall"; + if (end_rf_ != RiseFallBoth::riseFall()) + str += (end_rf_ == RiseFallBoth::rise()) ? " -rise" : " -fall"; char *result = makeTmpString(str.size() + 1); strcpy(result, str.c_str()); @@ -1398,8 +1398,8 @@ ExceptionTo::asString(const Network *network) const bool ExceptionTo::intersectsPts(ExceptionTo *to) const { - return to->transition() == tr_ - && to->endTransition() == end_tr_ + return to->transition() == rf_ + && to->endTransition() == end_rf_ && ((pins_ && PinSet::intersects(pins_, to->pins())) || (clks_ && ClockSet::intersects(clks_, to->clks())) || (insts_ && InstanceSet::intersects(insts_, to->instances()))); @@ -1408,65 +1408,65 @@ ExceptionTo::intersectsPts(ExceptionTo *to) const bool ExceptionTo::matchesFilter(const Pin *pin, const ClockEdge *clk_edge, - const TransRiseFall *end_tr, + const RiseFall *end_rf, const Network *network) const { // "report -to reg" does match clock pins. - return matches(pin, clk_edge, end_tr, true, network); + return matches(pin, clk_edge, end_rf, true, network); } bool ExceptionTo::matches(const Pin *pin, const ClockEdge *clk_edge, - const TransRiseFall *end_tr, + const RiseFall *end_rf, const Network *network) const { // "exception -to reg" does not match reg clock pins. - return matches(pin, clk_edge, end_tr, false, network); + return matches(pin, clk_edge, end_rf, false, network); } bool ExceptionTo::matches(const Pin *pin, const ClockEdge *clk_edge, - const TransRiseFall *end_tr, + const RiseFall *end_rf, bool inst_matches_reg_clk_pin, const Network *network) const { return (pins_ && pins_->hasKey(const_cast(pin)) - && tr_->matches(end_tr) - && end_tr_->matches(end_tr)) + && rf_->matches(end_rf) + && end_rf_->matches(end_rf)) || (clk_edge && clks_ && clks_->hasKey(const_cast(clk_edge->clock())) - && tr_->matches(clk_edge->transition()) - && end_tr_->matches(end_tr)) + && rf_->matches(clk_edge->transition()) + && end_rf_->matches(end_rf)) || (insts_ && (inst_matches_reg_clk_pin || !network->isRegClkPin(pin)) && insts_->hasKey(network->instance(pin)) && network->direction(pin)->isAnyInput() - && tr_->matches(end_tr) - && end_tr_->matches(end_tr)) + && rf_->matches(end_rf) + && end_rf_->matches(end_rf)) || (pins_ == nullptr && clks_ == nullptr && insts_ == nullptr - && end_tr_->matches(end_tr)); + && end_rf_->matches(end_rf)); } bool ExceptionTo::matches(const Pin *pin, - const TransRiseFall *end_tr) const + const RiseFall *end_rf) const { return (pins_ && pins_->hasKey(const_cast(pin)) - && tr_->matches(end_tr) - && end_tr_->matches(end_tr)) + && rf_->matches(end_rf) + && end_rf_->matches(end_rf)) || (pins_ == nullptr && clks_ == nullptr && insts_ == nullptr - && end_tr_->matches(end_tr)); + && end_rf_->matches(end_rf)); } bool @@ -1479,9 +1479,9 @@ ExceptionTo::matches(const Clock *clk) const const char * ExceptionTo::cmdKeyword() const { - if (tr_ == TransRiseFallBoth::rise()) + if (rf_ == RiseFallBoth::rise()) return "-rise_to"; - else if (tr_ == TransRiseFallBoth::fall()) + else if (rf_ == RiseFallBoth::fall()) return "-fall_to"; else return "-to"; @@ -1494,7 +1494,7 @@ ExceptionTo::nameCmp(ExceptionPt *pt2, ExceptionTo *to2 = dynamic_cast(pt2); int cmp = ExceptionFromTo::nameCmp(pt2, network); if (cmp == 0) - return end_tr_->index() - to2->endTransition()->index(); + return end_rf_->index() - to2->endTransition()->index(); else return cmp; } @@ -1504,10 +1504,10 @@ ExceptionTo::nameCmp(ExceptionPt *pt2, ExceptionThru::ExceptionThru(PinSet *pins, NetSet *nets, InstanceSet *insts, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, bool own_pts, const Network *network) : - ExceptionPt(tr, own_pts), + ExceptionPt(rf, own_pts), pins_(pins), edges_(nullptr), nets_(nets), @@ -1739,9 +1739,9 @@ ExceptionThru::asString(const Network *network) const } if (obj_count == as_string_max_objects_) str += ", ..."; - if (tr_ == TransRiseFallBoth::rise()) + if (rf_ == RiseFallBoth::rise()) str += " rise"; - else if (tr_ == TransRiseFallBoth::fall()) + else if (rf_ == RiseFallBoth::fall()) str += " fall"; char *result = makeTmpString(str.size() + 1); @@ -1779,7 +1779,7 @@ ExceptionThru::clone(const Network *network) InstanceSet *insts = nullptr; if (insts_) insts = new InstanceSet(*insts_); - return new ExceptionThru(pins, nets, insts, tr_, true, network); + return new ExceptionThru(pins, nets, insts, rf_, true, network); } bool @@ -1915,7 +1915,7 @@ ExceptionThru::allPins(const Network *network, bool ExceptionThru::matches(const Pin *from_pin, const Pin *to_pin, - const TransRiseFall *to_tr, + const RiseFall *to_rf, const Network *network) { EdgePins edge_pins(const_cast(from_pin), const_cast(to_pin)); @@ -1923,7 +1923,7 @@ ExceptionThru::matches(const Pin *from_pin, || (edges_ && edges_->hasKey(&edge_pins)) || (nets_ && nets_->hasKey(network->net(to_pin))) || (insts_ && insts_->hasKey(network->instance(to_pin)))) - && tr_->matches(to_tr); + && rf_->matches(to_rf); } void @@ -1957,7 +1957,7 @@ ExceptionThru::findHash() } hash_ += hash * hash_inst; } - hash_ += tr_->index() * 13; + hash_ += rf_->index() * 13; } bool @@ -1967,7 +1967,7 @@ ExceptionThru::equal(ExceptionThru *thru) const return PinSet::equal(thru->pins_, pins_) && NetSet::equal(thru->nets_, nets_) && InstanceSet::equal(thru->insts_, insts_) - && tr_ == thru->tr_; + && rf_ == thru->rf_; } int @@ -1982,7 +1982,7 @@ ExceptionThru::nameCmp(ExceptionPt *pt2, if (net_cmp == 0) { int inst_cmp = setNameCmp(insts_, pt2->instances(), network); if (inst_cmp == 0) - return tr_->index() - pt2->transition()->index(); + return rf_->index() - pt2->transition()->index(); else return inst_cmp; } @@ -2071,7 +2071,7 @@ ExceptionThru::deleteObjects(ExceptionThru *pt) bool ExceptionThru::intersectsPts(ExceptionThru *thru) const { - return thru->transition() == tr_ + return thru->transition() == rf_ && ((pins_ && PinSet::intersects(pins_, thru->pins())) || (nets_ && NetSet::intersects(nets_, thru->nets())) || (insts_ && InstanceSet::intersects(insts_, thru->instances()))); @@ -2210,13 +2210,13 @@ ExpandedExceptionVisitor::visitExpansions() { ExceptionFrom *from = exception_->from(); if (from) { - const TransRiseFallBoth *tr = from->transition(); + const RiseFallBoth *rf = from->transition(); PinSet::Iterator pin_iter(from->pins()); while (pin_iter.hasNext()) { Pin *pin = pin_iter.next(); PinSet pins; pins.insert(pin); - ExceptionFrom expanded_from(&pins, nullptr, nullptr, tr, false); + ExceptionFrom expanded_from(&pins, nullptr, nullptr, rf, false); expandThrus(&expanded_from); } ClockSet::Iterator clk_iter(from->clks()); @@ -2224,7 +2224,7 @@ ExpandedExceptionVisitor::visitExpansions() Clock *clk = clk_iter.next(); ClockSet clks; clks.insert(clk); - ExceptionFrom expanded_from(nullptr, &clks, nullptr, tr, false); + ExceptionFrom expanded_from(nullptr, &clks, nullptr, rf, false); expandThrus(&expanded_from); } InstanceSet::Iterator inst_iter(from->instances()); @@ -2232,7 +2232,7 @@ ExpandedExceptionVisitor::visitExpansions() Instance *inst = inst_iter.next(); InstanceSet insts; insts.insert(inst); - ExceptionFrom expanded_from(nullptr, nullptr, &insts, tr, false); + ExceptionFrom expanded_from(nullptr, nullptr, &insts, rf, false); expandThrus(&expanded_from); } } @@ -2261,13 +2261,13 @@ ExpandedExceptionVisitor::expandThru(ExceptionFrom *expanded_from, { if (thru_iter.hasNext()) { ExceptionThru *thru = thru_iter.next(); - const TransRiseFallBoth *tr = thru->transition(); + const RiseFallBoth *rf = thru->transition(); PinSet::Iterator pin_iter(thru->pins()); while (pin_iter.hasNext()) { Pin *pin = pin_iter.next(); PinSet pins; pins.insert(pin); - ExceptionThru expanded_thru(&pins, nullptr, nullptr, tr, false, network_); + ExceptionThru expanded_thru(&pins, nullptr, nullptr, rf, false, network_); expanded_thrus->push_back(&expanded_thru); expandThru(expanded_from, thru_iter, expanded_thrus); expanded_thrus->pop_back(); @@ -2277,7 +2277,7 @@ ExpandedExceptionVisitor::expandThru(ExceptionFrom *expanded_from, Net *net = net_iter.next(); NetSet nets; nets.insert(net); - ExceptionThru expanded_thru(nullptr, &nets, nullptr, tr, false, network_); + ExceptionThru expanded_thru(nullptr, &nets, nullptr, rf, false, network_); expanded_thrus->push_back(&expanded_thru); expandThru(expanded_from, thru_iter, expanded_thrus); expanded_thrus->pop_back(); @@ -2287,7 +2287,7 @@ ExpandedExceptionVisitor::expandThru(ExceptionFrom *expanded_from, Instance *inst = inst_iter.next(); InstanceSet insts; insts.insert(inst); - ExceptionThru expanded_thru(nullptr, nullptr, &insts, tr, false, network_); + ExceptionThru expanded_thru(nullptr, nullptr, &insts, rf, false, network_); expanded_thrus->push_back(&expanded_thru); expandThru(expanded_from, thru_iter, expanded_thrus); expanded_thrus->pop_back(); @@ -2304,14 +2304,14 @@ ExpandedExceptionVisitor::expandTo(ExceptionFrom *expanded_from, { ExceptionTo *to = exception_->to(); if (to) { - const TransRiseFallBoth *tr = to->transition(); - const TransRiseFallBoth *end_tr = to->endTransition(); + const RiseFallBoth *rf = to->transition(); + const RiseFallBoth *end_rf = to->endTransition(); PinSet::Iterator pin_iter(to->pins()); while (pin_iter.hasNext()) { Pin *pin = pin_iter.next(); PinSet pins; pins.insert(pin); - ExceptionTo expanded_to(&pins, nullptr, nullptr, tr, end_tr, false); + ExceptionTo expanded_to(&pins, nullptr, nullptr, rf, end_rf, false); visit(expanded_from, expanded_thrus, &expanded_to); } ClockSet::Iterator clk_iter(to->clks()); @@ -2319,7 +2319,7 @@ ExpandedExceptionVisitor::expandTo(ExceptionFrom *expanded_from, Clock *clk = clk_iter.next(); ClockSet clks; clks.insert(clk); - ExceptionTo expanded_to(nullptr, &clks, nullptr, tr, end_tr, false); + ExceptionTo expanded_to(nullptr, &clks, nullptr, rf, end_rf, false); visit(expanded_from, expanded_thrus, &expanded_to); } InstanceSet::Iterator inst_iter(to->instances()); @@ -2327,7 +2327,7 @@ ExpandedExceptionVisitor::expandTo(ExceptionFrom *expanded_from, Instance *inst = inst_iter.next(); InstanceSet insts; insts.insert(inst); - ExceptionTo expanded_to(nullptr, nullptr, &insts, tr, end_tr, false); + ExceptionTo expanded_to(nullptr, nullptr, &insts, rf, end_rf, false); visit(expanded_from, expanded_thrus, &expanded_to); } } @@ -2356,14 +2356,14 @@ ExceptionState::setNextState(ExceptionState *next_state) bool ExceptionState::matchesNextThru(const Pin *from_pin, const Pin *to_pin, - const TransRiseFall *to_tr, + const RiseFall *to_rf, const MinMax *min_max, const Network *network) const { // Don't advance the state if the exception is complete (no next_thru_). return next_thru_ && exception_->matches(min_max, false) - && next_thru_->matches(from_pin, to_pin, to_tr, network); + && next_thru_->matches(from_pin, to_pin, to_rf, network); } bool diff --git a/sdc/ExceptionPath.hh b/sdc/ExceptionPath.hh index 5a5961bd..4aa641eb 100644 --- a/sdc/ExceptionPath.hh +++ b/sdc/ExceptionPath.hh @@ -25,8 +25,8 @@ namespace sta { -class TransRiseFall; -class TransRiseFallBoth; +class RiseFall; +class RiseFallBoth; class MinMaxAll; class Network; class Pin; @@ -67,7 +67,8 @@ public: const MinMaxAll *minMax() const { return min_max_; } virtual bool matches(const MinMax *min_max, bool exact) const; - bool matchesFirstPt(const TransRiseFall *to_tr, const MinMax *min_max); + bool matchesFirstPt(const RiseFall *to_rf, + const MinMax *min_max); ExceptionState *firstState(); virtual bool resetMatch(ExceptionFrom *from, ExceptionThruSeq *thrus, @@ -323,13 +324,13 @@ private: class ExceptionPt { public: - ExceptionPt(const TransRiseFallBoth *tr, + ExceptionPt(const RiseFallBoth *rf, bool own_pts); virtual ~ExceptionPt() {}; virtual bool isFrom() const { return false; } virtual bool isThru() const { return false; } virtual bool isTo() const { return false; } - const TransRiseFallBoth *transition() const { return tr_; } + const RiseFallBoth *transition() const { return rf_; } virtual PinSet *pins() = 0; virtual ClockSet *clks() = 0; virtual InstanceSet *instances() = 0; @@ -355,7 +356,7 @@ public: Network *network) = 0; protected: - const TransRiseFallBoth *tr_; + const RiseFallBoth *rf_; // True when the pin/net/inst/edge sets are owned by the exception point. bool own_pts_; // Hash is cached because there may be many objects to speed up @@ -378,7 +379,7 @@ class ExceptionFromTo : public ExceptionPt public: ExceptionFromTo(PinSet *pins, ClockSet *clks, InstanceSet *insts, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, bool own_pts); ~ExceptionFromTo(); virtual PinSet *pins() { return pins_; } @@ -431,7 +432,7 @@ public: ExceptionFrom(PinSet *pins, ClockSet *clks, InstanceSet *insts, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, bool own_pts); ExceptionFrom *clone(); virtual bool isFrom() const { return true; } @@ -453,39 +454,39 @@ public: ClockSet *clks, InstanceSet *insts, // -to|-rise_to|-fall_to - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, // -rise|-fall endpoint transition. - const TransRiseFallBoth *end_tr, + const RiseFallBoth *end_rf, bool own_pts); ExceptionTo *clone(); virtual bool isTo() const { return true; } const char *asString(const Network *network) const; - const TransRiseFallBoth *endTransition() { return end_tr_; } + const RiseFallBoth *endTransition() { return end_rf_; } bool intersectsPts(ExceptionTo *to) const; virtual int typePriority() const { return 1; } bool matches(const Pin *pin, const ClockEdge *clk_edge, - const TransRiseFall *end_tr, + const RiseFall *end_rf, const Network *network) const; bool matches(const Pin *pin, - const TransRiseFall *end_tr) const; + const RiseFall *end_rf) const; bool matches(const Clock *clk) const; bool matchesFilter(const Pin *pin, const ClockEdge *clk_edge, - const TransRiseFall *end_tr, + const RiseFall *end_rf, const Network *network) const; virtual int nameCmp(ExceptionPt *pt, const Network *network) const; protected: bool matches(const Pin *pin, const ClockEdge *clk_edge, - const TransRiseFall *end_tr, + const RiseFall *end_rf, bool inst_matches_reg_clk_pin, const Network *network) const; virtual const char *cmdKeyword() const; // -rise|-fall endpoint transition. - const TransRiseFallBoth *end_tr_; + const RiseFallBoth *end_rf_; private: DISALLOW_COPY_AND_ASSIGN(ExceptionTo); @@ -497,7 +498,7 @@ public: ExceptionThru(PinSet *pins, NetSet *nets, InstanceSet *insts, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, bool own_pts, const Network *network); ~ExceptionThru(); @@ -515,7 +516,7 @@ public: PinSet *pins); bool matches(const Pin *from_pin, const Pin *to_pin, - const TransRiseFall *to_tr, + const RiseFall *to_rf, const Network *network); bool equal(ExceptionThru *thru) const; virtual int nameCmp(ExceptionPt *pt, @@ -637,7 +638,7 @@ public: ExceptionPath *exception() { return exception_; } bool matchesNextThru(const Pin *from_pin, const Pin *to_pin, - const TransRiseFall *to_tr, + const RiseFall *to_rf, const MinMax *min_max, const Network *network) const; bool isComplete() const; diff --git a/sdc/InputDrive.cc b/sdc/InputDrive.cc index e5162918..80dc85a1 100644 --- a/sdc/InputDrive.cc +++ b/sdc/InputDrive.cc @@ -21,7 +21,7 @@ namespace sta { InputDrive::InputDrive() { - for (auto tr_index : TransRiseFall::rangeIndex()) { + for (auto tr_index : RiseFall::rangeIndex()) { for (auto mm_index : MinMax::rangeIndex()) drive_cells_[tr_index][mm_index] = nullptr; } @@ -29,7 +29,7 @@ InputDrive::InputDrive() InputDrive::~InputDrive() { - for (auto tr_index : TransRiseFall::rangeIndex()) { + for (auto tr_index : RiseFall::rangeIndex()) { for (auto mm_index : MinMax::rangeIndex()) { InputDriveCell *drive_cell = drive_cells_[tr_index][mm_index]; delete drive_cell; @@ -38,43 +38,43 @@ InputDrive::~InputDrive() } void -InputDrive::setSlew(const TransRiseFallBoth *tr, +InputDrive::setSlew(const RiseFallBoth *rf, const MinMaxAll *min_max, float slew) { - slews_.setValue(tr, min_max, slew); + slews_.setValue(rf, min_max, slew); } void -InputDrive::setDriveResistance(const TransRiseFallBoth *tr, +InputDrive::setDriveResistance(const RiseFallBoth *rf, const MinMaxAll *min_max, float res) { - drive_resistances_.setValue(tr, min_max, res); + drive_resistances_.setValue(rf, min_max, res); } void -InputDrive::driveResistance(const TransRiseFall *tr, +InputDrive::driveResistance(const RiseFall *rf, const MinMax *min_max, float &res, bool &exists) { - drive_resistances_.value(tr, min_max, res, exists); + drive_resistances_.value(rf, min_max, res, exists); } bool -InputDrive::hasDriveResistance(const TransRiseFall *tr, const MinMax *min_max) +InputDrive::hasDriveResistance(const RiseFall *rf, const MinMax *min_max) { - return drive_resistances_.hasValue(tr, min_max); + return drive_resistances_.hasValue(rf, min_max); } bool -InputDrive::driveResistanceMinMaxEqual(const TransRiseFall *tr) +InputDrive::driveResistanceMinMaxEqual(const RiseFall *rf) { float min_res, max_res; bool min_exists, max_exists; - drive_resistances_.value(tr, MinMax::min(), min_res, min_exists); - drive_resistances_.value(tr, MinMax::max(), max_res, max_exists); + drive_resistances_.value(rf, MinMax::min(), min_res, min_exists); + drive_resistances_.value(rf, MinMax::max(), max_res, max_exists); return min_exists && max_exists && min_res == max_res; } @@ -84,12 +84,12 @@ InputDrive::setDriveCell(LibertyLibrary *library, LibertyPort *from_port, float *from_slews, LibertyPort *to_port, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, const MinMaxAll *min_max) { - for (auto tr_index : tr->rangeIndex()) { + for (auto rf_index : rf->rangeIndex()) { for (auto mm_index : min_max->rangeIndex()) { - InputDriveCell *drive = drive_cells_[tr_index][mm_index]; + InputDriveCell *drive = drive_cells_[rf_index][mm_index]; if (drive) { drive->setLibrary(library); drive->setCell(cell); @@ -100,21 +100,21 @@ InputDrive::setDriveCell(LibertyLibrary *library, else { drive = new InputDriveCell(library, cell, from_port, from_slews, to_port); - drive_cells_[tr_index][mm_index] = drive; + drive_cells_[rf_index][mm_index] = drive; } } } } void -InputDrive::driveCell(const TransRiseFall *tr, +InputDrive::driveCell(const RiseFall *rf, const MinMax *min_max, LibertyCell *&cell, LibertyPort *&from_port, float *&from_slews, LibertyPort *&to_port) { - InputDriveCell *drive = drive_cells_[tr->index()][min_max->index()]; + InputDriveCell *drive = drive_cells_[rf->index()][min_max->index()]; if (drive) { cell = drive->cell(); from_port = drive->fromPort(); @@ -126,24 +126,24 @@ InputDrive::driveCell(const TransRiseFall *tr, } InputDriveCell * -InputDrive::driveCell(const TransRiseFall *tr, +InputDrive::driveCell(const RiseFall *rf, const MinMax *min_max) { - return drive_cells_[tr->index()][min_max->index()]; + return drive_cells_[rf->index()][min_max->index()]; } bool -InputDrive::hasDriveCell(const TransRiseFall *tr, +InputDrive::hasDriveCell(const RiseFall *rf, const MinMax *min_max) { - return drive_cells_[tr->index()][min_max->index()] != nullptr; + return drive_cells_[rf->index()][min_max->index()] != nullptr; } bool InputDrive::driveCellsEqual() { - int rise_index = TransRiseFall::riseIndex(); - int fall_index = TransRiseFall::fallIndex(); + int rise_index = RiseFall::riseIndex(); + int fall_index = RiseFall::fallIndex(); int min_index = MinMax::minIndex(); int max_index = MinMax::maxIndex(); InputDriveCell *drive1 = drive_cells_[rise_index][min_index]; @@ -156,12 +156,12 @@ InputDrive::driveCellsEqual() } void -InputDrive::slew(const TransRiseFall *tr, +InputDrive::slew(const RiseFall *rf, const MinMax *min_max, float &slew, bool &exists) { - slews_.value(tr, min_max, slew, exists); + slews_.value(rf, min_max, slew, exists); } //////////////////////////////////////////////////////////////// @@ -206,15 +206,15 @@ InputDriveCell::setToPort(LibertyPort *to_port) void InputDriveCell::setFromSlews(float *from_slews) { - for (auto tr_index : TransRiseFall::rangeIndex()) + for (auto tr_index : RiseFall::rangeIndex()) from_slews_[tr_index] = from_slews[tr_index]; } bool InputDriveCell::equal(InputDriveCell *drive) const { - int rise_index = TransRiseFall::riseIndex(); - int fall_index = TransRiseFall::fallIndex(); + int rise_index = RiseFall::riseIndex(); + int fall_index = RiseFall::fallIndex(); return cell_ == drive->cell_ && from_port_ == drive->from_port_ && from_slews_[rise_index] == drive->from_slews_[rise_index] diff --git a/sdc/InputDrive.hh b/sdc/InputDrive.hh index 8861fb3b..3c8b4062 100644 --- a/sdc/InputDrive.hh +++ b/sdc/InputDrive.hh @@ -36,39 +36,39 @@ class InputDrive public: explicit InputDrive(); ~InputDrive(); - void setSlew(const TransRiseFallBoth *tr, + void setSlew(const RiseFallBoth *rf, const MinMaxAll *min_max, float slew); - void setDriveResistance(const TransRiseFallBoth *tr, + void setDriveResistance(const RiseFallBoth *rf, const MinMaxAll *min_max, float res); - void driveResistance(const TransRiseFall *tr, + void driveResistance(const RiseFall *rf, const MinMax *min_max, float &res, bool &exists); - bool hasDriveResistance(const TransRiseFall *tr, + bool hasDriveResistance(const RiseFall *rf, const MinMax *min_max); - bool driveResistanceMinMaxEqual(const TransRiseFall *tr); + bool driveResistanceMinMaxEqual(const RiseFall *rf); void setDriveCell(LibertyLibrary *library, LibertyCell *cell, LibertyPort *from_port, float *from_slews, LibertyPort *to_port, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, const MinMaxAll *min_max); - void driveCell(const TransRiseFall *tr, + void driveCell(const RiseFall *rf, const MinMax *min_max, LibertyCell *&cell, LibertyPort *&from_port, float *&from_slews, LibertyPort *&to_port); - InputDriveCell *driveCell(const TransRiseFall *tr, + InputDriveCell *driveCell(const RiseFall *rf, const MinMax *min_max); - bool hasDriveCell(const TransRiseFall *tr, + bool hasDriveCell(const RiseFall *rf, const MinMax *min_max); // True if rise/fall/min/max drive cells are equal. bool driveCellsEqual(); - void slew(const TransRiseFall *tr, + void slew(const RiseFall *rf, const MinMax *min_max, float &slew, bool &exists); @@ -80,7 +80,7 @@ private: RiseFallMinMax slews_; RiseFallMinMax drive_resistances_; // Separate rise/fall/min/max drive cells. - InputDriveCell *drive_cells_[TransRiseFall::index_count][MinMax::index_count]; + InputDriveCell *drive_cells_[RiseFall::index_count][MinMax::index_count]; }; class InputDriveCell @@ -109,7 +109,7 @@ private: LibertyLibrary *library_; LibertyCell *cell_; LibertyPort *from_port_; - float from_slews_[TransRiseFall::index_count]; + float from_slews_[RiseFall::index_count]; LibertyPort *to_port_; }; diff --git a/sdc/PortDelay.cc b/sdc/PortDelay.cc index f3393c1f..c91d5d32 100644 --- a/sdc/PortDelay.cc +++ b/sdc/PortDelay.cc @@ -66,14 +66,14 @@ PortDelay::setNetworkLatencyIncluded(bool included) network_latency_included_ = included; } -TransRiseFall * +RiseFall * PortDelay::refTransition() const { // Reference pin transition is the clock transition. if (clk_edge_) return clk_edge_->transition(); else - return TransRiseFall::rise(); + return RiseFall::rise(); } InputDelay::InputDelay(Pin *pin, diff --git a/sdc/PortDelay.hh b/sdc/PortDelay.hh index 18ae11a7..4f607290 100644 --- a/sdc/PortDelay.hh +++ b/sdc/PortDelay.hh @@ -41,7 +41,7 @@ public: bool networkLatencyIncluded() const; void setNetworkLatencyIncluded(bool included); Pin *refPin() const { return ref_pin_; } - TransRiseFall *refTransition() const; + RiseFall *refTransition() const; protected: PortDelay(Pin *pin, diff --git a/sdc/PortExtCap.cc b/sdc/PortExtCap.cc index a9d8b93b..fe73a156 100644 --- a/sdc/PortExtCap.cc +++ b/sdc/PortExtCap.cc @@ -25,39 +25,39 @@ PortExtCap::PortExtCap(Port *port) : } void -PortExtCap::pinCap(const TransRiseFall *tr, +PortExtCap::pinCap(const RiseFall *rf, const MinMax *min_max, // Return values. float &cap, bool &exists) { - pin_cap_.value(tr, min_max, cap, exists); + pin_cap_.value(rf, min_max, cap, exists); } void PortExtCap::setPinCap(float cap, - const TransRiseFall *tr, + const RiseFall *rf, const MinMax *min_max) { - pin_cap_.setValue(tr, min_max, cap); + pin_cap_.setValue(rf, min_max, cap); } void -PortExtCap::wireCap(const TransRiseFall *tr, +PortExtCap::wireCap(const RiseFall *rf, const MinMax *min_max, // Return values. float &cap, bool &exists) { - wire_cap_.value(tr, min_max, cap, exists); + wire_cap_.value(rf, min_max, cap, exists); } void PortExtCap::setWireCap(float cap, - const TransRiseFall *tr, + const RiseFall *rf, const MinMax *min_max) { - wire_cap_.setValue(tr, min_max, cap); + wire_cap_.setValue(rf, min_max, cap); } void diff --git a/sdc/PortExtCap.hh b/sdc/PortExtCap.hh index 06385c04..6da6546d 100644 --- a/sdc/PortExtCap.hh +++ b/sdc/PortExtCap.hh @@ -34,21 +34,21 @@ class PortExtCap public: explicit PortExtCap(Port *port); Port *port() { return port_; } - void pinCap(const TransRiseFall *tr, + void pinCap(const RiseFall *rf, const MinMax *min_max, // Return values. float &cap, bool &exists); RiseFallMinMax *pinCap() { return &pin_cap_; } void setPinCap(float cap, - const TransRiseFall *tr, + const RiseFall *rf, const MinMax *min_max); - void wireCap(const TransRiseFall *tr, + void wireCap(const RiseFall *rf, const MinMax *min_max, // Return values. float &cap, bool &exists); RiseFallMinMax *wireCap() { return &wire_cap_; } void setWireCap(float cap, - const TransRiseFall *tr, + const RiseFall *rf, const MinMax *min_max); void setFanout(int fanout, const MinMax *min_max); diff --git a/sdc/RiseFallMinMax.cc b/sdc/RiseFallMinMax.cc index 949654ee..ba785888 100644 --- a/sdc/RiseFallMinMax.cc +++ b/sdc/RiseFallMinMax.cc @@ -27,7 +27,7 @@ RiseFallMinMax::RiseFallMinMax() void RiseFallMinMax::clear() { - for (int tr_index=0; tr_indexvalues_[tr_index][mm_index]; exists_[tr_index][mm_index] = rfmm->exists_[tr_index][mm_index]; @@ -57,105 +57,105 @@ RiseFallMinMax::RiseFallMinMax(const RiseFallMinMax *rfmm) void RiseFallMinMax::setValue(float value) { - setValue(TransRiseFallBoth::riseFall(), MinMaxAll::all(), value); + setValue(RiseFallBoth::riseFall(), MinMaxAll::all(), value); } void -RiseFallMinMax::setValue(const TransRiseFallBoth *tr, +RiseFallMinMax::setValue(const RiseFallBoth *rf, const MinMaxAll *min_max, float value) { - for (auto tr_index : tr->rangeIndex()) { + for (auto rf_index : rf->rangeIndex()) { for (auto mm_index : min_max->rangeIndex()) { - values_[tr_index][mm_index] = value; - exists_[tr_index][mm_index] = true; + values_[rf_index][mm_index] = value; + exists_[rf_index][mm_index] = true; } } } void -RiseFallMinMax::removeValue(const TransRiseFallBoth *tr, +RiseFallMinMax::removeValue(const RiseFallBoth *rf, const MinMax *min_max) { int mm_index = min_max->index(); - for (auto tr_index : tr->rangeIndex()) - exists_[tr_index][mm_index] = false; + for (auto rf_index : rf->rangeIndex()) + exists_[rf_index][mm_index] = false; } void -RiseFallMinMax::removeValue(const TransRiseFallBoth *tr, +RiseFallMinMax::removeValue(const RiseFallBoth *rf, const MinMaxAll *min_max) { for (auto mm : min_max->range()) - removeValue(tr, mm); + removeValue(rf, mm); } void -RiseFallMinMax::mergeValue(const TransRiseFallBoth *tr, +RiseFallMinMax::mergeValue(const RiseFallBoth *rf, const MinMaxAll *min_max, float value) { - for (auto tr_index : tr->rangeIndex()) { + for (auto rf_index : rf->rangeIndex()) { for (auto mm : min_max->range()) { int mm_index = mm->index(); - if (!exists_[tr_index][mm_index] - || mm->compare(value, values_[tr_index][mm_index])) { - values_[tr_index][mm_index] = value; - exists_[tr_index][mm_index] = true; + if (!exists_[rf_index][mm_index] + || mm->compare(value, values_[rf_index][mm_index])) { + values_[rf_index][mm_index] = value; + exists_[rf_index][mm_index] = true; } } } } void -RiseFallMinMax::setValue(const TransRiseFallBoth *tr, +RiseFallMinMax::setValue(const RiseFallBoth *rf, const MinMax *min_max, float value) { int mm_index = min_max->index(); - for (auto tr_index : tr->rangeIndex()) { - values_[tr_index][mm_index] = value; - exists_[tr_index][mm_index] = true; + for (auto rf_index : rf->rangeIndex()) { + values_[rf_index][mm_index] = value; + exists_[rf_index][mm_index] = true; } } void -RiseFallMinMax::setValue(const TransRiseFall *tr, +RiseFallMinMax::setValue(const RiseFall *rf, const MinMax *min_max, float value) { - int tr_index = tr->index(); + int rf_index = rf->index(); int mm_index = min_max->index(); - values_[tr_index][mm_index] = value; - exists_[tr_index][mm_index] = true; + values_[rf_index][mm_index] = value; + exists_[rf_index][mm_index] = true; } void RiseFallMinMax::setValues(RiseFallMinMax *values) { - for (int tr_index=0;tr_indexvalues_[tr_index][mm_index]; - exists_[tr_index][mm_index] = values->exists_[tr_index][mm_index]; + values_[rf_index][mm_index] = values->values_[rf_index][mm_index]; + exists_[rf_index][mm_index] = values->exists_[rf_index][mm_index]; } } } void -RiseFallMinMax::value(const TransRiseFall *tr, +RiseFallMinMax::value(const RiseFall *rf, const MinMax *min_max, float &value, bool &exists) const { - exists = exists_[tr->index()][min_max->index()]; + exists = exists_[rf->index()][min_max->index()]; if (exists) - value = values_[tr->index()][min_max->index()]; + value = values_[rf->index()][min_max->index()]; } float -RiseFallMinMax::value(const TransRiseFall *tr, +RiseFallMinMax::value(const RiseFall *rf, const MinMax *min_max) const { - return values_[tr->index()][min_max->index()]; + return values_[rf->index()][min_max->index()]; } bool @@ -167,9 +167,9 @@ RiseFallMinMax::hasValue() const bool RiseFallMinMax::empty() const { - for (int tr_index=0;tr_indexindex()][min_max->index()]; + return exists_[rf->index()][min_max->index()]; } void @@ -187,17 +187,17 @@ RiseFallMinMax::mergeWith(RiseFallMinMax *rfmm) { for (auto min_max : MinMax::range()) { int mm_index = min_max->index(); - for (auto tr_index : TransRiseFall::rangeIndex()) { - bool exists1 = exists_[tr_index][mm_index]; - bool exists2 = rfmm->exists_[tr_index][mm_index]; + for (auto rf_index : RiseFall::rangeIndex()) { + bool exists1 = exists_[rf_index][mm_index]; + bool exists2 = rfmm->exists_[rf_index][mm_index]; if (exists1 && exists2) { - float rfmm_value = rfmm->values_[tr_index][mm_index]; - if (min_max->compare(rfmm_value, values_[tr_index][mm_index])) - values_[tr_index][mm_index] = rfmm_value; + float rfmm_value = rfmm->values_[rf_index][mm_index]; + if (min_max->compare(rfmm_value, values_[rf_index][mm_index])) + values_[rf_index][mm_index] = rfmm_value; } else if (!exists1 && exists2) { - values_[tr_index][mm_index] = rfmm->values_[tr_index][mm_index]; - exists_[tr_index][mm_index] = true; + values_[rf_index][mm_index] = rfmm->values_[rf_index][mm_index]; + exists_[rf_index][mm_index] = true; } } } @@ -206,14 +206,14 @@ RiseFallMinMax::mergeWith(RiseFallMinMax *rfmm) bool RiseFallMinMax::equal(const RiseFallMinMax *values) const { - for (int tr_index=0;tr_indexexists_[tr_index][mm_index]; + bool exists1 = exists_[rf_index][mm_index]; + bool exists2 = values->exists_[rf_index][mm_index]; if (exists1 != exists2) return false; if (exists1 && exists2 - && values_[tr_index][mm_index] != values->values_[tr_index][mm_index]) + && values_[rf_index][mm_index] != values->values_[rf_index][mm_index]) return false; } } @@ -232,10 +232,10 @@ RiseFallMinMax::isOneValue(float &value) const { if (exists_[0][0]) { value = values_[0][0]; - for (int tr_index=0;tr_indexindex(); if (exists_[0][mm_index]) { value = values_[0][mm_index]; - for (int tr_index=0;tr_indexrangeIndex()) { - values_[tr_index] = value; - exists_[tr_index] = true; + for (auto rf_index : rf->rangeIndex()) { + values_[rf_index] = value; + exists_[rf_index] = true; } } void -RiseFallValues::setValue(const TransRiseFall *tr, +RiseFallValues::setValue(const RiseFall *rf, float value) { - int tr_index = tr->index(); - values_[tr_index] = value; - exists_[tr_index] = true; + int rf_index = rf->index(); + values_[rf_index] = value; + exists_[rf_index] = true; } void RiseFallValues::setValues(RiseFallValues *values) { - for (auto tr_index : TransRiseFall::rangeIndex()) { - values_[tr_index] = values->values_[tr_index]; - exists_[tr_index] = values->exists_[tr_index]; + for (auto rf_index : RiseFall::rangeIndex()) { + values_[rf_index] = values->values_[rf_index]; + exists_[rf_index] = values->exists_[rf_index]; } } void -RiseFallValues::value(const TransRiseFall *tr, +RiseFallValues::value(const RiseFall *rf, float &value, bool &exists) const { - int tr_index = tr->index(); - exists = exists_[tr_index]; + int rf_index = rf->index(); + exists = exists_[rf_index]; if (exists) - value = values_[tr_index]; + value = values_[rf_index]; } float -RiseFallValues::value(const TransRiseFall *tr) const +RiseFallValues::value(const RiseFall *rf) const { - return values_[tr->index()]; + return values_[rf->index()]; } bool -RiseFallValues::hasValue(const TransRiseFall *tr) const +RiseFallValues::hasValue(const RiseFall *rf) const { - return exists_[tr->index()]; + return exists_[rf->index()]; } } // namespace diff --git a/sdc/RiseFallValues.hh b/sdc/RiseFallValues.hh index 7ecc5397..b81ee70c 100644 --- a/sdc/RiseFallValues.hh +++ b/sdc/RiseFallValues.hh @@ -28,12 +28,12 @@ class RiseFallValues public: RiseFallValues(); explicit RiseFallValues(float init_value); - float value(const TransRiseFall *tr) const; - void value(const TransRiseFall *tr, + float value(const RiseFall *rf) const; + void value(const RiseFall *rf, float &value, bool &exists) const; - bool hasValue(const TransRiseFall *tr) const; - void setValue(const TransRiseFallBoth *tr, float value); - void setValue(const TransRiseFall *tr, float value); + bool hasValue(const RiseFall *rf) const; + void setValue(const RiseFallBoth *rf, float value); + void setValue(const RiseFall *rf, float value); void setValue(float value); void setValues(RiseFallValues *values); void clear(); @@ -41,8 +41,8 @@ public: private: DISALLOW_COPY_AND_ASSIGN(RiseFallValues); - float values_[TransRiseFall::index_count]; - bool exists_[TransRiseFall::index_count]; + float values_[RiseFall::index_count]; + bool exists_[RiseFall::index_count]; }; } // namespace diff --git a/sdc/Sdc.cc b/sdc/Sdc.cc index 79ad9755..2d7b931d 100644 --- a/sdc/Sdc.cc +++ b/sdc/Sdc.cc @@ -549,19 +549,19 @@ Sdc::setPvt(Instance *inst, const void Sdc::setTimingDerate(TimingDerateType type, PathClkOrData clk_data, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, const EarlyLate *early_late, float derate) { if (derating_factors_ == nullptr) derating_factors_ = new DeratingFactorsGlobal; - derating_factors_->setFactor(type, clk_data, tr, early_late, derate); + derating_factors_->setFactor(type, clk_data, rf, early_late, derate); } void Sdc::setTimingDerate(const Net *net, PathClkOrData clk_data, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, const EarlyLate *early_late, float derate) { @@ -572,14 +572,14 @@ Sdc::setTimingDerate(const Net *net, factors = new DeratingFactorsNet; (*net_derating_factors_)[net] = factors; } - factors->setFactor(clk_data, tr, early_late, derate); + factors->setFactor(clk_data, rf, early_late, derate); } void Sdc::setTimingDerate(const Instance *inst, TimingDerateType type, PathClkOrData clk_data, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, const EarlyLate *early_late, float derate) { @@ -590,14 +590,14 @@ Sdc::setTimingDerate(const Instance *inst, factors = new DeratingFactorsCell; (*inst_derating_factors_)[inst] = factors; } - factors->setFactor(type, clk_data, tr, early_late, derate); + factors->setFactor(type, clk_data, rf, early_late, derate); } void Sdc::setTimingDerate(const LibertyCell *cell, TimingDerateType type, PathClkOrData clk_data, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, const EarlyLate *early_late, float derate) { @@ -608,14 +608,14 @@ Sdc::setTimingDerate(const LibertyCell *cell, factors = new DeratingFactorsCell; (*cell_derating_factors_)[cell] = factors; } - factors->setFactor(type, clk_data, tr, early_late, derate); + factors->setFactor(type, clk_data, rf, early_late, derate); } float Sdc::timingDerateInstance(const Pin *pin, TimingDerateType type, PathClkOrData clk_data, - const TransRiseFall *tr, + const RiseFall *rf, const EarlyLate *early_late) const { if (inst_derating_factors_) { @@ -624,7 +624,7 @@ Sdc::timingDerateInstance(const Pin *pin, if (factors) { float factor; bool exists; - factors->factor(type, clk_data, tr, early_late, factor, exists); + factors->factor(type, clk_data, rf, early_late, factor, exists); if (exists) return factor; } @@ -638,7 +638,7 @@ Sdc::timingDerateInstance(const Pin *pin, float factor; bool exists; if (factors) { - factors->factor(type, clk_data, tr, early_late, factor, exists); + factors->factor(type, clk_data, rf, early_late, factor, exists); if (exists) return factor; } @@ -647,7 +647,7 @@ Sdc::timingDerateInstance(const Pin *pin, if (derating_factors_) { float factor; bool exists; - derating_factors_->factor(type, clk_data, tr, early_late, factor, exists); + derating_factors_->factor(type, clk_data, rf, early_late, factor, exists); if (exists) return factor; } @@ -657,7 +657,7 @@ Sdc::timingDerateInstance(const Pin *pin, float Sdc::timingDerateNet(const Pin *pin, PathClkOrData clk_data, - const TransRiseFall *tr, + const RiseFall *rf, const EarlyLate *early_late) const { if (net_derating_factors_) { @@ -666,7 +666,7 @@ Sdc::timingDerateNet(const Pin *pin, if (factors) { float factor; bool exists; - factors->factor(clk_data, tr, early_late, factor, exists); + factors->factor(clk_data, rf, early_late, factor, exists); if (exists) return factor; } @@ -674,7 +674,7 @@ Sdc::timingDerateNet(const Pin *pin, if (derating_factors_) { float factor; bool exists; - derating_factors_->factor(TimingDerateType::net_delay, clk_data, tr, + derating_factors_->factor(TimingDerateType::net_delay, clk_data, rf, early_late, factor, exists); if (exists) return factor; @@ -734,29 +734,29 @@ Sdc::setDriveCell(LibertyLibrary *library, LibertyPort *from_port, float *from_slews, LibertyPort *to_port, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, const MinMaxAll *min_max) { ensureInputDrive(port)->setDriveCell(library, cell, from_port, from_slews, - to_port, tr, min_max); + to_port, rf, min_max); } void Sdc::setInputSlew(Port *port, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, const MinMaxAll *min_max, float slew) { - ensureInputDrive(port)->setSlew(tr, min_max, slew); + ensureInputDrive(port)->setSlew(rf, min_max, slew); } void Sdc::setDriveResistance(Port *port, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, const MinMaxAll *min_max, float res) { - ensureInputDrive(port)->setDriveResistance(tr, min_max, res); + ensureInputDrive(port)->setDriveResistance(rf, min_max, res); } InputDrive * @@ -774,12 +774,12 @@ Sdc::ensureInputDrive(Port *port) void Sdc::setSlewLimit(Clock *clk, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, const PathClkOrData clk_data, const MinMax *min_max, float slew) { - clk->setSlewLimit(tr, clk_data, min_max, slew); + clk->setSlewLimit(rf, clk_data, min_max, slew); have_clk_slew_limits_ = true; } @@ -790,13 +790,13 @@ Sdc::haveClkSlewLimits() const } void -Sdc::slewLimit(Clock *clk, const TransRiseFall *tr, +Sdc::slewLimit(Clock *clk, const RiseFall *rf, const PathClkOrData clk_data, const MinMax *min_max, float &slew, bool &exists) { - clk->slewLimit(tr, clk_data, min_max, slew, exists); + clk->slewLimit(rf, clk_data, min_max, slew, exists); } void @@ -1545,11 +1545,11 @@ Sdc::isPropagatedClock(const Pin *pin) void Sdc::setClockSlew(Clock *clk, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, const MinMaxAll *min_max, float slew) { - clk->setSlew(tr, min_max, slew); + clk->setSlew(rf, min_max, slew); } void @@ -1561,7 +1561,7 @@ Sdc::removeClockSlew(Clock *clk) void Sdc::setClockLatency(Clock *clk, Pin *pin, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, const MinMaxAll *min_max, float delay) { @@ -1571,7 +1571,7 @@ Sdc::setClockLatency(Clock *clk, latency = new ClockLatency(clk, pin); clk_latencies_.insert(latency); } - latency->setDelay(tr, min_max, delay); + latency->setDelay(rf, min_max, delay); if (pin && graph_ && network_->isHierarchical(pin)) annotateHierClkLatency(pin, latency); @@ -1623,7 +1623,7 @@ Sdc::hasClockLatency(const Pin *pin) const void Sdc::clockLatency(const Clock *clk, const Pin *pin, - const TransRiseFall *tr, + const RiseFall *rf, const MinMax *min_max, // Return values. float &latency, @@ -1635,19 +1635,19 @@ Sdc::clockLatency(const Clock *clk, ClockLatency probe(clk, pin); ClockLatency *latencies = clk_latencies_.findKey(&probe); if (latencies) - latencies->delay(tr, min_max, latency, exists); + latencies->delay(rf, min_max, latency, exists); } if (!exists) { ClockLatency probe(nullptr, pin); ClockLatency *latencies = clk_latencies_.findKey(&probe); if (latencies) - latencies->delay(tr, min_max, latency, exists); + latencies->delay(rf, min_max, latency, exists); } } void Sdc::clockLatency(const Clock *clk, - const TransRiseFall *tr, + const RiseFall *rf, const MinMax *min_max, // Return values. float &latency, @@ -1658,17 +1658,17 @@ Sdc::clockLatency(const Clock *clk, ClockLatency probe(clk, nullptr); ClockLatency *latencies = clk_latencies_.findKey(&probe); if (latencies) - latencies->delay(tr, min_max, latency, exists); + latencies->delay(rf, min_max, latency, exists); } float Sdc::clockLatency(const Clock *clk, - const TransRiseFall *tr, + const RiseFall *rf, const MinMax *min_max) const { float latency; bool exists; - clockLatency(clk, tr, min_max, + clockLatency(clk, rf, min_max, latency, exists); return latency; } @@ -1723,9 +1723,9 @@ Sdc::clockUncertainty(const Pin *pin, void Sdc::clockUncertainty(const Clock *src_clk, - const TransRiseFall *src_tr, + const RiseFall *src_rf, const Clock *tgt_clk, - const TransRiseFall *tgt_tr, + const RiseFall *tgt_rf, const SetupHold *setup_hold, float &uncertainty, bool &exists) @@ -1734,7 +1734,7 @@ Sdc::clockUncertainty(const Clock *src_clk, InterClockUncertainty *uncertainties = inter_clk_uncertainties_.findKey(&probe); if (uncertainties) - uncertainties->uncertainty(src_tr, tgt_tr, setup_hold, + uncertainties->uncertainty(src_rf, tgt_rf, setup_hold, uncertainty, exists); else { uncertainty = 0.0; @@ -1744,9 +1744,9 @@ Sdc::clockUncertainty(const Clock *src_clk, void Sdc::setClockUncertainty(Clock *from_clk, - const TransRiseFallBoth *from_tr, + const RiseFallBoth *from_rf, Clock *to_clk, - const TransRiseFallBoth *to_tr, + const RiseFallBoth *to_rf, const SetupHoldAll *setup_hold, float uncertainty) { @@ -1757,21 +1757,21 @@ Sdc::setClockUncertainty(Clock *from_clk, uncertainties = new InterClockUncertainty(from_clk, to_clk); inter_clk_uncertainties_.insert(uncertainties); } - uncertainties->setUncertainty(from_tr, to_tr, setup_hold, uncertainty); + uncertainties->setUncertainty(from_rf, to_rf, setup_hold, uncertainty); } void Sdc::removeClockUncertainty(Clock *from_clk, - const TransRiseFallBoth *from_tr, + const RiseFallBoth *from_rf, Clock *to_clk, - const TransRiseFallBoth *to_tr, + const RiseFallBoth *to_rf, const SetupHoldAll *setup_hold) { InterClockUncertainty probe(from_clk, to_clk); InterClockUncertainty *uncertainties = inter_clk_uncertainties_.findKey(&probe); if (uncertainties) { - uncertainties->removeUncertainty(from_tr, to_tr, setup_hold); + uncertainties->removeUncertainty(from_rf, to_rf, setup_hold); if (uncertainties->empty()) { inter_clk_uncertainties_.erase(uncertainties); delete uncertainties; @@ -1803,7 +1803,7 @@ Sdc::deleteInterClockUncertaintiesReferencing(Clock *clk) void Sdc::setClockInsertion(const Clock *clk, const Pin *pin, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, const MinMaxAll *min_max, const EarlyLateAll *early_late, float delay) @@ -1816,13 +1816,13 @@ Sdc::setClockInsertion(const Clock *clk, insertion = new ClockInsertion(clk, pin); clk_insertions_->insert(insertion); } - insertion->setDelay(tr, min_max, early_late, delay); + insertion->setDelay(rf, min_max, early_late, delay); } void Sdc::setClockInsertion(const Clock *clk, const Pin *pin, - const TransRiseFall *tr, + const RiseFall *rf, const MinMax *min_max, const EarlyLate *early_late, float delay) @@ -1835,7 +1835,7 @@ Sdc::setClockInsertion(const Clock *clk, insertion = new ClockInsertion(clk, pin); clk_insertions_->insert(insertion); } - insertion->setDelay(tr, min_max, early_late, delay); + insertion->setDelay(rf, min_max, early_late, delay); } void @@ -1870,13 +1870,13 @@ Sdc::deleteClockInsertionsReferencing(Clock *clk) float Sdc::clockInsertion(const Clock *clk, - const TransRiseFall *tr, + const RiseFall *rf, const MinMax *min_max, const EarlyLate *early_late) const { float insertion; bool exists; - clockInsertion(clk, nullptr, tr, min_max, early_late, insertion, exists); + clockInsertion(clk, nullptr, rf, min_max, early_late, insertion, exists); return insertion; } @@ -1894,7 +1894,7 @@ Sdc::hasClockInsertion(const Pin *pin) const void Sdc::clockInsertion(const Clock *clk, const Pin *pin, - const TransRiseFall *tr, + const RiseFall *rf, const MinMax *min_max, const EarlyLate *early_late, // Return values. @@ -1917,7 +1917,7 @@ Sdc::clockInsertion(const Clock *clk, } } if (insert) - insert->delay(tr, min_max, early_late, insertion, exists); + insert->delay(rf, min_max, early_late, insertion, exists); else { insertion = 0.0; exists = false; @@ -2270,8 +2270,8 @@ Sdc::clkStopPropagation(const Pin *pin, bool Sdc::clkStopSense(const Pin *to_pin, const Clock *clk, - const TransRiseFall *from_tr, - const TransRiseFall *to_tr) const + const RiseFall *from_rf, + const RiseFall *to_rf) const { PinClockPair pin_clk(to_pin, clk); ClockSense sense; @@ -2284,20 +2284,20 @@ Sdc::clkStopSense(const Pin *to_pin, return exists && (sense == ClockSense::stop || (sense == ClockSense::positive - && from_tr != to_tr) + && from_rf != to_rf) || (sense == ClockSense::negative - && from_tr == to_tr)); + && from_rf == to_rf)); } bool Sdc::clkStopPropagation(const Clock *clk, const Pin *from_pin, - const TransRiseFall *from_tr, + const RiseFall *from_rf, const Pin *to_pin, - const TransRiseFall *to_tr) const + const RiseFall *to_rf) const { return clkStopPropagation(from_pin, clk) - || clkStopSense(to_pin, clk, from_tr, to_tr); + || clkStopSense(to_pin, clk, from_rf, to_rf); } PinClockPairLess::PinClockPairLess(const Network *network) : @@ -2323,18 +2323,18 @@ PinClockPairLess::operator()(const PinClockPair &pin_clk1, //////////////////////////////////////////////////////////////// void -Sdc::setClockGatingCheck(const TransRiseFallBoth *tr, +Sdc::setClockGatingCheck(const RiseFallBoth *rf, const SetupHold *setup_hold, float margin) { if (clk_gating_check_ == nullptr) clk_gating_check_ = new ClockGatingCheck; - clk_gating_check_->margins()->setValue(tr, setup_hold, margin); + clk_gating_check_->margins()->setValue(rf, setup_hold, margin); } void Sdc::setClockGatingCheck(Clock *clk, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, const SetupHold *setup_hold, float margin) { @@ -2343,12 +2343,12 @@ Sdc::setClockGatingCheck(Clock *clk, check = new ClockGatingCheck(); clk_gating_check_map_[clk] = check; } - check->margins()->setValue(tr, setup_hold, margin); + check->margins()->setValue(rf, setup_hold, margin); } void Sdc::setClockGatingCheck(Instance *inst, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, const SetupHold *setup_hold, float margin, LogicValue active_value) @@ -2358,13 +2358,13 @@ Sdc::setClockGatingCheck(Instance *inst, check = new ClockGatingCheck(); inst_clk_gating_check_map_[inst] = check; } - check->margins()->setValue(tr, setup_hold, margin); + check->margins()->setValue(rf, setup_hold, margin); check->setActiveValue(active_value); } void Sdc::setClockGatingCheck(const Pin *pin, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, const SetupHold *setup_hold, float margin, LogicValue active_value) @@ -2374,73 +2374,73 @@ Sdc::setClockGatingCheck(const Pin *pin, check = new ClockGatingCheck(); pin_clk_gating_check_map_[pin] = check; } - check->margins()->setValue(tr, setup_hold, margin); + check->margins()->setValue(rf, setup_hold, margin); check->setActiveValue(active_value); } void Sdc::clockGatingMarginEnablePin(const Pin *enable_pin, - const TransRiseFall *enable_tr, + const RiseFall *enable_rf, const SetupHold *setup_hold, bool &exists, float &margin) { ClockGatingCheck *check = pin_clk_gating_check_map_.findKey(enable_pin); if (check) - check->margins()->value(enable_tr, setup_hold, margin, exists); + check->margins()->value(enable_rf, setup_hold, margin, exists); else exists = false; } void Sdc::clockGatingMarginInstance(Instance *inst, - const TransRiseFall *enable_tr, + const RiseFall *enable_rf, const SetupHold *setup_hold, bool &exists, float &margin) { ClockGatingCheck *check = inst_clk_gating_check_map_.findKey(inst); if (check) - check->margins()->value(enable_tr, setup_hold, margin, exists); + check->margins()->value(enable_rf, setup_hold, margin, exists); else exists = false; } void Sdc::clockGatingMarginClkPin(const Pin *clk_pin, - const TransRiseFall *enable_tr, + const RiseFall *enable_rf, const SetupHold *setup_hold, bool &exists, float &margin) { ClockGatingCheck *check = pin_clk_gating_check_map_.findKey(clk_pin); if (check) - check->margins()->value(enable_tr, setup_hold, margin, exists); + check->margins()->value(enable_rf, setup_hold, margin, exists); else exists = false; } void Sdc::clockGatingMarginClk(const Clock *clk, - const TransRiseFall *enable_tr, + const RiseFall *enable_rf, const SetupHold *setup_hold, bool &exists, float &margin) { ClockGatingCheck *check = clk_gating_check_map_.findKey(clk); if (check) - check->margins()->value(enable_tr, setup_hold, margin, exists); + check->margins()->value(enable_rf, setup_hold, margin, exists); else exists = false; } void -Sdc::clockGatingMargin(const TransRiseFall *enable_tr, +Sdc::clockGatingMargin(const RiseFall *enable_rf, const SetupHold *setup_hold, bool &exists, float &margin) { if (clk_gating_check_) - clk_gating_check_->margins()->value(enable_tr, setup_hold, margin, exists); + clk_gating_check_->margins()->value(enable_rf, setup_hold, margin, exists); else exists = false; } @@ -2535,9 +2535,9 @@ Sdc::clearCycleAcctings() void Sdc::setDataCheck(Pin *from, - const TransRiseFallBoth *from_tr, + const RiseFallBoth *from_rf, Pin *to, - const TransRiseFallBoth *to_tr, + const RiseFallBoth *to_rf, Clock *clk, const SetupHoldAll *setup_hold, float margin) @@ -2554,7 +2554,7 @@ Sdc::setDataCheck(Pin *from, } if (check == nullptr) check = new DataCheck(from, to, clk); - check->setMargin(from_tr, to_tr, setup_hold, margin); + check->setMargin(from_rf, to_rf, setup_hold, margin); checks->insert(check); checks = data_checks_to_map_.findKey(to); @@ -2570,9 +2570,9 @@ Sdc::setDataCheck(Pin *from, void Sdc::removeDataCheck(Pin *from, - const TransRiseFallBoth *from_tr, + const RiseFallBoth *from_rf, Pin *to, - const TransRiseFallBoth *to_tr, + const RiseFallBoth *to_rf, Clock *clk, const SetupHoldAll *setup_hold) { @@ -2581,7 +2581,7 @@ Sdc::removeDataCheck(Pin *from, if (checks) { DataCheck *check = checks->findKey(&probe); if (check) { - check->removeMargin(from_tr, to_tr, setup_hold); + check->removeMargin(from_rf, to_rf, setup_hold); if (check->empty()) { checks->erase(check); checks = data_checks_to_map_.findKey(to); @@ -2657,16 +2657,16 @@ Sdc::latchBorrowLimit(Pin *data_pin, //////////////////////////////////////////////////////////////// void -Sdc::setMinPulseWidth(const TransRiseFallBoth *tr, +Sdc::setMinPulseWidth(const RiseFallBoth *rf, float min_width) { - for (auto tr1 : tr->range()) - min_pulse_width_.setValue(tr1, min_width); + for (auto rf1 : rf->range()) + min_pulse_width_.setValue(rf1, min_width); } void Sdc::setMinPulseWidth(const Pin *pin, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, float min_width) { RiseFallValues *widths = pin_min_pulse_width_map_.findKey(pin); @@ -2674,13 +2674,13 @@ Sdc::setMinPulseWidth(const Pin *pin, widths = new RiseFallValues; pin_min_pulse_width_map_[pin] = widths; } - for (auto tr1 : tr->range()) - widths->setValue(tr1, min_width); + for (auto rf1 : rf->range()) + widths->setValue(rf1, min_width); } void Sdc::setMinPulseWidth(const Instance *inst, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, float min_width) { RiseFallValues *widths = inst_min_pulse_width_map_.findKey(inst); @@ -2688,13 +2688,13 @@ Sdc::setMinPulseWidth(const Instance *inst, widths = new RiseFallValues; inst_min_pulse_width_map_[inst] = widths; } - for (auto tr1 : tr->range()) - widths->setValue(tr1, min_width); + for (auto rf1 : rf->range()) + widths->setValue(rf1, min_width); } void Sdc::setMinPulseWidth(const Clock *clk, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, float min_width) { RiseFallValues *widths = clk_min_pulse_width_map_.findKey(clk); @@ -2702,14 +2702,14 @@ Sdc::setMinPulseWidth(const Clock *clk, widths = new RiseFallValues; clk_min_pulse_width_map_[clk] = widths; } - for (auto tr1 : tr->range()) - widths->setValue(tr1, min_width); + for (auto rf1 : rf->range()) + widths->setValue(rf1, min_width); } void Sdc::minPulseWidth(const Pin *pin, const Clock *clk, - const TransRiseFall *hi_low, + const RiseFall *hi_low, float &min_width, bool &exists) const { @@ -2750,9 +2750,9 @@ Sdc::findInputDrive(Port *port) void Sdc::setInputDelay(Pin *pin, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, Clock *clk, - const TransRiseFall *clk_tr, + const RiseFall *clk_rf, Pin *ref_pin, bool source_latency_included, bool network_latency_included, @@ -2760,18 +2760,18 @@ Sdc::setInputDelay(Pin *pin, bool add, float delay) { - ClockEdge *clk_edge = clk ? clk->edge(clk_tr) : nullptr; + ClockEdge *clk_edge = clk ? clk->edge(clk_rf) : nullptr; InputDelay *input_delay = findInputDelay(pin, clk_edge, ref_pin); if (input_delay == nullptr) input_delay = makeInputDelay(pin, clk_edge, ref_pin); if (add) { RiseFallMinMax *delays = input_delay->delays(); - delays->mergeValue(tr, min_max, delay); + delays->mergeValue(rf, min_max, delay); } else { deleteInputDelays(pin, input_delay); RiseFallMinMax *delays = input_delay->delays(); - delays->setValue(tr, min_max, delay); + delays->setValue(rf, min_max, delay); } input_delay->setSourceLatencyIncluded(source_latency_included); input_delay->setNetworkLatencyIncluded(network_latency_included); @@ -2840,16 +2840,16 @@ Sdc::findInputDelay(const Pin *pin, void Sdc::removeInputDelay(Pin *pin, - TransRiseFallBoth *tr, + RiseFallBoth *rf, Clock *clk, - TransRiseFall *clk_tr, + RiseFall *clk_rf, MinMaxAll *min_max) { - ClockEdge *clk_edge = clk ? clk->edge(clk_tr) : nullptr; + ClockEdge *clk_edge = clk ? clk->edge(clk_rf) : nullptr; InputDelay *input_delay = findInputDelay(pin, clk_edge, nullptr); if (input_delay) { RiseFallMinMax *delays = input_delay->delays(); - delays->removeValue(tr, min_max); + delays->removeValue(rf, min_max); if (delays->empty()) deleteInputDelay(input_delay); } @@ -2925,9 +2925,9 @@ Sdc::deleteInputDelay(InputDelay *input_delay) void Sdc::setOutputDelay(Pin *pin, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, Clock *clk, - const TransRiseFall *clk_tr, + const RiseFall *clk_rf, Pin *ref_pin, bool source_latency_included, bool network_latency_included, @@ -2935,18 +2935,18 @@ Sdc::setOutputDelay(Pin *pin, bool add, float delay) { - ClockEdge *clk_edge = clk ? clk->edge(clk_tr) : nullptr; + ClockEdge *clk_edge = clk ? clk->edge(clk_rf) : nullptr; OutputDelay *output_delay = findOutputDelay(pin, clk_edge, ref_pin); if (output_delay == nullptr) output_delay = makeOutputDelay(pin, clk_edge, ref_pin); if (add) { RiseFallMinMax *delays = output_delay->delays(); - delays->mergeValue(tr, min_max, delay); + delays->mergeValue(rf, min_max, delay); } else { deleteOutputDelays(pin, output_delay); RiseFallMinMax *delays = output_delay->delays(); - delays->setValue(tr, min_max, delay); + delays->setValue(rf, min_max, delay); } output_delay->setSourceLatencyIncluded(source_latency_included); output_delay->setNetworkLatencyIncluded(network_latency_included); @@ -3007,16 +3007,16 @@ Sdc::makeOutputDelay(Pin *pin, void Sdc::removeOutputDelay(Pin *pin, - TransRiseFallBoth *tr, + RiseFallBoth *rf, Clock *clk, - TransRiseFall *clk_tr, + RiseFall *clk_rf, MinMaxAll *min_max) { - ClockEdge *clk_edge = clk ? clk->edge(clk_tr) : nullptr; + ClockEdge *clk_edge = clk ? clk->edge(clk_rf) : nullptr; OutputDelay *output_delay = findOutputDelay(pin, clk_edge, nullptr); if (output_delay) { RiseFallMinMax *delays = output_delay->delays(); - delays->removeValue(tr, min_max); + delays->removeValue(rf, min_max); } } @@ -3077,18 +3077,18 @@ Sdc::deleteOutputDelay(OutputDelay *output_delay) void Sdc::setPortExtPinCap(Port *port, - const TransRiseFall *tr, + const RiseFall *rf, const MinMax *min_max, float cap) { PortExtCap *port_cap = ensurePortExtPinCap(port); - port_cap->setPinCap(cap, tr, min_max); + port_cap->setPinCap(cap, rf, min_max); } void Sdc::setPortExtWireCap(Port *port, bool subtract_pin_cap, - const TransRiseFall *tr, + const RiseFall *rf, const Corner *corner, const MinMax *min_max, float cap) @@ -3097,11 +3097,11 @@ Sdc::setPortExtWireCap(Port *port, if (subtract_pin_cap) { Pin *pin = network_->findPin(network_->name(port)); const OperatingConditions *op_cond = operatingConditions(min_max); - cap -= connectedPinCap(pin, tr, op_cond, corner, min_max); + cap -= connectedPinCap(pin, rf, op_cond, corner, min_max); if (cap < 0.0) cap = 0.0; } - port_cap->setWireCap(cap, tr, min_max); + port_cap->setWireCap(cap, rf, min_max); } PortExtCap * @@ -3124,7 +3124,7 @@ Sdc::hasPortExtCap(Port *port) const void Sdc::portExtCap(Port *port, - const TransRiseFall *tr, + const RiseFall *rf, const MinMax *min_max, // Return values. float &pin_cap, @@ -3137,8 +3137,8 @@ Sdc::portExtCap(Port *port, if (port_cap_map_) { PortExtCap *port_cap = port_cap_map_->findKey(port); if (port_cap) { - port_cap->pinCap(tr, min_max, pin_cap, has_pin_cap); - port_cap->wireCap(tr, min_max, wire_cap, has_wire_cap); + port_cap->pinCap(rf, min_max, pin_cap, has_pin_cap); + port_cap->wireCap(rf, min_max, wire_cap, has_wire_cap); port_cap->fanout(min_max, fanout, has_fanout); return; } @@ -3153,13 +3153,13 @@ Sdc::portExtCap(Port *port, float Sdc::portExtCap(Port *port, - const TransRiseFall *tr, + const RiseFall *rf, const MinMax *min_max) const { float pin_cap, wire_cap; int fanout; bool has_pin_cap, has_wire_cap, has_fanout; - portExtCap(port, tr, min_max, + portExtCap(port, rf, min_max, pin_cap, has_pin_cap, wire_cap, has_wire_cap, fanout, has_fanout); @@ -3209,9 +3209,9 @@ Sdc::setNetWireCap(Net *net, NetConnectedPinIterator *pin_iter = network_->connectedPinIterator(net); if (pin_iter->hasNext()) { Pin *pin = pin_iter->next(); - float pin_cap_rise = connectedPinCap(pin, TransRiseFall::rise(), + float pin_cap_rise = connectedPinCap(pin, RiseFall::rise(), op_cond, corner, min_max); - float pin_cap_fall = connectedPinCap(pin, TransRiseFall::fall(), + float pin_cap_fall = connectedPinCap(pin, RiseFall::fall(), op_cond, corner, min_max); float pin_cap = (pin_cap_rise + pin_cap_fall) / 2.0F; wire_cap -= pin_cap; @@ -3252,7 +3252,7 @@ Sdc::hasNetWireCap(Net *net) const void Sdc::connectedCap(const Pin *pin, - const TransRiseFall *tr, + const RiseFall *rf, const OperatingConditions *op_cond, const Corner *corner, const MinMax *min_max, @@ -3262,7 +3262,7 @@ Sdc::connectedCap(const Pin *pin, float &fanout, bool &has_set_load) const { - netCaps(pin, tr, op_cond, corner, min_max, + netCaps(pin, rf, op_cond, corner, min_max, pin_cap, wire_cap, fanout, has_set_load); float net_wire_cap; bool has_net_wire_cap; @@ -3275,14 +3275,14 @@ Sdc::connectedCap(const Pin *pin, float Sdc::connectedPinCap(const Pin *pin, - const TransRiseFall *tr, + const RiseFall *rf, const OperatingConditions *op_cond, const Corner *corner, const MinMax *min_max) { float pin_cap, wire_cap, fanout; bool has_set_load; - connectedCap(pin, tr, op_cond, corner, min_max, + connectedCap(pin, rf, op_cond, corner, min_max, pin_cap, wire_cap, fanout, has_set_load); return pin_cap; } @@ -3290,7 +3290,7 @@ Sdc::connectedPinCap(const Pin *pin, class FindNetCaps : public PinVisitor { public: - FindNetCaps(const TransRiseFall *tr, + FindNetCaps(const RiseFall *rf, const OperatingConditions *op_cond, const Corner *corner, const MinMax *min_max, @@ -3302,7 +3302,7 @@ public: virtual void operator()(Pin *pin); protected: - const TransRiseFall *tr_; + const RiseFall *rf_; const OperatingConditions *op_cond_; const Corner *corner_; const MinMax *min_max_; @@ -3316,7 +3316,7 @@ private: DISALLOW_COPY_AND_ASSIGN(FindNetCaps); }; -FindNetCaps::FindNetCaps(const TransRiseFall *tr, +FindNetCaps::FindNetCaps(const RiseFall *rf, const OperatingConditions *op_cond, const Corner *corner, const MinMax *min_max, @@ -3326,7 +3326,7 @@ FindNetCaps::FindNetCaps(const TransRiseFall *tr, bool &has_set_load, const Sdc *sdc) : PinVisitor(), - tr_(tr), + rf_(rf), op_cond_(op_cond), corner_(corner), min_max_(min_max), @@ -3341,14 +3341,14 @@ FindNetCaps::FindNetCaps(const TransRiseFall *tr, void FindNetCaps::operator()(Pin *pin) { - sdc_->pinCaps(pin, tr_, op_cond_, corner_, min_max_, + sdc_->pinCaps(pin, rf_, op_cond_, corner_, min_max_, pin_cap_, wire_cap_, fanout_, has_set_load_); } // Capacitances for all pins connected to drvr_pin's net. void Sdc::netCaps(const Pin *drvr_pin, - const TransRiseFall *tr, + const RiseFall *rf, const OperatingConditions *op_cond, const Corner *corner, const MinMax *min_max, @@ -3362,14 +3362,14 @@ Sdc::netCaps(const Pin *drvr_pin, wire_cap = 0.0; fanout = 0.0; has_set_load = false; - FindNetCaps visitor(tr, op_cond, corner, min_max, pin_cap, + FindNetCaps visitor(rf, op_cond, corner, min_max, pin_cap, wire_cap, fanout, has_set_load, this); network_->visitConnectedPins(const_cast(drvr_pin), visitor); } void Sdc::pinCaps(const Pin *pin, - const TransRiseFall *tr, + const RiseFall *rf, const OperatingConditions *op_cond, const Corner *corner, const MinMax *min_max, @@ -3385,7 +3385,7 @@ Sdc::pinCaps(const Pin *pin, float port_pin_cap, port_wire_cap; int port_fanout; bool has_pin_cap, has_wire_cap, has_fanout; - portExtCap(port, tr, min_max, + portExtCap(port, rf, min_max, port_pin_cap, has_pin_cap, port_wire_cap, has_wire_cap, port_fanout, has_fanout); @@ -3405,7 +3405,7 @@ Sdc::pinCaps(const Pin *pin, LibertyPort *port = network_->libertyPort(pin); if (port) { Instance *inst = network_->instance(pin); - pin_cap += portCapacitance(inst, port, tr, op_cond, corner, min_max); + pin_cap += portCapacitance(inst, port, rf, op_cond, corner, min_max); if (port->direction()->isAnyInput()) fanout++; } @@ -3415,7 +3415,7 @@ Sdc::pinCaps(const Pin *pin, float Sdc::portCapacitance(Instance *inst, LibertyPort *port, - const TransRiseFall *tr, + const RiseFall *rf, const OperatingConditions *op_cond, const Corner *corner, const MinMax *min_max) const @@ -3424,12 +3424,12 @@ Sdc::portCapacitance(Instance *inst, if (inst) inst_pvt = pvt(inst, min_max); LibertyPort *corner_port = port->cornerPort(corner->libertyIndex(min_max)); - return corner_port->capacitance(tr, min_max, op_cond, inst_pvt); + return corner_port->capacitance(rf, min_max, op_cond, inst_pvt); } float Sdc::pinCapacitance(const Pin *pin, - const TransRiseFall *tr, + const RiseFall *rf, const OperatingConditions *op_cond, const Corner *corner, const MinMax *min_max) @@ -3437,7 +3437,7 @@ Sdc::pinCapacitance(const Pin *pin, LibertyPort *port = network_->libertyPort(pin); if (port) { Instance *inst = network_->instance(pin); - return portCapacitance(inst, port, tr, op_cond, corner, min_max); + return portCapacitance(inst, port, rf, op_cond, corner, min_max); } else return 0.0; @@ -3977,12 +3977,12 @@ ExceptionFrom * Sdc::makeExceptionFrom(PinSet *from_pins, ClockSet *from_clks, InstanceSet *from_insts, - const TransRiseFallBoth *from_tr) + const RiseFallBoth *from_rf) { if ((from_pins && !from_pins->empty()) || (from_clks && !from_clks->empty()) || (from_insts && !from_insts->empty())) - return new ExceptionFrom(from_pins, from_clks, from_insts, from_tr, true); + return new ExceptionFrom(from_pins, from_clks, from_insts, from_rf, true); else return nullptr; } @@ -3991,12 +3991,12 @@ ExceptionThru * Sdc::makeExceptionThru(PinSet *pins, NetSet *nets, InstanceSet *insts, - const TransRiseFallBoth *tr) + const RiseFallBoth *rf) { if ((pins && !pins->empty()) || (nets && !nets->empty()) || (insts && !insts->empty())) - return new ExceptionThru(pins, nets, insts, tr, true, network_); + return new ExceptionThru(pins, nets, insts, rf, true, network_); else return nullptr; } @@ -4005,15 +4005,15 @@ ExceptionTo * Sdc::makeExceptionTo(PinSet *pins, ClockSet *clks, InstanceSet *insts, - const TransRiseFallBoth *tr, - const TransRiseFallBoth *end_tr) + const RiseFallBoth *rf, + const RiseFallBoth *end_rf) { if ((pins && !pins->empty()) || (clks && !clks->empty()) || (insts && !insts->empty()) - || (tr != TransRiseFallBoth::riseFall()) - || (end_tr != TransRiseFallBoth::riseFall())) - return new ExceptionTo(pins, clks, insts, tr, end_tr, true); + || (rf != RiseFallBoth::riseFall()) + || (end_rf != RiseFallBoth::riseFall())) + return new ExceptionTo(pins, clks, insts, rf, end_rf, true); else return nullptr; } @@ -4380,7 +4380,7 @@ Sdc::makeLoopExceptionThru(Pin *pin, PinSet *pins = new PinSet; pins->insert(pin); ExceptionThru *thru = makeExceptionThru(pins, nullptr, nullptr, - TransRiseFallBoth::riseFall()); + RiseFallBoth::riseFall()); thrus->push_back(thru); } @@ -5475,20 +5475,20 @@ Sdc::resetPath(ExceptionFrom *from, bool Sdc::exceptionFromStates(const Pin *pin, - const TransRiseFall *tr, + const RiseFall *rf, const Clock *clk, - const TransRiseFall *clk_tr, + const RiseFall *clk_rf, const MinMax *min_max, ExceptionStateSet *&states) const { - return exceptionFromStates(pin, tr, clk, clk_tr, min_max, true, states); + return exceptionFromStates(pin, rf, clk, clk_rf, min_max, true, states); } bool Sdc::exceptionFromStates(const Pin *pin, - const TransRiseFall *tr, + const RiseFall *rf, const Clock *clk, - const TransRiseFall *clk_tr, + const RiseFall *clk_rf, const MinMax *min_max, bool include_filter, ExceptionStateSet *&states) const @@ -5497,11 +5497,11 @@ Sdc::exceptionFromStates(const Pin *pin, if (pin) { if (srch_from && first_from_pin_exceptions_) srch_from &= exceptionFromStates(first_from_pin_exceptions_->findKey(pin), - nullptr, tr, min_max, include_filter, + nullptr, rf, min_max, include_filter, states); if (srch_from && first_thru_pin_exceptions_) srch_from &= exceptionFromStates(first_thru_pin_exceptions_->findKey(pin), - nullptr, tr, min_max, include_filter, + nullptr, rf, min_max, include_filter, states); if (srch_from @@ -5509,17 +5509,17 @@ Sdc::exceptionFromStates(const Pin *pin, Instance *inst = network_->instance(pin); if (srch_from && first_from_inst_exceptions_) srch_from &= exceptionFromStates(first_from_inst_exceptions_->findKey(inst), - pin, tr, min_max, include_filter, + pin, rf, min_max, include_filter, states); if (srch_from && first_thru_inst_exceptions_) srch_from &= exceptionFromStates(first_thru_inst_exceptions_->findKey(inst), - pin, tr, min_max, include_filter, + pin, rf, min_max, include_filter, states); } } if (srch_from && clk && first_from_clk_exceptions_) srch_from &= exceptionFromStates(first_from_clk_exceptions_->findKey(clk), - pin, clk_tr, min_max, include_filter, + pin, clk_rf, min_max, include_filter, states); if (!srch_from) { delete states; @@ -5531,7 +5531,7 @@ Sdc::exceptionFromStates(const Pin *pin, bool Sdc::exceptionFromStates(const ExceptionPathSet *exceptions, const Pin *pin, - const TransRiseFall *tr, + const RiseFall *rf, const MinMax *min_max, bool include_filter, ExceptionStateSet *&states) const @@ -5542,10 +5542,10 @@ Sdc::exceptionFromStates(const ExceptionPathSet *exceptions, ExceptionPath *exception = exception_iter.next(); if (exception->matches(min_max, false) && (exception->from() == nullptr - || exception->from()->transition()->matches(tr)) + || exception->from()->transition()->matches(rf)) && (include_filter || !exception->isFilter())) { ExceptionState *state = exception->firstState(); - if (state->matchesNextThru(nullptr, pin, tr, min_max, network_)) + if (state->matchesNextThru(nullptr, pin, rf, min_max, network_)) // -from clk -thru reg/clk state = state->nextState(); // If the exception is -from and has no -to transition it is @@ -5574,30 +5574,30 @@ Sdc::exceptionFromStates(const ExceptionPathSet *exceptions, void Sdc::exceptionFromClkStates(const Pin *pin, - const TransRiseFall *tr, + const RiseFall *rf, const Clock *clk, - const TransRiseFall *clk_tr, + const RiseFall *clk_rf, const MinMax *min_max, ExceptionStateSet *&states) const { if (pin) { if (first_from_pin_exceptions_) exceptionFromStates(first_from_pin_exceptions_->findKey(pin), - nullptr, tr, min_max, true, states); + nullptr, rf, min_max, true, states); if (first_from_inst_exceptions_) { Instance *inst = network_->instance(pin); exceptionFromStates(first_from_inst_exceptions_->findKey(inst), - pin, tr, min_max, true, states); + pin, rf, min_max, true, states); } } if (first_from_clk_exceptions_) exceptionFromStates(first_from_clk_exceptions_->findKey(clk), - pin, clk_tr, min_max, true, states); + pin, clk_rf, min_max, true, states); } void Sdc::filterRegQStates(const Pin *to_pin, - const TransRiseFall *to_tr, + const RiseFall *to_rf, const MinMax *min_max, ExceptionStateSet *&states) const { @@ -5610,7 +5610,7 @@ Sdc::filterRegQStates(const Pin *to_pin, ExceptionPath *exception = exception_iter.next(); // Hack for filter -from reg/Q. if (exception->isFilter() - && exception->matchesFirstPt(to_tr, min_max)) { + && exception->matchesFirstPt(to_rf, min_max)) { ExceptionState *state = exception->firstState(); if (states == nullptr) states = new ExceptionStateSet; @@ -5624,30 +5624,30 @@ Sdc::filterRegQStates(const Pin *to_pin, void Sdc::exceptionThruStates(const Pin *from_pin, const Pin *to_pin, - const TransRiseFall *to_tr, + const RiseFall *to_rf, const MinMax *min_max, ExceptionStateSet *&states) const { if (first_thru_pin_exceptions_) exceptionThruStates(first_thru_pin_exceptions_->findKey(to_pin), - to_tr, min_max, states); + to_rf, min_max, states); if (first_thru_edge_exceptions_) { EdgePins edge_pins(const_cast(from_pin), const_cast(to_pin)); exceptionThruStates(first_thru_edge_exceptions_->findKey(&edge_pins), - to_tr, min_max, states); + to_rf, min_max, states); } if (first_thru_inst_exceptions_ && (network_->direction(to_pin)->isAnyOutput() || network_->isLatchData(to_pin))) { const Instance *to_inst = network_->instance(to_pin); exceptionThruStates(first_thru_inst_exceptions_->findKey(to_inst), - to_tr, min_max, states); + to_rf, min_max, states); } } void Sdc::exceptionThruStates(const ExceptionPathSet *exceptions, - const TransRiseFall *to_tr, + const RiseFall *to_rf, const MinMax *min_max, // Return value. ExceptionStateSet *&states) const @@ -5656,7 +5656,7 @@ Sdc::exceptionThruStates(const ExceptionPathSet *exceptions, ExceptionPathSet::ConstIterator exception_iter(exceptions); while (exception_iter.hasNext()) { ExceptionPath *exception = exception_iter.next(); - if (exception->matchesFirstPt(to_tr, min_max)) { + if (exception->matchesFirstPt(to_rf, min_max)) { ExceptionState *state = exception->firstState(); if (states == nullptr) states = new ExceptionStateSet; @@ -5669,7 +5669,7 @@ Sdc::exceptionThruStates(const ExceptionPathSet *exceptions, void Sdc::exceptionTo(ExceptionPathType type, const Pin *pin, - const TransRiseFall *tr, + const RiseFall *rf, const ClockEdge *clk_edge, const MinMax *min_max, bool match_min_max_exactly, @@ -5679,17 +5679,17 @@ Sdc::exceptionTo(ExceptionPathType type, { if (first_to_inst_exceptions_) { Instance *inst = network_->instance(pin); - exceptionTo(first_to_inst_exceptions_->findKey(inst), type, pin, tr, + exceptionTo(first_to_inst_exceptions_->findKey(inst), type, pin, rf, clk_edge, min_max, match_min_max_exactly, hi_priority_exception, hi_priority); } if (first_to_pin_exceptions_) - exceptionTo(first_to_pin_exceptions_->findKey(pin), type, pin, tr, + exceptionTo(first_to_pin_exceptions_->findKey(pin), type, pin, rf, clk_edge, min_max, match_min_max_exactly, hi_priority_exception, hi_priority); if (clk_edge && first_to_clk_exceptions_) exceptionTo(first_to_clk_exceptions_->findKey(clk_edge->clock()), - type, pin, tr, clk_edge, min_max, match_min_max_exactly, + type, pin, rf, clk_edge, min_max, match_min_max_exactly, hi_priority_exception, hi_priority); } @@ -5697,7 +5697,7 @@ void Sdc::exceptionTo(const ExceptionPathSet *to_exceptions, ExceptionPathType type, const Pin *pin, - const TransRiseFall *tr, + const RiseFall *rf, const ClockEdge *clk_edge, const MinMax *min_max, bool match_min_max_exactly, @@ -5709,7 +5709,7 @@ Sdc::exceptionTo(const ExceptionPathSet *to_exceptions, ExceptionPathSet::ConstIterator exception_iter(to_exceptions); while (exception_iter.hasNext()) { ExceptionPath *exception = exception_iter.next(); - exceptionTo(exception, type, pin, tr, clk_edge, + exceptionTo(exception, type, pin, rf, clk_edge, min_max, match_min_max_exactly, hi_priority_exception, hi_priority); } @@ -5720,7 +5720,7 @@ void Sdc::exceptionTo(ExceptionPath *exception, ExceptionPathType type, const Pin *pin, - const TransRiseFall *tr, + const RiseFall *rf, const ClockEdge *clk_edge, const MinMax *min_max, bool match_min_max_exactly, @@ -5730,7 +5730,7 @@ Sdc::exceptionTo(ExceptionPath *exception, { if ((type == ExceptionPathType::any || exception->type() == type) - && exceptionMatchesTo(exception, pin, tr, clk_edge, min_max, + && exceptionMatchesTo(exception, pin, rf, clk_edge, min_max, match_min_max_exactly, false)) { int priority = exception->priority(min_max); if (hi_priority_exception == nullptr @@ -5746,7 +5746,7 @@ Sdc::exceptionTo(ExceptionPath *exception, bool Sdc::exceptionMatchesTo(ExceptionPath *exception, const Pin *pin, - const TransRiseFall *tr, + const RiseFall *rf, const ClockEdge *clk_edge, const MinMax *min_max, bool match_min_max_exactly, @@ -5757,20 +5757,20 @@ Sdc::exceptionMatchesTo(ExceptionPath *exception, && ((to == nullptr && !require_to_pin) || (to - && to->matches(pin, clk_edge, tr, network_))); + && to->matches(pin, clk_edge, rf, network_))); } bool Sdc::isCompleteTo(ExceptionState *state, const Pin *pin, - const TransRiseFall *tr, + const RiseFall *rf, const ClockEdge *clk_edge, const MinMax *min_max, bool match_min_max_exactly, bool require_to_pin) const { return state->nextThru() == nullptr - && exceptionMatchesTo(state->exception(), pin, tr, clk_edge, + && exceptionMatchesTo(state->exception(), pin, rf, clk_edge, min_max, match_min_max_exactly, require_to_pin); } @@ -6022,7 +6022,7 @@ Sdc::setClkThruTristateEnabled(bool enable) ClockEdge * Sdc::defaultArrivalClockEdge() const { - return default_arrival_clk_->edge(TransRiseFall::rise()); + return default_arrival_clk_->edge(RiseFall::rise()); } bool @@ -6425,7 +6425,7 @@ Sdc::clockLatency(Edge *edge) const void Sdc::clockLatency(Edge *edge, - const TransRiseFall *tr, + const RiseFall *rf, const MinMax *min_max, // Return values. float &latency, @@ -6433,7 +6433,7 @@ Sdc::clockLatency(Edge *edge, { ClockLatency *latencies = edge_clk_latency_.findKey(edge); if (latencies) - latencies->delay(tr, min_max, latency, exists); + latencies->delay(rf, min_max, latency, exists); else { latency = 0.0; exists = false; diff --git a/sdc/Sdc.hh b/sdc/Sdc.hh index 6369994c..4fa9cd89 100644 --- a/sdc/Sdc.hh +++ b/sdc/Sdc.hh @@ -197,42 +197,42 @@ public: const MinMax *min_max); void setTimingDerate(TimingDerateType type, PathClkOrData clk_data, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, const EarlyLate *early_late, float derate); // Delay type is always net for net derating. void setTimingDerate(const Net *net, PathClkOrData clk_data, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, const EarlyLate *early_late, float derate); void setTimingDerate(const Instance *inst, TimingDerateType type, PathClkOrData clk_data, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, const EarlyLate *early_late, float derate); void setTimingDerate(const LibertyCell *cell, TimingDerateType type, PathClkOrData clk_data, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, const EarlyLate *early_late, float derate); float timingDerateInstance(const Pin *pin, TimingDerateType type, PathClkOrData clk_data, - const TransRiseFall *tr, + const RiseFall *rf, const EarlyLate *early_late) const; float timingDerateNet(const Pin *pin, PathClkOrData clk_data, - const TransRiseFall *tr, + const RiseFall *rf, const EarlyLate *early_late) const; void unsetTimingDerate(); - void setInputSlew(Port *port, const TransRiseFallBoth *tr, + void setInputSlew(Port *port, const RiseFallBoth *rf, const MinMaxAll *min_max, float slew); // Set the rise/fall drive resistance on design port. void setDriveResistance(Port *port, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, const MinMaxAll *min_max, float res); // Set the drive on design port using external cell timing arcs of @@ -243,7 +243,7 @@ public: LibertyPort *from_port, float *from_slews, LibertyPort *to_port, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, const MinMaxAll *min_max); void setLatchBorrowLimit(Pin *pin, float limit); @@ -259,31 +259,31 @@ public: // Return values. float &limit, bool &exists); - void setMinPulseWidth(const TransRiseFallBoth *tr, + void setMinPulseWidth(const RiseFallBoth *rf, float min_width); void setMinPulseWidth(const Pin *pin, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, float min_width); void setMinPulseWidth(const Instance *inst, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, float min_width); void setMinPulseWidth(const Clock *clk, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, float min_width); // Return min pulse with respecting precidence. void minPulseWidth(const Pin *pin, const Clock *clk, - const TransRiseFall *hi_low, + const RiseFall *hi_low, float &min_width, bool &exists) const; void setSlewLimit(Clock *clk, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, const PathClkOrData clk_data, const MinMax *min_max, float slew); bool haveClkSlewLimits() const; void slewLimit(Clock *clk, - const TransRiseFall *tr, + const RiseFall *rf, const PathClkOrData clk_data, const MinMax *min_max, float &slew, @@ -385,14 +385,14 @@ public: void removePropagatedClock(Pin *pin); bool isPropagatedClock(const Pin *pin); void setClockSlew(Clock *clk, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, const MinMaxAll *min_max, float slew); void removeClockSlew(Clock *clk); // Latency can be on a clk, pin, or clk/pin combination. void setClockLatency(Clock *clk, Pin *pin, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, const MinMaxAll *min_max, float delay); void removeClockLatency(const Clock *clk, @@ -400,7 +400,7 @@ public: ClockLatency *clockLatency(Edge *edge) const; bool hasClockLatency(const Pin *pin) const; void clockLatency(Edge *edge, - const TransRiseFall *tr, + const RiseFall *rf, const MinMax *min_max, // Return values. float &latency, @@ -411,30 +411,30 @@ public: // This does NOT check for latency on clk (without pin). void clockLatency(const Clock *clk, const Pin *pin, - const TransRiseFall *tr, + const RiseFall *rf, const MinMax *min_max, // Return values. float &latency, bool &exists) const; void clockLatency(const Clock *clk, - const TransRiseFall *tr, + const RiseFall *rf, const MinMax *min_max, // Return values. float &latency, bool &exists) const; float clockLatency(const Clock *clk, - const TransRiseFall *tr, + const RiseFall *rf, const MinMax *min_max) const; // Clock insertion delay (set_clk_latency -source). // Insertion delay can be on a clk, pin, or clk/pin combination. void setClockInsertion(const Clock *clk, const Pin *pin, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, const MinMaxAll *min_max, const EarlyLateAll *early_late, float delay); void setClockInsertion(const Clock *clk, const Pin *pin, - const TransRiseFall *tr, + const RiseFall *rf, const MinMax *min_max, const EarlyLate *early_late, float delay); @@ -442,13 +442,13 @@ public: const Pin *pin); bool hasClockInsertion(const Pin *pin) const; float clockInsertion(const Clock *clk, - const TransRiseFall *tr, + const RiseFall *rf, const MinMax *min_max, const EarlyLate *early_late) const; // Respects precedence of pin/clk and set_input_delay on clk pin. void clockInsertion(const Clock *clk, const Pin *pin, - const TransRiseFall *tr, + const RiseFall *rf, const MinMax *min_max, const EarlyLate *early_late, // Return values. @@ -462,15 +462,15 @@ public: virtual void removeClockUncertainty(Pin *pin, const SetupHoldAll *setup_hold); virtual void setClockUncertainty(Clock *from_clk, - const TransRiseFallBoth *from_tr, + const RiseFallBoth *from_rf, Clock *to_clk, - const TransRiseFallBoth *to_tr, + const RiseFallBoth *to_rf, const SetupHoldAll *setup_hold, float uncertainty); virtual void removeClockUncertainty(Clock *from_clk, - const TransRiseFallBoth *from_tr, + const RiseFallBoth *from_rf, Clock *to_clk, - const TransRiseFallBoth *to_tr, + const RiseFallBoth *to_rf, const SetupHoldAll *setup_hold); ClockGroups *makeClockGroups(const char *name, bool logically_exclusive, @@ -498,78 +498,78 @@ public: const Clock *clk) const; bool clkStopPropagation(const Clock *clk, const Pin *from_pin, - const TransRiseFall *from_tr, + const RiseFall *from_rf, const Pin *to_pin, - const TransRiseFall *to_tr) const; - void setClockGatingCheck(const TransRiseFallBoth *tr, + const RiseFall *to_rf) const; + void setClockGatingCheck(const RiseFallBoth *rf, const SetupHold *setup_hold, float margin); void setClockGatingCheck(Instance *inst, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, const SetupHold *setup_hold, float margin, LogicValue active_value); void setClockGatingCheck(Clock *clk, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, const SetupHold *setup_hold, float margin); void setClockGatingCheck(const Pin *pin, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, const SetupHold *setup_hold, float margin, LogicValue active_value); void setDataCheck(Pin *from, - const TransRiseFallBoth *from_tr, + const RiseFallBoth *from_rf, Pin *to, - const TransRiseFallBoth *to_tr, + const RiseFallBoth *to_rf, Clock *clk, const SetupHoldAll *setup_hold, float margin); void removeDataCheck(Pin *from, - const TransRiseFallBoth *from_tr, + const RiseFallBoth *from_rf, Pin *to, - const TransRiseFallBoth *to_tr, + const RiseFallBoth *to_rf, Clock *clk, const SetupHoldAll *setup_hold); DataCheckSet *dataChecksFrom(const Pin *from) const; DataCheckSet *dataChecksTo(const Pin *to) const; void setInputDelay(Pin *pin, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, Clock *clk, - const TransRiseFall *clk_tr, + const RiseFall *clk_rf, Pin *ref_pin, bool source_latency_included, bool network_latency_included, const MinMaxAll *min_max, bool add, float delay); void removeInputDelay(Pin *pin, - TransRiseFallBoth *tr, + RiseFallBoth *rf, Clock *clk, - TransRiseFall *clk_tr, + RiseFall *clk_rf, MinMaxAll *min_max); void setOutputDelay(Pin *pin, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, Clock *clk, - const TransRiseFall *clk_tr, + const RiseFall *clk_tr, Pin *ref_pin, bool source_latency_included, bool network_latency_included, const MinMaxAll *min_max, bool add, float delay); void removeOutputDelay(Pin *pin, - TransRiseFallBoth *tr, + RiseFallBoth *rf, Clock *clk, - TransRiseFall *clk_tr, + RiseFall *clk_rf, MinMaxAll *min_max); // Set port external pin load (set_load -pin_load port). void setPortExtPinCap(Port *port, - const TransRiseFall *tr, + const RiseFall *rf, const MinMax *min_max, float cap); // Set port external wire load (set_load -wire port). void setPortExtWireCap(Port *port, bool subtract_pin_cap, - const TransRiseFall *tr, + const RiseFall *rf, const Corner *corner, const MinMax *min_max, float cap); @@ -594,7 +594,7 @@ public: bool &exists) const; // Pin capacitance derated by operating conditions and instance pvt. float pinCapacitance(const Pin *pin, - const TransRiseFall *tr, + const RiseFall *rf, const OperatingConditions *op_cond, const Corner *corner, const MinMax *min_max); @@ -733,19 +733,19 @@ public: ExceptionFrom *makeExceptionFrom(PinSet *from_pins, ClockSet *from_clks, InstanceSet *from_insts, - const TransRiseFallBoth *from_tr); + const RiseFallBoth *from_rf); // Make an exception -through specification. ExceptionThru *makeExceptionThru(PinSet *pins, NetSet *nets, InstanceSet *insts, - const TransRiseFallBoth *tr); + const RiseFallBoth *rf); bool exceptionToInvalid(const Pin *pin); // Make an exception -to specification. ExceptionTo *makeExceptionTo(PinSet *pins, ClockSet *clks, InstanceSet *insts, - const TransRiseFallBoth *tr, - const TransRiseFallBoth *end_tr); + const RiseFallBoth *rf, + const RiseFallBoth *end_rf); FilterPath *makeFilterPath(ExceptionFrom *from, ExceptionThruSeq *thrus, ExceptionTo *to); @@ -848,28 +848,28 @@ public: bool &exists); // Inter-clock uncertainty. void clockUncertainty(const Clock *src_clk, - const TransRiseFall *src_tr, + const RiseFall *src_rf, const Clock *tgt_clk, - const TransRiseFall *tgt_tr, + const RiseFall *tgt_rf, const SetupHold *setup_hold, float &uncertainty, bool &exists); void clockGatingMarginEnablePin(const Pin *enable_pin, - const TransRiseFall *enable_tr, + const RiseFall *enable_rf, const SetupHold *setup_hold, bool &exists, float &margin); void clockGatingMarginInstance(Instance *inst, - const TransRiseFall *enable_tr, + const RiseFall *enable_rf, const SetupHold *setup_hold, bool &exists, float &margin); void clockGatingMarginClkPin(const Pin *clk_pin, - const TransRiseFall *enable_tr, + const RiseFall *enable_rf, const SetupHold *setup_hold, bool &exists, float &margin); void clockGatingMarginClk(const Clock *clk, - const TransRiseFall *enable_tr, + const RiseFall *enable_rf, const SetupHold *setup_hold, bool &exists, float &margin); - void clockGatingMargin(const TransRiseFall *enable_tr, + void clockGatingMargin(const RiseFall *enable_rf, const SetupHold *setup_hold, bool &exists, float &margin); // Gated clock active (non-controlling) logic value. @@ -901,7 +901,7 @@ public: PortExtCap *portExtCap(Port *port) const; bool hasPortExtCap(Port *port) const; void portExtCap(Port *port, - const TransRiseFall *tr, + const RiseFall *rf, const MinMax *min_max, // Return values. float &pin_cap, @@ -911,13 +911,13 @@ public: int &fanout, bool &has_fanout) const; float portExtCap(Port *port, - const TransRiseFall *tr, + const RiseFall *rf, const MinMax *min_max) const; // Connected total capacitance. // pin_cap = pin capacitance + port external pin // wire_cap = port external wire capacitance + net wire capacitance void connectedCap(const Pin *pin, - const TransRiseFall *tr, + const RiseFall *rf, const OperatingConditions *op_cond, const Corner *corner, const MinMax *min_max, @@ -937,40 +937,40 @@ public: // that start at pin/net/instance also). Transition tr applies to // pin, not clk. bool exceptionFromStates(const Pin *pin, - const TransRiseFall *tr, + const RiseFall *rf, const Clock *clk, - const TransRiseFall *clk_tr, + const RiseFall *clk_rf, const MinMax *min_max, ExceptionStateSet *&states) const; bool exceptionFromStates(const Pin *pin, - const TransRiseFall *tr, + const RiseFall *rf, const Clock *clk, - const TransRiseFall *clk_tr, + const RiseFall *clk_rf, const MinMax *min_max, bool include_filter, ExceptionStateSet *&states) const; void exceptionFromClkStates(const Pin *pin, - const TransRiseFall *tr, + const RiseFall *rf, const Clock *clk, - const TransRiseFall *clk_tr, + const RiseFall *clk_rf, const MinMax *min_max, ExceptionStateSet *&states) const; void filterRegQStates(const Pin *to_pin, - const TransRiseFall *to_tr, + const RiseFall *to_rf, const MinMax *min_max, ExceptionStateSet *&states) const; // Return hierarchical -thru exceptions that start between // from_pin and to_pin. void exceptionThruStates(const Pin *from_pin, const Pin *to_pin, - const TransRiseFall *to_tr, + const RiseFall *to_rf, const MinMax *min_max, ExceptionStateSet *&states) const; // Find the highest priority exception with first exception pt at // pin/clk end. void exceptionTo(ExceptionPathType type, const Pin *pin, - const TransRiseFall *tr, + const RiseFall *rf, const ClockEdge *clk_edge, const MinMax *min_max, bool match_min_max_exactly, @@ -979,14 +979,14 @@ public: int &hi_priority) const; virtual bool exceptionMatchesTo(ExceptionPath *exception, const Pin *pin, - const TransRiseFall *tr, + const RiseFall *rf, const ClockEdge *clk_edge, const MinMax *min_max, bool match_min_max_exactly, bool require_to_pin) const; bool isCompleteTo(ExceptionState *state, const Pin *pin, - const TransRiseFall *tr, + const RiseFall *rf, const ClockEdge *clk_edge, const MinMax *min_max, bool match_min_max_exactly, @@ -1122,19 +1122,19 @@ protected: ExceptionPathSet &expansions); bool exceptionFromStates(const ExceptionPathSet *exceptions, const Pin *pin, - const TransRiseFall *tr, + const RiseFall *rf, const MinMax *min_max, bool include_filter, ExceptionStateSet *&states) const; void exceptionThruStates(const ExceptionPathSet *exceptions, - const TransRiseFall *to_tr, + const RiseFall *to_rf, const MinMax *min_max, // Return value. ExceptionStateSet *&states) const; void exceptionTo(const ExceptionPathSet *to_exceptions, ExceptionPathType type, const Pin *pin, - const TransRiseFall *tr, + const RiseFall *rf, const ClockEdge *clk_edge, const MinMax *min_max, bool match_min_max_exactly, @@ -1144,7 +1144,7 @@ protected: void exceptionTo(ExceptionPath *exception, ExceptionPathType type, const Pin *pin, - const TransRiseFall *tr, + const RiseFall *rf, const ClockEdge *clk_edge, const MinMax *min_max, bool match_min_max_exactly, @@ -1219,7 +1219,7 @@ protected: void deannotateHierClkLatency(const Pin *hpin); void initInstancePvtMaps(); void pinCaps(const Pin *pin, - const TransRiseFall *tr, + const RiseFall *rf, const OperatingConditions *op_cond, const Corner *corner, const MinMax *min_max, @@ -1228,7 +1228,7 @@ protected: float &fanout, bool &has_ext_cap) const; void netCaps(const Pin *drvr_pin, - const TransRiseFall *tr, + const RiseFall *rf, const OperatingConditions *op_cond, const Corner *corner, const MinMax *min_max, @@ -1239,12 +1239,12 @@ protected: bool &has_set_load) const; // connectedCap pin_cap. float connectedPinCap(const Pin *pin, - const TransRiseFall *tr, + const RiseFall *rf, const OperatingConditions *op_cond, const Corner *corner, const MinMax *min_max); float portCapacitance(Instance *inst, LibertyPort *port, - const TransRiseFall *tr, + const RiseFall *rf, const OperatingConditions *op_cond, const Corner *corner, const MinMax *min_max) const; @@ -1261,8 +1261,8 @@ protected: ClockSense sense); bool clkStopSense(const Pin *to_pin, const Clock *clk, - const TransRiseFall *from_tr, - const TransRiseFall *to_tr) const; + const RiseFall *from_rf, + const RiseFall *to_rf) const; void disconnectPinBefore(Pin *pin, ExceptionPathSet *exceptions); void clockGroupsDeleteClkRefs(Clock *clk); diff --git a/sdc/WriteSdc.cc b/sdc/WriteSdc.cc index 6ed5df67..e39ba647 100644 --- a/sdc/WriteSdc.cc +++ b/sdc/WriteSdc.cc @@ -52,9 +52,9 @@ typedef Set ClockSenseSet; typedef Vector ClockSenseSeq; static const char * -transRiseFallFlag(const TransRiseFall *tr); +transRiseFallFlag(const RiseFall *rf); static const char * -transRiseFallFlag(const TransRiseFallBoth *tr); +transRiseFallFlag(const RiseFallBoth *rf); static const char * minMaxFlag(const MinMaxAll *min_max); static const char * @@ -678,9 +678,9 @@ writeInterClockUncertainty(InterClockUncertainty *uncertainty) const const Clock *src_clk = uncertainty->src(); const Clock *tgt_clk = uncertainty->target(); const RiseFallMinMax *src_rise = - uncertainty->uncertainties(TransRiseFall::rise()); + uncertainty->uncertainties(RiseFall::rise()); const RiseFallMinMax *src_fall = - uncertainty->uncertainties(TransRiseFall::fall()); + uncertainty->uncertainties(RiseFall::fall()); float value; if (src_rise->equal(src_fall) && src_rise->isOneValue(value)) { @@ -693,19 +693,19 @@ writeInterClockUncertainty(InterClockUncertainty *uncertainty) const fprintf(stream_, "\n"); } else { - for (auto src_tr : TransRiseFall::range()) { - for (auto tgt_tr : TransRiseFall::range()) { + for (auto src_rf : RiseFall::range()) { + for (auto tgt_rf : RiseFall::range()) { for (auto setup_hold : SetupHold::range()) { float value; bool exists; - sdc_->clockUncertainty(src_clk, src_tr, tgt_clk, tgt_tr, + sdc_->clockUncertainty(src_clk, src_rf, tgt_clk, tgt_rf, setup_hold, value, exists); if (exists) { fprintf(stream_, "set_clock_uncertainty -%s_from ", - src_tr == TransRiseFall::rise() ? "rise" : "fall"); + src_rf == RiseFall::rise() ? "rise" : "fall"); writeGetClock(uncertainty->src()); fprintf(stream_, " -%s_to ", - tgt_tr == TransRiseFall::rise() ? "rise" : "fall"); + tgt_rf == RiseFall::rise() ? "rise" : "fall"); writeGetClock(uncertainty->target()); fprintf(stream_, " %s ", setupHoldFlag(setup_hold)); @@ -762,13 +762,13 @@ WriteSdc::writePortDelay(PortDelay *port_delay, RiseFallMinMax *delays = port_delay->delays(); float rise_min, rise_max, fall_min, fall_max; bool rise_min_exists, rise_max_exists, fall_min_exists, fall_max_exists; - delays->value(TransRiseFall::rise(), MinMax::min(), + delays->value(RiseFall::rise(), MinMax::min(), rise_min, rise_min_exists); - delays->value(TransRiseFall::rise(), MinMax::max(), + delays->value(RiseFall::rise(), MinMax::max(), rise_max, rise_max_exists); - delays->value(TransRiseFall::fall(), MinMax::min(), + delays->value(RiseFall::fall(), MinMax::min(), fall_min, fall_min_exists); - delays->value(TransRiseFall::fall(), MinMax::max(), + delays->value(RiseFall::fall(), MinMax::max(), fall_max, fall_max_exists); // Try to compress the four port delays. if (rise_min_exists @@ -779,7 +779,7 @@ WriteSdc::writePortDelay(PortDelay *port_delay, && fall_min == rise_min && fall_max == rise_min) writePortDelay(port_delay, is_input_delay, rise_min, - TransRiseFallBoth::riseFall(), MinMaxAll::all(), sdc_cmd); + RiseFallBoth::riseFall(), MinMaxAll::all(), sdc_cmd); else if (rise_min_exists && rise_max_exists && rise_max == rise_min @@ -787,9 +787,9 @@ WriteSdc::writePortDelay(PortDelay *port_delay, && fall_max_exists && fall_min == fall_max) { writePortDelay(port_delay, is_input_delay, rise_min, - TransRiseFallBoth::rise(), MinMaxAll::all(), sdc_cmd); + RiseFallBoth::rise(), MinMaxAll::all(), sdc_cmd); writePortDelay(port_delay, is_input_delay, fall_min, - TransRiseFallBoth::fall(), MinMaxAll::all(), sdc_cmd); + RiseFallBoth::fall(), MinMaxAll::all(), sdc_cmd); } else if (rise_min_exists && fall_min_exists @@ -798,23 +798,23 @@ WriteSdc::writePortDelay(PortDelay *port_delay, && fall_max_exists && rise_max == fall_max) { writePortDelay(port_delay, is_input_delay, rise_min, - TransRiseFallBoth::riseFall(), MinMaxAll::min(), sdc_cmd); + RiseFallBoth::riseFall(), MinMaxAll::min(), sdc_cmd); writePortDelay(port_delay, is_input_delay, rise_max, - TransRiseFallBoth::riseFall(), MinMaxAll::max(), sdc_cmd); + RiseFallBoth::riseFall(), MinMaxAll::max(), sdc_cmd); } else { if (rise_min_exists) writePortDelay(port_delay, is_input_delay, rise_min, - TransRiseFallBoth::rise(), MinMaxAll::min(), sdc_cmd); + RiseFallBoth::rise(), MinMaxAll::min(), sdc_cmd); if (rise_max_exists) writePortDelay(port_delay, is_input_delay, rise_max, - TransRiseFallBoth::rise(), MinMaxAll::max(), sdc_cmd); + RiseFallBoth::rise(), MinMaxAll::max(), sdc_cmd); if (fall_min_exists) writePortDelay(port_delay, is_input_delay, fall_min, - TransRiseFallBoth::fall(), MinMaxAll::min(), sdc_cmd); + RiseFallBoth::fall(), MinMaxAll::min(), sdc_cmd); if (fall_max_exists) writePortDelay(port_delay, is_input_delay, fall_max, - TransRiseFallBoth::fall(), MinMaxAll::max(), sdc_cmd); + RiseFallBoth::fall(), MinMaxAll::max(), sdc_cmd); } } @@ -822,7 +822,7 @@ void WriteSdc::writePortDelay(PortDelay *port_delay, bool is_input_delay, float delay, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, const MinMaxAll *min_max, const char *sdc_cmd) const { @@ -831,11 +831,11 @@ WriteSdc::writePortDelay(PortDelay *port_delay, ClockEdge *clk_edge = port_delay->clkEdge(); if (clk_edge) { writeClockKey(clk_edge->clock()); - if (clk_edge->transition() == TransRiseFall::fall()) + if (clk_edge->transition() == RiseFall::fall()) fprintf(stream_, " -clock_fall"); } fprintf(stream_, "%s%s -add_delay ", - transRiseFallFlag(tr), + transRiseFallFlag(rf), minMaxFlag(min_max)); Pin *ref_pin = port_delay->refPin(); if (ref_pin) { @@ -1352,9 +1352,9 @@ WriteSdc::writeExceptionFrom(ExceptionFrom *from) const void WriteSdc::writeExceptionTo(ExceptionTo *to) const { - const TransRiseFallBoth *end_tr = to->endTransition(); - if (end_tr != TransRiseFallBoth::riseFall()) - fprintf(stream_, "%s ", transRiseFallFlag(end_tr)); + const RiseFallBoth *end_rf = to->endTransition(); + if (end_rf != RiseFallBoth::riseFall()) + fprintf(stream_, "%s ", transRiseFallFlag(end_rf)); if (to->hasObjects()) writeExceptionFromTo(to, "to", false); } @@ -1364,11 +1364,11 @@ WriteSdc::writeExceptionFromTo(ExceptionFromTo *from_to, const char *from_to_key, bool map_hpin_to_drvr) const { - const TransRiseFallBoth *tr = from_to->transition(); + const RiseFallBoth *rf = from_to->transition(); const char *tr_prefix = "-"; - if (tr == TransRiseFallBoth::rise()) + if (rf == RiseFallBoth::rise()) tr_prefix = "-rise_"; - else if (tr == TransRiseFallBoth::fall()) + else if (rf == RiseFallBoth::fall()) tr_prefix = "-fall_"; fprintf(stream_, "\\\n %s%s ", tr_prefix, from_to_key); bool multi_objs = @@ -1411,11 +1411,11 @@ WriteSdc::writeExceptionFromTo(ExceptionFromTo *from_to, void WriteSdc::writeExceptionThru(ExceptionThru *thru) const { - const TransRiseFallBoth *tr = thru->transition(); + const RiseFallBoth *rf = thru->transition(); const char *tr_prefix = "-"; - if (tr == TransRiseFallBoth::rise()) + if (rf == RiseFallBoth::rise()) tr_prefix = "-rise_"; - else if (tr == TransRiseFallBoth::fall()) + else if (rf == RiseFallBoth::fall()) tr_prefix = "-fall_"; fprintf(stream_, "\\\n %sthrough ", tr_prefix); PinSeq pins; @@ -1524,17 +1524,17 @@ WriteSdc::writeDataCheck(DataCheck *check) const bool one_value; check->marginIsOneValue(setup_hold, margin, one_value); if (one_value) - writeDataCheck(check, TransRiseFallBoth::riseFall(), - TransRiseFallBoth::riseFall(), setup_hold, margin); + writeDataCheck(check, RiseFallBoth::riseFall(), + RiseFallBoth::riseFall(), setup_hold, margin); else { - for (auto from_tr : TransRiseFall::range()) { - for (auto to_tr : TransRiseFall::range()) { + for (auto from_rf : RiseFall::range()) { + for (auto to_rf : RiseFall::range()) { float margin; bool margin_exists; - check->margin(from_tr, to_tr, setup_hold, margin, margin_exists); + check->margin(from_rf, to_rf, setup_hold, margin, margin_exists); if (margin_exists) { - writeDataCheck(check, from_tr->asRiseFallBoth(), - to_tr->asRiseFallBoth(), setup_hold, margin); + writeDataCheck(check, from_rf->asRiseFallBoth(), + to_rf->asRiseFallBoth(), setup_hold, margin); } } } @@ -1544,22 +1544,22 @@ WriteSdc::writeDataCheck(DataCheck *check) const void WriteSdc::writeDataCheck(DataCheck *check, - TransRiseFallBoth *from_tr, - TransRiseFallBoth *to_tr, + RiseFallBoth *from_rf, + RiseFallBoth *to_rf, SetupHold *setup_hold, float margin) const { const char *from_key = "-from"; - if (from_tr == TransRiseFallBoth::rise()) + if (from_rf == RiseFallBoth::rise()) from_key = "-rise_from"; - else if (from_tr == TransRiseFallBoth::fall()) + else if (from_rf == RiseFallBoth::fall()) from_key = "-fall_from"; fprintf(stream_, "set_data_check %s ", from_key); writeGetPin(check->from(), true); const char *to_key = "-to"; - if (to_tr == TransRiseFallBoth::rise()) + if (to_rf == RiseFallBoth::rise()) to_key = "-rise_to"; - else if (to_tr == TransRiseFallBoth::fall()) + else if (to_rf == RiseFallBoth::fall()) to_key = "-fall_to"; fprintf(stream_, " %s ", to_key); writeGetPin(check->to(), false); @@ -1640,7 +1640,7 @@ WriteSdc::writeDriveResistances() const Port *port = port_iter->next(); InputDrive *drive = sdc_->findInputDrive(port); if (drive) { - for (auto tr : TransRiseFall::range()) { + for (auto tr : RiseFall::range()) { if (drive->driveResistanceMinMaxEqual(tr)) { float res; bool exists; @@ -1682,13 +1682,13 @@ WriteSdc::writeDrivingCells() const Port *port = port_iter->next(); InputDrive *drive = sdc_->findInputDrive(port); if (drive) { - InputDriveCell *drive_rise_min = drive->driveCell(TransRiseFall::rise(), + InputDriveCell *drive_rise_min = drive->driveCell(RiseFall::rise(), MinMax::min()); - InputDriveCell *drive_rise_max = drive->driveCell(TransRiseFall::rise(), + InputDriveCell *drive_rise_max = drive->driveCell(RiseFall::rise(), MinMax::max()); - InputDriveCell *drive_fall_min = drive->driveCell(TransRiseFall::fall(), + InputDriveCell *drive_fall_min = drive->driveCell(RiseFall::fall(), MinMax::min()); - InputDriveCell *drive_fall_max = drive->driveCell(TransRiseFall::fall(), + InputDriveCell *drive_fall_max = drive->driveCell(RiseFall::fall(), MinMax::max()); if (drive_rise_min && drive_rise_max @@ -1703,25 +1703,25 @@ WriteSdc::writeDrivingCells() const if (drive_rise_min && drive_rise_max && drive_rise_min->equal(drive_rise_max)) - writeDrivingCell(port, drive_rise_min, TransRiseFall::rise(), nullptr); + writeDrivingCell(port, drive_rise_min, RiseFall::rise(), nullptr); else { if (drive_rise_min) - writeDrivingCell(port, drive_rise_min, TransRiseFall::rise(), + writeDrivingCell(port, drive_rise_min, RiseFall::rise(), MinMax::min()); if (drive_rise_max) - writeDrivingCell(port, drive_rise_max, TransRiseFall::rise(), + writeDrivingCell(port, drive_rise_max, RiseFall::rise(), MinMax::max()); } if (drive_fall_min && drive_fall_max && drive_fall_min->equal(drive_fall_max)) - writeDrivingCell(port, drive_fall_min, TransRiseFall::fall(), nullptr); + writeDrivingCell(port, drive_fall_min, RiseFall::fall(), nullptr); else { if (drive_fall_min) - writeDrivingCell(port, drive_fall_min, TransRiseFall::fall(), + writeDrivingCell(port, drive_fall_min, RiseFall::fall(), MinMax::min()); if (drive_fall_max) - writeDrivingCell(port, drive_fall_max, TransRiseFall::fall(), + writeDrivingCell(port, drive_fall_max, RiseFall::fall(), MinMax::max()); } } @@ -1733,7 +1733,7 @@ WriteSdc::writeDrivingCells() const void WriteSdc::writeDrivingCell(Port *port, InputDriveCell *drive_cell, - const TransRiseFall *tr, + const RiseFall *rf, const MinMax *min_max) const { LibertyCell *cell = drive_cell->cell(); @@ -1742,8 +1742,8 @@ WriteSdc::writeDrivingCell(Port *port, float *from_slews = drive_cell->fromSlews(); LibertyLibrary *lib = drive_cell->library(); fprintf(stream_, "set_driving_cell"); - if (tr) - fprintf(stream_, " %s", transRiseFallFlag(tr)); + if (rf) + fprintf(stream_, " %s", transRiseFallFlag(rf)); if (min_max) fprintf(stream_, " %s", minMaxFlag(min_max)); // Only write -library if it was specified in the sdc. @@ -1756,9 +1756,9 @@ WriteSdc::writeDrivingCell(Port *port, fprintf(stream_, " -pin {%s} -input_transition_rise ", to_port->name()); - writeTime(from_slews[TransRiseFall::riseIndex()]); + writeTime(from_slews[RiseFall::riseIndex()]); fprintf(stream_, " -input_transition_fall "); - writeTime(from_slews[TransRiseFall::fallIndex()]); + writeTime(from_slews[RiseFall::fallIndex()]); fprintf(stream_, " "); writeGetPort(port); fprintf(stream_, "\n"); @@ -2059,7 +2059,7 @@ WriteSdc::writeDerating(DeratingFactors *factors, } } else { - for (auto tr : TransRiseFall::range()) { + for (auto tr : RiseFall::range()) { float factor; bool exists; factors->factor(clk_data, tr, early_late, factor, exists); @@ -2141,8 +2141,8 @@ WriteSdc::writeMinPulseWidths(RiseFallValues *min_widths, { bool hi_exists, low_exists; float hi, low; - min_widths->value(TransRiseFall::rise(), hi, hi_exists); - min_widths->value(TransRiseFall::fall(), low, low_exists); + min_widths->value(RiseFall::rise(), hi, hi_exists); + min_widths->value(RiseFall::fall(), low, low_exists); if (hi_exists && low_exists && hi == low) writeMinPulseWidth("", hi, write_obj); @@ -2270,13 +2270,13 @@ WriteSdc::writeClkSlewLimits() const Clock *clk = clk_iter.next(); float rise_clk_limit, fall_clk_limit, rise_data_limit, fall_data_limit; bool rise_clk_exists, fall_clk_exists, rise_data_exists, fall_data_exists; - clk->slewLimit(TransRiseFall::rise(), PathClkOrData::clk, min_max, + clk->slewLimit(RiseFall::rise(), PathClkOrData::clk, min_max, rise_clk_limit, rise_clk_exists); - clk->slewLimit(TransRiseFall::fall(), PathClkOrData::clk, min_max, + clk->slewLimit(RiseFall::fall(), PathClkOrData::clk, min_max, fall_clk_limit, fall_clk_exists); - clk->slewLimit(TransRiseFall::rise(), PathClkOrData::data, min_max, + clk->slewLimit(RiseFall::rise(), PathClkOrData::data, min_max, rise_data_limit, rise_data_exists); - clk->slewLimit(TransRiseFall::fall(), PathClkOrData::data, min_max, + clk->slewLimit(RiseFall::fall(), PathClkOrData::data, min_max, fall_data_limit, fall_data_exists); if (rise_clk_exists && fall_clk_exists && rise_data_exists && fall_data_exists @@ -2709,13 +2709,13 @@ WriteSdc::writeRiseFallMinMaxCmd(const char *sdc_cmd, { float fall_min, fall_max, rise_min, rise_max; bool fall_min_exists, fall_max_exists, rise_min_exists, rise_max_exists; - values->value(TransRiseFall::fall(), MinMax::min(), + values->value(RiseFall::fall(), MinMax::min(), fall_min, fall_min_exists); - values->value(TransRiseFall::fall(), MinMax::max(), + values->value(RiseFall::fall(), MinMax::max(), fall_max, fall_max_exists); - values->value(TransRiseFall::rise(), MinMax::min(), + values->value(RiseFall::rise(), MinMax::min(), rise_min, rise_min_exists); - values->value(TransRiseFall::rise(), MinMax::max(), + values->value(RiseFall::rise(), MinMax::max(), rise_max, rise_max_exists); if (fall_min_exists && fall_max_exists && rise_min_exists && rise_max_exists) { @@ -2724,46 +2724,46 @@ WriteSdc::writeRiseFallMinMaxCmd(const char *sdc_cmd, && fall_max == rise_min) { // rise/fall/min/max match. writeRiseFallMinMaxCmd(sdc_cmd, rise_min, scale, - TransRiseFallBoth::riseFall(), MinMaxAll::all(), + RiseFallBoth::riseFall(), MinMaxAll::all(), write_object); } else if (rise_min == fall_min && rise_max == fall_max) { // rise/fall match. writeRiseFallMinMaxCmd(sdc_cmd, rise_min, scale, - TransRiseFallBoth::riseFall(), MinMaxAll::min(), + RiseFallBoth::riseFall(), MinMaxAll::min(), write_object); writeRiseFallMinMaxCmd(sdc_cmd, rise_max, scale, - TransRiseFallBoth::riseFall(), MinMaxAll::max(), + RiseFallBoth::riseFall(), MinMaxAll::max(), write_object); } else if (rise_min == rise_max && fall_min == fall_max) { // min/max match. writeRiseFallMinMaxCmd(sdc_cmd, rise_min, scale, - TransRiseFallBoth::rise(), MinMaxAll::all(), + RiseFallBoth::rise(), MinMaxAll::all(), write_object); writeRiseFallMinMaxCmd(sdc_cmd, fall_min, scale, - TransRiseFallBoth::fall(), MinMaxAll::all(), + RiseFallBoth::fall(), MinMaxAll::all(), write_object); } } else { if (rise_min_exists) writeRiseFallMinMaxCmd(sdc_cmd, rise_min, scale, - TransRiseFallBoth::rise(), MinMaxAll::min(), + RiseFallBoth::rise(), MinMaxAll::min(), write_object); if (rise_max_exists) writeRiseFallMinMaxCmd(sdc_cmd, rise_max, scale, - TransRiseFallBoth::rise(), MinMaxAll::max(), + RiseFallBoth::rise(), MinMaxAll::max(), write_object); if (fall_min_exists) writeRiseFallMinMaxCmd(sdc_cmd, fall_min, scale, - TransRiseFallBoth::fall(), MinMaxAll::min(), + RiseFallBoth::fall(), MinMaxAll::min(), write_object); if (fall_max_exists) writeRiseFallMinMaxCmd(sdc_cmd, fall_max, scale, - TransRiseFallBoth::fall(), MinMaxAll::max(), + RiseFallBoth::fall(), MinMaxAll::max(), write_object); } } @@ -2772,13 +2772,13 @@ void WriteSdc::writeRiseFallMinMaxCmd(const char *sdc_cmd, float value, float scale, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, const MinMaxAll *min_max, WriteSdcObject &write_object) const { fprintf(stream_, "%s%s%s ", sdc_cmd, - transRiseFallFlag(tr), + transRiseFallFlag(rf), minMaxFlag(min_max)); writeFloat(value / scale); fprintf(stream_, " "); @@ -2951,19 +2951,19 @@ WriteSdc::writeIntSeq(IntSeq *ints) const //////////////////////////////////////////////////////////////// static const char * -transRiseFallFlag(const TransRiseFall *tr) +transRiseFallFlag(const RiseFall *rf) { - return (tr == TransRiseFall::rise()) ? "-rise" : "-fall"; + return (rf == RiseFall::rise()) ? "-rise" : "-fall"; } static const char * -transRiseFallFlag(const TransRiseFallBoth *tr) +transRiseFallFlag(const RiseFallBoth *rf) { - if (tr == TransRiseFallBoth::rise()) + if (rf == RiseFallBoth::rise()) return " -rise"; - else if (tr == TransRiseFallBoth::fall()) + else if (rf == RiseFallBoth::fall()) return " -fall"; - else if (tr == TransRiseFallBoth::riseFall()) + else if (rf == RiseFallBoth::riseFall()) return ""; else { internalError("unknown transition"); diff --git a/sdc/WriteSdcPvt.hh b/sdc/WriteSdcPvt.hh index b2c2a378..48e9432e 100644 --- a/sdc/WriteSdcPvt.hh +++ b/sdc/WriteSdcPvt.hh @@ -88,7 +88,7 @@ public: void writePortDelay(PortDelay *port_delay, bool is_input_delay, float delay, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, const MinMaxAll *min_max, const char *sdc_cmd) const; void writeClockSenses() const; @@ -111,8 +111,8 @@ public: void writeDataChecks() const; void writeDataCheck(DataCheck *check) const; void writeDataCheck(DataCheck *check, - TransRiseFallBoth *from_tr, - TransRiseFallBoth *to_tr, + RiseFallBoth *from_rf, + RiseFallBoth *to_rf, SetupHold *setup_hold, float margin) const; void writeEnvironment() const; @@ -126,7 +126,7 @@ public: void writeInputTransitions() const; void writeDrivingCell(Port *port, InputDriveCell *drive_cell, - const TransRiseFall *tr, + const RiseFall *rf, const MinMax *min_max) const; void writeConstants() const; virtual void writeConstant(Pin *pin) const; @@ -220,7 +220,7 @@ public: void writeRiseFallMinMaxCmd(const char *sdc_cmd, float value, float scale, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, const MinMaxAll *min_max, WriteSdcObject &write_object) const; void writeMinMaxFloatValuesCmd(const char *sdc_cmd, diff --git a/sdf/ReportAnnotation.cc b/sdf/ReportAnnotation.cc index a1d49080..92211e27 100644 --- a/sdf/ReportAnnotation.cc +++ b/sdf/ReportAnnotation.cc @@ -403,7 +403,7 @@ ReportAnnotated::findWidthPeriodCount(Pin *pin) int width_index = TimingRole::width()->index(); if (report_role_[width_index]) { - for (auto hi_low : TransRiseFall::range()) { + for (auto hi_low : RiseFall::range()) { port->minPulseWidth(hi_low, value, exists); if (exists) { edge_count_[width_index]++; @@ -557,7 +557,7 @@ ReportAnnotated::reportWidthPeriodArcs(Pin *pin, if (report_role_[width_index] && (max_lines_ == 0 || i < max_lines_)) { bool report = false; - for (auto hi_low : TransRiseFall::range()) { + for (auto hi_low : RiseFall::range()) { port->minPulseWidth(hi_low, value, exists); if (exists) { edge_count_[width_index]++; diff --git a/sdf/SdfReader.cc b/sdf/SdfReader.cc index b0fa545b..0800688b 100644 --- a/sdf/SdfReader.cc +++ b/sdf/SdfReader.cc @@ -581,19 +581,19 @@ SdfReader::timingCheckWidth(SdfPortSpec *edge, else { Pin *pin = network_->findPin(instance_, port_name); if (pin) { - const TransRiseFall *tr = edge->transition()->asRiseFall(); + const RiseFall *rf = edge->transition()->asRiseFall(); float **values = triple->values(); float *value_ptr = values[triple_min_index_]; if (value_ptr) { float value = *value_ptr; - graph_->setWidthCheckAnnotation(pin, tr, arc_delay_min_index_, + graph_->setWidthCheckAnnotation(pin, rf, arc_delay_min_index_, value); } if (triple_max_index_ != null_index_) { value_ptr = values[triple_max_index_]; if (value_ptr) { float value = *value_ptr; - graph_->setWidthCheckAnnotation(pin, tr, arc_delay_max_index_, + graph_->setWidthCheckAnnotation(pin, rf, arc_delay_max_index_, value); } } diff --git a/sdf/SdfWriter.cc b/sdf/SdfWriter.cc index 5618d72c..d3b0c1e7 100644 --- a/sdf/SdfWriter.cc +++ b/sdf/SdfWriter.cc @@ -81,12 +81,12 @@ protected: bool use_clk_edge); void writeEdgeCheck(Edge *edge, const char *sdf_check, - int clk_tr_index, - TimingArc *arcs[TransRiseFall::index_count][TransRiseFall::index_count]); + int clk_rf_index, + TimingArc *arcs[RiseFall::index_count][RiseFall::index_count]); void writeTimingCheckHeader(); void writeTimingCheckTrailer(); void writeWidthCheck(const Pin *pin, - const TransRiseFall *hi_low, + const RiseFall *hi_low, float min_width, float max_width); void writePeriodCheck(const Pin *pin, @@ -94,7 +94,7 @@ protected: const char *sdfEdge(const Transition *tr); void writeArcDelays(Edge *edge); void writeSdfTuple(RiseFallMinMax &delays, - TransRiseFall *tr); + RiseFall *rf); void writeSdfTuple(float min_delay, float max_delay); void writeSdfDelay(double delay); @@ -416,45 +416,45 @@ SdfWriter::writeArcDelays(Edge *edge) TimingArcSetArcIterator arc_iter(arc_set); while (arc_iter.hasNext()) { TimingArc *arc = arc_iter.next(); - TransRiseFall *tr = arc->toTrans()->asRiseFall(); + RiseFall *rf = arc->toTrans()->asRiseFall(); ArcDelay min_delay = graph_->arcDelay(edge, arc, arc_delay_min_index_); - delays.setValue(tr, MinMax::min(), delayAsFloat(min_delay)); + delays.setValue(rf, MinMax::min(), delayAsFloat(min_delay)); ArcDelay max_delay = graph_->arcDelay(edge, arc, arc_delay_max_index_); - delays.setValue(tr, MinMax::max(), delayAsFloat(max_delay)); + delays.setValue(rf, MinMax::max(), delayAsFloat(max_delay)); } - if (delays.hasValue(TransRiseFall::rise(), MinMax::min()) - && delays.hasValue(TransRiseFall::fall(), MinMax::min())) { + if (delays.hasValue(RiseFall::rise(), MinMax::min()) + && delays.hasValue(RiseFall::fall(), MinMax::min())) { // Rise and fall. - writeSdfTuple(delays, TransRiseFall::rise()); + writeSdfTuple(delays, RiseFall::rise()); // Merge rise/fall values if they are the same. - if (!(fuzzyEqual(delays.value(TransRiseFall::rise(), MinMax::min()), - delays.value(TransRiseFall::fall(), MinMax::min())) - && fuzzyEqual(delays.value(TransRiseFall::rise(), MinMax::max()), - delays.value(TransRiseFall::fall(),MinMax::max())))) { + if (!(fuzzyEqual(delays.value(RiseFall::rise(), MinMax::min()), + delays.value(RiseFall::fall(), MinMax::min())) + && fuzzyEqual(delays.value(RiseFall::rise(), MinMax::max()), + delays.value(RiseFall::fall(),MinMax::max())))) { gzprintf(stream_, " "); - writeSdfTuple(delays, TransRiseFall::fall()); + writeSdfTuple(delays, RiseFall::fall()); } } - else if (delays.hasValue(TransRiseFall::rise(), MinMax::min())) + else if (delays.hasValue(RiseFall::rise(), MinMax::min())) // Rise only. - writeSdfTuple(delays, TransRiseFall::rise()); - else if (delays.hasValue(TransRiseFall::fall(), MinMax::min())) { + writeSdfTuple(delays, RiseFall::rise()); + else if (delays.hasValue(RiseFall::fall(), MinMax::min())) { // Fall only. gzprintf(stream_, "() "); - writeSdfTuple(delays, TransRiseFall::fall()); + writeSdfTuple(delays, RiseFall::fall()); } } void SdfWriter::writeSdfTuple(RiseFallMinMax &delays, - TransRiseFall *tr) + RiseFall *rf) { gzprintf(stream_, "("); - writeSdfDelay(delays.value(tr, MinMax::min())); + writeSdfDelay(delays.value(rf, MinMax::min())); gzprintf(stream_, "::"); - writeSdfDelay(delays.value(tr, MinMax::max())); + writeSdfDelay(delays.value(rf, MinMax::max())); gzprintf(stream_, ")"); } @@ -503,7 +503,7 @@ SdfWriter::writeTimingChecks(const Instance *inst, writeCheck(edge, sdf_check); } } - for (auto hi_low : TransRiseFall::range()) { + for (auto hi_low : RiseFall::range()) { float min_width, max_width; bool exists; graph_delay_calc_->minPulseWidth(pin, hi_low, arc_delay_min_index_, @@ -564,22 +564,22 @@ SdfWriter::writeCheck(Edge *edge, { TimingArcSet *arc_set = edge->timingArcSet(); // Examine the arcs to see if the check requires clk or data edge specifiers. - TimingArc *arcs[TransRiseFall::index_count][TransRiseFall::index_count] = + TimingArc *arcs[RiseFall::index_count][RiseFall::index_count] = {{nullptr, nullptr}, {nullptr, nullptr}}; TimingArcSetArcIterator arc_iter(arc_set); while (arc_iter.hasNext()) { TimingArc *arc = arc_iter.next(); - TransRiseFall *clk_tr = arc->fromTrans()->asRiseFall(); - TransRiseFall *data_tr = arc->toTrans()->asRiseFall();; - arcs[clk_tr->index()][data_tr->index()] = arc; + RiseFall *clk_rf = arc->fromTrans()->asRiseFall(); + RiseFall *data_rf = arc->toTrans()->asRiseFall();; + arcs[clk_rf->index()][data_rf->index()] = arc; } - if (arcs[TransRiseFall::fallIndex()][TransRiseFall::riseIndex()] == nullptr - && arcs[TransRiseFall::fallIndex()][TransRiseFall::fallIndex()] == nullptr) - writeEdgeCheck(edge, sdf_check, TransRiseFall::riseIndex(), arcs); - else if (arcs[TransRiseFall::riseIndex()][TransRiseFall::riseIndex()] == nullptr - && arcs[TransRiseFall::riseIndex()][TransRiseFall::fallIndex()] == nullptr) - writeEdgeCheck(edge, sdf_check, TransRiseFall::fallIndex(), arcs); + if (arcs[RiseFall::fallIndex()][RiseFall::riseIndex()] == nullptr + && arcs[RiseFall::fallIndex()][RiseFall::fallIndex()] == nullptr) + writeEdgeCheck(edge, sdf_check, RiseFall::riseIndex(), arcs); + else if (arcs[RiseFall::riseIndex()][RiseFall::riseIndex()] == nullptr + && arcs[RiseFall::riseIndex()][RiseFall::fallIndex()] == nullptr) + writeEdgeCheck(edge, sdf_check, RiseFall::fallIndex(), arcs); else { // No special case; write all the checks with data and clock edge specifiers. TimingArcSetArcIterator arc_iter(arc_set); @@ -593,38 +593,38 @@ SdfWriter::writeCheck(Edge *edge, void SdfWriter::writeEdgeCheck(Edge *edge, const char *sdf_check, - int clk_tr_index, - TimingArc *arcs[TransRiseFall::index_count][TransRiseFall::index_count]) + int clk_rf_index, + TimingArc *arcs[RiseFall::index_count][RiseFall::index_count]) { // SDF requires edge specifiers on the data port to define separate // rise/fall check values. // Check the rise/fall margins to see if they are the same to avoid adding // data port edge specifiers if they aren't necessary. - if (arcs[clk_tr_index][TransRiseFall::riseIndex()] - && arcs[clk_tr_index][TransRiseFall::fallIndex()] - && arcs[clk_tr_index][TransRiseFall::riseIndex()] - && arcs[clk_tr_index][TransRiseFall::fallIndex()] + if (arcs[clk_rf_index][RiseFall::riseIndex()] + && arcs[clk_rf_index][RiseFall::fallIndex()] + && arcs[clk_rf_index][RiseFall::riseIndex()] + && arcs[clk_rf_index][RiseFall::fallIndex()] && fuzzyEqual(graph_->arcDelay(edge, - arcs[clk_tr_index][TransRiseFall::riseIndex()], + arcs[clk_rf_index][RiseFall::riseIndex()], arc_delay_min_index_), graph_->arcDelay(edge, - arcs[clk_tr_index][TransRiseFall::fallIndex()], + arcs[clk_rf_index][RiseFall::fallIndex()], arc_delay_min_index_)) && fuzzyEqual(graph_->arcDelay(edge, - arcs[clk_tr_index][TransRiseFall::riseIndex()], + arcs[clk_rf_index][RiseFall::riseIndex()], arc_delay_max_index_), graph_->arcDelay(edge, - arcs[clk_tr_index][TransRiseFall::fallIndex()], + arcs[clk_rf_index][RiseFall::fallIndex()], arc_delay_max_index_))) // Rise/fall margins are the same, so no data edge specifier is required. - writeCheck(edge, arcs[clk_tr_index][TransRiseFall::riseIndex()], + writeCheck(edge, arcs[clk_rf_index][RiseFall::riseIndex()], sdf_check, false, true); else { - if (arcs[clk_tr_index][TransRiseFall::riseIndex()]) - writeCheck(edge, arcs[clk_tr_index][TransRiseFall::riseIndex()], + if (arcs[clk_rf_index][RiseFall::riseIndex()]) + writeCheck(edge, arcs[clk_rf_index][RiseFall::riseIndex()], sdf_check, true, true); - if (arcs[clk_tr_index][TransRiseFall::fallIndex()]) - writeCheck(edge, arcs[clk_tr_index][TransRiseFall::fallIndex()], + if (arcs[clk_rf_index][RiseFall::fallIndex()]) + writeCheck(edge, arcs[clk_rf_index][RiseFall::fallIndex()], sdf_check, true, true); } } @@ -683,7 +683,7 @@ SdfWriter::writeCheck(Edge *edge, void SdfWriter::writeWidthCheck(const Pin *pin, - const TransRiseFall *hi_low, + const RiseFall *hi_low, float min_width, float max_width) { diff --git a/search/CheckMaxSkews.cc b/search/CheckMaxSkews.cc index dcd47490..74cfceb2 100644 --- a/search/CheckMaxSkews.cc +++ b/search/CheckMaxSkews.cc @@ -199,15 +199,15 @@ CheckMaxSkews:: visitMaxSkewChecks(Vertex *vertex, TimingArcSetArcIterator arc_iter(arc_set); while (arc_iter.hasNext()) { TimingArc *arc = arc_iter.next(); - TransRiseFall *clk_tr = arc->fromTrans()->asRiseFall(); - TransRiseFall *ref_tr = arc->toTrans()->asRiseFall(); - VertexPathIterator clk_path_iter(vertex, clk_tr, clk_min_max, search); + RiseFall *clk_rf = arc->fromTrans()->asRiseFall(); + RiseFall *ref_rf = arc->toTrans()->asRiseFall(); + VertexPathIterator clk_path_iter(vertex, clk_rf, clk_min_max, search); while (clk_path_iter.hasNext()) { PathVertex *clk_path = clk_path_iter.next(); if (clk_path->isClock(search)) { const PathAnalysisPt *clk_ap = clk_path->pathAnalysisPt(sta_); PathAnalysisPt *ref_ap = clk_ap->tgtClkAnalysisPt(); - VertexPathIterator ref_path_iter(ref_vertex, ref_tr, ref_ap, sta_); + VertexPathIterator ref_path_iter(ref_vertex, ref_rf, ref_ap, sta_); while (ref_path_iter.hasNext()) { PathVertex *ref_path = ref_path_iter.next(); if (ref_path->isClock(search)) { diff --git a/search/CheckMinPulseWidths.cc b/search/CheckMinPulseWidths.cc index 7eef8360..fc07e662 100644 --- a/search/CheckMinPulseWidths.cc +++ b/search/CheckMinPulseWidths.cc @@ -311,7 +311,7 @@ MinPulseWidthCheck::pin(const StaState *sta) const return open_path_.pin(sta); } -const TransRiseFall * +const RiseFall * MinPulseWidthCheck::openTransition(const StaState *sta) const { return open_path_.transition(sta); @@ -324,8 +324,8 @@ MinPulseWidthCheck::closePath(const StaState *sta, { PathAnalysisPt *open_ap = open_path_.pathAnalysisPt(sta); PathAnalysisPt *close_ap = open_ap->tgtClkAnalysisPt(); - const TransRiseFall *open_tr = open_path_.transition(sta); - const TransRiseFall *close_tr = open_tr->opposite(); + const RiseFall *open_rf = open_path_.transition(sta); + const RiseFall *close_rf = open_rf->opposite(); Tag *open_tag = open_path_.tag(sta); ClkInfo *open_clk_info = open_tag->clkInfo(); ClkInfo close_clk_info(open_clk_info->clkEdge()->opposite(), @@ -339,7 +339,7 @@ MinPulseWidthCheck::closePath(const StaState *sta, open_clk_info->crprClkPath(), sta); Tag close_tag(0, - close_tr->index(), + close_rf->index(), close_ap->index(), &close_clk_info, open_tag->isClock(), @@ -351,7 +351,7 @@ MinPulseWidthCheck::closePath(const StaState *sta, open_tag->asString(sta)); debugPrint1(sta->debug(), "mpw", 3, " close %s\n", close_tag.asString(sta)); - VertexPathIterator close_iter(open_path_.vertex(sta), close_tr, + VertexPathIterator close_iter(open_path_.vertex(sta), close_rf, close_ap, sta); while (close_iter.hasNext()) { PathVertex *close_path = close_iter.next(); @@ -445,16 +445,16 @@ minPulseWidth(const Path *path, { Pin *pin = path->pin(sta); Clock *clk = path->clock(sta); - const TransRiseFall *tr = path->transition(sta); + const RiseFall *rf = path->transition(sta); Sdc *sdc = sta->sdc(); // set_min_pulse_width command. - sdc->minPulseWidth(pin, clk, tr, min_width, exists); + sdc->minPulseWidth(pin, clk, rf, min_width, exists); if (!exists) { GraphDelayCalc *graph_dcalc = sta->graphDelayCalc(); const MinMax *min_max = path->minMax(sta); const PathAnalysisPt *path_ap = path->pathAnalysisPt(sta); const DcalcAnalysisPt *dcalc_ap = path_ap->dcalcAnalysisPt(); - graph_dcalc->minPulseWidth(pin, tr, dcalc_ap->index(), min_max, + graph_dcalc->minPulseWidth(pin, rf, dcalc_ap->index(), min_max, min_width, exists); } } @@ -503,8 +503,8 @@ MinPulseWidthSlackLess::operator()(const MinPulseWidthCheck *check1, // Break ties for the sake of regression stability. && (sta_->network()->pinLess(pin1, pin2) || (pin1 == pin2 - && check1->openPath()->trIndex(sta_) - < check2->openPath()->trIndex(sta_)))); + && check1->openPath()->rfIndex(sta_) + < check2->openPath()->rfIndex(sta_)))); } } // namespace diff --git a/search/CheckMinPulseWidths.hh b/search/CheckMinPulseWidths.hh index dcae4af4..c7b948a0 100644 --- a/search/CheckMinPulseWidths.hh +++ b/search/CheckMinPulseWidths.hh @@ -25,7 +25,7 @@ namespace sta { -class TransRiseFall; +class RiseFall; class MinPulseWidthCheck; class MinPulseWidthCheckVisitor; @@ -68,7 +68,7 @@ public: MinPulseWidthCheck(Path *open_path); MinPulseWidthCheck *copy(); Pin *pin(const StaState *sta) const; - const TransRiseFall *openTransition(const StaState *sta) const; + const RiseFall *openTransition(const StaState *sta) const; Arrival width(const StaState *sta) const; float minWidth(const StaState *sta) const; Slack slack(const StaState *sta) const; diff --git a/search/CheckSlewLimits.cc b/search/CheckSlewLimits.cc index 34d4ce12..d3058478 100644 --- a/search/CheckSlewLimits.cc +++ b/search/CheckSlewLimits.cc @@ -63,13 +63,13 @@ PinSlewLimitSlackLess::operator()(Pin *pin1, Pin *pin2) const { const Corner *corner1, *corner2; - const TransRiseFall *tr1, *tr2; + const RiseFall *rf1, *rf2; Slew slew1, slew2; float limit1, limit2, slack1, slack2; check_slew_limit_->checkSlews(pin1, corner_, min_max_, - corner1, tr1, slew1, limit1, slack1); + corner1, rf1, slew1, limit1, slack1); check_slew_limit_->checkSlews(pin2, corner_, min_max_, - corner2, tr2, slew2, limit2, slack2); + corner2, rf2, slew2, limit2, slack2); return slack1 < slack2 || (fuzzyEqual(slack1, slack2) // Break ties for the sake of regression stability. @@ -102,23 +102,23 @@ CheckSlewLimits::checkSlews(const Pin *pin, const MinMax *min_max, // Return values. const Corner *&corner1, - const TransRiseFall *&tr, + const RiseFall *&rf, Slew &slew, float &limit, float &slack) const { corner1 = nullptr; - tr = nullptr; + rf = nullptr; slew = 0.0; limit = 0.0; slack = MinMax::min()->initValue(); if (corner) checkSlews1(pin, corner, min_max, - corner1, tr, slew, limit, slack); + corner1, rf, slew, limit, slack); else { for (auto corner : *sta_->corners()) { checkSlews1(pin, corner, min_max, - corner1, tr, slew, limit, slack); + corner1, rf, slew, limit, slack); } } } @@ -129,7 +129,7 @@ CheckSlewLimits::checkSlews1(const Pin *pin, const MinMax *min_max, // Return values. const Corner *&corner1, - const TransRiseFall *&tr, + const RiseFall *&rf, Slew &slew, float &limit, float &slack) const @@ -137,10 +137,10 @@ CheckSlewLimits::checkSlews1(const Pin *pin, Vertex *vertex, *bidirect_drvr_vertex; sta_->graph()->pinVertices(pin, vertex, bidirect_drvr_vertex); checkSlews1(vertex, corner, min_max, - corner1, tr, slew, limit, slack); + corner1, rf, slew, limit, slack); if (bidirect_drvr_vertex) checkSlews1(bidirect_drvr_vertex, corner, min_max, - corner1, tr, slew, limit, slack); + corner1, rf, slew, limit, slack); } void @@ -149,18 +149,18 @@ CheckSlewLimits::checkSlews1(Vertex *vertex, const MinMax *min_max, // Return values. const Corner *&corner, - const TransRiseFall *&tr, + const RiseFall *&rf, Slew &slew, float &limit, float &slack) const { - for (auto tr1 : TransRiseFall::range()) { + for (auto rf1 : RiseFall::range()) { float limit1; bool limit1_exists; - findLimit(vertex->pin(), vertex, tr1, min_max, limit1, limit1_exists); + findLimit(vertex->pin(), vertex, rf1, min_max, limit1, limit1_exists); if (limit1_exists) { - checkSlew(vertex, corner1, min_max, tr1, limit1, - corner, tr, slew, slack, limit); + checkSlew(vertex, corner1, min_max, rf1, limit1, + corner, rf, slew, slack, limit); } } } @@ -168,7 +168,7 @@ CheckSlewLimits::checkSlews1(Vertex *vertex, void CheckSlewLimits::findLimit(const Pin *pin, const Vertex *vertex, - const TransRiseFall *tr, + const RiseFall *rf, const MinMax *min_max, // Return values. float &limit, @@ -188,7 +188,7 @@ CheckSlewLimits::findLimit(const Pin *pin, PathClkOrData clk_data = is_clk ? PathClkOrData::clk : PathClkOrData::data; float clk_limit; bool clk_limit_exists; - sdc->slewLimit(clk, tr, clk_data, min_max, + sdc->slewLimit(clk, rf, clk_data, min_max, clk_limit, clk_limit_exists); if (clk_limit_exists && (!exists @@ -263,17 +263,17 @@ void CheckSlewLimits::checkSlew(Vertex *vertex, const Corner *corner1, const MinMax *min_max, - const TransRiseFall *tr1, + const RiseFall *rf1, float limit1, // Return values. const Corner *&corner, - const TransRiseFall *&tr, + const RiseFall *&rf, Slew &slew, float &slack, float &limit) const { const DcalcAnalysisPt *dcalc_ap = corner1->findDcalcAnalysisPt(min_max); - Slew slew1 = sta_->graph()->slew(vertex, tr1, dcalc_ap->index()); + Slew slew1 = sta_->graph()->slew(vertex, rf1, dcalc_ap->index()); float slew2 = delayAsFloat(slew1); float slack1 = (min_max == MinMax::max()) ? limit1 - slew2 : slew2 - limit1; @@ -281,9 +281,9 @@ CheckSlewLimits::checkSlew(Vertex *vertex, || (slack1 < slack // Break ties for the sake of regression stability. || (fuzzyEqual(slack1, slack) - && tr1->index() < tr->index()))) { + && rf1->index() < rf->index()))) { corner = corner1; - tr = tr1; + rf = rf1; slew = slew1; slack = slack1; limit = limit1; @@ -320,11 +320,11 @@ CheckSlewLimits::pinSlewLimitViolations(Instance *inst, while (pin_iter->hasNext()) { Pin *pin = pin_iter->next(); const Corner *corner1; - const TransRiseFall *tr; + const RiseFall *rf; Slew slew; float limit, slack; - checkSlews(pin, corner, min_max, corner1, tr, slew, limit, slack ); - if (tr && slack < 0.0) + checkSlews(pin, corner, min_max, corner1, rf, slew, limit, slack ); + if (rf && slack < 0.0) violators->push_back(pin); } delete pin_iter; @@ -363,11 +363,11 @@ CheckSlewLimits::pinMinSlewLimitSlack(Instance *inst, while (pin_iter->hasNext()) { Pin *pin = pin_iter->next(); const Corner *corner1; - const TransRiseFall *tr; + const RiseFall *rf; Slew slew; float limit, slack; - checkSlews(pin, corner, min_max, corner1, tr, slew, limit, slack); - if (tr + checkSlews(pin, corner, min_max, corner1, rf, slew, limit, slack); + if (rf && (min_slack_pin == 0 || slack < min_slack)) { min_slack_pin = pin; diff --git a/search/CheckSlewLimits.hh b/search/CheckSlewLimits.hh index 3bb4b2a0..caecc7ab 100644 --- a/search/CheckSlewLimits.hh +++ b/search/CheckSlewLimits.hh @@ -41,7 +41,7 @@ public: // Return values. // Corner is nullptr for no slew limit. const Corner *&corner1, - const TransRiseFall *&tr, + const RiseFall *&rf, Slew &slew, float &limit, float &slack) const; @@ -58,7 +58,7 @@ protected: const MinMax *min_max, // Return values. const Corner *&corner1, - const TransRiseFall *&tr, + const RiseFall *&rf, Slew &slew, float &limit, float &slack) const; @@ -67,24 +67,24 @@ protected: const MinMax *min_max, // Return values. const Corner *&corner, - const TransRiseFall *&tr, + const RiseFall *&rf, Slew &slew, float &limit, float &slack) const; void checkSlew(Vertex *vertex, const Corner *corner1, const MinMax *min_max, - const TransRiseFall *tr1, + const RiseFall *rf1, float limit1, // Return values. const Corner *&corner, - const TransRiseFall *&tr, + const RiseFall *&rf, Slew &slew, float &slack, float &limit) const; void findLimit(const Pin *pin, const Vertex *vertex, - const TransRiseFall *tr, + const RiseFall *rf, const MinMax *min_max, // Return values. float &limit1, diff --git a/search/ClkInfo.cc b/search/ClkInfo.cc index 968727a9..f44245d9 100644 --- a/search/ClkInfo.cc +++ b/search/ClkInfo.cc @@ -40,7 +40,7 @@ ClkInfo::ClkInfo(ClockEdge *clk_edge, bool is_propagated, const Pin *gen_clk_src, bool is_gen_clk_src_path, - const TransRiseFall *pulse_clk_sense, + const RiseFall *pulse_clk_sense, Arrival insertion, float latency, ClockUncertainties *uncertainties, @@ -152,11 +152,11 @@ ClkInfo::clock() const return nullptr; } -TransRiseFall * +RiseFall * ClkInfo::pulseClkSense() const { if (is_pulse_clk_) - return TransRiseFall::find(pulse_clk_sense_); + return RiseFall::find(pulse_clk_sense_); else return nullptr; } diff --git a/search/ClkInfo.hh b/search/ClkInfo.hh index 9b36b3d9..c35a55ef 100644 --- a/search/ClkInfo.hh +++ b/search/ClkInfo.hh @@ -34,7 +34,7 @@ public: bool is_propagated, const Pin *gen_clk_src, bool is_gen_clk_src_path, - const TransRiseFall *pulse_clk_sense, + const RiseFall *pulse_clk_sense, Arrival insertion, float latency, ClockUncertainties *uncertainties, @@ -49,7 +49,7 @@ public: bool isPropagated() const { return is_propagated_; } const Pin *genClkSrc() const { return gen_clk_src_; } bool isPulseClk() const { return is_pulse_clk_; } - TransRiseFall *pulseClkSense() const; + RiseFall *pulseClkSense() const; int pulseClkSenseTrIndex() const { return pulse_clk_sense_; } float latency() const { return latency_; } Arrival &insertion() { return insertion_; } @@ -87,7 +87,7 @@ private: unsigned int is_propagated_:1; unsigned int is_gen_clk_src_path_:1; unsigned int is_pulse_clk_:1; - unsigned int pulse_clk_sense_:TransRiseFall::index_bit_count; + unsigned int pulse_clk_sense_:RiseFall::index_bit_count; unsigned int path_ap_index_:path_ap_index_bit_count; }; diff --git a/search/ClkSkew.cc b/search/ClkSkew.cc index a98c9e48..2438cbac 100644 --- a/search/ClkSkew.cc +++ b/search/ClkSkew.cc @@ -181,11 +181,11 @@ ClkSkews::findClkSkew(ClockSet *clks, Edge *edge = edge_iter.next(); if (edge->role()->genericRole() == TimingRole::regClkToQ()) { Vertex *q_vertex = edge->to(graph_); - TransRiseFall *tr = edge->timingArcSet()->isRisingFallingEdge(); - TransRiseFallBoth *src_tr = tr - ? tr->asRiseFallBoth() - : TransRiseFallBoth::riseFall(); - findClkSkewFrom(src_vertex, q_vertex, src_tr, clks, + RiseFall *rf = edge->timingArcSet()->isRisingFallingEdge(); + RiseFallBoth *src_rf = rf + ? rf->asRiseFallBoth() + : RiseFallBoth::riseFall(); + findClkSkewFrom(src_vertex, q_vertex, src_rf, clks, corner, setup_hold, skews); } } @@ -210,7 +210,7 @@ ClkSkews::hasClkPaths(Vertex *vertex, void ClkSkews::findClkSkewFrom(Vertex *src_vertex, Vertex *q_vertex, - TransRiseFallBoth *src_tr, + RiseFallBoth *src_rf, ClockSet *clks, const Corner *corner, const SetupHold *setup_hold, @@ -231,11 +231,11 @@ ClkSkews::findClkSkewFrom(Vertex *src_vertex, || ((setup_hold == SetupHold::min() && role->genericRole() == TimingRole::hold())))) { Vertex *tgt_vertex = edge->from(graph_); - TransRiseFall *tgt_tr1 = edge->timingArcSet()->isRisingFallingEdge(); - TransRiseFallBoth *tgt_tr = tgt_tr1 - ? tgt_tr1->asRiseFallBoth() - : TransRiseFallBoth::riseFall(); - findClkSkew(src_vertex, src_tr, tgt_vertex, tgt_tr, + RiseFall *tgt_rf1 = edge->timingArcSet()->isRisingFallingEdge(); + RiseFallBoth *tgt_rf = tgt_rf1 + ? tgt_rf1->asRiseFallBoth() + : RiseFallBoth::riseFall(); + findClkSkew(src_vertex, src_rf, tgt_vertex, tgt_rf, clks, corner, setup_hold, skews); } } @@ -244,9 +244,9 @@ ClkSkews::findClkSkewFrom(Vertex *src_vertex, void ClkSkews::findClkSkew(Vertex *src_vertex, - TransRiseFallBoth *src_tr, + RiseFallBoth *src_rf, Vertex *tgt_vertex, - TransRiseFallBoth *tgt_tr, + RiseFallBoth *tgt_rf, ClockSet *clks, const Corner *corner, const SetupHold *setup_hold, @@ -258,7 +258,7 @@ ClkSkews::findClkSkew(Vertex *src_vertex, while (src_iter.hasNext()) { PathVertex *src_path = src_iter.next(); Clock *src_clk = src_path->clock(this); - if (src_tr->matches(src_path->transition(this)) + if (src_rf->matches(src_path->transition(this)) && src_path->minMax(this) == setup_hold && clks->hasKey(src_clk)) { Corner *src_corner = src_path->pathAnalysisPt(this)->corner(); @@ -269,7 +269,7 @@ ClkSkews::findClkSkew(Vertex *src_vertex, PathVertex *tgt_path = tgt_iter.next(); Clock *tgt_clk = tgt_path->clock(this); if (tgt_clk == src_clk - && tgt_tr->matches(tgt_path->transition(this)) + && tgt_rf->matches(tgt_path->transition(this)) && tgt_path->minMax(this) == tgt_min_max && tgt_path->pathAnalysisPt(this)->corner() == src_corner) { ClkSkew probe(src_path, tgt_path, this); diff --git a/search/ClkSkew.hh b/search/ClkSkew.hh index 66c57049..4a7aed39 100644 --- a/search/ClkSkew.hh +++ b/search/ClkSkew.hh @@ -46,15 +46,15 @@ protected: ClockSet *clks); void findClkSkewFrom(Vertex *src_vertex, Vertex *q_vertex, - TransRiseFallBoth *src_tr, + RiseFallBoth *src_rf, ClockSet *clks, const Corner *corner, const SetupHold *setup_hold, ClkSkewMap &skews); void findClkSkew(Vertex *src_vertex, - TransRiseFallBoth *src_tr, + RiseFallBoth *src_rf, Vertex *tgt_vertex, - TransRiseFallBoth *tgt_tr, + RiseFallBoth *tgt_rf, ClockSet *clks, const Corner *corner, const SetupHold *setup_hold, diff --git a/search/FindRegister.cc b/search/FindRegister.cc index c5ad4db0..b6e1a0e5 100644 --- a/search/FindRegister.cc +++ b/search/FindRegister.cc @@ -85,7 +85,7 @@ public: FindRegVisitor(StaState *sta); virtual ~FindRegVisitor() {} void visitRegs(ClockSet *clks, - const TransRiseFallBoth *clk_tr, + const RiseFallBoth *clk_rf, bool edge_triggered, bool latches); @@ -93,7 +93,7 @@ private: DISALLOW_COPY_AND_ASSIGN(FindRegVisitor); void visitRegs(const Pin *clk_pin, TimingSense clk_sense, - const TransRiseFallBoth *clk_tr, + const RiseFallBoth *clk_rf, bool edge_triggered, bool latches); virtual void visitReg(Instance *inst) = 0; @@ -101,7 +101,7 @@ private: Sequential *seq) = 0; void visitFanoutRegs(Vertex *from_vertex, TimingSense from_sense, - const TransRiseFallBoth *clk_tr, + const RiseFallBoth *clk_rf, bool edge_triggered, bool latches, SearchPred &clk_pred, @@ -110,14 +110,14 @@ private: Instance *inst, LibertyCell *cell, TimingSense clk_sense, - const TransRiseFallBoth *clk_tr, + const RiseFallBoth *clk_rf, bool edge_triggered, bool latches, bool &has_seqs, bool &matches); bool findInferedSequential(LibertyCell *cell, TimingSense clk_sense, - const TransRiseFallBoth *clk_tr, + const RiseFallBoth *clk_rf, bool edge_triggered, bool latches); bool hasTimingCheck(LibertyCell *cell, @@ -133,7 +133,7 @@ FindRegVisitor::FindRegVisitor(StaState *sta) : void FindRegVisitor::visitRegs(ClockSet *clks, - const TransRiseFallBoth *clk_tr, + const RiseFallBoth *clk_rf, bool edge_triggered, bool latches) { @@ -148,14 +148,14 @@ FindRegVisitor::visitRegs(ClockSet *clks, Vertex *vertex, *bidirect_drvr_vertex; graph_->pinVertices(pin, vertex, bidirect_drvr_vertex); visitFanoutRegs(vertex, TimingSense::positive_unate, - clk_tr, edge_triggered, + clk_rf, edge_triggered, latches, clk_pred, visited_vertices); // Clocks defined on bidirect pins blow it out both ends. if (bidirect_drvr_vertex) visitFanoutRegs(bidirect_drvr_vertex, TimingSense::positive_unate, - clk_tr, edge_triggered, + clk_rf, edge_triggered, latches, clk_pred, visited_vertices); } @@ -166,7 +166,7 @@ FindRegVisitor::visitRegs(ClockSet *clks, while (reg_clk_iter.hasNext()) { Vertex *vertex = reg_clk_iter.next(); visitRegs(vertex->pin(), TimingSense::positive_unate, - TransRiseFallBoth::riseFall(), + RiseFallBoth::riseFall(), edge_triggered, latches); } } @@ -175,7 +175,7 @@ FindRegVisitor::visitRegs(ClockSet *clks, void FindRegVisitor::visitFanoutRegs(Vertex *from_vertex, TimingSense from_sense, - const TransRiseFallBoth *clk_tr, + const RiseFallBoth *clk_rf, bool edge_triggered, bool latches, SearchPred &clk_pred, @@ -191,11 +191,11 @@ FindRegVisitor::visitFanoutRegs(Vertex *from_vertex, const Pin *to_pin = to_vertex->pin(); TimingSense to_sense = pathSenseThru(from_sense, edge->sense()); if (to_vertex->isRegClk()) - visitRegs(to_pin, to_sense, clk_tr, edge_triggered, latches); + visitRegs(to_pin, to_sense, clk_rf, edge_triggered, latches); // Even register clock pins can have combinational fanout arcs. if (clk_pred.searchThru(edge) && clk_pred.searchTo(to_vertex)) - visitFanoutRegs(to_vertex, to_sense, clk_tr, edge_triggered, latches, + visitFanoutRegs(to_vertex, to_sense, clk_rf, edge_triggered, latches, clk_pred, visited_vertices); } } @@ -204,20 +204,20 @@ FindRegVisitor::visitFanoutRegs(Vertex *from_vertex, void FindRegVisitor::visitRegs(const Pin *clk_pin, TimingSense clk_sense, - const TransRiseFallBoth *clk_tr, + const RiseFallBoth *clk_rf, bool edge_triggered, bool latches) { Instance *inst = network_->instance(clk_pin); LibertyCell *cell = network_->libertyCell(inst); if (!edge_triggered || !latches - || clk_tr != TransRiseFallBoth::riseFall()) { + || clk_rf != RiseFallBoth::riseFall()) { bool matches, has_seqs; - findSequential(clk_pin, inst, cell, clk_sense, clk_tr, + findSequential(clk_pin, inst, cell, clk_sense, clk_rf, edge_triggered, latches, has_seqs, matches); if (!has_seqs) - matches = findInferedSequential(cell, clk_sense, clk_tr, + matches = findInferedSequential(cell, clk_sense, clk_rf, edge_triggered, latches); if (matches) visitReg(inst); @@ -233,7 +233,7 @@ FindRegVisitor::findSequential(const Pin *clk_pin, Instance *inst, LibertyCell *cell, TimingSense clk_sense, - const TransRiseFallBoth *clk_tr, + const RiseFallBoth *clk_rf, bool edge_triggered, bool latches, bool &has_seqs, @@ -247,7 +247,7 @@ FindRegVisitor::findSequential(const Pin *clk_pin, Sequential *seq = seq_iter.next(); if ((seq->isRegister() && edge_triggered) || (seq->isLatch() && latches)) { - if (clk_tr == TransRiseFallBoth::riseFall()) { + if (clk_rf == RiseFallBoth::riseFall()) { visitSequential(inst, seq); matches = true; break; @@ -258,9 +258,9 @@ FindRegVisitor::findSequential(const Pin *clk_pin, TimingSense port_sense = clk_func->portTimingSense(port); TimingSense path_sense = pathSenseThru(clk_sense, port_sense); if ((path_sense == TimingSense::positive_unate - && clk_tr == TransRiseFallBoth::rise()) + && clk_rf == RiseFallBoth::rise()) || (path_sense == TimingSense::negative_unate - && clk_tr == TransRiseFallBoth::fall())) { + && clk_rf == RiseFallBoth::fall())) { visitSequential(inst, seq); matches = true; break; @@ -273,22 +273,22 @@ FindRegVisitor::findSequential(const Pin *clk_pin, bool FindRegVisitor::findInferedSequential(LibertyCell *cell, TimingSense clk_sense, - const TransRiseFallBoth *clk_tr, + const RiseFallBoth *clk_rf, bool edge_triggered, bool latches) { bool matches = false; - const TransRiseFall *clk_tr1 = clk_tr->asRiseFall(); + const RiseFall *clk_rf1 = clk_rf->asRiseFall(); LibertyCellTimingArcSetIterator set_iter(cell); while (set_iter.hasNext()) { TimingArcSet *set = set_iter.next(); TimingArcSetArcIterator arc_iter(set); TimingArc *arc = arc_iter.next(); - TransRiseFall *arc_clk_tr = arc->fromTrans()->asRiseFall(); - bool tr_matches = (clk_tr == TransRiseFallBoth::riseFall() - || (arc_clk_tr == clk_tr1 + RiseFall *arc_clk_rf = arc->fromTrans()->asRiseFall(); + bool tr_matches = (clk_rf == RiseFallBoth::riseFall() + || (arc_clk_rf == clk_rf1 && clk_sense == TimingSense::positive_unate) - || (arc_clk_tr == clk_tr1->opposite() + || (arc_clk_rf == clk_rf1->opposite() && clk_sense == TimingSense::negative_unate)); TimingRole *role = set->role(); if (tr_matches @@ -323,7 +323,7 @@ class FindRegInstances : public FindRegVisitor public: explicit FindRegInstances(StaState *sta); InstanceSet *findRegs(ClockSet *clks, - const TransRiseFallBoth *clk_tr, + const RiseFallBoth *clk_rf, bool edge_triggered, bool latches); @@ -344,12 +344,12 @@ FindRegInstances::FindRegInstances(StaState *sta) : InstanceSet * FindRegInstances::findRegs(ClockSet *clks, - const TransRiseFallBoth *clk_tr, + const RiseFallBoth *clk_rf, bool edge_triggered, bool latches) { regs_ = new InstanceSet; - visitRegs(clks, clk_tr, edge_triggered, latches); + visitRegs(clks, clk_rf, edge_triggered, latches); return regs_; } @@ -367,13 +367,13 @@ FindRegInstances::visitReg(Instance *inst) InstanceSet * findRegInstances(ClockSet *clks, - const TransRiseFallBoth *clk_tr, + const RiseFallBoth *clk_rf, bool edge_triggered, bool latches, StaState *sta) { FindRegInstances find_regs(sta); - return find_regs.findRegs(clks, clk_tr, edge_triggered, latches); + return find_regs.findRegs(clks, clk_rf, edge_triggered, latches); } //////////////////////////////////////////////////////////////// @@ -383,7 +383,7 @@ class FindRegPins : public FindRegVisitor public: explicit FindRegPins(StaState *sta); PinSet *findPins(ClockSet *clks, - const TransRiseFallBoth *clk_tr, + const RiseFallBoth *clk_rf, bool edge_triggered, bool latches); @@ -411,12 +411,12 @@ FindRegPins::FindRegPins(StaState *sta) : PinSet * FindRegPins::findPins(ClockSet *clks, - const TransRiseFallBoth *clk_tr, + const RiseFallBoth *clk_rf, bool edge_triggered, bool latches) { pins_ = new PinSet; - visitRegs(clks, clk_tr, edge_triggered, latches); + visitRegs(clks, clk_rf, edge_triggered, latches); return pins_; } @@ -509,22 +509,22 @@ hasMinPulseWidthCheck(LibertyPort *port) { float ignore; bool exists; - port->minPulseWidth(TransRiseFall::rise(), ignore, exists); + port->minPulseWidth(RiseFall::rise(), ignore, exists); if (exists) return true; - port->minPulseWidth(TransRiseFall::fall(), ignore, exists); + port->minPulseWidth(RiseFall::fall(), ignore, exists); return exists; } PinSet * findRegDataPins(ClockSet *clks, - const TransRiseFallBoth *clk_tr, + const RiseFallBoth *clk_rf, bool edge_triggered, bool latches, StaState *sta) { FindRegDataPins find_regs(sta); - return find_regs.findPins(clks, clk_tr, edge_triggered, latches); + return find_regs.findPins(clks, clk_rf, edge_triggered, latches); } //////////////////////////////////////////////////////////////// @@ -576,13 +576,13 @@ FindRegClkPins::seqExpr2(Sequential *) PinSet * findRegClkPins(ClockSet *clks, - const TransRiseFallBoth *clk_tr, + const RiseFallBoth *clk_rf, bool edge_triggered, bool latches, StaState *sta) { FindRegClkPins find_regs(sta); - return find_regs.findPins(clks, clk_tr, edge_triggered, latches); + return find_regs.findPins(clks, clk_rf, edge_triggered, latches); } //////////////////////////////////////////////////////////////// @@ -621,13 +621,13 @@ FindRegAsyncPins::matchPin(Pin *pin) PinSet * findRegAsyncPins(ClockSet *clks, - const TransRiseFallBoth *clk_tr, + const RiseFallBoth *clk_rf, bool edge_triggered, bool latches, StaState *sta) { FindRegAsyncPins find_regs(sta); - return find_regs.findPins(clks, clk_tr, edge_triggered, latches); + return find_regs.findPins(clks, clk_rf, edge_triggered, latches); } //////////////////////////////////////////////////////////////// @@ -715,13 +715,13 @@ FindRegOutputPins::seqExpr2(Sequential *) PinSet * findRegOutputPins(ClockSet *clks, - const TransRiseFallBoth *clk_tr, + const RiseFallBoth *clk_rf, bool edge_triggered, bool latches, StaState *sta) { FindRegOutputPins find_regs(sta); - return find_regs.findPins(clks, clk_tr, edge_triggered, latches); + return find_regs.findPins(clks, clk_rf, edge_triggered, latches); } //////////////////////////////////////////////////////////////// diff --git a/search/FindRegister.hh b/search/FindRegister.hh index 24631e02..622b7e48 100644 --- a/search/FindRegister.hh +++ b/search/FindRegister.hh @@ -25,19 +25,19 @@ namespace sta { InstanceSet * -findRegInstances(ClockSet *clks, const TransRiseFallBoth *clk_tr, +findRegInstances(ClockSet *clks, const RiseFallBoth *clk_rf, bool edge_triggered, bool latches, StaState *sta); PinSet * -findRegDataPins(ClockSet *clks, const TransRiseFallBoth *clk_tr, +findRegDataPins(ClockSet *clks, const RiseFallBoth *clk_rf, bool edge_triggered, bool latches, StaState *sta); PinSet * -findRegClkPins(ClockSet *clks, const TransRiseFallBoth *clk_tr, +findRegClkPins(ClockSet *clks, const RiseFallBoth *clk_rf, bool edge_triggered, bool latches, StaState *sta); PinSet * -findRegAsyncPins(ClockSet *clks, const TransRiseFallBoth *clk_tr, +findRegAsyncPins(ClockSet *clks, const RiseFallBoth *clk_rf, bool edge_triggered, bool latches, StaState *sta); PinSet * -findRegOutputPins(ClockSet *clks, const TransRiseFallBoth *clk_tr, +findRegOutputPins(ClockSet *clks, const RiseFallBoth *clk_rf, bool edge_triggered, bool latches, StaState *sta); void diff --git a/search/GatedClk.cc b/search/GatedClk.cc index 3fe2d917..6909e445 100644 --- a/search/GatedClk.cc +++ b/search/GatedClk.cc @@ -230,28 +230,28 @@ GatedClk::functionClkOperands(FuncExpr *root_expr, } } -TransRiseFall * +RiseFall * GatedClk::gatedClkActiveTrans(LogicValue active_value, const MinMax *min_max) const { - TransRiseFall *leading_tr; + RiseFall *leading_rf; switch (active_value) { case LogicValue::one: case LogicValue::unknown: - leading_tr = TransRiseFall::rise(); + leading_rf = RiseFall::rise(); break; case LogicValue::zero: - leading_tr = TransRiseFall::fall(); + leading_rf = RiseFall::fall(); break; default: internalError("illegal gated clock active value"); - leading_tr = TransRiseFall::rise(); + leading_rf = RiseFall::rise(); break; } if (min_max == MinMax::max()) - return leading_tr; + return leading_rf; else - return leading_tr->opposite(); + return leading_rf->opposite(); } } // namespace diff --git a/search/GatedClk.hh b/search/GatedClk.hh index aba7fc2d..3af3c27e 100644 --- a/search/GatedClk.hh +++ b/search/GatedClk.hh @@ -38,7 +38,7 @@ public: void gatedClkEnables(Vertex *clk_vertex, // Return value. PinSet &enable_pins); - TransRiseFall *gatedClkActiveTrans(LogicValue active_value, + RiseFall *gatedClkActiveTrans(LogicValue active_value, const MinMax *min_max) const; protected: diff --git a/search/Genclks.cc b/search/Genclks.cc index 932de201..d7ddb90e 100644 --- a/search/Genclks.cc +++ b/search/Genclks.cc @@ -691,7 +691,7 @@ Genclks::makeSrcFilter(Clock *gclk) { ClockSet *from_clks = new ClockSet; from_clks->insert(gclk->masterClk()); - const TransRiseFallBoth *rf = TransRiseFallBoth::riseFall(); + const RiseFallBoth *rf = RiseFallBoth::riseFall(); ExceptionFrom *from = sdc_->makeExceptionFrom(nullptr,from_clks,nullptr,rf); PinSet *thru_pins = new PinSet; @@ -723,7 +723,7 @@ Genclks::seedSrcPins(Clock *gclk, for (auto path_ap : corners_->pathAnalysisPts()) { const MinMax *min_max = path_ap->pathMinMax(); const EarlyLate *early_late = min_max; - for (auto tr : TransRiseFall::range()) { + for (auto tr : RiseFall::range()) { Tag *tag = makeTag(gclk, master_clk, master_pin, tr, src_filter, path_ap); Arrival insert = search_->clockInsertion(master_clk, master_pin, tr, @@ -740,7 +740,7 @@ Tag * Genclks::makeTag(const Clock *gclk, const Clock *master_clk, const Pin *master_pin, - const TransRiseFall *master_tr, + const RiseFall *master_rf, FilterPath *src_filter, const PathAnalysisPt *path_ap) { @@ -751,11 +751,11 @@ Genclks::makeTag(const Clock *gclk, state = state->nextState(); ExceptionStateSet *states = new ExceptionStateSet; states->insert(state); - ClkInfo *clk_info = search_->findClkInfo(master_clk->edge(master_tr), + ClkInfo *clk_info = search_->findClkInfo(master_clk->edge(master_rf), master_pin, true, nullptr, true, nullptr, 0.0, 0.0, nullptr, path_ap, nullptr); - return search_->findTag(master_tr, path_ap, clk_info, false, nullptr, false, + return search_->findTag(master_rf, path_ap, clk_info, false, nullptr, false, states, true); } @@ -928,16 +928,16 @@ Genclks::clearSrcPaths() } int -Genclks::srcPathIndex(const TransRiseFall *clk_tr, +Genclks::srcPathIndex(const RiseFall *clk_rf, const PathAnalysisPt *path_ap) const { - return path_ap->index() * TransRiseFall::index_count + clk_tr->index(); + return path_ap->index() * RiseFall::index_count + clk_rf->index(); } void Genclks::recordSrcPaths(Clock *gclk) { - int path_count = TransRiseFall::index_count + int path_count = RiseFall::index_count * corners_->pathAnalysisPtCount(); bool divide_by_1 = gclk->isDivideByOneCombinational(); @@ -957,16 +957,16 @@ Genclks::recordSrcPaths(Clock *gclk) if (src_clk_edge && matchesSrcFilter(path, gclk)) { const EarlyLate *early_late = path->minMax(this); - TransRiseFall *src_clk_tr = src_clk_edge->transition(); - const TransRiseFall *tr = path->transition(this); - bool inverting_path = (tr != src_clk_tr); + RiseFall *src_clk_rf = src_clk_edge->transition(); + const RiseFall *rf = path->transition(this); + bool inverting_path = (rf != src_clk_rf); const PathAnalysisPt *path_ap = path->pathAnalysisPt(this); - int path_index = srcPathIndex(tr, path_ap); + int path_index = srcPathIndex(rf, path_ap); PathVertexRep &src_path = src_paths[path_index]; if ((!divide_by_1 || (inverting_path == invert)) && (!has_edges - || src_clk_tr == gclk->masterClkEdgeTr(tr)) + || src_clk_rf == gclk->masterClkEdgeTr(rf)) && (src_path.isNull() || fuzzyGreater(path->arrival(this), src_path.arrival(this), @@ -974,7 +974,7 @@ Genclks::recordSrcPaths(Clock *gclk) debugPrint4(debug_, "genclk", 2, " %s insertion %s %s %s\n", network_->pathName(gclk_pin), early_late->asString(), - tr->asString(), + rf->asString(), delayAsString(path->arrival(this), this)); src_path.init(path, this); found_src_paths = true; @@ -1042,7 +1042,7 @@ Genclks::srcPath(const ClockEdge *clk_edge, void Genclks::srcPath(const Clock *gclk, const Pin *src_pin, - const TransRiseFall *tr, + const RiseFall *rf, const PathAnalysisPt *path_ap, // Return value. PathVertex &src_path) const @@ -1050,7 +1050,7 @@ Genclks::srcPath(const Clock *gclk, PathVertexRep *src_paths = genclk_src_paths_.findKey(ClockPinPair(gclk, src_pin)); if (src_paths) { - int path_index = srcPathIndex(tr, path_ap); + int path_index = srcPathIndex(rf, path_ap); src_path.init(src_paths[path_index], this); } else @@ -1060,17 +1060,17 @@ Genclks::srcPath(const Clock *gclk, Arrival Genclks::insertionDelay(const Clock *clk, const Pin *pin, - const TransRiseFall *tr, + const RiseFall *rf, const EarlyLate *early_late, const PathAnalysisPt *path_ap) const { PathVertex src_path; PathAnalysisPt *insert_ap = path_ap->insertionAnalysisPt(early_late); - srcPath(clk, pin, tr, insert_ap, src_path); + srcPath(clk, pin, rf, insert_ap, src_path); if (clk->pllFdbk()) { const MinMax *min_max = path_ap->pathMinMax(); PathAnalysisPt *pll_ap = path_ap->insertionAnalysisPt(min_max->opposite()); - Arrival pll_delay = pllDelay(clk, tr, pll_ap); + Arrival pll_delay = pllDelay(clk, rf, pll_ap); if (src_path.isNull()) return -pll_delay; else { @@ -1112,7 +1112,7 @@ Genclks::makePllFilter(const Clock *gclk) { PinSet *from_pins = new PinSet; from_pins->insert(gclk->pllOut()); - TransRiseFallBoth *rf = TransRiseFallBoth::riseFall(); + RiseFallBoth *rf = RiseFallBoth::riseFall(); ExceptionFrom *from = sdc_->makeExceptionFrom(from_pins,nullptr,nullptr,rf); PinSet *to_pins = new PinSet; @@ -1135,7 +1135,7 @@ Genclks::seedPllPin(const Clock *gclk, tag_bldr.init(vertex); copyGenClkSrcPaths(vertex, &tag_bldr); for (auto path_ap : corners_->pathAnalysisPts()) { - for (auto tr : TransRiseFall::range()) { + for (auto tr : RiseFall::range()) { Tag *tag = makeTag(gclk, gclk, pll_out_pin, tr, pll_filter, path_ap); tag_bldr.setArrival(tag, 0.0, nullptr); } @@ -1217,14 +1217,14 @@ Genclks::findPllArrivals(const Clock *gclk, Arrival Genclks::pllDelay(const Clock *clk, - const TransRiseFall *tr, + const RiseFall *rf, const PathAnalysisPt *path_ap) const { Vertex *fdbk_vertex = graph_->pinLoadVertex(clk->pllFdbk()); GenclkInfo *genclk_info = genclkInfo(clk); if (genclk_info) { FilterPath *pll_filter = genclk_info->pllFilter(); - VertexPathIterator fdbk_path_iter(fdbk_vertex, tr, path_ap, this); + VertexPathIterator fdbk_path_iter(fdbk_vertex, rf, path_ap, this); while (fdbk_path_iter.hasNext()) { Path *path = fdbk_path_iter.next(); if (matchesPllFilter(path, pll_filter)) diff --git a/search/Genclks.hh b/search/Genclks.hh index 8114817c..cee24788 100644 --- a/search/Genclks.hh +++ b/search/Genclks.hh @@ -59,7 +59,7 @@ public: // Generated clock insertion delay. Arrival insertionDelay(const Clock *clk, const Pin *pin, - const TransRiseFall *tr, + const RiseFall *rf, const EarlyLate *early_late, const PathAnalysisPt *path_ap) const; // Generated clock source path for a clock path root. @@ -74,12 +74,12 @@ public: PathVertex &src_path) const; void srcPath(const Clock *clk, const Pin *src_pin, - const TransRiseFall *tr, + const RiseFall *rf, const PathAnalysisPt *path_ap, // Return value. PathVertex &src_path) const; Arrival pllDelay(const Clock *clk, - const TransRiseFall *tr, + const RiseFall *rf, const PathAnalysisPt *path_ap) const; Vertex *srcPathVertex(const Pin *pin) const; Level clkPinMaxLevel(Clock *clk) const; @@ -95,7 +95,7 @@ private: void seedClkVertices(Clock *clk, BfsBkwdIterator &iter, VertexSet *fanins); - int srcPathIndex(const TransRiseFall *clk_tr, + int srcPathIndex(const RiseFall *clk_rf, const PathAnalysisPt *path_ap) const; bool matchesSrcFilter(Path *path, const Clock *gclk) const; @@ -119,7 +119,7 @@ private: virtual Tag *makeTag(const Clock *gclk, const Clock *master_clk, const Pin *master_pin, - const TransRiseFall *tr, + const RiseFall *rf, FilterPath *src_filter, const PathAnalysisPt *path_ap); void seedSrcPins(Clock *clk, diff --git a/search/Latches.cc b/search/Latches.cc index 18cc1c03..24696017 100644 --- a/search/Latches.cc +++ b/search/Latches.cc @@ -205,11 +205,11 @@ Latches::latchRequired(const Path *data_path, Delay &time_given_to_startpoint) { Vertex *data_vertex = data_path->vertex(this); - const TransRiseFall *data_tr = data_path->transition(this); - ArcDelay setup = latchSetupMargin(data_vertex,data_tr,disable_path,path_ap); + const RiseFall *data_rf = data_path->transition(this); + ArcDelay setup = latchSetupMargin(data_vertex,data_rf,disable_path,path_ap); ExceptionPath *excpt = search_->exceptionTo(ExceptionPathType::any, data_path, data_vertex->pin(), - data_tr, + data_rf, enable_path->clkEdge(this), path_ap->pathMinMax(), false, false); @@ -235,8 +235,8 @@ Latches::latchEnableOtherPath(Path *path, ClockEdge *clk_edge = path->clkEdge(this); ClockEdge *other_clk_edge = path->clkInfo(this)->isPulseClk() ? clk_edge:clk_edge->opposite(); - TransRiseFall *other_tr = path->transition(this)->opposite(); - VertexPathIterator path_iter(vertex, other_tr, tgt_clk_path_ap, this); + RiseFall *other_rf = path->transition(this)->opposite(); + VertexPathIterator path_iter(vertex, other_rf, tgt_clk_path_ap, this); while (path_iter.hasNext()) { PathVertex *path = path_iter.next(); if (path->isClock(this) @@ -259,11 +259,11 @@ Latches::latchEnablePath(Path *q_path, const PathAnalysisPt *tgt_clk_path_ap = path_ap->tgtClkAnalysisPt(); const Instance *latch = network_->instance(q_path->pin(this)); Vertex *en_vertex; - TransRiseFall *en_tr; + RiseFall *en_rf; LatchEnableState state; - latchDtoQEnable(d_q_edge, latch, en_vertex, en_tr, state); + latchDtoQEnable(d_q_edge, latch, en_vertex, en_rf, state); if (state == LatchEnableState::enabled) { - VertexPathIterator path_iter(en_vertex, en_tr, tgt_clk_path_ap, this); + VertexPathIterator path_iter(en_vertex, en_rf, tgt_clk_path_ap, this); while (path_iter.hasNext()) { PathVertex *path = path_iter.next(); const ClockEdge *clk_edge = path->clkEdge(this); @@ -293,9 +293,9 @@ Latches::latchOutArrival(Path *data_path, Vertex *data_vertex = d_q_edge->from(graph_); const Instance *inst = network_->instance(data_vertex->pin()); Vertex *enable_vertex; - TransRiseFall *enable_tr; + RiseFall *enable_rf; LatchEnableState state; - latchDtoQEnable(d_q_edge, inst, enable_vertex, enable_tr, state); + latchDtoQEnable(d_q_edge, inst, enable_vertex, enable_rf, state); // Latch enable may be missing if library is malformed. switch (state) { case LatchEnableState::closed: @@ -313,7 +313,7 @@ Latches::latchOutArrival(Path *data_path, break; case LatchEnableState::enabled: { const PathAnalysisPt *tgt_clk_path_ap = path_ap->tgtClkAnalysisPt(); - VertexPathIterator enable_iter(enable_vertex, enable_tr, + VertexPathIterator enable_iter(enable_vertex, enable_rf, tgt_clk_path_ap, this); while (enable_iter.hasNext()) { PathVertex *enable_path = enable_iter.next(); @@ -353,7 +353,7 @@ Latches::latchOutArrival(Path *data_path, en_clk_info->uncertainties(), path_ap, crpr_clk_path); - TransRiseFall *q_tr = d_q_arc->toTrans()->asRiseFall(); + RiseFall *q_rf = d_q_arc->toTrans()->asRiseFall(); ExceptionStateSet *states = nullptr; // Latch data pin is a valid exception -from pin. if (sdc_->exceptionFromStates(data_path->pin(this), @@ -362,11 +362,11 @@ Latches::latchOutArrival(Path *data_path, MinMax::max(), states) // -from enable non-filter exceptions apply. && sdc_->exceptionFromStates(enable_vertex->pin(), - enable_tr, + enable_rf, en_clk_edge->clock(), en_clk_edge->transition(), MinMax::max(), false, states)) - q_tag = search_->findTag(q_tr, path_ap, q_clk_info, false, + q_tag = search_->findTag(q_rf, path_ap, q_clk_info, false, nullptr, false, states, true); } return; @@ -395,13 +395,13 @@ Latches::exceptionTo(Path *data_path, ArcDelay Latches::latchSetupMargin(Vertex *data_vertex, - const TransRiseFall *data_tr, + const RiseFall *data_rf, const Path *disable_path, const PathAnalysisPt *path_ap) { if (disable_path) { Vertex *enable_vertex = disable_path->vertex(this); - const TransRiseFall *disable_tr = disable_path->transition(this); + const RiseFall *disable_rf = disable_path->transition(this); VertexInEdgeIterator edge_iter(data_vertex, graph_); while (edge_iter.hasNext()) { Edge *edge = edge_iter.next(); @@ -415,8 +415,8 @@ Latches::latchSetupMargin(Vertex *data_vertex, TimingArcSetArcIterator arc_iter(arc_set); while (arc_iter.hasNext()) { TimingArc *check_arc = arc_iter.next(); - if (check_arc->toTrans()->asRiseFall() == data_tr - && check_arc->fromTrans()->asRiseFall() == disable_tr) + if (check_arc->toTrans()->asRiseFall() == data_rf + && check_arc->fromTrans()->asRiseFall() == disable_rf) return search_->deratedDelay(from_vertex, check_arc, edge, false, path_ap); } @@ -458,7 +458,7 @@ Latches::latchDtoQEnable(Edge *d_q_edge, const Instance *inst, // Return values. Vertex *&enable_vertex, - TransRiseFall *&enable_tr, + RiseFall *&enable_rf, LatchEnableState &state) const { enable_vertex = nullptr; @@ -468,7 +468,7 @@ Latches::latchDtoQEnable(Edge *d_q_edge, TimingArcSet *d_q_set = d_q_edge->timingArcSet(); LibertyPort *enable_port; FuncExpr *enable_func; - cell->latchEnable(d_q_set, enable_port, enable_func, enable_tr); + cell->latchEnable(d_q_set, enable_port, enable_func, enable_rf); if (enable_port) { Pin *enable_pin = network_->findPin(inst, enable_port); if (enable_pin) { @@ -507,9 +507,9 @@ Latches::latchDtoQState(Edge *edge) const const Pin *from_pin = from_vertex->pin(); const Instance *inst = network_->instance(from_pin); Vertex *enable_vertex; - TransRiseFall *enable_tr; + RiseFall *enable_rf; LatchEnableState state; - latchDtoQEnable(edge, inst, enable_vertex, enable_tr, state); + latchDtoQEnable(edge, inst, enable_vertex, enable_rf, state); return state; } diff --git a/search/Latches.hh b/search/Latches.hh index 0d204477..9227ec45 100644 --- a/search/Latches.hh +++ b/search/Latches.hh @@ -76,7 +76,7 @@ public: const Instance *inst, // Return values. Vertex *&enable_vertex, - TransRiseFall *&enable_tr, + RiseFall *&enable_rf, LatchEnableState &state) const; LatchEnableState latchDtoQState(Edge *d_q_edge) const; void latchEnableOtherPath(Path *path, @@ -96,7 +96,7 @@ public: protected: ArcDelay latchSetupMargin(Vertex *data_vertex, - const TransRiseFall *data_tr, + const RiseFall *data_rf, const Path *disable_path, const PathAnalysisPt *path_ap); ExceptionPath *exceptionTo(Path *data_path, diff --git a/search/Path.cc b/search/Path.cc index bc3b7b92..3e5763b0 100644 --- a/search/Path.cc +++ b/search/Path.cc @@ -110,7 +110,7 @@ Path::slew(const StaState *sta) const } int -Path::trIndex(const StaState *sta) const +Path::rfIndex(const StaState *sta) const { return transition(sta)->index(); } @@ -194,8 +194,8 @@ Path::cmpPinTrClk(const Path *path1, const Pin *pin2 = path2->pin(sta); const Network *network = sta->network(); if (pin1 == pin2) { - int tr_index1 = path1->trIndex(sta); - int tr_index2 = path2->trIndex(sta); + int tr_index1 = path1->rfIndex(sta); + int tr_index2 = path2->rfIndex(sta); if (tr_index1 == tr_index2) return cmpClk(path1, path2, sta); else if (tr_index1 < tr_index2) diff --git a/search/Path.hh b/search/Path.hh index a7da5b87..583e9630 100644 --- a/search/Path.hh +++ b/search/Path.hh @@ -52,8 +52,8 @@ public: virtual ClockEdge *clkEdge(const StaState *sta) const; virtual Clock *clock(const StaState *sta) const; virtual bool isClock(const StaState *sta) const; - virtual const TransRiseFall *transition(const StaState *sta) const = 0; - virtual int trIndex(const StaState *sta) const; + virtual const RiseFall *transition(const StaState *sta) const = 0; + virtual int rfIndex(const StaState *sta) const; virtual const MinMax *minMax(const StaState *sta) const; virtual PathAnalysisPt *pathAnalysisPt(const StaState *sta) const = 0; virtual PathAPIndex pathAnalysisPtIndex(const StaState *sta) const; diff --git a/search/PathEnd.cc b/search/PathEnd.cc index a45adc30..dea75332 100644 --- a/search/PathEnd.cc +++ b/search/PathEnd.cc @@ -80,7 +80,7 @@ PathEnd::clkEarlyLate(const StaState *sta) const return checkRole(sta)->tgtClkEarlyLate(); } -const TransRiseFall * +const RiseFall * PathEnd::transition(const StaState *sta) const { return path_.transition(sta); @@ -122,7 +122,7 @@ PathEnd::requiredTimeOffset(const StaState *sta) const return requiredTime(sta) + sourceClkOffset(sta); } -const TransRiseFall * +const RiseFall * PathEnd::targetClkEndTrans(const StaState *sta) const { const PathVertex *clk_path = targetClkPath(); @@ -354,14 +354,14 @@ PathEnd::checkTgtClkDelay(const PathVertex *tgt_clk_path, ClkInfo *clk_info = tgt_clk_path->clkInfo(sta); const Pin *tgt_src_pin = clk_info->clkSrc(); const Clock *tgt_clk = tgt_clk_edge->clock(); - const TransRiseFall *tgt_clk_tr = tgt_clk_edge->transition(); - insertion = search->clockInsertion(tgt_clk, tgt_src_pin, tgt_clk_tr, + const RiseFall *tgt_clk_rf = tgt_clk_edge->transition(); + insertion = search->clockInsertion(tgt_clk, tgt_src_pin, tgt_clk_rf, min_max, early_late, tgt_path_ap); if (clk_info->isPropagated()) { // Propagated clock. Propagated arrival is seeded with // early_late==path_min_max insertion delay. Arrival path_insertion = search->clockInsertion(tgt_clk, tgt_src_pin, - tgt_clk_tr, min_max, + tgt_clk_rf, min_max, min_max, tgt_path_ap); latency=tgt_clk_path->arrival(sta)-tgt_clk_edge->time()-path_insertion; } @@ -913,7 +913,7 @@ PathEndClkConstrainedMcp::findHoldMcps(const ClockEdge *tgt_clk_edge, { Pin *pin = path_.pin(sta); - const TransRiseFall *tr = path_.transition(sta); + const RiseFall *rf = path_.transition(sta); // Mcp may be setup, hold or setup_hold, since all match min paths. const MinMaxAll *mcp_min_max = mcp_->minMax(); Search *search = sta->search(); @@ -921,7 +921,7 @@ PathEndClkConstrainedMcp::findHoldMcps(const ClockEdge *tgt_clk_edge, hold_mcp = mcp_; setup_mcp = dynamic_cast(search->exceptionTo(ExceptionPathType::multi_cycle, - path_.path(), pin, tr, + path_.path(), pin, rf, tgt_clk_edge, MinMax::max(), true, false)); @@ -930,7 +930,7 @@ PathEndClkConstrainedMcp::findHoldMcps(const ClockEdge *tgt_clk_edge, setup_mcp = mcp_; hold_mcp = dynamic_cast(search->exceptionTo(ExceptionPathType::multi_cycle, - path_.path(), pin, tr, + path_.path(), pin, rf, tgt_clk_edge, MinMax::min(), true, false)); @@ -1340,9 +1340,9 @@ PathEnd::outputDelayMargin(OutputDelay *output_delay, const Path *path, const StaState *sta) { - const TransRiseFall *tr = path->transition(sta); + const RiseFall *rf = path->transition(sta); const MinMax *min_max = path->minMax(sta); - float margin = output_delay->delays()->value(tr, min_max); + float margin = output_delay->delays()->value(rf, min_max); if (min_max == MinMax::max()) return margin; else @@ -1428,11 +1428,11 @@ PathEndOutputDelay::tgtClkDelay(const ClockEdge *tgt_clk_edge, const PathAnalysisPt *path_ap = path_.pathAnalysisPt(sta); const MinMax *latency_min_max = path_ap->tgtClkAnalysisPt()->pathMinMax(); Clock *tgt_clk = tgt_clk_edge->clock(); - TransRiseFall *tgt_clk_tr = tgt_clk_edge->transition(); + RiseFall *tgt_clk_rf = tgt_clk_edge->transition(); if (!output_delay_->sourceLatencyIncluded()) insertion = sta->search()->clockInsertion(tgt_clk, tgt_clk->defaultPin(), - tgt_clk_tr, + tgt_clk_rf, latency_min_max, early_late, path_ap); else @@ -1440,7 +1440,7 @@ PathEndOutputDelay::tgtClkDelay(const ClockEdge *tgt_clk_edge, const Sdc *sdc = sta->sdc(); if (!tgt_clk->isPropagated() && !output_delay_->networkLatencyIncluded()) - latency = sdc->clockLatency(tgt_clk, tgt_clk_tr, latency_min_max); + latency = sdc->clockLatency(tgt_clk, tgt_clk_rf, latency_min_max); else latency = 0.0; } diff --git a/search/PathEnd.hh b/search/PathEnd.hh index c2778e1c..f05ae4b9 100644 --- a/search/PathEnd.hh +++ b/search/PathEnd.hh @@ -30,7 +30,7 @@ namespace sta { class StaState; -class TransRiseFall; +class RiseFall; class MinMax; class ReportPath; @@ -77,7 +77,7 @@ public: // Synonym for minMax(). const EarlyLate *pathEarlyLate(const StaState *sta) const; virtual const EarlyLate *clkEarlyLate(const StaState *sta) const; - const TransRiseFall *transition(const StaState *sta) const; + const RiseFall *transition(const StaState *sta) const; PathAnalysisPt *pathAnalysisPt(const StaState *sta) const; PathAPIndex pathIndex(const StaState *sta) const; virtual void reportShort(ReportPath *report, @@ -118,7 +118,7 @@ public: virtual const PathVertex *targetClkPath() const; virtual Clock *targetClk(const StaState *sta) const; virtual ClockEdge *targetClkEdge(const StaState *sta) const; - const TransRiseFall *targetClkEndTrans(const StaState *sta) const; + const RiseFall *targetClkEndTrans(const StaState *sta) const; // Target clock with cycle accounting and source clock offsets. virtual float targetClkTime(const StaState *sta) const; // Time offset for the target clock. diff --git a/search/PathEnum.cc b/search/PathEnum.cc index ad14e3d4..41a9a2ca 100644 --- a/search/PathEnum.cc +++ b/search/PathEnum.cc @@ -237,14 +237,14 @@ public: TimingArc *prev_arc); virtual bool visitFromToPath(const Pin *from_pin, Vertex *from_vertex, - const TransRiseFall *from_tr, + const RiseFall *from_rf, Tag *from_tag, PathVertex *from_path, Edge *edge, TimingArc *arc, ArcDelay arc_delay, Vertex *to_vertex, - const TransRiseFall *to_tr, + const RiseFall *to_rf, Tag *to_tag, Arrival &to_arrival, const MinMax *min_max, @@ -264,7 +264,7 @@ private: Slack path_end_slack_; PathRef &before_div_; bool unique_pins_; - int before_div_tr_index_; + int before_div_rf_index_; Tag *before_div_tag_; PathAPIndex before_div_ap_index_; Arrival before_div_arrival_; @@ -283,7 +283,7 @@ PathEnumFaninVisitor::PathEnumFaninVisitor(PathEnd *path_end, path_end_slack_(path_end->slack(sta_)), before_div_(before_div), unique_pins_(unique_pins), - before_div_tr_index_(before_div_.trIndex(sta_)), + before_div_rf_index_(before_div_.rfIndex(sta_)), before_div_tag_(before_div_.tag(sta_)), before_div_ap_index_(before_div_.pathAnalysisPtIndex(sta_)), before_div_arrival_(before_div_.arrival(sta_)), @@ -297,7 +297,7 @@ PathEnumFaninVisitor::visitFaninPathsThru(Vertex *vertex, Vertex *prev_vertex, TimingArc *prev_arc) { - before_div_tr_index_ = before_div_.trIndex(sta_); + before_div_rf_index_ = before_div_.rfIndex(sta_); before_div_tag_ = before_div_.tag(sta_); before_div_ap_index_ = before_div_.pathAnalysisPtIndex(sta_); before_div_arrival_ = before_div_.arrival(sta_); @@ -316,14 +316,14 @@ PathEnumFaninVisitor::copy() bool PathEnumFaninVisitor::visitFromToPath(const Pin *, Vertex *from_vertex, - const TransRiseFall *, + const RiseFall *, Tag *, PathVertex *from_path, Edge *edge, TimingArc *arc, ArcDelay, Vertex *to_vertex, - const TransRiseFall *to_tr, + const RiseFall *to_rf, Tag *to_tag, Arrival &to_arrival, const MinMax *min_max, @@ -333,11 +333,11 @@ PathEnumFaninVisitor::visitFromToPath(const Pin *, debugPrint4(debug, "path_enum", 3, "visit fanin %s -> %s %s %s\n", from_path->name(sta_), to_vertex->name(sta_->network()), - to_tr->asString(), + to_rf->asString(), delayAsString(sta_->search()->deratedDelay(from_vertex, arc, edge, false,path_ap),sta_)); // These paths fanin to before_div_ so we know to_vertex matches. - if (to_tr->index() == before_div_tr_index_ + if (to_rf->index() == before_div_rf_index_ && path_ap->index() == before_div_ap_index_ && arc != prev_arc_ && (!unique_pins_ || from_vertex != prev_vertex_) diff --git a/search/PathEnumed.cc b/search/PathEnumed.cc index 19ece450..5bc122a2 100644 --- a/search/PathEnumed.cc +++ b/search/PathEnumed.cc @@ -81,7 +81,7 @@ PathEnumed::setTag(Tag *tag) tag_index_ = tag->index(); } -const TransRiseFall * +const RiseFall * PathEnumed::transition(const StaState *sta) const { return tag(sta)->transition(); diff --git a/search/PathEnumed.hh b/search/PathEnumed.hh index dee31d0d..101c6c3c 100644 --- a/search/PathEnumed.hh +++ b/search/PathEnumed.hh @@ -36,7 +36,7 @@ public: virtual Vertex *vertex(const StaState *sta) const; virtual VertexId vertexId(const StaState *sta) const; virtual Tag *tag(const StaState *sta) const; - virtual const TransRiseFall *transition(const StaState *sta) const; + virtual const RiseFall *transition(const StaState *sta) const; virtual int trIndex(const StaState *) const; virtual PathAnalysisPt *pathAnalysisPt(const StaState *sta) const; virtual PathAPIndex pathAnalysisPtIndex(const StaState *sta) const; diff --git a/search/PathRef.cc b/search/PathRef.cc index 2b77308a..f9dfb4dc 100644 --- a/search/PathRef.cc +++ b/search/PathRef.cc @@ -159,7 +159,7 @@ PathRef::tagIndex(const StaState *sta) const return path_vertex_.tagIndex(sta); } -const TransRiseFall * +const RiseFall * PathRef::transition(const StaState *sta) const { if (path_enumed_) @@ -169,12 +169,12 @@ PathRef::transition(const StaState *sta) const } int -PathRef::trIndex(const StaState *sta) const +PathRef::rfIndex(const StaState *sta) const { if (path_enumed_) - return path_enumed_->trIndex(sta); + return path_enumed_->rfIndex(sta); else - return path_vertex_.trIndex(sta); + return path_vertex_.rfIndex(sta); } PathAnalysisPt * diff --git a/search/PathRef.hh b/search/PathRef.hh index de960d35..9ae98a64 100644 --- a/search/PathRef.hh +++ b/search/PathRef.hh @@ -53,8 +53,8 @@ public: virtual VertexId vertexId(const StaState *sta) const; virtual Tag *tag(const StaState *sta) const; virtual TagIndex tagIndex(const StaState *sta) const; - virtual const TransRiseFall *transition(const StaState *sta) const; - virtual int trIndex(const StaState *sta) const; + virtual const RiseFall *transition(const StaState *sta) const; + virtual int rfIndex(const StaState *sta) const; virtual PathAnalysisPt *pathAnalysisPt(const StaState *sta) const; virtual PathAPIndex pathAnalysisPtIndex(const StaState *sta) const; void arrivalIndex(int &arrival_index, diff --git a/search/PathVertex.cc b/search/PathVertex.cc index a087c449..ccaeab0c 100644 --- a/search/PathVertex.cc +++ b/search/PathVertex.cc @@ -182,14 +182,14 @@ PathVertex::tagIndex(const StaState *) const return tag_->index(); } -const TransRiseFall * +const RiseFall * PathVertex::transition(const StaState *) const { return tag_->transition(); } int -PathVertex::trIndex(const StaState *) const +PathVertex::rfIndex(const StaState *) const { return tag_->trIndex(); } @@ -329,14 +329,14 @@ public: virtual void visit(Vertex *) {} virtual bool visitFromToPath(const Pin *from_pin, Vertex *from_vertex, - const TransRiseFall *from_tr, + const RiseFall *from_rf, Tag *from_tag, PathVertex *from_path, Edge *edge, TimingArc *arc, ArcDelay arc_delay, Vertex *to_vertex, - const TransRiseFall *to_tr, + const RiseFall *to_rf, Tag *to_tag, Arrival &to_arrival, const MinMax *min_max, @@ -350,7 +350,7 @@ protected: const Path *path_; Arrival path_arrival_; Tag *path_tag_; - int path_tr_index_; + int path_rf_index_; PathAPIndex path_ap_index_; PathVertex prev_path_; TimingArc *prev_arc_; @@ -367,7 +367,7 @@ PrevPathVisitor::PrevPathVisitor(const Path *path, path_(path), path_arrival_(path->arrival(sta)), path_tag_(path->tag(sta)), - path_tr_index_(path->trIndex(sta)), + path_rf_index_(path->rfIndex(sta)), path_ap_index_(path->pathAnalysisPtIndex(sta)), prev_path_(), prev_arc_(nullptr), @@ -384,21 +384,21 @@ PrevPathVisitor::copy() bool PrevPathVisitor::visitFromToPath(const Pin *, Vertex *, - const TransRiseFall *, + const RiseFall *, Tag *from_tag, PathVertex *from_path, Edge *, TimingArc *arc, ArcDelay, Vertex *, - const TransRiseFall *to_tr, + const RiseFall *to_rf, Tag *to_tag, Arrival &to_arrival, const MinMax *, const PathAnalysisPt *path_ap) { PathAPIndex path_ap_index = path_ap->index(); - if (to_tr->index() == path_tr_index_ + if (to_rf->index() == path_rf_index_ && path_ap_index == path_ap_index_ && (dcalc_tol_ > 0.0 ? std::abs(delayAsFloat(to_arrival - path_arrival_)) < dcalc_tol_ @@ -493,7 +493,7 @@ VertexPathIterator::VertexPathIterator(Vertex *vertex, const StaState *sta) : search_(sta->search()), vertex_(vertex), - tr_(nullptr), + rf_(nullptr), path_ap_(nullptr), min_max_(nullptr) { @@ -507,12 +507,12 @@ VertexPathIterator::VertexPathIterator(Vertex *vertex, // Iterate over vertex paths with the same transition and // analysis pt but different but different tags. VertexPathIterator::VertexPathIterator(Vertex *vertex, - const TransRiseFall *tr, + const RiseFall *rf, const PathAnalysisPt *path_ap, const StaState *sta) : search_(sta->search()), vertex_(vertex), - tr_(tr), + rf_(rf), path_ap_(path_ap), min_max_(nullptr) { @@ -524,12 +524,12 @@ VertexPathIterator::VertexPathIterator(Vertex *vertex, } VertexPathIterator::VertexPathIterator(Vertex *vertex, - const TransRiseFall *tr, + const RiseFall *rf, const MinMax *min_max, const StaState *sta) : search_(sta->search()), vertex_(vertex), - tr_(tr), + rf_(rf), path_ap_(nullptr), min_max_(min_max) { @@ -557,8 +557,8 @@ VertexPathIterator::findNext() Tag *tag; int arrival_index; arrival_iter_.next(tag, arrival_index); - if ((tr_ == nullptr - || tag->trIndex() == tr_->index()) + if ((rf_ == nullptr + || tag->trIndex() == rf_->index()) && (path_ap_ == nullptr || tag->pathAPIndex() == path_ap_->index()) && (min_max_ == nullptr diff --git a/search/PathVertex.hh b/search/PathVertex.hh index da908b5d..e7d65da2 100644 --- a/search/PathVertex.hh +++ b/search/PathVertex.hh @@ -61,8 +61,8 @@ public: virtual VertexId vertexId(const StaState *sta) const; virtual Tag *tag(const StaState *) const { return tag_; } virtual TagIndex tagIndex(const StaState *sta) const; - virtual const TransRiseFall *transition(const StaState *) const; - virtual int trIndex(const StaState *sta) const; + virtual const RiseFall *transition(const StaState *) const; + virtual int rfIndex(const StaState *sta) const; virtual PathAnalysisPt *pathAnalysisPt(const StaState *sta) const; virtual PathAPIndex pathAnalysisPtIndex(const StaState *sta) const; void arrivalIndex(int &arrival_index, @@ -115,13 +115,13 @@ public: // Iterate over vertex paths with the same transition and // analysis pt but different tags. VertexPathIterator(Vertex *vertex, - const TransRiseFall *tr, + const RiseFall *rf, const PathAnalysisPt *path_ap, const StaState *sta); // Iterate over vertex paths with the same transition and // analysis pt min/max but different tags. VertexPathIterator(Vertex *vertex, - const TransRiseFall *tr, + const RiseFall *rf, const MinMax *min_max, const StaState *sta); virtual ~VertexPathIterator(); @@ -134,7 +134,7 @@ private: const Search *search_; Vertex *vertex_; - const TransRiseFall *tr_; + const RiseFall *rf_; const PathAnalysisPt *path_ap_; const MinMax *min_max_; ArrivalMap::Iterator arrival_iter_; diff --git a/search/Power.cc b/search/Power.cc index deb7577a..634462bb 100644 --- a/search/Power.cc +++ b/search/Power.cc @@ -590,16 +590,16 @@ Power::findInternalPower(const Pin *to_pin, else duty = 0.5; float port_energy = 0.0; - for (auto to_tr : TransRiseFall::range()) { - // Should use unateness to find from_tr. - TransRiseFall *from_tr = to_tr; + for (auto to_rf : RiseFall::range()) { + // Should use unateness to find from_rf. + RiseFall *from_rf = to_rf; float slew = delayAsFloat(graph_->slew(from_vertex, - from_tr, + from_rf, dcalc_ap->index())); - float table_energy = pwr->power(to_tr, pvt, slew, load_cap); + float table_energy = pwr->power(to_rf, pvt, slew, load_cap); float tr_energy = table_energy * duty; debugPrint4(debug_, "power", 3, " %s energy = %9.2e * %.2f = %9.2e\n", - to_tr->shortName(), + to_rf->shortName(), table_energy, duty, tr_energy); diff --git a/search/Property.cc b/search/Property.cc index b263bc19..480bf0d4 100644 --- a/search/Property.cc +++ b/search/Property.cc @@ -39,27 +39,27 @@ using std::string; static PropertyValue pinSlewProperty(const Pin *pin, - const TransRiseFall *tr, + const RiseFall *rf, const MinMax *min_max, Sta *sta); static PropertyValue pinSlackProperty(const Pin *pin, - const TransRiseFall *tr, + const RiseFall *rf, const MinMax *min_max, Sta *sta); static PropertyValue portSlewProperty(const Port *port, - const TransRiseFall *tr, + const RiseFall *rf, const MinMax *min_max, Sta *sta); static PropertyValue portSlackProperty(const Port *port, - const TransRiseFall *tr, + const RiseFall *rf, const MinMax *min_max, Sta *sta); static PropertyValue edgeDelayProperty(Edge *edge, - const TransRiseFall *tr, + const RiseFall *rf, const MinMax *min_max, Sta *sta); static float @@ -623,22 +623,22 @@ getProperty(const Port *port, } else if (stringEqual(property, "actual_fall_transition_min")) - return portSlewProperty(port, TransRiseFall::fall(), MinMax::min(), sta); + return portSlewProperty(port, RiseFall::fall(), MinMax::min(), sta); else if (stringEqual(property, "actual_fall_transition_max")) - return portSlewProperty(port, TransRiseFall::fall(), MinMax::max(), sta); + return portSlewProperty(port, RiseFall::fall(), MinMax::max(), sta); else if (stringEqual(property, "actual_rise_transition_min")) - return portSlewProperty(port, TransRiseFall::rise(), MinMax::min(), sta); + return portSlewProperty(port, RiseFall::rise(), MinMax::min(), sta); else if (stringEqual(property, "actual_rise_transition_max")) - return portSlewProperty(port, TransRiseFall::rise(), MinMax::max(), sta); + return portSlewProperty(port, RiseFall::rise(), MinMax::max(), sta); else if (stringEqual(property, "min_fall_slack")) - return portSlackProperty(port, TransRiseFall::fall(), MinMax::min(), sta); + return portSlackProperty(port, RiseFall::fall(), MinMax::min(), sta); else if (stringEqual(property, "max_fall_slack")) - return portSlackProperty(port, TransRiseFall::fall(), MinMax::max(), sta); + return portSlackProperty(port, RiseFall::fall(), MinMax::max(), sta); else if (stringEqual(property, "min_rise_slack")) - return portSlackProperty(port, TransRiseFall::rise(), MinMax::min(), sta); + return portSlackProperty(port, RiseFall::rise(), MinMax::min(), sta); else if (stringEqual(property, "max_rise_slack")) - return portSlackProperty(port, TransRiseFall::rise(), MinMax::max(), sta); + return portSlackProperty(port, RiseFall::rise(), MinMax::max(), sta); else throw PropertyUnknown("port", property); @@ -646,26 +646,26 @@ getProperty(const Port *port, static PropertyValue portSlewProperty(const Port *port, - const TransRiseFall *tr, + const RiseFall *rf, const MinMax *min_max, Sta *sta) { auto network = sta->cmdNetwork(); Instance *top_inst = network->topInstance(); Pin *pin = network->findPin(top_inst, port); - return pinSlewProperty(pin, tr, min_max, sta); + return pinSlewProperty(pin, rf, min_max, sta); } static PropertyValue portSlackProperty(const Port *port, - const TransRiseFall *tr, + const RiseFall *rf, const MinMax *min_max, Sta *sta) { auto network = sta->cmdNetwork(); Instance *top_inst = network->topInstance(); Pin *pin = network->findPin(top_inst, port); - return pinSlackProperty(pin, tr, min_max, sta); + return pinSlackProperty(pin, rf, min_max, sta); } PropertyValue @@ -680,20 +680,20 @@ getProperty(const LibertyPort *port, else if (stringEqual(property, "direction")) return PropertyValue(port->direction()->name()); else if (stringEqual(property, "capacitance")) { - float cap = port->capacitance(TransRiseFall::rise(), MinMax::max()); + float cap = port->capacitance(RiseFall::rise(), MinMax::max()); return PropertyValue(sta->units()->capacitanceUnit()->asString(cap, 6)); } else if (stringEqual(property, "drive_resistance_rise_min")) - return PropertyValue(port->driveResistance(TransRiseFall::rise(), + return PropertyValue(port->driveResistance(RiseFall::rise(), MinMax::min())); else if (stringEqual(property, "drive_resistance_rise_max")) - return PropertyValue(port->driveResistance(TransRiseFall::rise(), + return PropertyValue(port->driveResistance(RiseFall::rise(), MinMax::max())); else if (stringEqual(property, "drive_resistance_fall_min")) - return PropertyValue(port->driveResistance(TransRiseFall::fall(), + return PropertyValue(port->driveResistance(RiseFall::fall(), MinMax::min())); else if (stringEqual(property, "drive_resistance_fall_max")) - return PropertyValue(port->driveResistance(TransRiseFall::fall(), + return PropertyValue(port->driveResistance(RiseFall::fall(), MinMax::max())); else throw PropertyUnknown("liberty port", property); @@ -747,22 +747,22 @@ getProperty(const Pin *pin, } else if (stringEqual(property, "max_fall_slack")) - return pinSlackProperty(pin, TransRiseFall::fall(), MinMax::max(), sta); + return pinSlackProperty(pin, RiseFall::fall(), MinMax::max(), sta); else if (stringEqual(property, "max_rise_slack")) - return pinSlackProperty(pin, TransRiseFall::rise(), MinMax::max(), sta); + return pinSlackProperty(pin, RiseFall::rise(), MinMax::max(), sta); else if (stringEqual(property, "min_fall_slack")) - return pinSlackProperty(pin, TransRiseFall::fall(), MinMax::min(), sta); + return pinSlackProperty(pin, RiseFall::fall(), MinMax::min(), sta); else if (stringEqual(property, "min_rise_slack")) - return pinSlackProperty(pin, TransRiseFall::rise(), MinMax::min(), sta); + return pinSlackProperty(pin, RiseFall::rise(), MinMax::min(), sta); else if (stringEqual(property, "actual_fall_transition_max")) - return pinSlewProperty(pin, TransRiseFall::fall(), MinMax::max(), sta); + return pinSlewProperty(pin, RiseFall::fall(), MinMax::max(), sta); else if (stringEqual(property, "actual_rise_transition_max")) - return pinSlewProperty(pin, TransRiseFall::rise(), MinMax::max(), sta); + return pinSlewProperty(pin, RiseFall::rise(), MinMax::max(), sta); else if (stringEqual(property, "actual_rise_transition_min")) - return pinSlewProperty(pin, TransRiseFall::rise(), MinMax::min(), sta); + return pinSlewProperty(pin, RiseFall::rise(), MinMax::min(), sta); else if (stringEqual(property, "actual_fall_transition_min")) - return pinSlewProperty(pin, TransRiseFall::fall(), MinMax::min(), sta); + return pinSlewProperty(pin, RiseFall::fall(), MinMax::min(), sta); else throw PropertyUnknown("pin", property); @@ -770,17 +770,17 @@ getProperty(const Pin *pin, static PropertyValue pinSlackProperty(const Pin *pin, - const TransRiseFall *tr, + const RiseFall *rf, const MinMax *min_max, Sta *sta) { - Slack slack = sta->pinSlack(pin, tr, min_max); + Slack slack = sta->pinSlack(pin, rf, min_max); return PropertyValue(delayPropertyValue(slack, sta)); } static PropertyValue pinSlewProperty(const Pin *pin, - const TransRiseFall *tr, + const RiseFall *rf, const MinMax *min_max, Sta *sta) { @@ -789,12 +789,12 @@ pinSlewProperty(const Pin *pin, graph->pinVertices(pin, vertex, bidirect_drvr_vertex); Slew slew = min_max->initValue(); if (vertex) { - Slew vertex_slew = sta->vertexSlew(vertex, tr, min_max); + Slew vertex_slew = sta->vertexSlew(vertex, rf, min_max); if (fuzzyGreater(vertex_slew, slew, min_max)) slew = vertex_slew; } if (bidirect_drvr_vertex) { - Slew vertex_slew = sta->vertexSlew(bidirect_drvr_vertex, tr, min_max); + Slew vertex_slew = sta->vertexSlew(bidirect_drvr_vertex, rf, min_max); if (fuzzyGreater(vertex_slew, slew, min_max)) slew = vertex_slew; } @@ -832,13 +832,13 @@ getProperty(Edge *edge, return stringPrintTmp("%s -> %s", from, to); } if (stringEqual(property, "delay_min_fall")) - return edgeDelayProperty(edge, TransRiseFall::fall(), MinMax::min(), sta); + return edgeDelayProperty(edge, RiseFall::fall(), MinMax::min(), sta); else if (stringEqual(property, "delay_max_fall")) - return edgeDelayProperty(edge, TransRiseFall::fall(), MinMax::max(), sta); + return edgeDelayProperty(edge, RiseFall::fall(), MinMax::max(), sta); else if (stringEqual(property, "delay_min_rise")) - return edgeDelayProperty(edge, TransRiseFall::rise(), MinMax::min(), sta); + return edgeDelayProperty(edge, RiseFall::rise(), MinMax::min(), sta); else if (stringEqual(property, "delay_max_rise")) - return edgeDelayProperty(edge, TransRiseFall::rise(), MinMax::max(), sta); + return edgeDelayProperty(edge, RiseFall::rise(), MinMax::max(), sta); else if (stringEqual(property, "sense")) return PropertyValue(timingSenseString(edge->sense())); else if (stringEqual(property, "from_pin")) @@ -851,7 +851,7 @@ getProperty(Edge *edge, static PropertyValue edgeDelayProperty(Edge *edge, - const TransRiseFall *tr, + const RiseFall *rf, const MinMax *min_max, Sta *sta) { @@ -861,8 +861,8 @@ edgeDelayProperty(Edge *edge, TimingArcSetArcIterator arc_iter(arc_set); while (arc_iter.hasNext()) { TimingArc *arc = arc_iter.next(); - TransRiseFall *to_tr = arc->toTrans()->asRiseFall(); - if (to_tr == tr) { + RiseFall *to_rf = arc->toTrans()->asRiseFall(); + if (to_rf == rf) { for (auto corner : *sta->corners()) { DcalcAnalysisPt *dcalc_ap = corner->findDcalcAnalysisPt(min_max); ArcDelay arc_delay = sta->arcDelay(edge, arc, dcalc_ap); diff --git a/search/ReportPath.cc b/search/ReportPath.cc index 5bdc0afd..aa9eeaed 100644 --- a/search/ReportPath.cc +++ b/search/ReportPath.cc @@ -608,8 +608,8 @@ ReportPath::latchDesc(const PathEndLatchCheck *end) TimingArc *check_arc = end->checkArc(); TimingArcSet *check_set = check_arc->set(); LibertyCell *cell = check_set->from()->libertyCell(); - TransRiseFall *enable_tr = cell->latchCheckEnableTrans(check_set); - return latchDesc(enable_tr); + RiseFall *enable_rf = cell->latchCheckEnableTrans(check_set); + return latchDesc(enable_rf); } void @@ -890,10 +890,10 @@ ReportPath::reportEndpoint(const PathEndGatedClock *end, Instance *inst = network_->instance(end->vertex(this)->pin()); const char *inst_name = cmd_network_->pathName(inst); string clk_name = tgtClkName(end); - const TransRiseFall *clk_end_tr = end->targetClkEndTrans(this); - const TransRiseFall *clk_tr = - (end->minMax(this) == MinMax::max()) ? clk_end_tr : clk_end_tr->opposite(); - const char *rise_fall = asRisingFalling(clk_tr); + const RiseFall *clk_end_rf = end->targetClkEndTrans(this); + const RiseFall *clk_rf = + (end->minMax(this) == MinMax::max()) ? clk_end_rf : clk_end_rf->opposite(); + const char *rise_fall = asRisingFalling(clk_rf); // Note that target clock transition is ignored. auto reason = stdstrPrint("%s clock gating-check end-point clocked by %s", rise_fall, @@ -960,10 +960,10 @@ ReportPath::reportEndpoint(const PathEndDataCheck *end, { Instance *inst = network_->instance(end->vertex(this)->pin()); const char *inst_name = cmd_network_->pathName(inst); - const char *tgt_clk_tr = asRisingFalling(end->dataClkPath()->transition(this)); + const char *tgt_clk_rf = asRisingFalling(end->dataClkPath()->transition(this)); const char *tgt_clk_name = end->targetClk(this)->name(); auto reason = stdstrPrint("%s edge-triggered data to data check clocked by %s", - tgt_clk_tr, + tgt_clk_rf, tgt_clk_name); reportEndpoint(inst_name, reason, result); @@ -1257,7 +1257,7 @@ ReportPath::reportVerbose(MinPulseWidthCheck *check, const char * ReportPath::mpwCheckHiLow(MinPulseWidthCheck *check) { - if (check->openTransition(this) == TransRiseFall::rise()) + if (check->openTransition(this) == RiseFall::rise()) return "high"; else return "low"; @@ -1502,22 +1502,22 @@ ReportPath::reportSkewClkPath(const char *arrival_msg, ClockEdge *clk_edge = clk_path->clkEdge(this); Clock *clk = clk_edge->clock(); const EarlyLate *early_late = clk_path->minMax(this); - const TransRiseFall *clk_tr = clk_edge->transition(); - const TransRiseFall *clk_end_tr = clk_path->transition(this); - string clk_name = clkName(clk, clk_end_tr != clk_tr); + const RiseFall *clk_rf = clk_edge->transition(); + const RiseFall *clk_end_rf = clk_path->transition(this); + string clk_name = clkName(clk, clk_end_rf != clk_rf); float clk_time = clk_edge->time(); const Arrival &clk_arrival = search_->clkPathArrival(clk_path); Arrival clk_delay = clk_arrival - clk_time; PathAnalysisPt *path_ap = clk_path->pathAnalysisPt(this); const MinMax *min_max = path_ap->pathMinMax(); Vertex *clk_vertex = clk_path->vertex(this); - reportClkLine(clk, clk_name.c_str(), clk_end_tr, clk_time, min_max, result); + reportClkLine(clk, clk_name.c_str(), clk_end_rf, clk_time, min_max, result); bool is_prop = isPropagated(clk_path); if (is_prop && reportClkPath()) { const EarlyLate *early_late = TimingRole::skew()->tgtClkEarlyLate(); - if (reportGenClkSrcPath(clk_path, clk, clk_tr, min_max, early_late)) - reportGenClkSrcAndPath(clk_path, clk, clk_tr, early_late, path_ap, + if (reportGenClkSrcPath(clk_path, clk, clk_rf, min_max, early_late)) + reportGenClkSrcAndPath(clk_path, clk, clk_rf, early_late, path_ap, 0.0, 0.0, false, result); else { Arrival insertion, latency; @@ -1532,7 +1532,7 @@ ReportPath::reportSkewClkPath(const char *arrival_msg, reportLine(clkNetworkDelayIdealProp(is_prop), clk_delay, clk_arrival, early_late, result); reportLine(descriptionField(clk_vertex).c_str(), clk_arrival, - early_late, clk_end_tr, result); + early_late, clk_end_rf, result); } reportLine(arrival_msg, search_->clkPathArrival(clk_path), early_late, result); @@ -1566,19 +1566,19 @@ ReportPath::reportSlewLimitShortHeader(string &result) void ReportPath::reportSlewLimitShort(Pin *pin, - const TransRiseFall *tr, + const RiseFall *rf, Slew slew, float limit, float slack) { string result; - reportSlewLimitShort(pin, tr, slew, limit, slack, result); + reportSlewLimitShort(pin, rf, slew, limit, slack, result); report_->print(result); } void ReportPath::reportSlewLimitShort(Pin *pin, - const TransRiseFall *, + const RiseFall *, Slew slew, float limit, float slack, @@ -1594,21 +1594,21 @@ ReportPath::reportSlewLimitShort(Pin *pin, void ReportPath::reportSlewLimitVerbose(Pin *pin, const Corner *corner, - const TransRiseFall *tr, + const RiseFall *rf, Slew slew, float limit, float slack, const MinMax *min_max) { string result; - reportSlewLimitVerbose(pin, corner, tr, slew, limit, slack, min_max, result); + reportSlewLimitVerbose(pin, corner, rf, slew, limit, slack, min_max, result); report_->print(result); } void ReportPath::reportSlewLimitVerbose(Pin *pin, const Corner *, - const TransRiseFall *tr, + const RiseFall *rf, Slew slew, float limit, float slack, @@ -1618,7 +1618,7 @@ ReportPath::reportSlewLimitVerbose(Pin *pin, result += "Pin "; result += cmd_network_->pathName(pin); result += ' '; - result += tr->shortName(); + result += rf->shortName(); reportEndOfLine(result); result += min_max->asString(); @@ -1672,11 +1672,11 @@ ReportPath::reportStartpoint(const PathEnd *end, Instance *inst = network_->instance(pin); const char *inst_name = cmd_network_->pathName(inst); if (clk_edge) { - const TransRiseFall *clk_tr = clk_edge->transition(); + const RiseFall *clk_rf = clk_edge->transition(); PathRef clk_path; expanded.clkPath(clk_path); bool clk_inverted = !clk_path.isNull() - && clk_tr != clk_path.transition(this); + && clk_rf != clk_path.transition(this); string clk_name = clkName(clk, clk_inverted); const char *reg_desc = edgeRegLatchDesc(prev_edge, prev_arc); auto reason = stdstrPrint("%s clocked by %s", reg_desc, clk_name.c_str()); @@ -1845,9 +1845,9 @@ ReportPath::tgtClkName(const PathEnd *end) { ClockEdge *tgt_clk_edge = end->targetClkEdge(this); const Clock *tgt_clk = tgt_clk_edge->clock(); - const TransRiseFall *clk_tr = tgt_clk_edge->transition(); - const TransRiseFall *clk_end_tr = end->targetClkEndTrans(this); - return clkName(tgt_clk, clk_end_tr != clk_tr); + const RiseFall *clk_rf = tgt_clk_edge->transition(); + const RiseFall *clk_end_rf = end->targetClkEndTrans(this); + return clkName(tgt_clk, clk_end_rf != clk_rf); } string @@ -1865,9 +1865,9 @@ ReportPath::clkRegLatchDesc(const PathEnd *end) { // Goofy libraries can have registers with both rising and falling // clk->q timing arcs. Try and match the timing check transition. - const TransRiseFall *check_clk_tr=end->checkArc()->fromTrans()->asRiseFall(); + const RiseFall *check_clk_rf=end->checkArc()->fromTrans()->asRiseFall(); TimingArcSet *clk_set = nullptr; - TimingArcSet *clk_tr_set = nullptr; + TimingArcSet *clk_rf_set = nullptr; Vertex *tgt_clk_vertex = end->targetClkPath()->vertex(this); VertexOutEdgeIterator iter(tgt_clk_vertex, graph_); while (iter.hasNext()) { @@ -1876,20 +1876,20 @@ ReportPath::clkRegLatchDesc(const PathEnd *end) TimingRole *role = arc_set->role(); if (role == TimingRole::regClkToQ() || role == TimingRole::latchEnToQ()) { - TransRiseFall *arc_tr = arc_set->isRisingFallingEdge(); + RiseFall *arc_rf = arc_set->isRisingFallingEdge(); clk_set = arc_set; - if (arc_tr == check_clk_tr) - clk_tr_set = arc_set; + if (arc_rf == check_clk_rf) + clk_rf_set = arc_set; } } - if (clk_tr_set) - return checkRegLatchDesc(clk_tr_set->role(), - clk_tr_set->isRisingFallingEdge()); + if (clk_rf_set) + return checkRegLatchDesc(clk_rf_set->role(), + clk_rf_set->isRisingFallingEdge()); else if (clk_set) return checkRegLatchDesc(clk_set->role(), clk_set->isRisingFallingEdge()); else - return checkRegLatchDesc(TimingRole::regClkToQ(), check_clk_tr); + return checkRegLatchDesc(TimingRole::regClkToQ(), check_clk_rf); } void @@ -1931,7 +1931,7 @@ ReportPath::reportSrcClkAndPath(const Path *path, const MinMax *min_max = path->minMax(this); if (clk_edge) { Clock *clk = clk_edge->clock(); - TransRiseFall *clk_tr = clk_edge->transition(); + RiseFall *clk_rf = clk_edge->transition(); float clk_time = clk_edge->time() + time_offset; if (clk == sdc_->defaultArrivalClock()) { if (!is_path_delay) { @@ -1950,15 +1950,15 @@ ReportPath::reportSrcClkAndPath(const Path *path, Arrival clk_delay, clk_end_time; PathRef clk_path; expanded.clkPath(clk_path); - const TransRiseFall *clk_end_tr; + const RiseFall *clk_end_rf; if (!clk_path.isNull()) { clk_end_time = search_->clkPathArrival(&clk_path) + time_offset; clk_delay = clk_end_time - clk_time; - clk_end_tr = clk_path.transition(this); + clk_end_rf = clk_path.transition(this); } else { // Path from input port or clk used as data. - clk_end_tr = clk_tr; + clk_end_rf = clk_rf; clk_delay = clk_insertion + clk_latency; clk_end_time = clk_time + clk_delay; @@ -1979,24 +1979,24 @@ ReportPath::reportSrcClkAndPath(const Path *path, } } } - string clk_name = clkName(clk, clk_tr != clk_end_tr); + string clk_name = clkName(clk, clk_rf != clk_end_rf); bool clk_used_as_data = pathFromClkPin(expanded); bool is_prop = isPropagated(path); const EarlyLate *early_late = min_max; if (reportGenClkSrcPath(clk_path.isNull() ? nullptr : &clk_path, - clk, clk_tr, min_max, early_late) + clk, clk_rf, min_max, early_late) && !(path_from_input && !input_has_ref_path)) { - reportClkLine(clk, clk_name.c_str(), clk_end_tr, clk_time, + reportClkLine(clk, clk_name.c_str(), clk_end_rf, clk_time, min_max, result); const PathAnalysisPt *path_ap = path->pathAnalysisPt(this); - reportGenClkSrcAndPath(path, clk, clk_tr, early_late, path_ap, + reportGenClkSrcAndPath(path, clk, clk_rf, early_late, path_ap, time_offset, time_offset, clk_used_as_data, result); } else if (clk_used_as_data && pathFromGenPropClk(path, path->minMax(this))) { - reportClkLine(clk, clk_name.c_str(), clk_end_tr, clk_time, + reportClkLine(clk, clk_name.c_str(), clk_end_rf, clk_time, min_max, result); ClkInfo *clk_info = path->tag(search_)->clkInfo(); if (clk_info->isPropagated()) @@ -2006,13 +2006,13 @@ ReportPath::reportSrcClkAndPath(const Path *path, else if (is_prop && reportClkPath() && !(path_from_input && !input_has_ref_path)) { - reportClkLine(clk, clk_name.c_str(), clk_end_tr, clk_time, + reportClkLine(clk, clk_name.c_str(), clk_end_rf, clk_time, early_late, result); reportClkSrcLatency(clk_insertion, clk_time, early_late, result); reportPath1(path, expanded, false, time_offset, result); } else if (clk_used_as_data) { - reportClkLine(clk, clk_name.c_str(), clk_end_tr, clk_time, + reportClkLine(clk, clk_name.c_str(), clk_end_rf, clk_time, early_late, result); if (clk_insertion > 0.0) reportClkSrcLatency(clk_insertion, clk_time, early_late, result); @@ -2025,7 +2025,7 @@ ReportPath::reportSrcClkAndPath(const Path *path, clk_end_time, early_late, result); } else { - reportClkLine(clk, clk_name.c_str(), clk_end_tr, clk_time, + reportClkLine(clk, clk_name.c_str(), clk_end_rf, clk_time, min_max, result); Arrival clk_arrival = clk_end_time; reportLine(clkNetworkDelayIdealProp(is_prop), clk_delay, @@ -2065,9 +2065,9 @@ ReportPath::reportTgtClk(const PathEnd *end, float src_offset = end->sourceClkOffset(this); const ClockEdge *clk_edge = end->targetClkEdge(this); Clock *clk = clk_edge->clock(); - const TransRiseFall *clk_tr = clk_edge->transition(); - const TransRiseFall *clk_end_tr = end->targetClkEndTrans(this); - string clk_name = clkName(clk, clk_end_tr != clk_tr); + const RiseFall *clk_rf = clk_edge->transition(); + const RiseFall *clk_end_rf = end->targetClkEndTrans(this); + string clk_name = clkName(clk, clk_end_rf != clk_rf); float clk_time = prev_time + end->targetClkTime(this) + end->targetClkMcpAdjustment(this) @@ -2077,7 +2077,7 @@ ReportPath::reportTgtClk(const PathEnd *end, PathAnalysisPt *path_ap = end->pathAnalysisPt(this)->tgtClkAnalysisPt(); const MinMax *min_max = path_ap->pathMinMax(); const Path *clk_path = end->targetClkPath(); - reportClkLine(clk, clk_name.c_str(), clk_end_tr, prev_time, clk_time, + reportClkLine(clk, clk_name.c_str(), clk_end_rf, prev_time, clk_time, min_max, result); TimingRole *check_role = end->checkRole(this); if (is_prop && reportClkPath()) { @@ -2085,10 +2085,10 @@ ReportPath::reportTgtClk(const PathEnd *end, + end->targetClkOffset(this) + end->targetClkMcpAdjustment(this); const EarlyLate *early_late = check_role->tgtClkEarlyLate(); - if (reportGenClkSrcPath(clk_path, clk, clk_tr, min_max, early_late)) { + if (reportGenClkSrcPath(clk_path, clk, clk_rf, min_max, early_late)) { float insertion_offset = clk_path ? tgtClkInsertionOffet(clk_path, early_late, path_ap) : 0.0; - reportGenClkSrcAndPath(clk_path, clk, clk_tr, early_late, path_ap, + reportGenClkSrcAndPath(clk_path, clk, clk_rf, early_late, path_ap, time_offset, time_offset + insertion_offset, false, result); } @@ -2124,7 +2124,7 @@ ReportPath::reportTgtClk(const PathEnd *end, prev_time + end->targetClkArrival(this) + end->sourceClkOffset(this), - min_max, clk_end_tr, result); + min_max, clk_end_rf, result); } } } @@ -2138,12 +2138,12 @@ ReportPath::tgtClkInsertionOffet(const Path *clk_path, const Pin *src_pin = clk_info->clkSrc(); const ClockEdge *clk_edge = clk_info->clkEdge(); const Clock *clk = clk_edge->clock(); - const TransRiseFall *clk_tr = clk_edge->transition(); + const RiseFall *clk_rf = clk_edge->transition(); const MinMax *min_max = path_ap->pathMinMax(); - Arrival path_insertion = search_->clockInsertion(clk, src_pin, clk_tr, + Arrival path_insertion = search_->clockInsertion(clk, src_pin, clk_rf, min_max, min_max, path_ap); - Arrival tgt_insertion = search_->clockInsertion(clk, src_pin, clk_tr, + Arrival tgt_insertion = search_->clockInsertion(clk, src_pin, clk_rf, min_max, early_late, path_ap); return delayAsFloat(tgt_insertion - path_insertion); @@ -2173,13 +2173,13 @@ ReportPath::pathFromGenPropClk(const Path *clk_path, bool ReportPath::isGenPropClk(const Clock *clk, - const TransRiseFall *clk_tr, + const RiseFall *clk_rf, const MinMax *min_max, const EarlyLate *early_late) { float insertion; bool exists; - sdc_->clockInsertion(clk, clk->srcPin(), clk_tr, + sdc_->clockInsertion(clk, clk->srcPin(), clk_rf, min_max, early_late, insertion, exists); return !exists @@ -2189,30 +2189,30 @@ ReportPath::isGenPropClk(const Clock *clk, void ReportPath::reportClkLine(const Clock *clk, const char *clk_name, - const TransRiseFall *clk_tr, + const RiseFall *clk_rf, Arrival clk_time, const MinMax *min_max, string &result) { - reportClkLine(clk, clk_name, clk_tr, 0.0, clk_time, min_max, result); + reportClkLine(clk, clk_name, clk_rf, 0.0, clk_time, min_max, result); } void ReportPath::reportClkLine(const Clock *clk, const char *clk_name, - const TransRiseFall *clk_tr, + const RiseFall *clk_rf, Arrival prev_time, Arrival clk_time, const MinMax *min_max, string &result) { - const char *rise_fall = asRiseFall(clk_tr); + const char *rise_fall = asRiseFall(clk_rf); auto clk_msg = stdstrPrint("clock %s (%s edge)", clk_name, rise_fall); if (clk->isPropagated()) reportLine(clk_msg.c_str(), clk_time - prev_time, clk_time, min_max, result); else { // Report ideal clock slew. - float clk_slew = clk->slew(clk_tr, min_max); + float clk_slew = clk->slew(clk_rf, min_max); reportLine(clk_msg.c_str(), clk_slew, clk_time - prev_time, clk_time, min_max, result); } @@ -2221,13 +2221,13 @@ ReportPath::reportClkLine(const Clock *clk, bool ReportPath::reportGenClkSrcPath(const Path *clk_path, Clock *clk, - const TransRiseFall *clk_tr, + const RiseFall *clk_rf, const MinMax *min_max, const EarlyLate *early_late) { bool from_gen_prop_clk = clk_path ? pathFromGenPropClk(clk_path, early_late) - : isGenPropClk(clk, clk_tr, min_max, early_late); + : isGenPropClk(clk, clk_rf, min_max, early_late); return from_gen_prop_clk && format_ == ReportPathFormat::full_clock_expanded; } @@ -2235,7 +2235,7 @@ ReportPath::reportGenClkSrcPath(const Path *clk_path, void ReportPath::reportGenClkSrcAndPath(const Path *path, Clock *clk, - const TransRiseFall *clk_tr, + const RiseFall *clk_rf, const EarlyLate *early_late, const PathAnalysisPt *path_ap, float time_offset, @@ -2246,8 +2246,8 @@ ReportPath::reportGenClkSrcAndPath(const Path *path, const Pin *clk_pin = path ? path->clkInfo(search_)->clkSrc() : clk->defaultPin(); - float gclk_time = clk->edge(clk_tr)->time() + time_offset; - bool skip_first_path = reportGenClkSrcPath1(clk, clk_pin, clk_tr, + float gclk_time = clk->edge(clk_rf)->time() + time_offset; + bool skip_first_path = reportGenClkSrcPath1(clk, clk_pin, clk_rf, early_late, path_ap, gclk_time, time_offset, clk_used_as_data, result); @@ -2261,7 +2261,7 @@ ReportPath::reportGenClkSrcAndPath(const Path *path, bool ReportPath::reportGenClkSrcPath1(Clock *clk, const Pin *clk_pin, - const TransRiseFall *clk_tr, + const RiseFall *clk_rf, const EarlyLate *early_late, const PathAnalysisPt *path_ap, float gclk_time, @@ -2272,24 +2272,24 @@ ReportPath::reportGenClkSrcPath1(Clock *clk, PathAnalysisPt *insert_ap = path_ap->insertionAnalysisPt(early_late); PathVertex src_path; const MinMax *min_max = path_ap->pathMinMax(); - search_->genclks()->srcPath(clk, clk_pin, clk_tr, insert_ap, src_path); + search_->genclks()->srcPath(clk, clk_pin, clk_rf, insert_ap, src_path); if (!src_path.isNull()) { ClkInfo *src_clk_info = src_path.clkInfo(search_); ClockEdge *src_clk_edge = src_clk_info->clkEdge(); Clock *src_clk = src_clk_info->clock(); bool skip_first_path = false; - const TransRiseFall *src_clk_tr = src_clk_edge->transition(); + const RiseFall *src_clk_rf = src_clk_edge->transition(); const Pin *src_clk_pin = src_clk_info->clkSrc(); if (src_clk->isGeneratedWithPropagatedMaster() && src_clk_info->isPropagated()) { skip_first_path = reportGenClkSrcPath1(src_clk, src_clk_pin, - src_clk_tr, early_late, path_ap, + src_clk_rf, early_late, path_ap, gclk_time, time_offset, clk_used_as_data, result); } else { const Arrival insertion = search_->clockInsertion(src_clk, src_clk_pin, - src_clk_tr, + src_clk_rf, path_ap->pathMinMax(), early_late, path_ap); reportClkSrcLatency(insertion, gclk_time, early_late, result); @@ -2299,7 +2299,7 @@ ReportPath::reportGenClkSrcPath1(Clock *clk, reportPath4(&src_path, src_expanded, skip_first_path, true, clk_used_as_data, gclk_time, result); PathAnalysisPt *pll_ap=path_ap->insertionAnalysisPt(min_max->opposite()); - Arrival pll_delay = search_->genclks()->pllDelay(clk, clk_tr, pll_ap); + Arrival pll_delay = search_->genclks()->pllDelay(clk, clk_rf, pll_ap); size_t path_length = src_expanded.size(); if (path_length < 2) internalError("generated clock pll source path too short.\n"); @@ -2345,19 +2345,19 @@ ReportPath::reportPathLine(const Path *path, Vertex *vertex = path->vertex(this); Pin *pin = vertex->pin(); auto what = descriptionField(vertex); - const TransRiseFall *tr = path->transition(this); + const RiseFall *rf = path->transition(this); bool is_driver = network_->isDriver(pin); PathAnalysisPt *path_ap = path->pathAnalysisPt(this); const EarlyLate *early_late = path_ap->pathMinMax(); DcalcAnalysisPt *dcalc_ap = path_ap->dcalcAnalysisPt(); DcalcAPIndex ap_index = dcalc_ap->index(); - Slew slew = graph_->slew(vertex, tr, ap_index); + Slew slew = graph_->slew(vertex, rf, ap_index); float cap = field_blank_; // Don't show capacitance field for input pins. if (is_driver && field_capacitance_->enabled()) - cap = loadCap(pin, tr, dcalc_ap); + cap = loadCap(pin, rf, dcalc_ap); reportLine(what.c_str(), cap, slew, field_blank_, - incr, time, false, early_late, tr, line_case, result); + incr, time, false, early_late, rf, line_case, result); } void @@ -2610,8 +2610,8 @@ ReportPath::reportPath5(const Path *path, if (is_clk_start || report_clk_path || !is_clk) { - const TransRiseFall *tr = path1->transition(this); - Slew slew = graph_->slew(vertex, tr, ap_index); + const RiseFall *rf = path1->transition(this); + Slew slew = graph_->slew(vertex, rf, ap_index); if (prev_arc == nullptr) { // First path. reportInputExternalDelay(path1, time_offset, result); @@ -2620,7 +2620,7 @@ ReportPath::reportPath5(const Path *path, if (network_->isTopLevelPort(pin) && next_path && !nextArcAnnotated(next_path, next_index, expanded, ap_index) - && hasExtInputDriver(pin, tr, min_max)) { + && hasExtInputDriver(pin, rf, min_max)) { // Pin is an input port with drive_cell/drive_resistance. // The delay calculator annotates wire delays on the edges // from the input to the loads. Report the wire delay on the @@ -2655,8 +2655,8 @@ ReportPath::reportPath5(const Path *path, time = search_->clkPathArrival(path1) + time_offset; if (src_clk_edge) { Clock *src_clk = src_clk_edge->clock(); - TransRiseFall *src_clk_tr = src_clk_edge->transition(); - slew = src_clk->slew(src_clk_tr, min_max); + RiseFall *src_clk_rf = src_clk_edge->transition(); + slew = src_clk->slew(src_clk_rf, min_max); } } line_case = "clk_start"; @@ -2669,8 +2669,8 @@ ReportPath::reportPath5(const Path *path, time = prev_time; ClockEdge *src_clk_edge = path->clkEdge(this); Clock *src_clk = src_clk_edge->clock(); - TransRiseFall *src_clk_tr = src_clk_edge->transition(); - slew = src_clk->slew(src_clk_tr, min_max); + RiseFall *src_clk_rf = src_clk_edge->transition(); + slew = src_clk->slew(src_clk_rf, min_max); line_case = "clk_ideal"; } else if (is_clk && !is_clk_start) { @@ -2695,12 +2695,12 @@ ReportPath::reportPath5(const Path *path, float cap = field_blank_; // Don't show capacitance field for input pins. if (is_driver && field_capacitance_->enabled()) - cap = loadCap(pin, tr, dcalc_ap); + cap = loadCap(pin, rf, dcalc_ap); auto what = descriptionField(vertex); if (report_net_ && is_driver) { // Capacitance field is reported on the net line. reportLine(what.c_str(), field_blank_, slew, field_blank_, - incr, time, false, min_max, tr, line_case, result); + incr, time, false, min_max, rf, line_case, result); string what2; if (network_->isTopLevelPort(pin)) { const char *pin_name = cmd_network_->pathName(pin); @@ -2723,7 +2723,7 @@ ReportPath::reportPath5(const Path *path, } else reportLine(what.c_str(), cap, slew, field_blank_, - incr, time, false, min_max, tr, line_case, result); + incr, time, false, min_max, rf, line_case, result); prev_time = time; } } @@ -2792,14 +2792,14 @@ ReportPath::drvrFanout(Vertex *drvr, bool ReportPath::hasExtInputDriver(const Pin *pin, - const TransRiseFall *tr, + const RiseFall *rf, const MinMax *min_max) { Port *port = network_->port(pin); InputDrive *drive = sdc_->findInputDrive(port); return (drive - && (drive->hasDriveResistance(tr, min_max) - || drive->hasDriveCell(tr, min_max))); + && (drive->hasDriveResistance(rf, min_max) + || drive->hasDriveCell(rf, min_max))); } void @@ -2809,7 +2809,7 @@ ReportPath::reportInputExternalDelay(const Path *first_path, { const Pin *first_pin = first_path->pin(graph_); if (!pathFromClkPin(first_path, first_pin)) { - const TransRiseFall *tr = first_path->transition(this); + const RiseFall *rf = first_path->transition(this); Arrival time = first_path->arrival(this) + time_offset; const EarlyLate *early_late = first_path->minMax(this); InputDelay *input_delay = pathInputDelay(first_path); @@ -2831,12 +2831,12 @@ ReportPath::reportInputExternalDelay(const Path *first_path, } } float input_arrival = - input_delay->delays()->value(tr, first_path->minMax(this)); + input_delay->delays()->value(rf, first_path->minMax(this)); reportLine("input external delay", input_arrival, time, - early_late, tr, result); + early_late, rf, result); } else if (network_->isTopLevelPort(first_pin)) - reportLine("input external delay", 0.0, time, early_late, tr, result); + reportLine("input external delay", 0.0, time, early_late, rf, result); } } @@ -2854,11 +2854,11 @@ ReportPath::pathInputDelayRefPath(const Path *path, PathRef &ref_path) { Pin *ref_pin = input_delay->refPin(); - TransRiseFall *ref_tr = input_delay->refTransition(); + RiseFall *ref_rf = input_delay->refTransition(); Vertex *ref_vertex = graph_->pinDrvrVertex(ref_pin); const PathAnalysisPt *path_ap = path->pathAnalysisPt(this); const ClockEdge *clk_edge = path->clkEdge(this); - VertexPathIterator path_iter(ref_vertex, ref_tr, path_ap, this); + VertexPathIterator path_iter(ref_vertex, ref_rf, path_ap, this); while (path_iter.hasNext()) { PathVertex *path = path_iter.next(); if (path->isClock(this) @@ -2871,13 +2871,13 @@ ReportPath::pathInputDelayRefPath(const Path *path, float ReportPath::loadCap(Pin *drvr_pin, - const TransRiseFall *tr, + const RiseFall *rf, DcalcAnalysisPt *dcalc_ap) { Parasitic *parasitic = nullptr; if (arc_delay_calc_) - parasitic = arc_delay_calc_->findParasitic(drvr_pin, tr, dcalc_ap); - return graph_delay_calc_->loadCap(drvr_pin, parasitic, tr, dcalc_ap); + parasitic = arc_delay_calc_->findParasitic(drvr_pin, rf, dcalc_ap); + return graph_delay_calc_->loadCap(drvr_pin, parasitic, rf, dcalc_ap); } //////////////////////////////////////////////////////////////// @@ -2929,11 +2929,11 @@ void ReportPath::reportLine(const char *what, Delay total, const EarlyLate *early_late, - const TransRiseFall *tr, + const RiseFall *rf, string &result) { reportLine(what, field_blank_, field_blank_, field_blank_, - field_blank_, total, false, early_late, tr, nullptr, result); + field_blank_, total, false, early_late, rf, nullptr, result); } // Report increment, and total. @@ -2954,11 +2954,11 @@ ReportPath::reportLine(const char *what, Delay incr, Delay total, const EarlyLate *early_late, - const TransRiseFall *tr, + const RiseFall *rf, string &result) { reportLine(what, field_blank_, field_blank_, field_blank_, - incr, total, false, early_late, tr, nullptr, result); + incr, total, false, early_late, rf, nullptr, result); } // Report slew, increment, and total. @@ -2983,7 +2983,7 @@ ReportPath::reportLine(const char *what, Delay total, bool total_with_minus, const EarlyLate *early_late, - const TransRiseFall *tr, + const RiseFall *rf, const char *line_case, string &result) { @@ -3021,8 +3021,8 @@ ReportPath::reportLine(const char *what, reportFieldDelay(total, early_late, field, result); } else if (field == field_edge_) { - if (tr) - reportField(tr->shortName(), field, result); + if (rf) + reportField(rf->shortName(), field, result); // Compatibility kludge; suppress trailing spaces. else if (field_iter.hasNext()) reportFieldBlank(field, result); @@ -3267,18 +3267,18 @@ ReportPath::reportClkPath() const //////////////////////////////////////////////////////////////// const char * -ReportPath::asRisingFalling(const TransRiseFall *tr) +ReportPath::asRisingFalling(const RiseFall *rf) { - if (tr == TransRiseFall::rise()) + if (rf == RiseFall::rise()) return "rising"; else return "falling"; } const char * -ReportPath::asRiseFall(const TransRiseFall *tr) +ReportPath::asRiseFall(const RiseFall *rf) { - if (tr == TransRiseFall::rise()) + if (rf == RiseFall::rise()) return "rise"; else return "fall"; @@ -3296,10 +3296,10 @@ ReportPath::edgeRegLatchDesc(Edge *first_edge, if (cell) { LibertyPort *enable_port; FuncExpr *enable_func; - TransRiseFall *enable_tr; + RiseFall *enable_rf; cell->latchEnable(first_edge->timingArcSet(), - enable_port, enable_func, enable_tr); - return latchDesc(enable_tr); + enable_port, enable_func, enable_rf); + return latchDesc(enable_rf); } } else if (role == TimingRole::regClkToQ()) @@ -3312,33 +3312,33 @@ ReportPath::edgeRegLatchDesc(Edge *first_edge, const char * ReportPath::checkRegLatchDesc(const TimingRole *role, - const TransRiseFall *clk_tr) const + const RiseFall *clk_rf) const { if (role == TimingRole::regClkToQ()) - return regDesc(clk_tr); + return regDesc(clk_rf); else if (role == TimingRole::latchEnToQ() || role == TimingRole::latchDtoQ()) - return latchDesc(clk_tr); + return latchDesc(clk_rf); else // Default when we don't know better. return "edge-triggered flip-flop"; } const char * -ReportPath::regDesc(const TransRiseFall *clk_tr) const +ReportPath::regDesc(const RiseFall *clk_rf) const { - if (clk_tr == TransRiseFall::rise()) + if (clk_rf == RiseFall::rise()) return "rising edge-triggered flip-flop"; - else if (clk_tr == TransRiseFall::fall()) + else if (clk_rf == RiseFall::fall()) return "falling edge-triggered flip-flop"; else return "edge-triggered flip-flop"; } const char * -ReportPath::latchDesc(const TransRiseFall *clk_tr) const +ReportPath::latchDesc(const RiseFall *clk_rf) const { - return (clk_tr == TransRiseFall::rise()) + return (clk_rf == RiseFall::rise()) ? "positive level-sensitive latch" : "negative level-sensitive latch"; } diff --git a/search/ReportPath.hh b/search/ReportPath.hh index 6c5540bd..2c83f0ba 100644 --- a/search/ReportPath.hh +++ b/search/ReportPath.hh @@ -138,26 +138,26 @@ public: void reportSlewLimitShortHeader(); void reportSlewLimitShortHeader(string &result); void reportSlewLimitShort(Pin *pin, - const TransRiseFall *tr, + const RiseFall *rf, Slew slew, float limit, float slack); void reportSlewLimitShort(Pin *pin, const - TransRiseFall *tr, + RiseFall *rf, Slew slew, float limit, float slack, string &result); void reportSlewLimitVerbose(Pin *pin, const Corner *corner, - const TransRiseFall *tr, + const RiseFall *rf, Slew slew, float limit, float slack, const MinMax *min_max); void reportSlewLimitVerbose(Pin *pin, const Corner *corner, - const TransRiseFall *tr, + const RiseFall *rf, Slew slew, float limit, float slack, @@ -254,7 +254,7 @@ protected: bool pathFromGenPropClk(const Path *clk_path, const EarlyLate *early_late); bool isGenPropClk(const Clock *clk, - const TransRiseFall *clk_tr, + const RiseFall *clk_rf, const MinMax *min_max, const EarlyLate *early_late); void reportSrcClkAndPath(const Path *path, @@ -265,19 +265,21 @@ protected: bool is_path_delay, string &result); bool reportGenClkSrcPath(const Path *clk_path, Clock *clk, - const TransRiseFall *clk_tr, + const RiseFall *clk_rf, const MinMax *min_max, const EarlyLate *early_late); - void reportGenClkSrcAndPath(const Path *path, Clock *clk, - const TransRiseFall *clk_tr, + void reportGenClkSrcAndPath(const Path *path, + Clock *clk, + const RiseFall *clk_rf, const EarlyLate *early_late, const PathAnalysisPt *path_ap, float time_offset, float path_time_offset, bool clk_used_as_data, string &result); - bool reportGenClkSrcPath1(Clock *clk, const Pin *clk_pin, - const TransRiseFall *clk_tr, + bool reportGenClkSrcPath1(Clock *clk, + const Pin *clk_pin, + const RiseFall *clk_rf, const EarlyLate *early_late, const PathAnalysisPt *path_ap, float gclk_time, @@ -301,13 +303,13 @@ protected: string &result); void reportClkLine(const Clock *clk, const char *clk_name, - const TransRiseFall *clk_tr, + const RiseFall *clk_rf, Arrival clk_time, const MinMax *min_max, string &result); void reportClkLine(const Clock *clk, const char *clk_name, - const TransRiseFall *clk_tr, + const RiseFall *clk_rf, Arrival prev_time, Arrival clk_time, const MinMax *min_max, @@ -379,7 +381,7 @@ protected: void reportLine(const char *what, Delay total, const EarlyLate *early_late, - const TransRiseFall *tr, + const RiseFall *rf, string &result); void reportLine(const char *what, Delay incr, @@ -390,7 +392,7 @@ protected: Delay incr, Delay total, const EarlyLate *early_late, - const TransRiseFall *tr, + const RiseFall *rf, string &result); void reportLine(const char *what, Slew slew, @@ -406,7 +408,7 @@ protected: Delay total, bool total_with_minus, const EarlyLate *early_late, - const TransRiseFall *tr, + const RiseFall *rf, const char *line_case, string &result); void reportLineTotal(const char *what, @@ -465,10 +467,10 @@ protected: string clkName(const Clock *clk, bool inverted); bool hasExtInputDriver(const Pin *pin, - const TransRiseFall *tr, + const RiseFall *rf, const MinMax *min_max); float loadCap(Pin *drvr_pin, - const TransRiseFall *tr, + const RiseFall *rf, DcalcAnalysisPt *dcalc_ap); float drvrFanout(Vertex *drvr, const MinMax *min_max); @@ -479,9 +481,9 @@ protected: const char *edgeRegLatchDesc(Edge *edge, TimingArc *arc); const char *checkRegLatchDesc(const TimingRole *role, - const TransRiseFall *clk_tr) const; - const char *regDesc(const TransRiseFall *clk_tr) const; - const char *latchDesc(const TransRiseFall *clk_tr) const; + const RiseFall *clk_rf) const; + const char *regDesc(const RiseFall *clk_rf) const; + const char *latchDesc(const RiseFall *clk_rf) const; void pathClkPath(const Path *path, PathRef &clk_path) const; bool isPropagated(const Path *clk_path); @@ -508,8 +510,8 @@ protected: InputDelay *input_delay, // Return value. PathRef &ref_path); - const char *asRisingFalling(const TransRiseFall *tr); - const char *asRiseFall(const TransRiseFall *tr); + const char *asRisingFalling(const RiseFall *rf); + const char *asRiseFall(const RiseFall *rf); // Path options. ReportPathFormat format_; diff --git a/search/Search.cc b/search/Search.cc index a75a1cc8..b32f66f8 100644 --- a/search/Search.cc +++ b/search/Search.cc @@ -141,11 +141,11 @@ DynLoopSrchPred::hasPendingLoopPaths(Edge *edge, int arrival_index; arrival_iter.next(from_tag, arrival_index); if (from_tag->isLoop()) { - // Loop false path exceptions apply to rise/fall edges so to_tr + // Loop false path exceptions apply to rise/fall edges so to_rf // does not matter. PathAPIndex path_ap_index = from_tag->pathAPIndex(); PathAnalysisPt *path_ap = corners->findPathAnalysisPt(path_ap_index); - Tag *to_tag = search->thruTag(from_tag, edge, TransRiseFall::rise(), + Tag *to_tag = search->thruTag(from_tag, edge, RiseFall::rise(), path_ap->pathMinMax(), path_ap); if (to_tag && (prev_tag_group == nullptr @@ -624,7 +624,7 @@ Search::seedFilterStarts() ExceptionPt *first_pt = filter_->firstPt(); PinSet first_pins; first_pt->allPins(network_, &first_pins); - for (auto pin : first_pins) { + for (Pin *pin : first_pins) { if (network_->isHierarchical(pin)) { SeedFaninsThruHierPin visitor(graph_, this); visitDrvrLoadsThruHierPin(pin, network_, &visitor); @@ -810,7 +810,7 @@ Search::seedClkVertexArrivals() { PinSet clk_pins; findClkVertexPins(clk_pins); - for (auto pin : clk_pins) { + for (Pin *pin : clk_pins) { Vertex *vertex, *bidirect_drvr_vertex; graph_->pinVertices(pin, vertex, bidirect_drvr_vertex); seedClkVertexArrivals(pin, vertex); @@ -833,18 +833,18 @@ Search::seedClkVertexArrivals(const Pin *pin, Arrival Search::clockInsertion(const Clock *clk, const Pin *pin, - const TransRiseFall *tr, + const RiseFall *rf, const MinMax *min_max, const EarlyLate *early_late, const PathAnalysisPt *path_ap) const { float insert; bool exists; - sdc_->clockInsertion(clk, pin, tr, min_max, early_late, insert, exists); + sdc_->clockInsertion(clk, pin, rf, min_max, early_late, insert, exists); if (exists) return insert; else if (clk->isGeneratedWithPropagatedMaster()) - return genclks_->insertionDelay(clk, pin, tr, early_late, path_ap); + return genclks_->insertionDelay(clk, pin, rf, early_late, path_ap); else return 0.0; } @@ -886,12 +886,12 @@ Search::visitStartpoints(VertexVisitor *visitor) } // Register clk pins. - for (auto vertex : *graph_->regClkVertices()) + for (Vertex *vertex : *graph_->regClkVertices()) visitor->visit(vertex); auto startpoints = sdc_->pathDelayInternalStartpoints(); if (startpoints) { - for (auto pin : *startpoints) { + for (Pin *pin : *startpoints) { Vertex *vertex = graph_->pinDrvrVertex(pin); visitor->visit(vertex); } @@ -901,7 +901,7 @@ Search::visitStartpoints(VertexVisitor *visitor) void Search::visitEndpoints(VertexVisitor *visitor) { - for (auto end : *endpoints()) { + for (Vertex *end : *endpoints()) { Pin *pin = end->pin(); // Filter register clock pins (fails on set_max_delay -from clk_src). if (!network_->isRegClkPin(pin) @@ -945,7 +945,7 @@ Search::clearPendingLatchOutputs() void Search::enqueuePendingLatchOutputs() { - for (auto latch_vertex : pending_latch_outputs_) + for (Vertex *latch_vertex : pending_latch_outputs_) arrival_iter_->enqueue(latch_vertex); clearPendingLatchOutputs(); } @@ -1169,7 +1169,7 @@ ArrivalVisitor::constrainedRequiredsInvalid(Vertex *vertex, // Data checks (vertex does not need to be a clk). DataCheckSet *data_checks = sdc->dataChecksFrom(pin); if (data_checks) { - for (auto data_check : *data_checks) { + for (DataCheck *data_check : *data_checks) { Pin *to = data_check->to(); search->requiredInvalid(to); } @@ -1178,7 +1178,7 @@ ArrivalVisitor::constrainedRequiredsInvalid(Vertex *vertex, if (is_clk && sdc->gatedClkChecksEnabled()) { PinSet enable_pins; search->gatedClk()->gatedClkEnables(vertex, enable_pins); - for (auto enable : enable_pins) + for (Pin *enable : enable_pins) search->requiredInvalid(enable); } } @@ -1215,14 +1215,14 @@ Search::arrivalsChanged(Vertex *vertex, bool ArrivalVisitor::visitFromToPath(const Pin *, Vertex *from_vertex, - const TransRiseFall *from_tr, + const RiseFall *from_rf, Tag *from_tag, PathVertex *from_path, Edge *, TimingArc *, ArcDelay arc_delay, Vertex *, - const TransRiseFall *to_tr, + const RiseFall *to_rf, Tag *to_tag, Arrival &to_arrival, const MinMax *min_max, @@ -1233,8 +1233,8 @@ ArrivalVisitor::visitFromToPath(const Pin *, debugPrint1(debug, "search", 3, " %s\n", from_vertex->name(sdc_network)); debugPrint3(debug, "search", 3, " %s -> %s %s\n", - from_tr->asString(), - to_tr->asString(), + from_rf->asString(), + to_rf->asString(), min_max->asString()); debugPrint1(debug, "search", 3, " from tag: %s\n", from_tag->asString(sta_)); @@ -1378,14 +1378,14 @@ Search::seedArrivals() findRootVertices(vertices); findInputDrvrVertices(vertices); - for (auto vertex : vertices) + for (Vertex *vertex : vertices) seedArrival(vertex); } void Search::findClockVertices(VertexSet &vertices) { - for (auto clk : sdc_->clks()) { + for (Clock *clk : sdc_->clks()) { for (Pin *pin : clk->leafPins()) { Vertex *vertex, *bidirect_drvr_vertex; graph_->pinVertices(pin, vertex, bidirect_drvr_vertex); @@ -1399,7 +1399,7 @@ Search::findClockVertices(VertexSet &vertices) void Search::seedInvalidArrivals() { - for (auto vertex : invalid_arrivals_) + for (Vertex *vertex : invalid_arrivals_) seedArrival(vertex); invalid_arrivals_.clear(); } @@ -1458,7 +1458,7 @@ Search::seedArrival(Vertex *vertex) void Search::findClkVertexPins(PinSet &clk_pins) { - for (auto clk : sdc_->clks()) { + for (Clock *clk : sdc_->clks()) { for (Pin *pin : clk->leafPins()) { clk_pins.insert(pin); } @@ -1470,22 +1470,22 @@ Search::seedClkArrivals(const Pin *pin, Vertex *vertex, TagGroupBldr *tag_bldr) { - for (auto clk : *sdc_->findLeafPinClocks(pin)) { + for (Clock *clk : *sdc_->findLeafPinClocks(pin)) { debugPrint2(debug_, "search", 2, "arrival seed clk %s pin %s\n", clk->name(), network_->pathName(pin)); - for (auto path_ap : corners_->pathAnalysisPts()) { + for (PathAnalysisPt *path_ap : corners_->pathAnalysisPts()) { const MinMax *min_max = path_ap->pathMinMax(); - for (auto tr : TransRiseFall::range()) { - ClockEdge *clk_edge = clk->edge(tr); + for (RiseFall *rf : RiseFall::range()) { + ClockEdge *clk_edge = clk->edge(rf); const EarlyLate *early_late = min_max; if (clk->isGenerated() && clk->masterClk() == nullptr) - seedClkDataArrival(pin, tr, clk, clk_edge, min_max, path_ap, + seedClkDataArrival(pin, rf, clk, clk_edge, min_max, path_ap, 0.0, tag_bldr); else { - Arrival insertion = clockInsertion(clk, pin, tr, min_max, + Arrival insertion = clockInsertion(clk, pin, rf, min_max, early_late, path_ap); - seedClkArrival(pin, tr, clk, clk_edge, min_max, path_ap, + seedClkArrival(pin, rf, clk, clk_edge, min_max, path_ap, insertion, tag_bldr); } } @@ -1496,7 +1496,7 @@ Search::seedClkArrivals(const Pin *pin, void Search::seedClkArrival(const Pin *pin, - const TransRiseFall *tr, + const RiseFall *rf, Clock *clk, ClockEdge *clk_edge, const MinMax *min_max, @@ -1508,11 +1508,11 @@ Search::seedClkArrival(const Pin *pin, float latency = 0.0; bool latency_exists; // Check for clk pin latency. - sdc_->clockLatency(clk, pin, tr, min_max, + sdc_->clockLatency(clk, pin, rf, min_max, latency, latency_exists); if (!latency_exists) { // Check for clk latency (lower priority). - sdc_->clockLatency(clk, tr, min_max, + sdc_->clockLatency(clk, rf, min_max, latency, latency_exists); if (latency_exists) { // Propagated pin overrides latency on clk. @@ -1532,21 +1532,21 @@ Search::seedClkArrival(const Pin *pin, uncertainties = clk->uncertainties(); // Propagate liberty "pulse_clock" transition to transitive fanout. LibertyPort *port = network_->libertyPort(pin); - TransRiseFall *pulse_clk_sense = (port ? port->pulseClkSense() : nullptr); + RiseFall *pulse_clk_sense = (port ? port->pulseClkSense() : nullptr); ClkInfo *clk_info = findClkInfo(clk_edge, pin, is_propagated, nullptr, false, pulse_clk_sense, insertion, latency, uncertainties, path_ap, nullptr); // Only false_paths -from apply to clock tree pins. ExceptionStateSet *states = nullptr; - sdc_->exceptionFromClkStates(pin,tr,clk,tr,min_max,states); - Tag *tag = findTag(tr, path_ap, clk_info, true, nullptr, false, states, true); + sdc_->exceptionFromClkStates(pin,rf,clk,rf,min_max,states); + Tag *tag = findTag(rf, path_ap, clk_info, true, nullptr, false, states, true); Arrival arrival(clk_edge->time() + insertion); tag_bldr->setArrival(tag, arrival, nullptr); } void Search::seedClkDataArrival(const Pin *pin, - const TransRiseFall *tr, + const RiseFall *rf, Clock *clk, ClockEdge *clk_edge, const MinMax *min_max, @@ -1554,7 +1554,7 @@ Search::seedClkDataArrival(const Pin *pin, Arrival insertion, TagGroupBldr *tag_bldr) { - Tag *tag = clkDataTag(pin, clk, tr, clk_edge, insertion, min_max, path_ap); + Tag *tag = clkDataTag(pin, clk, rf, clk_edge, insertion, min_max, path_ap); if (tag) { // Data arrivals include insertion delay. Arrival arrival(clk_edge->time() + insertion); @@ -1565,19 +1565,19 @@ Search::seedClkDataArrival(const Pin *pin, Tag * Search::clkDataTag(const Pin *pin, Clock *clk, - const TransRiseFall *tr, + const RiseFall *rf, ClockEdge *clk_edge, Arrival insertion, const MinMax *min_max, const PathAnalysisPt *path_ap) { ExceptionStateSet *states = nullptr; - if (sdc_->exceptionFromStates(pin, tr, clk, tr, min_max, states)) { + if (sdc_->exceptionFromStates(pin, rf, clk, rf, min_max, states)) { bool is_propagated = (clk->isPropagated() || sdc_->isPropagatedClock(pin)); ClkInfo *clk_info = findClkInfo(clk_edge, pin, is_propagated, insertion, path_ap); - return findTag(tr, path_ap, clk_info, false, nullptr, false, states, true); + return findTag(rf, path_ap, clk_info, false, nullptr, false, states, true); } else return nullptr; @@ -1592,10 +1592,10 @@ Search::makeUnclkedPaths(Vertex *vertex, { bool search_from = false; const Pin *pin = vertex->pin(); - for (auto path_ap : corners_->pathAnalysisPts()) { + for (PathAnalysisPt *path_ap : corners_->pathAnalysisPts()) { const MinMax *min_max = path_ap->pathMinMax(); - for (auto tr : TransRiseFall::range()) { - Tag *tag = fromUnclkedInputTag(pin, tr, min_max, path_ap, + for (RiseFall *rf : RiseFall::range()) { + Tag *tag = fromUnclkedInputTag(pin, rf, min_max, path_ap, is_segment_start); if (tag) { tag_bldr->setArrival(tag, delay_zero, nullptr); @@ -1610,7 +1610,7 @@ Search::makeUnclkedPaths(Vertex *vertex, void Search::findRootVertices(VertexSet &vertices) { - for (auto vertex : levelize_->roots()) { + for (Vertex *vertex : levelize_->roots()) { const Pin *pin = vertex->pin(); if (!sdc_->isLeafPinClock(pin) && !sdc_->hasInputDelay(pin) @@ -1764,11 +1764,11 @@ Search::seedInputDelayArrival(const Pin *pin, clk_edge = sdc_->defaultArrivalClockEdge(); if (ref_pin) { Vertex *ref_vertex = graph_->pinLoadVertex(ref_pin); - for (auto path_ap : corners_->pathAnalysisPts()) { + for (PathAnalysisPt *path_ap : corners_->pathAnalysisPts()) { const MinMax *min_max = path_ap->pathMinMax(); - TransRiseFall *ref_tr = input_delay->refTransition(); + RiseFall *ref_rf = input_delay->refTransition(); const Clock *clk = input_delay->clock(); - VertexPathIterator ref_path_iter(ref_vertex, ref_tr, path_ap, this); + VertexPathIterator ref_path_iter(ref_vertex, ref_rf, path_ap, this); while (ref_path_iter.hasNext()) { Path *ref_path = ref_path_iter.next(); if (ref_path->isClock(this) @@ -1785,7 +1785,7 @@ Search::seedInputDelayArrival(const Pin *pin, } } else { - for (auto path_ap : corners_->pathAnalysisPts()) { + for (PathAnalysisPt *path_ap : corners_->pathAnalysisPts()) { const MinMax *min_max = path_ap->pathMinMax(); float clk_arrival, clk_insertion, clk_latency; inputDelayClkArrival(input_delay, clk_edge, min_max, path_ap, @@ -1816,11 +1816,11 @@ Search::inputDelayRefPinArrival(Path *ref_path, ref_latency = clk_info->latency(); } else { - const TransRiseFall *clk_tr = clk_edge->transition(); + const RiseFall *clk_rf = clk_edge->transition(); const EarlyLate *early_late = min_max; // Input delays from ideal clk reference pins include clock // insertion delay but not latency. - ref_insertion = sdc_->clockInsertion(clk, clk_tr, min_max, early_late); + ref_insertion = sdc_->clockInsertion(clk, clk_rf, min_max, early_late); ref_arrival = clk_edge->time() + ref_insertion; ref_latency = 0.0; } @@ -1838,19 +1838,19 @@ Search::seedInputDelayArrival(const Pin *pin, PathAnalysisPt *path_ap, TagGroupBldr *tag_bldr) { - for (auto tr : TransRiseFall::range()) { + for (RiseFall *rf : RiseFall::range()) { if (input_delay) { float delay; bool exists; - input_delay->delays()->value(tr, min_max, delay, exists); + input_delay->delays()->value(rf, min_max, delay, exists); if (exists) - seedInputDelayArrival(pin, tr, clk_arrival + delay, + seedInputDelayArrival(pin, rf, clk_arrival + delay, input_delay, clk_edge, clk_insertion, clk_latency, is_segment_start, min_max, path_ap, tag_bldr); } else - seedInputDelayArrival(pin, tr, 0.0, nullptr, clk_edge, + seedInputDelayArrival(pin, rf, 0.0, nullptr, clk_edge, clk_insertion, clk_latency, is_segment_start, min_max, path_ap, tag_bldr); } @@ -1858,7 +1858,7 @@ Search::seedInputDelayArrival(const Pin *pin, void Search::seedInputDelayArrival(const Pin *pin, - const TransRiseFall *tr, + const RiseFall *rf, float arrival, InputDelay *input_delay, ClockEdge *clk_edge, @@ -1869,7 +1869,7 @@ Search::seedInputDelayArrival(const Pin *pin, PathAnalysisPt *path_ap, TagGroupBldr *tag_bldr) { - Tag *tag = inputDelayTag(pin, tr, clk_edge, clk_insertion, clk_latency, + Tag *tag = inputDelayTag(pin, rf, clk_edge, clk_insertion, clk_latency, input_delay, is_segment_start, min_max, path_ap); if (tag) tag_bldr->setArrival(tag, arrival, nullptr); @@ -1890,17 +1890,17 @@ Search::inputDelayClkArrival(InputDelay *input_delay, if (input_delay && clk_edge) { clk_arrival = clk_edge->time(); Clock *clk = clk_edge->clock(); - TransRiseFall *clk_tr = clk_edge->transition(); + RiseFall *clk_rf = clk_edge->transition(); if (!input_delay->sourceLatencyIncluded()) { const EarlyLate *early_late = min_max; clk_insertion = delayAsFloat(clockInsertion(clk, clk->defaultPin(), - clk_tr, min_max, early_late, + clk_rf, min_max, early_late, path_ap)); clk_arrival += clk_insertion; } if (!clk->isPropagated() && !input_delay->networkLatencyIncluded()) { - clk_latency = sdc_->clockLatency(clk, clk_tr, min_max); + clk_latency = sdc_->clockLatency(clk, clk_rf, min_max); clk_arrival += clk_latency; } } @@ -1908,7 +1908,7 @@ Search::inputDelayClkArrival(InputDelay *input_delay, Tag * Search::inputDelayTag(const Pin *pin, - const TransRiseFall *tr, + const RiseFall *rf, ClockEdge *clk_edge, float clk_insertion, float clk_latency, @@ -1919,12 +1919,12 @@ Search::inputDelayTag(const Pin *pin, { Clock *clk = nullptr; Pin *clk_pin = nullptr; - TransRiseFall *clk_tr = nullptr; + RiseFall *clk_rf = nullptr; bool is_propagated = false; ClockUncertainties *clk_uncertainties = nullptr; if (clk_edge) { clk = clk_edge->clock(); - clk_tr = clk_edge->transition(); + clk_rf = clk_edge->transition(); clk_pin = clk->defaultPin(); is_propagated = clk->isPropagated(); clk_uncertainties = clk->uncertainties(); @@ -1932,19 +1932,19 @@ Search::inputDelayTag(const Pin *pin, ExceptionStateSet *states = nullptr; Tag *tag = nullptr; - if (sdc_->exceptionFromStates(pin,tr,clk,clk_tr,min_max,states)) { + if (sdc_->exceptionFromStates(pin,rf,clk,clk_rf,min_max,states)) { ClkInfo *clk_info = findClkInfo(clk_edge, clk_pin, is_propagated, nullptr, false, nullptr, clk_insertion, clk_latency, clk_uncertainties, path_ap, nullptr); - tag = findTag(tr, path_ap, clk_info, false, input_delay, is_segment_start, + tag = findTag(rf, path_ap, clk_info, false, input_delay, is_segment_start, states, true); } if (tag) { ClkInfo *clk_info = tag->clkInfo(); // Check for state changes on existing tag exceptions (pending -thru pins). - tag = mutateTag(tag, pin, tr, false, clk_info, - pin, tr, false, false, is_segment_start, clk_info, + tag = mutateTag(tag, pin, rf, false, clk_info, + pin, rf, false, false, is_segment_start, clk_info, input_delay, min_max, path_ap); } return tag; @@ -2027,17 +2027,17 @@ PathVisitor::visitEdge(const Pin *from_pin, || from_tag->isSegmentStart()) { PathAnalysisPt *path_ap = from_path->pathAnalysisPt(sta_); const MinMax *min_max = path_ap->pathMinMax(); - const TransRiseFall *from_tr = from_path->transition(sta_); + const RiseFall *from_rf = from_path->transition(sta_); // Do not propagate paths from a clock source unless they are // defined on the from pin. if (!search->pathPropagatedToClkSrc(from_pin, from_path)) { TimingArc *arc1, *arc2; - arc_set->arcsFrom(from_tr, arc1, arc2); - if (!visitArc(from_pin, from_vertex, from_tr, from_path, + arc_set->arcsFrom(from_rf, arc1, arc2); + if (!visitArc(from_pin, from_vertex, from_rf, from_path, edge, arc1, to_pin, to_vertex, min_max, path_ap)) return false; - if (!visitArc(from_pin, from_vertex, from_tr, from_path, + if (!visitArc(from_pin, from_vertex, from_rf, from_path, edge, arc2, to_pin, to_vertex, min_max, path_ap)) return false; @@ -2051,7 +2051,7 @@ PathVisitor::visitEdge(const Pin *from_pin, bool PathVisitor::visitArc(const Pin *from_pin, Vertex *from_vertex, - const TransRiseFall *from_tr, + const RiseFall *from_rf, PathVertex *from_path, Edge *edge, TimingArc *arc, @@ -2061,10 +2061,10 @@ PathVisitor::visitArc(const Pin *from_pin, PathAnalysisPt *path_ap) { if (arc) { - TransRiseFall *to_tr = arc->toTrans()->asRiseFall(); - if (searchThru(from_vertex, from_tr, edge, to_vertex, to_tr)) - return visitFromPath(from_pin, from_vertex, from_tr, from_path, - edge, arc, to_pin, to_vertex, to_tr, + RiseFall *to_rf = arc->toTrans()->asRiseFall(); + if (searchThru(from_vertex, from_rf, edge, to_vertex, to_rf)) + return visitFromPath(from_pin, from_vertex, from_rf, from_path, + edge, arc, to_pin, to_vertex, to_rf, min_max, path_ap); } return true; @@ -2090,13 +2090,13 @@ Search::pathPropagatedToClkSrc(const Pin *pin, bool PathVisitor::visitFromPath(const Pin *from_pin, Vertex *from_vertex, - const TransRiseFall *from_tr, + const RiseFall *from_rf, PathVertex *from_path, Edge *edge, TimingArc *arc, const Pin *to_pin, Vertex *to_vertex, - const TransRiseFall *to_tr, + const RiseFall *to_rf, const MinMax *min_max, const PathAnalysisPt *path_ap) { @@ -2114,7 +2114,7 @@ PathVisitor::visitFromPath(const Pin *from_pin, ArcDelay arc_delay = 0.0; Arrival to_arrival; if (from_clk_info->isGenClkSrcPath()) { - if (!sdc->clkStopPropagation(clk,from_pin,from_tr,to_pin,to_tr) + if (!sdc->clkStopPropagation(clk,from_pin,from_rf,to_pin,to_rf) && (sdc->clkThruTristateEnabled() || !(role == TimingRole::tristateEnable() || role == TimingRole::tristateDisable()))) { @@ -2133,7 +2133,7 @@ PathVisitor::visitFromPath(const Pin *from_pin, || !gclk->combinational()) && fanins->hasKey(to_vertex) && !(fdbk_edges && fdbk_edges->hasKey(edge))) { - to_tag = search->thruClkTag(from_path, from_tag, true, edge, to_tr, + to_tag = search->thruClkTag(from_path, from_tag, true, edge, to_rf, min_max, path_ap); if (to_tag) { arc_delay = search->deratedDelay(from_vertex, arc, edge, true, @@ -2144,7 +2144,7 @@ PathVisitor::visitFromPath(const Pin *from_pin, } else { // PLL out to feedback path. - to_tag = search->thruTag(from_tag, edge, to_tr, min_max, path_ap); + to_tag = search->thruTag(from_tag, edge, to_rf, min_max, path_ap); if (to_tag) { arc_delay = search->deratedDelay(from_vertex, arc, edge, true, path_ap); @@ -2167,16 +2167,16 @@ PathVisitor::visitFromPath(const Pin *from_pin, // Only propagate paths from clocks that have not // passed thru reg/latch D->Q edges. && from_tag->isClock())) { - const TransRiseFall *clk_tr = clk_edge ? clk_edge->transition() : nullptr; + const RiseFall *clk_rf = clk_edge ? clk_edge->transition() : nullptr; ClkInfo *to_clk_info = from_clk_info; if (network->direction(to_pin)->isInternal()) to_clk_info = search->clkInfoWithCrprClkPath(from_clk_info, from_path, path_ap); - to_tag = search->fromRegClkTag(from_pin, from_tr, clk, clk_tr, - to_clk_info, to_pin, to_tr, min_max, + to_tag = search->fromRegClkTag(from_pin, from_rf, clk, clk_rf, + to_clk_info, to_pin, to_rf, min_max, path_ap); if (to_tag) - to_tag = search->thruTag(to_tag, edge, to_tr, min_max, path_ap); + to_tag = search->thruTag(to_tag, edge, to_rf, min_max, path_ap); from_arrival = search->clkPathArrival(from_path, from_clk_info, clk_edge, min_max, path_ap); to_arrival = from_arrival + arc_delay; @@ -2191,7 +2191,7 @@ PathVisitor::visitFromPath(const Pin *from_pin, latches->latchOutArrival(from_path, arc, edge, path_ap, to_tag, arc_delay, to_arrival); if (to_tag) - to_tag = search->thruTag(to_tag, edge, to_tr, min_max, path_ap); + to_tag = search->thruTag(to_tag, edge, to_rf, min_max, path_ap); } } else if (from_tag->isClock()) { @@ -2203,14 +2203,14 @@ PathVisitor::visitFromPath(const Pin *from_pin, && sdc->clkDisabledByHpinThru(clk, from_pin, to_pin))) { // Propagate arrival as non-clock at the end of the clock tree. bool to_propagates_clk = - !sdc->clkStopPropagation(clk,from_pin,from_tr,to_pin,to_tr) + !sdc->clkStopPropagation(clk,from_pin,from_rf,to_pin,to_rf) && (sdc->clkThruTristateEnabled() || !(role == TimingRole::tristateEnable() || role == TimingRole::tristateDisable())); arc_delay = search->deratedDelay(from_vertex, arc, edge, to_propagates_clk, path_ap); to_tag = search->thruClkTag(from_path, from_tag, to_propagates_clk, - edge, to_tr, min_max, path_ap); + edge, to_rf, min_max, path_ap); to_arrival = from_arrival + arc_delay; } } @@ -2218,13 +2218,13 @@ PathVisitor::visitFromPath(const Pin *from_pin, arc_delay = search->deratedDelay(from_vertex, arc, edge, false, path_ap); if (!fuzzyEqual(arc_delay, min_max->initValue())) { to_arrival = from_arrival + arc_delay; - to_tag = search->thruTag(from_tag, edge, to_tr, min_max, path_ap); + to_tag = search->thruTag(from_tag, edge, to_rf, min_max, path_ap); } } if (to_tag) - return visitFromToPath(from_pin, from_vertex, from_tr, from_tag, from_path, + return visitFromToPath(from_pin, from_vertex, from_rf, from_tag, from_path, edge, arc, arc_delay, - to_vertex, to_tr, to_tag, to_arrival, + to_vertex, to_rf, to_tag, to_arrival, min_max, path_ap); else return true; @@ -2317,15 +2317,15 @@ Search::pathClkPathArrival1(const Path *path, // Return nullptr if a false path starts at pin/clk_edge. Tag * Search::fromUnclkedInputTag(const Pin *pin, - const TransRiseFall *tr, + const RiseFall *rf, const MinMax *min_max, const PathAnalysisPt *path_ap, bool is_segment_start) { ExceptionStateSet *states = nullptr; - if (sdc_->exceptionFromStates(pin, tr, nullptr, nullptr, min_max, states)) { + if (sdc_->exceptionFromStates(pin, rf, nullptr, nullptr, min_max, states)) { ClkInfo *clk_info = findClkInfo(nullptr, nullptr, false, 0.0, path_ap); - return findTag(tr, path_ap, clk_info, false, nullptr, + return findTag(rf, path_ap, clk_info, false, nullptr, is_segment_start, states, true); } else @@ -2334,21 +2334,21 @@ Search::fromUnclkedInputTag(const Pin *pin, Tag * Search::fromRegClkTag(const Pin *from_pin, - const TransRiseFall *from_tr, + const RiseFall *from_rf, Clock *clk, - const TransRiseFall *clk_tr, + const RiseFall *clk_rf, ClkInfo *clk_info, const Pin *to_pin, - const TransRiseFall *to_tr, + const RiseFall *to_rf, const MinMax *min_max, const PathAnalysisPt *path_ap) { ExceptionStateSet *states = nullptr; - if (sdc_->exceptionFromStates(from_pin, from_tr, clk, clk_tr, + if (sdc_->exceptionFromStates(from_pin, from_rf, clk, clk_rf, min_max, states)) { // Hack for filter -from reg/Q. - sdc_->filterRegQStates(to_pin, to_tr, min_max, states); - return findTag(to_tr, path_ap, clk_info, false, nullptr, false, states, true); + sdc_->filterRegQStates(to_pin, to_rf, min_max, states); + return findTag(to_rf, path_ap, clk_info, false, nullptr, false, states, true); } else return nullptr; @@ -2380,18 +2380,18 @@ Search::clkInfoWithCrprClkPath(ClkInfo *from_clk_info, Tag * Search::thruTag(Tag *from_tag, Edge *edge, - const TransRiseFall *to_tr, + const RiseFall *to_rf, const MinMax *min_max, const PathAnalysisPt *path_ap) { const Pin *from_pin = edge->from(graph_)->pin(); Vertex *to_vertex = edge->to(graph_); const Pin *to_pin = to_vertex->pin(); - const TransRiseFall *from_tr = from_tag->transition(); + const RiseFall *from_rf = from_tag->transition(); ClkInfo *from_clk_info = from_tag->clkInfo(); bool to_is_reg_clk = to_vertex->isRegClk(); - Tag *to_tag = mutateTag(from_tag, from_pin, from_tr, false, from_clk_info, - to_pin, to_tr, false, to_is_reg_clk, false, + Tag *to_tag = mutateTag(from_tag, from_pin, from_rf, false, from_clk_info, + to_pin, to_rf, false, to_is_reg_clk, false, // input delay is not propagated. from_clk_info, nullptr, min_max, path_ap); return to_tag; @@ -2402,14 +2402,14 @@ Search::thruClkTag(PathVertex *from_path, Tag *from_tag, bool to_propagates_clk, Edge *edge, - const TransRiseFall *to_tr, + const RiseFall *to_rf, const MinMax *min_max, const PathAnalysisPt *path_ap) { const Pin *from_pin = edge->from(graph_)->pin(); Vertex *to_vertex = edge->to(graph_); const Pin *to_pin = to_vertex->pin(); - const TransRiseFall *from_tr = from_tag->transition(); + const RiseFall *from_rf = from_tag->transition(); ClkInfo *from_clk_info = from_tag->clkInfo(); bool from_is_clk = from_tag->isClock(); bool to_is_reg_clk = to_vertex->isRegClk(); @@ -2420,8 +2420,8 @@ Search::thruClkTag(PathVertex *from_path, || role == TimingRole::combinational())); ClkInfo *to_clk_info = thruClkInfo(from_path, from_clk_info, edge, to_vertex, to_pin, min_max, path_ap); - Tag *to_tag = mutateTag(from_tag,from_pin,from_tr,from_is_clk,from_clk_info, - to_pin, to_tr, to_is_clk, to_is_reg_clk, false, + Tag *to_tag = mutateTag(from_tag,from_pin,from_rf,from_is_clk,from_clk_info, + to_pin, to_rf, to_is_clk, to_is_reg_clk, false, to_clk_info, nullptr, min_max, path_ap); return to_tag; } @@ -2439,7 +2439,7 @@ Search::thruClkInfo(PathVertex *from_path, ClkInfo *to_clk_info = from_clk_info; bool changed = false; ClockEdge *from_clk_edge = from_clk_info->clkEdge(); - const TransRiseFall *clk_tr = from_clk_edge->transition(); + const RiseFall *clk_rf = from_clk_edge->transition(); bool from_clk_prop = from_clk_info->isPropagated(); bool to_clk_prop = from_clk_prop; @@ -2469,8 +2469,8 @@ Search::thruClkInfo(PathVertex *from_path, } // Propagate liberty "pulse_clock" transition to transitive fanout. - TransRiseFall *from_pulse_sense = from_clk_info->pulseClkSense(); - TransRiseFall *to_pulse_sense = from_pulse_sense; + RiseFall *from_pulse_sense = from_clk_info->pulseClkSense(); + RiseFall *to_pulse_sense = from_pulse_sense; LibertyPort *port = network_->libertyPort(to_pin); if (port && port->pulseClkSense()) { to_pulse_sense = port->pulseClkSense(); @@ -2487,7 +2487,7 @@ Search::thruClkInfo(PathVertex *from_path, float to_latency = from_clk_info->latency(); float latency; bool exists; - sdc_->clockLatency(from_clk, to_pin, clk_tr, min_max, + sdc_->clockLatency(from_clk, to_pin, clk_rf, min_max, latency, exists); if (exists) { // Latency on pin has precidence over fanin or hierarchical @@ -2498,7 +2498,7 @@ Search::thruClkInfo(PathVertex *from_path, } else { // Check for hierarchical pin latency thru edge. - sdc_->clockLatency(edge, clk_tr, min_max, + sdc_->clockLatency(edge, clk_rf, min_max, latency, exists); if (exists) { to_latency = latency; @@ -2527,11 +2527,11 @@ Search::thruClkInfo(PathVertex *from_path, Tag * Search::mutateTag(Tag *from_tag, const Pin *from_pin, - const TransRiseFall *from_tr, + const RiseFall *from_rf, bool from_is_clk, ClkInfo *from_clk_info, const Pin *to_pin, - const TransRiseFall *to_tr, + const RiseFall *to_rf, bool to_is_clk, bool to_is_reg_clk, bool to_is_segment_start, @@ -2553,7 +2553,7 @@ Search::mutateTag(Tag *from_tag, // Don't propagate a completed false path -thru unless it is a // clock (which ignores exceptions). return nullptr; - if (state->matchesNextThru(from_pin,to_pin,to_tr,min_max,network_)) { + if (state->matchesNextThru(from_pin,to_pin,to_rf,min_max,network_)) { // Found a -thru that we've been waiting for. if (state->nextState()->isComplete() && exception->isLoop()) @@ -2569,7 +2569,7 @@ Search::mutateTag(Tag *from_tag, } } // Get the set of -thru exceptions starting at to_pin/edge. - sdc_->exceptionThruStates(from_pin, to_pin, to_tr, min_max, new_states); + sdc_->exceptionThruStates(from_pin, to_pin, to_rf, min_max, new_states); if (new_states || state_change) { // Second pass to apply state changes and add updated existing // states to new states. @@ -2587,7 +2587,7 @@ Search::mutateTag(Tag *from_tag, return nullptr; } // One edge may traverse multiple hierarchical thru pins. - while (state->matchesNextThru(from_pin,to_pin,to_tr,min_max,network_)) + while (state->matchesNextThru(from_pin,to_pin,to_rf,min_max,network_)) // Found a -thru that we've been waiting for. state = state->nextState(); @@ -2607,22 +2607,22 @@ Search::mutateTag(Tag *from_tag, } else // Get the set of -thru exceptions starting at to_pin/edge. - sdc_->exceptionThruStates(from_pin, to_pin, to_tr, min_max, new_states); + sdc_->exceptionThruStates(from_pin, to_pin, to_rf, min_max, new_states); if (new_states) - return findTag(to_tr, path_ap, to_clk_info, to_is_clk, + return findTag(to_rf, path_ap, to_clk_info, to_is_clk, from_tag->inputDelay(), to_is_segment_start, new_states, true); else { // No state change. if (to_clk_info == from_clk_info - && to_tr == from_tr + && to_rf == from_rf && to_is_clk == from_is_clk && from_tag->isSegmentStart() == to_is_segment_start && from_tag->inputDelay() == to_input_delay) return from_tag; else - return findTag(to_tr, path_ap, to_clk_info, to_is_clk, + return findTag(to_rf, path_ap, to_clk_info, to_is_clk, to_input_delay, to_is_segment_start, from_states, false); } @@ -2734,10 +2734,10 @@ Search::reportArrivals(Vertex *vertex) const int arrival_index; arrival_iter.next(tag, arrival_index); PathAnalysisPt *path_ap = tag->pathAnalysisPt(this); - const TransRiseFall *tr = tag->transition(); + const RiseFall *rf = tag->transition(); report_->print(" %d %s %s %s", arrival_index, - tr->asString(), + rf->asString(), path_ap->pathMinMax()->asString(), delayAsString(arrivals[arrival_index], this)); if (vertex->hasRequireds()) { @@ -2843,7 +2843,7 @@ Search::tagCount() const } Tag * -Search::findTag(const TransRiseFall *tr, +Search::findTag(const RiseFall *rf, const PathAnalysisPt *path_ap, ClkInfo *clk_info, bool is_clk, @@ -2852,7 +2852,7 @@ Search::findTag(const TransRiseFall *tr, ExceptionStateSet *states, bool own_states) { - Tag probe(0, tr->index(), path_ap->index(), clk_info, is_clk, input_delay, + Tag probe(0, rf->index(), path_ap->index(), clk_info, is_clk, input_delay, is_segment_start, states, false, this); Tag *tag = tag_set_->findKey(&probe); if (tag == nullptr) { @@ -2869,7 +2869,7 @@ Search::findTag(const TransRiseFall *tr, tag_index = tag_free_indices_.back(); tag_free_indices_.pop_back(); } - tag = new Tag(tag_index, tr->index(), path_ap->index(), + tag = new Tag(tag_index, rf->index(), path_ap->index(), clk_info, is_clk, input_delay, is_segment_start, new_states, true, this); own_states = false; @@ -2923,10 +2923,10 @@ Search::reportClkInfos() const { Vector clk_infos; // set -> vector for sorting. - for (auto clk_info : *clk_info_set_) + for (ClkInfo *clk_info : *clk_info_set_) clk_infos.push_back(clk_info); sort(clk_infos, ClkInfoLess(this)); - for (auto clk_info : clk_infos) + for (ClkInfo *clk_info : clk_infos) report_->print("ClkInfo %s\n", clk_info->asString(this)); printf("%lu clk infos\n", @@ -2939,7 +2939,7 @@ Search::findClkInfo(ClockEdge *clk_edge, bool is_propagated, const Pin *gen_clk_src, bool gen_clk_src_path, - const TransRiseFall *pulse_clk_sense, + const RiseFall *pulse_clk_sense, Arrival insertion, float latency, ClockUncertainties *uncertainties, @@ -3005,22 +3005,22 @@ Search::timingDerate(Vertex *from_vertex, TimingRole *role = edge->role(); const Pin *pin = from_vertex->pin(); if (role->isWire()) { - const TransRiseFall *tr = arc->toTrans()->asRiseFall(); - return sdc_->timingDerateNet(pin, derate_clk_data, tr, + const RiseFall *rf = arc->toTrans()->asRiseFall(); + return sdc_->timingDerateNet(pin, derate_clk_data, rf, path_ap->pathMinMax()); } else { TimingDerateType derate_type; - const TransRiseFall *tr; + const RiseFall *rf; if (role->isTimingCheck()) { derate_type = TimingDerateType::cell_check; - tr = arc->toTrans()->asRiseFall(); + rf = arc->toTrans()->asRiseFall(); } else { derate_type = TimingDerateType::cell_delay; - tr = arc->fromTrans()->asRiseFall(); + rf = arc->fromTrans()->asRiseFall(); } - return sdc_->timingDerateInstance(pin, derate_type, derate_clk_data, tr, + return sdc_->timingDerateInstance(pin, derate_type, derate_clk_data, rf, path_ap->pathMinMax()); } } @@ -3099,7 +3099,7 @@ void Search::seedRequireds() { ensureDownstreamClkPins(); - for (auto vertex : *endpoints()) + for (Vertex *vertex : *endpoints()) seedRequired(vertex); requireds_seeded_ = true; requireds_exist_ = true; @@ -3122,7 +3122,7 @@ Search::endpoints() } } if (invalid_endpoints_) { - for (auto vertex : *invalid_endpoints_) { + for (Vertex *vertex : *invalid_endpoints_) { if (isEndpoint(vertex)) { debugPrint1(debug_, "endpoint", 2, "insert %s\n", vertex->name(sdc_network_)); @@ -3198,7 +3198,7 @@ Search::endpointsInvalid() void Search::seedInvalidRequireds() { - for (auto vertex : invalid_requireds_) + for (Vertex *vertex : invalid_requireds_) required_iter_->enqueue(vertex); invalid_requireds_.clear(); } @@ -3426,14 +3426,14 @@ RequiredVisitor::visit(Vertex *vertex) bool RequiredVisitor::visitFromToPath(const Pin *, Vertex *from_vertex, - const TransRiseFall *from_tr, + const RiseFall *from_rf, Tag *from_tag, PathVertex *from_path, Edge *edge, TimingArc *, ArcDelay arc_delay, Vertex *to_vertex, - const TransRiseFall *to_tr, + const RiseFall *to_rf, Tag *to_tag, Arrival &, const MinMax *min_max, @@ -3443,8 +3443,8 @@ RequiredVisitor::visitFromToPath(const Pin *, if (edge->role() != TimingRole::latchDtoQ()) { const Debug *debug = sta_->debug(); debugPrint3(debug, "search", 3, " %s -> %s %s\n", - from_tr->asString(), - to_tr->asString(), + from_rf->asString(), + to_rf->asString(), min_max->asString()); debugPrint2(debug, "search", 3, " from tag %2u: %s\n", from_tag->index(), @@ -3475,7 +3475,7 @@ RequiredVisitor::visitFromToPath(const Pin *, // Arrival on to_vertex that differs by crpr_pin was pruned. // Find an arrival that matches everything but the crpr_pin // as an appromate required. - VertexPathIterator to_iter(to_vertex, to_tr, path_ap, sta_); + VertexPathIterator to_iter(to_vertex, to_rf, path_ap, sta_); while (to_iter.hasNext()) { PathVertex *to_path = to_iter.next(); Tag *to_path_tag = to_path->tag(sta_); @@ -3516,7 +3516,7 @@ Search::ensureDownstreamClkPins() // as having downstream clk pins. ClkTreeSearchPred pred(this); BfsBkwdIterator iter(BfsIndex::other, &pred, this); - for (auto vertex : *graph_->regClkVertices()) + for (Vertex *vertex : *graph_->regClkVertices()) iter.enqueue(vertex); // Enqueue PLL feedback pins. @@ -3569,10 +3569,10 @@ Search::matchesFilter(Path *path, // -from clks ClockEdge *path_clk_edge = path->clkEdge(this); Clock *path_clk = path_clk_edge ? path_clk_edge->clock() : nullptr; - TransRiseFall *path_clk_tr = + RiseFall *path_clk_rf = path_clk_edge ? path_clk_edge->transition() : nullptr; return filter_from_->clks()->hasKey(path_clk) - && filter_from_->transition()->matches(path_clk_tr) + && filter_from_->transition()->matches(path_clk_rf) && matchesFilterTo(path, to_clk_edge); } else if (filter_from_ == nullptr @@ -3601,7 +3601,7 @@ ExceptionPath * Search::exceptionTo(ExceptionPathType type, const Path *path, const Pin *pin, - const TransRiseFall *tr, + const RiseFall *rf, const ClockEdge *clk_edge, const MinMax *min_max, bool match_min_max_exactly, @@ -3617,7 +3617,7 @@ Search::exceptionTo(ExceptionPathType type, int priority = exception->priority(min_max); if ((type == ExceptionPathType::any || exception->type() == type) - && sdc_->isCompleteTo(state, pin, tr, clk_edge, min_max, + && sdc_->isCompleteTo(state, pin, rf, clk_edge, min_max, match_min_max_exactly, require_to_pin) && (hi_priority_exception == nullptr || priority > hi_priority @@ -3629,7 +3629,7 @@ Search::exceptionTo(ExceptionPathType type, } } // Check for -to exceptions originating at the end pin or target clock. - sdc_->exceptionTo(type, pin, tr, clk_edge, min_max, + sdc_->exceptionTo(type, pin, rf, clk_edge, min_max, match_min_max_exactly, hi_priority_exception, hi_priority); return hi_priority_exception; @@ -3642,7 +3642,7 @@ Search::totalNegativeSlack(const MinMax *min_max) { tnsPreamble(); Slack tns = 0.0; - for (auto corner : *corners_) { + for (Corner *corner : *corners_) { PathAPIndex path_ap_index = corner->findPathAnalysisPt(min_max)->index(); Slack tns1 = tns_[path_ap_index]; if (tns1 < tns) @@ -3689,7 +3689,7 @@ void Search::updateInvalidTns() { PathAPIndex path_ap_count = corners_->pathAnalysisPtCount(); - for (auto vertex : invalid_tns_) { + for (Vertex *vertex : invalid_tns_) { // Network edits can change endpointedness since tnsInvalid was called. if (isEndpoint(vertex)) { debugPrint1(debug_, "tns", 2, "update tns %s\n", @@ -3714,7 +3714,7 @@ Search::findTotalNegativeSlacks() tns_[i] = 0.0; tns_slacks_[i].clear(); } - for (auto vertex : *endpoints()) { + for (Vertex *vertex : *endpoints()) { // No locking required. SlackSeq slacks(path_ap_count); wnsSlacks(vertex, slacks); diff --git a/search/Search.hh b/search/Search.hh index daa06935..93335db8 100644 --- a/search/Search.hh +++ b/search/Search.hh @@ -160,7 +160,7 @@ public: virtual ExceptionPath *exceptionTo(ExceptionPathType type, const Path *path, const Pin *pin, - const TransRiseFall *tr, + const RiseFall *rf, const ClockEdge *clk_edge, const MinMax *min_max, bool match_min_max_exactly, @@ -216,29 +216,29 @@ public: SearchPred *pred) const; void endpointInvalid(Vertex *vertex); Tag *fromUnclkedInputTag(const Pin *pin, - const TransRiseFall *tr, + const RiseFall *rf, const MinMax *min_max, const PathAnalysisPt *path_ap, bool is_segment_start); Tag *fromRegClkTag(const Pin *from_pin, - const TransRiseFall *from_tr, + const RiseFall *from_rf, Clock *clk, - const TransRiseFall *clk_tr, + const RiseFall *clk_rf, ClkInfo *clk_info, const Pin *to_pin, - const TransRiseFall *to_tr, + const RiseFall *to_rf, const MinMax *min_max, const PathAnalysisPt *path_ap); virtual Tag *thruTag(Tag *from_tag, Edge *edge, - const TransRiseFall *to_tr, + const RiseFall *to_rf, const MinMax *min_max, const PathAnalysisPt *path_ap); virtual Tag *thruClkTag(PathVertex *from_path, Tag *from_tag, bool to_propagates_clk, Edge *edge, - const TransRiseFall *to_tr, + const RiseFall *to_rf, const MinMax *min_max, const PathAnalysisPt *path_ap); ClkInfo *thruClkInfo(PathVertex *from_path, @@ -284,15 +284,15 @@ public: // Insertion delay for regular or generated clock. Arrival clockInsertion(const Clock *clk, const Pin *pin, - const TransRiseFall *tr, + const RiseFall *rf, const MinMax *min_max, const EarlyLate *early_late, const PathAnalysisPt *path_ap) const; bool propagateClkSense(const Pin *from_pin, Path *from_path, - const TransRiseFall *to_tr); + const RiseFall *to_rf); - Tag *findTag(const TransRiseFall *tr, + Tag *findTag(const RiseFall *rf, const PathAnalysisPt *path_ap, ClkInfo *tag_clk, bool is_clk, @@ -307,7 +307,7 @@ public: bool is_propagated, const Pin *gen_clk_src, bool gen_clk_src_path, - const TransRiseFall *pulse_clk_sense, + const RiseFall *pulse_clk_sense, Arrival insertion, float latency, ClockUncertainties *uncertainties, @@ -362,7 +362,7 @@ protected: void seedArrivals(); void findClockVertices(VertexSet &vertices); void seedClkDataArrival(const Pin *pin, - const TransRiseFall *tr, + const RiseFall *rf, Clock *clk, ClockEdge *clk_edge, const MinMax *min_max, @@ -370,7 +370,7 @@ protected: Arrival insertion, TagGroupBldr *tag_bldr); void seedClkArrival(const Pin *pin, - const TransRiseFall *tr, + const RiseFall *rf, Clock *clk, ClockEdge *clk_edge, const MinMax *min_max, @@ -379,7 +379,7 @@ protected: TagGroupBldr *tag_bldr); Tag *clkDataTag(const Pin *pin, Clock *clk, - const TransRiseFall *tr, + const RiseFall *rf, ClockEdge *clk_edge, Arrival insertion, const MinMax *min_max, @@ -406,7 +406,7 @@ protected: PathAnalysisPt *path_ap, TagGroupBldr *tag_bldr); void seedInputDelayArrival(const Pin *pin, - const TransRiseFall *tr, + const RiseFall *rf, float arrival, InputDelay *input_delay, ClockEdge *clk_edge, @@ -432,7 +432,7 @@ protected: float &ref_insertion, float &ref_latency); Tag *inputDelayTag(const Pin *pin, - const TransRiseFall *tr, + const RiseFall *rf, ClockEdge *clk_edge, float clk_insertion, float clk_latency, @@ -449,11 +449,11 @@ protected: VertexVisitor *arrival_visitor); Tag *mutateTag(Tag *from_tag, const Pin *from_pin, - const TransRiseFall *from_tr, + const RiseFall *from_rf, bool from_is_clk, ClkInfo *from_clk_info, const Pin *to_pin, - const TransRiseFall *to_tr, + const RiseFall *to_rf, bool to_is_clk, bool to_is_reg_clk, bool to_is_segment_start, @@ -463,7 +463,7 @@ protected: const PathAnalysisPt *path_ap); ExceptionPath *exceptionTo(const Path *path, const Pin *pin, - const TransRiseFall *tr, + const RiseFall *rf, const ClockEdge *clk_edge, const MinMax *min_max) const; void seedRequireds(); @@ -653,7 +653,7 @@ protected: // Return false to stop visiting. bool visitArc(const Pin *from_pin, Vertex *from_vertex, - const TransRiseFall *from_tr, + const RiseFall *from_rf, PathVertex *from_path, Edge *edge, TimingArc *arc, @@ -665,26 +665,26 @@ protected: // Return false to stop visiting. virtual bool visitFromPath(const Pin *from_pin, Vertex *from_vertex, - const TransRiseFall *from_tr, + const RiseFall *from_rf, PathVertex *from_path, Edge *edge, TimingArc *arc, const Pin *to_pin, Vertex *to_vertex, - const TransRiseFall *to_tr, + const RiseFall *to_rf, const MinMax *min_max, const PathAnalysisPt *path_ap); // Return false to stop visiting. virtual bool visitFromToPath(const Pin *from_pin, Vertex *from_vertex, - const TransRiseFall *from_tr, + const RiseFall *from_rf, Tag *from_tag, PathVertex *from_path, Edge *edge, TimingArc *arc, ArcDelay arc_delay, Vertex *to_vertex, - const TransRiseFall *to_tr, + const RiseFall *to_rf, Tag *to_tag, Arrival &to_arrival, const MinMax *min_max, @@ -710,14 +710,14 @@ public: // Return false to stop visiting. virtual bool visitFromToPath(const Pin *from_pin, Vertex *from_vertex, - const TransRiseFall *from_tr, + const RiseFall *from_rf, Tag *from_tag, PathVertex *from_path, Edge *edge, TimingArc *arc, ArcDelay arc_delay, Vertex *to_vertex, - const TransRiseFall *to_tr, + const RiseFall *to_rf, Tag *to_tag, Arrival &to_arrival, const MinMax *min_max, @@ -778,14 +778,14 @@ protected: // Return false to stop visiting. virtual bool visitFromToPath(const Pin *from_pin, Vertex *from_vertex, - const TransRiseFall *from_tr, + const RiseFall *from_rf, Tag *from_tag, PathVertex *from_path, Edge *edge, TimingArc *arc, ArcDelay arc_delay, Vertex *to_vertex, - const TransRiseFall *to_tr, + const RiseFall *to_rf, Tag *to_tag, Arrival &to_arrival, const MinMax *min_max, diff --git a/search/SearchPred.cc b/search/SearchPred.cc index 151dcf71..c05ce187 100644 --- a/search/SearchPred.cc +++ b/search/SearchPred.cc @@ -29,10 +29,10 @@ namespace sta { static bool -searchThruSimEdge(const Vertex *vertex, const TransRiseFall *tr); +searchThruSimEdge(const Vertex *vertex, const RiseFall *rf); static bool -searchThruTimingSense(const Edge *edge, const TransRiseFall *from_tr, - const TransRiseFall *to_tr); +searchThruTimingSense(const Edge *edge, const RiseFall *from_rf, + const RiseFall *to_rf); SearchPred0::SearchPred0(const StaState *sta) : sta_(sta) @@ -176,51 +176,52 @@ searchThru(const Edge *edge, const TimingArc *arc, const Graph *graph) { - TransRiseFall *from_tr = arc->fromTrans()->asRiseFall(); - TransRiseFall *to_tr = arc->toTrans()->asRiseFall(); + RiseFall *from_rf = arc->fromTrans()->asRiseFall(); + RiseFall *to_rf = arc->toTrans()->asRiseFall(); // Ignore transitions other than rise/fall. - return from_tr && to_tr - && searchThru(edge->from(graph), from_tr, edge, edge->to(graph), to_tr); + return from_rf && to_rf + && searchThru(edge->from(graph), from_rf, edge, edge->to(graph), to_rf); } bool searchThru(Vertex *from_vertex, - const TransRiseFall *from_tr, + const RiseFall *from_rf, const Edge *edge, Vertex *to_vertex, - const TransRiseFall *to_tr) + const RiseFall *to_rf) { - return searchThruTimingSense(edge, from_tr, to_tr) - && searchThruSimEdge(from_vertex, from_tr) - && searchThruSimEdge(to_vertex, to_tr); + return searchThruTimingSense(edge, from_rf, to_rf) + && searchThruSimEdge(from_vertex, from_rf) + && searchThruSimEdge(to_vertex, to_rf); } // set_case_analysis rising/falling filters rise/fall edges during search. static bool -searchThruSimEdge(const Vertex *vertex, const TransRiseFall *tr) +searchThruSimEdge(const Vertex *vertex, + const RiseFall *rf) { LogicValue sim_value = vertex->simValue(); switch (sim_value) { case LogicValue::rise: - return tr == TransRiseFall::rise(); + return rf == RiseFall::rise(); case LogicValue::fall: - return tr == TransRiseFall::fall(); + return rf == RiseFall::fall(); default: return true; }; } static bool -searchThruTimingSense(const Edge *edge, const TransRiseFall *from_tr, - const TransRiseFall *to_tr) +searchThruTimingSense(const Edge *edge, const RiseFall *from_rf, + const RiseFall *to_rf) { switch (edge->simTimingSense()) { case TimingSense::unknown: return true; case TimingSense::positive_unate: - return from_tr == to_tr; + return from_rf == to_rf; case TimingSense::negative_unate: - return from_tr != to_tr; + return from_rf != to_rf; case TimingSense::non_unate: return true; case TimingSense::none: diff --git a/search/SearchPred.hh b/search/SearchPred.hh index 6d122030..87e67855 100644 --- a/search/SearchPred.hh +++ b/search/SearchPred.hh @@ -154,10 +154,10 @@ searchThru(const Edge *edge, const Graph *graph); bool searchThru(Vertex *from_vertex, - const TransRiseFall *from_tr, + const RiseFall *from_rf, const Edge *edge, Vertex *to_vertex, - const TransRiseFall *to_tr); + const RiseFall *to_rf); //////////////////////////////////////////////////////////////// diff --git a/search/Sta.cc b/search/Sta.cc index 7a4e45d9..0e7c98f2 100644 --- a/search/Sta.cc +++ b/search/Sta.cc @@ -771,11 +771,11 @@ Sta::setPvt(Instance *inst, void Sta::setTimingDerate(TimingDerateType type, PathClkOrData clk_data, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, const EarlyLate *early_late, float derate) { - sdc_->setTimingDerate(type, clk_data, tr, early_late, derate); + sdc_->setTimingDerate(type, clk_data, rf, early_late, derate); // Delay calculation results are still valid. // The search derates delays while finding arrival times. search_->arrivalsInvalid(); @@ -784,11 +784,11 @@ Sta::setTimingDerate(TimingDerateType type, void Sta::setTimingDerate(const Net *net, PathClkOrData clk_data, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, const EarlyLate *early_late, float derate) { - sdc_->setTimingDerate(net, clk_data, tr, early_late, derate); + sdc_->setTimingDerate(net, clk_data, rf, early_late, derate); // Delay calculation results are still valid. // The search derates delays while finding arrival times. search_->arrivalsInvalid(); @@ -798,11 +798,11 @@ void Sta::setTimingDerate(const Instance *inst, TimingDerateType type, PathClkOrData clk_data, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, const EarlyLate *early_late, float derate) { - sdc_->setTimingDerate(inst, type, clk_data, tr, early_late, derate); + sdc_->setTimingDerate(inst, type, clk_data, rf, early_late, derate); // Delay calculation results are still valid. // The search derates delays while finding arrival times. search_->arrivalsInvalid(); @@ -812,11 +812,11 @@ void Sta::setTimingDerate(const LibertyCell *cell, TimingDerateType type, PathClkOrData clk_data, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, const EarlyLate *early_late, float derate) { - sdc_->setTimingDerate(cell, type, clk_data, tr, early_late, derate); + sdc_->setTimingDerate(cell, type, clk_data, rf, early_late, derate); // Delay calculation results are still valid. // The search derates delays while finding arrival times. search_->arrivalsInvalid(); @@ -833,11 +833,11 @@ Sta::unsetTimingDerate() void Sta::setInputSlew(Port *port, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, const MinMaxAll *min_max, float slew) { - sdc_->setInputSlew(port, tr, min_max, slew); + sdc_->setInputSlew(port, rf, min_max, slew); delaysInvalidFrom(port); } @@ -848,21 +848,21 @@ Sta::setDriveCell(LibertyLibrary *library, LibertyPort *from_port, float *from_slews, LibertyPort *to_port, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, const MinMaxAll *min_max) { sdc_->setDriveCell(library, cell, port, from_port, from_slews, to_port, - tr, min_max); + rf, min_max); delaysInvalidFrom(port); } void Sta::setDriveResistance(Port *port, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, const MinMaxAll *min_max, float res) { - sdc_->setDriveResistance(port, tr, min_max, res); + sdc_->setDriveResistance(port, rf, min_max, res); delaysInvalidFrom(port); } @@ -891,34 +891,34 @@ Sta::setLatchBorrowLimit(Clock *clk, } void -Sta::setMinPulseWidth(const TransRiseFallBoth *tr, +Sta::setMinPulseWidth(const RiseFallBoth *rf, float min_width) { - sdc_->setMinPulseWidth(tr, min_width); + sdc_->setMinPulseWidth(rf, min_width); } void Sta::setMinPulseWidth(const Pin *pin, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, float min_width) { - sdc_->setMinPulseWidth(pin, tr, min_width); + sdc_->setMinPulseWidth(pin, rf, min_width); } void Sta::setMinPulseWidth(const Instance *inst, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, float min_width) { - sdc_->setMinPulseWidth(inst, tr, min_width); + sdc_->setMinPulseWidth(inst, rf, min_width); } void Sta::setMinPulseWidth(const Clock *clk, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, float min_width) { - sdc_->setMinPulseWidth(clk, tr, min_width); + sdc_->setMinPulseWidth(clk, rf, min_width); } void @@ -949,12 +949,12 @@ Sta::setWireloadSelection(WireloadSelection *selection, void Sta::setSlewLimit(Clock *clk, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, const PathClkOrData clk_data, const MinMax *min_max, float slew) { - sdc_->setSlewLimit(clk, tr, clk_data, min_max, slew); + sdc_->setSlewLimit(clk, rf, clk_data, min_max, slew); } void @@ -1139,11 +1139,11 @@ Sta::removePropagatedClock(Pin *pin) void Sta::setClockSlew(Clock *clk, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, const MinMaxAll *min_max, float slew) { - sdc_->setClockSlew(clk, tr, min_max, slew); + sdc_->setClockSlew(clk, rf, min_max, slew); clockSlewChanged(clk); } @@ -1165,11 +1165,11 @@ Sta::clockSlewChanged(Clock *clk) void Sta::setClockLatency(Clock *clk, Pin *pin, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, const MinMaxAll *min_max, float delay) { - sdc_->setClockLatency(clk, pin, tr, min_max, delay); + sdc_->setClockLatency(clk, pin, rf, min_max, delay); search_->arrivalsInvalid(); } @@ -1184,12 +1184,12 @@ Sta::removeClockLatency(const Clock *clk, void Sta::setClockInsertion(const Clock *clk, const Pin *pin, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, const MinMaxAll *min_max, const EarlyLateAll *early_late, float delay) { - sdc_->setClockInsertion(clk, pin, tr, min_max, early_late, delay); + sdc_->setClockInsertion(clk, pin, rf, min_max, early_late, delay); search_->arrivalsInvalid(); } @@ -1237,25 +1237,25 @@ Sta::removeClockUncertainty(Pin *pin, void Sta::setClockUncertainty(Clock *from_clk, - const TransRiseFallBoth *from_tr, + const RiseFallBoth *from_rf, Clock *to_clk, - const TransRiseFallBoth *to_tr, + const RiseFallBoth *to_rf, const SetupHoldAll *setup_hold, float uncertainty) { - sdc_->setClockUncertainty(from_clk, from_tr, to_clk, to_tr, + sdc_->setClockUncertainty(from_clk, from_rf, to_clk, to_rf, setup_hold, uncertainty); search_->arrivalsInvalid(); } void Sta::removeClockUncertainty(Clock *from_clk, - const TransRiseFallBoth *from_tr, + const RiseFallBoth *from_rf, Clock *to_clk, - const TransRiseFallBoth *to_tr, + const RiseFallBoth *to_rf, const SetupHoldAll *setup_hold) { - sdc_->removeClockUncertainty(from_clk, from_tr, to_clk, to_tr, + sdc_->removeClockUncertainty(from_clk, from_rf, to_clk, to_rf, setup_hold); search_->arrivalsInvalid(); } @@ -1318,68 +1318,68 @@ Sta::setClockSense(PinSet *pins, //////////////////////////////////////////////////////////////// void -Sta::setClockGatingCheck(const TransRiseFallBoth *tr, +Sta::setClockGatingCheck(const RiseFallBoth *rf, const SetupHold *setup_hold, float margin) { - sdc_->setClockGatingCheck(tr, setup_hold, margin); + sdc_->setClockGatingCheck(rf, setup_hold, margin); search_->arrivalsInvalid(); } void Sta::setClockGatingCheck(Clock *clk, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, const SetupHold *setup_hold, float margin) { - sdc_->setClockGatingCheck(clk, tr, setup_hold, margin); + sdc_->setClockGatingCheck(clk, rf, setup_hold, margin); search_->arrivalsInvalid(); } void Sta::setClockGatingCheck(Instance *inst, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, const SetupHold *setup_hold, float margin, LogicValue active_value) { - sdc_->setClockGatingCheck(inst, tr, setup_hold, margin,active_value); + sdc_->setClockGatingCheck(inst, rf, setup_hold, margin,active_value); search_->arrivalsInvalid(); } void Sta::setClockGatingCheck(Pin *pin, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, const SetupHold *setup_hold, float margin, LogicValue active_value) { - sdc_->setClockGatingCheck(pin, tr, setup_hold, margin,active_value); + sdc_->setClockGatingCheck(pin, rf, setup_hold, margin,active_value); search_->arrivalsInvalid(); } void Sta::setDataCheck(Pin *from, - const TransRiseFallBoth *from_tr, + const RiseFallBoth *from_rf, Pin *to, - const TransRiseFallBoth *to_tr, + const RiseFallBoth *to_rf, Clock *clk, const SetupHoldAll *setup_hold, float margin) { - sdc_->setDataCheck(from, from_tr, to, to_tr, clk, setup_hold,margin); + sdc_->setDataCheck(from, from_rf, to, to_rf, clk, setup_hold,margin); search_->requiredInvalid(to); } void Sta::removeDataCheck(Pin *from, - const TransRiseFallBoth *from_tr, + const RiseFallBoth *from_rf, Pin *to, - const TransRiseFallBoth *to_tr, + const RiseFallBoth *to_rf, Clock *clk, const SetupHoldAll *setup_hold) { - sdc_->removeDataCheck(from, from_tr, to, to_tr, clk, setup_hold); + sdc_->removeDataCheck(from, from_rf, to, to_rf, clk, setup_hold); search_->requiredInvalid(to); } @@ -1808,9 +1808,9 @@ Sta::removeCaseAnalysis(Pin *pin) void Sta::setInputDelay(Pin *pin, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, Clock *clk, - const TransRiseFall *clk_tr, + const RiseFall *clk_rf, Pin *ref_pin, bool source_latency_included, bool network_latency_included, @@ -1818,7 +1818,7 @@ Sta::setInputDelay(Pin *pin, bool add, float delay) { - sdc_->setInputDelay(pin, tr, clk, clk_tr, ref_pin, + sdc_->setInputDelay(pin, rf, clk, clk_rf, ref_pin, source_latency_included, network_latency_included, min_max, add, delay); @@ -1827,20 +1827,20 @@ Sta::setInputDelay(Pin *pin, void Sta::removeInputDelay(Pin *pin, - TransRiseFallBoth *tr, + RiseFallBoth *rf, Clock *clk, - TransRiseFall *clk_tr, + RiseFall *clk_rf, MinMaxAll *min_max) { - sdc_->removeInputDelay(pin, tr, clk, clk_tr, min_max); + sdc_->removeInputDelay(pin, rf, clk, clk_rf, min_max); search_->arrivalInvalid(pin); } void Sta::setOutputDelay(Pin *pin, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, Clock *clk, - const TransRiseFall *clk_tr, + const RiseFall *clk_rf, Pin *ref_pin, bool source_latency_included, bool network_latency_included, @@ -1848,7 +1848,7 @@ Sta::setOutputDelay(Pin *pin, bool add, float delay) { - sdc_->setOutputDelay(pin, tr, clk, clk_tr, ref_pin, + sdc_->setOutputDelay(pin, rf, clk, clk_rf, ref_pin, source_latency_included,network_latency_included, min_max, add, delay); search_->requiredInvalid(pin); @@ -1856,12 +1856,12 @@ Sta::setOutputDelay(Pin *pin, void Sta::removeOutputDelay(Pin *pin, - TransRiseFallBoth *tr, + RiseFallBoth *rf, Clock *clk, - TransRiseFall *clk_tr, + RiseFall *clk_rf, MinMaxAll *min_max) { - sdc_->removeOutputDelay(pin, tr, clk, clk_tr, min_max); + sdc_->removeOutputDelay(pin, rf, clk, clk_rf, min_max); search_->arrivalInvalid(pin); } @@ -1942,10 +1942,10 @@ ExceptionFrom * Sta::makeExceptionFrom(PinSet *from_pins, ClockSet *from_clks, InstanceSet *from_insts, - const TransRiseFallBoth *from_tr) + const RiseFallBoth *from_rf) { return sdc_->makeExceptionFrom(from_pins, from_clks, from_insts, - from_tr); + from_rf); } void @@ -1996,9 +1996,9 @@ ExceptionThru * Sta::makeExceptionThru(PinSet *pins, NetSet *nets, InstanceSet *insts, - const TransRiseFallBoth *tr) + const RiseFallBoth *rf) { - return sdc_->makeExceptionThru(pins, nets, insts, tr); + return sdc_->makeExceptionThru(pins, nets, insts, rf); } void @@ -2011,10 +2011,10 @@ ExceptionTo * Sta::makeExceptionTo(PinSet *to_pins, ClockSet *to_clks, InstanceSet *to_insts, - const TransRiseFallBoth *tr, - TransRiseFallBoth *end_tr) + const RiseFallBoth *rf, + RiseFallBoth *end_rf) { - return sdc_->makeExceptionTo(to_pins, to_clks, to_insts, tr, end_tr); + return sdc_->makeExceptionTo(to_pins, to_clks, to_insts, rf, end_rf); } void @@ -2604,29 +2604,29 @@ Sta::findRequireds() VertexPathIterator * Sta::vertexPathIterator(Vertex *vertex, - const TransRiseFall *tr, + const RiseFall *rf, const PathAnalysisPt *path_ap) { - return new VertexPathIterator(vertex, tr, path_ap, this); + return new VertexPathIterator(vertex, rf, path_ap, this); } VertexPathIterator * Sta::vertexPathIterator(Vertex *vertex, - const TransRiseFall *tr, + const RiseFall *rf, const MinMax *min_max) { - return new VertexPathIterator(vertex, tr, min_max, this); + return new VertexPathIterator(vertex, rf, min_max, this); } void Sta::vertexWorstArrivalPath(Vertex *vertex, - const TransRiseFall *tr, + const RiseFall *rf, const MinMax *min_max, // Return value. PathRef &worst_path) { Arrival worst_arrival = min_max->initValue(); - VertexPathIterator path_iter(vertex, tr, min_max, this); + VertexPathIterator path_iter(vertex, rf, min_max, this); while (path_iter.hasNext()) { PathVertex *path = path_iter.next(); Arrival arrival = path->arrival(this); @@ -2660,13 +2660,13 @@ Sta::vertexWorstArrivalPath(Vertex *vertex, void Sta::vertexWorstSlackPath(Vertex *vertex, - const TransRiseFall *tr, + const RiseFall *rf, const MinMax *min_max, // Return value. PathRef &worst_path) { Slack min_slack = MinMax::min()->initValue(); - VertexPathIterator path_iter(vertex, tr, min_max, this); + VertexPathIterator path_iter(vertex, rf, min_max, this); while (path_iter.hasNext()) { PathVertex *path = path_iter.next(); Slack slack = path->slack(this); @@ -2702,15 +2702,15 @@ Sta::vertexWorstSlackPath(Vertex *vertex, Arrival Sta::vertexArrival(Vertex *vertex, - const TransRiseFall *tr, + const RiseFall *rf, const PathAnalysisPt *path_ap) { - return vertexArrival(vertex, tr, clk_edge_wildcard, path_ap); + return vertexArrival(vertex, rf, clk_edge_wildcard, path_ap); } Arrival Sta::vertexArrival(Vertex *vertex, - const TransRiseFall *tr, + const RiseFall *rf, const ClockEdge *clk_edge, const PathAnalysisPt *path_ap) { @@ -2718,7 +2718,7 @@ Sta::vertexArrival(Vertex *vertex, search_->findArrivals(vertex->level()); const MinMax *min_max = path_ap->pathMinMax(); Arrival arrival = min_max->initValue(); - VertexPathIterator path_iter(vertex, tr, path_ap, this); + VertexPathIterator path_iter(vertex, rf, path_ap, this); while (path_iter.hasNext()) { Path *path = path_iter.next(); const Arrival &path_arrival = path->arrival(this); @@ -2753,22 +2753,22 @@ Sta::vertexRequired(Vertex *vertex, Required Sta::vertexRequired(Vertex *vertex, - const TransRiseFall *tr, + const RiseFall *rf, const PathAnalysisPt *path_ap) { - return vertexRequired(vertex, tr, clk_edge_wildcard, path_ap); + return vertexRequired(vertex, rf, clk_edge_wildcard, path_ap); } Required Sta::vertexRequired(Vertex *vertex, - const TransRiseFall *tr, + const RiseFall *rf, const ClockEdge *clk_edge, const PathAnalysisPt *path_ap) { findRequired(vertex); const MinMax *min_max = path_ap->pathMinMax()->opposite(); Required required = min_max->initValue(); - VertexPathIterator path_iter(vertex, tr, path_ap, this); + VertexPathIterator path_iter(vertex, rf, path_ap, this); while (path_iter.hasNext()) { const Path *path = path_iter.next(); const Required path_required = path->required(this); @@ -2815,7 +2815,7 @@ Sta::pinSlack(const Pin *pin, Slack Sta::pinSlack(const Pin *pin, - const TransRiseFall *tr, + const RiseFall *rf, const MinMax *min_max) { ensureGraph(); @@ -2823,9 +2823,9 @@ Sta::pinSlack(const Pin *pin, graph_->pinVertices(pin, vertex, bidirect_drvr_vertex); Slack slack = MinMax::min()->initValue(); if (vertex) - slack = vertexSlack(vertex, tr, min_max); + slack = vertexSlack(vertex, rf, min_max); if (bidirect_drvr_vertex) - slack = min(slack, vertexSlack(bidirect_drvr_vertex, tr, min_max)); + slack = min(slack, vertexSlack(bidirect_drvr_vertex, rf, min_max)); return slack; } @@ -2850,12 +2850,12 @@ Sta::vertexSlack(Vertex *vertex, Slack Sta::vertexSlack(Vertex *vertex, - const TransRiseFall *tr, + const RiseFall *rf, const MinMax *min_max) { findRequired(vertex); Slack slack = MinMax::min()->initValue(); - VertexPathIterator path_iter(vertex, tr, min_max, this); + VertexPathIterator path_iter(vertex, rf, min_max, this); while (path_iter.hasNext()) { Path *path = path_iter.next(); Slack path_slack = path->slack(this); @@ -2867,32 +2867,32 @@ Sta::vertexSlack(Vertex *vertex, Slack Sta::vertexSlack(Vertex *vertex, - const TransRiseFall *tr, + const RiseFall *rf, const PathAnalysisPt *path_ap) { findRequired(vertex); - return vertexSlack1(vertex, tr, clk_edge_wildcard, path_ap); + return vertexSlack1(vertex, rf, clk_edge_wildcard, path_ap); } Slack Sta::vertexSlack(Vertex *vertex, - const TransRiseFall *tr, + const RiseFall *rf, const ClockEdge *clk_edge, const PathAnalysisPt *path_ap) { findRequired(vertex); - return vertexSlack1(vertex, tr, clk_edge, path_ap); + return vertexSlack1(vertex, rf, clk_edge, path_ap); } Slack Sta::vertexSlack1(Vertex *vertex, - const TransRiseFall *tr, + const RiseFall *rf, const ClockEdge *clk_edge, const PathAnalysisPt *path_ap) { MinMax *min = MinMax::min(); Slack slack = min->initValue(); - VertexPathIterator path_iter(vertex, tr, path_ap, this); + VertexPathIterator path_iter(vertex, rf, path_ap, this); while (path_iter.hasNext()) { Path *path = path_iter.next(); Slack path_slack = path->slack(this); @@ -3078,22 +3078,22 @@ Sta::setArcDelayAnnotated(Edge *edge, Slew Sta::vertexSlew(Vertex *vertex, - const TransRiseFall *tr, + const RiseFall *rf, const DcalcAnalysisPt *dcalc_ap) { findDelays(vertex); - return graph_->slew(vertex, tr, dcalc_ap->index()); + return graph_->slew(vertex, rf, dcalc_ap->index()); } Slew Sta::vertexSlew(Vertex *vertex, - const TransRiseFall *tr, + const RiseFall *rf, const MinMax *min_max) { findDelays(vertex); Slew mm_slew = min_max->initValue(); for (auto dcalc_ap : corners_->dcalcAnalysisPts()) { - Slew slew = graph_->slew(vertex, tr, dcalc_ap->index()); + Slew slew = graph_->slew(vertex, rf, dcalc_ap->index()); if (fuzzyGreater(slew, mm_slew, min_max)) mm_slew = slew; } @@ -3139,7 +3139,7 @@ Sta::updateGeneratedClks() bool gen_clk_changed = true; while (gen_clk_changed) { gen_clk_changed = false; - for (auto clk : sdc_->clks()) { + for (Clock *clk : sdc_->clks()) { if (clk->isGenerated() && !clk->waveformValid()) { search_->genclks()->ensureMaster(clk); Clock *master_clk = clk->masterClk(); @@ -3244,7 +3244,7 @@ Sta::setArcDelay(Edge *edge, const MinMaxAll *min_max, ArcDelay delay) { - for (auto mm : min_max->range()) { + for (MinMax *mm : min_max->range()) { const DcalcAnalysisPt *dcalc_ap = corner->findDcalcAnalysisPt(mm); DcalcAPIndex ap_index = dcalc_ap->index(); graph_->setArcDelay(edge, arc, ap_index, delay); @@ -3263,16 +3263,16 @@ void Sta::setAnnotatedSlew(Vertex *vertex, const Corner *corner, const MinMaxAll *min_max, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, float slew) { - for (auto mm : min_max->range()) { + for (MinMax *mm : min_max->range()) { const DcalcAnalysisPt *dcalc_ap = corner->findDcalcAnalysisPt(mm); DcalcAPIndex ap_index = dcalc_ap->index(); - for (auto tr1 : tr->range()) { - graph_->setSlew(vertex, tr1, ap_index, slew); + for (RiseFall *rf1 : rf->range()) { + graph_->setSlew(vertex, rf1, ap_index, slew); // Don't let delay calculation clobber the value. - vertex->setSlewAnnotated(true, tr1, ap_index); + vertex->setSlewAnnotated(true, rf1, ap_index); } } graph_delay_calc_->delayInvalid(vertex); @@ -3309,13 +3309,13 @@ Sta::simLogicValue(const Pin *pin) float Sta::portExtPinCap(Port *port, - const TransRiseFall *tr, + const RiseFall *rf, const MinMax *min_max) { float pin_cap, wire_cap; int fanout; bool pin_exists, wire_exists, fanout_exists; - sdc_->portExtCap(port, tr, min_max, + sdc_->portExtCap(port, rf, min_max, pin_cap, pin_exists, wire_cap, wire_exists, fanout, fanout_exists); @@ -3327,13 +3327,13 @@ Sta::portExtPinCap(Port *port, void Sta::setPortExtPinCap(Port *port, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, const MinMaxAll *min_max, float cap) { - for (auto tr1 : tr->range()) { - for (auto mm : min_max->range()) { - sdc_->setPortExtPinCap(port, tr1, mm, cap); + for (RiseFall *rf1 : rf->range()) { + for (MinMax *mm : min_max->range()) { + sdc_->setPortExtPinCap(port, rf1, mm, cap); } } delaysInvalidFromFanin(port); @@ -3341,13 +3341,13 @@ Sta::setPortExtPinCap(Port *port, float Sta::portExtWireCap(Port *port, - const TransRiseFall *tr, + const RiseFall *rf, const MinMax *min_max) { float pin_cap, wire_cap; int fanout; bool pin_exists, wire_exists, fanout_exists; - sdc_->portExtCap(port, tr, min_max, + sdc_->portExtCap(port, rf, min_max, pin_cap, pin_exists, wire_cap, wire_exists, fanout, fanout_exists); @@ -3360,14 +3360,14 @@ Sta::portExtWireCap(Port *port, void Sta::setPortExtWireCap(Port *port, bool subtract_pin_cap, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, const MinMaxAll *min_max, float cap) { Corner *corner = cmd_corner_; - for (auto tr1 : tr->range()) { - for (auto mm : min_max->range()) { - sdc_->setPortExtWireCap(port, subtract_pin_cap, tr1, corner, mm, cap); + for (RiseFall *rf1 : rf->range()) { + for (MinMax *mm : min_max->range()) { + sdc_->setPortExtWireCap(port, subtract_pin_cap, rf1, corner, mm, cap); } } delaysInvalidFromFanin(port); @@ -3392,7 +3392,7 @@ Sta::setPortExtFanout(Port *port, int fanout, const MinMaxAll *min_max) { - for (auto mm : min_max->range()) + for (MinMax *mm : min_max->range()) sdc_->setPortExtFanout(port, mm, fanout); delaysInvalidFromFanin(port); } @@ -3404,14 +3404,14 @@ Sta::setNetWireCap(Net *net, const MinMaxAll *min_max, float cap) { - for (auto mm : min_max->range()) + for (MinMax *mm : min_max->range()) sdc_->setNetWireCap(net, subtract_pin_cap, corner, mm, cap); delaysInvalidFromFanin(net); } void Sta::connectedCap(Pin *drvr_pin, - const TransRiseFall *tr, + const RiseFall *rf, const Corner *corner, const MinMax *min_max, float &pin_cap, @@ -3421,10 +3421,10 @@ Sta::connectedCap(Pin *drvr_pin, wire_cap = 0.0; bool cap_exists = false; const DcalcAnalysisPt *dcalc_ap = corner->findDcalcAnalysisPt(min_max); - Parasitic *parasitic = arc_delay_calc_->findParasitic(drvr_pin, tr, dcalc_ap); + Parasitic *parasitic = arc_delay_calc_->findParasitic(drvr_pin, rf, dcalc_ap); float ap_pin_cap = 0.0; float ap_wire_cap = 0.0; - graph_delay_calc_->loadCap(drvr_pin, parasitic, tr, dcalc_ap, + graph_delay_calc_->loadCap(drvr_pin, parasitic, rf, dcalc_ap, ap_pin_cap, ap_wire_cap); arc_delay_calc_->finishDrvrPin(); if (!cap_exists @@ -3437,7 +3437,7 @@ Sta::connectedCap(Pin *drvr_pin, void Sta::connectedCap(Net *net, - const TransRiseFall *tr, + const RiseFall *rf, const Corner *corner, const MinMax *min_max, float &pin_cap, @@ -3445,7 +3445,7 @@ Sta::connectedCap(Net *net, { Pin *drvr_pin = findNetParasiticDrvrPin(net); if (drvr_pin) - connectedCap(drvr_pin, tr, corner, min_max, pin_cap, wire_cap); + connectedCap(drvr_pin, rf, corner, min_max, pin_cap, wire_cap); else { pin_cap = 0.0; wire_cap = 0.0; @@ -3523,7 +3523,7 @@ Sta::readSpef(const char *filename, void Sta::findPiElmore(Pin *drvr_pin, - const TransRiseFall *tr, + const RiseFall *rf, const MinMax *min_max, float &c2, float &rpi, @@ -3532,7 +3532,7 @@ Sta::findPiElmore(Pin *drvr_pin, { Corner *corner = cmd_corner_; const ParasiticAnalysisPt *ap = corner->findParasiticAnalysisPt(min_max); - Parasitic *pi_elmore = parasitics_->findPiElmore(drvr_pin, tr, ap); + Parasitic *pi_elmore = parasitics_->findPiElmore(drvr_pin, rf, ap); if (pi_elmore) { parasitics_->piModel(pi_elmore, c2, rpi, c1); exists = true; @@ -3543,16 +3543,16 @@ Sta::findPiElmore(Pin *drvr_pin, void Sta::makePiElmore(Pin *drvr_pin, - const TransRiseFall *tr, + const RiseFall *rf, const MinMaxAll *min_max, float c2, float rpi, float c1) { Corner *corner = cmd_corner_; - for (auto mm : min_max->range()) { + for (MinMax *mm : min_max->range()) { ParasiticAnalysisPt *ap = corner->findParasiticAnalysisPt(mm); - parasitics_->makePiElmore(drvr_pin, tr, ap, c2, rpi, c1); + parasitics_->makePiElmore(drvr_pin, rf, ap, c2, rpi, c1); } delaysInvalidFrom(drvr_pin); } @@ -3560,14 +3560,14 @@ Sta::makePiElmore(Pin *drvr_pin, void Sta::findElmore(Pin *drvr_pin, Pin *load_pin, - const TransRiseFall *tr, + const RiseFall *rf, const MinMax *min_max, float &elmore, bool &exists) const { Corner *corner = cmd_corner_; const ParasiticAnalysisPt *ap = corner->findParasiticAnalysisPt(min_max); - Parasitic *pi_elmore = parasitics_->findPiElmore(drvr_pin, tr, ap); + Parasitic *pi_elmore = parasitics_->findPiElmore(drvr_pin, rf, ap); if (pi_elmore) { exists = false; parasitics_->findElmore(pi_elmore, load_pin, elmore, exists); @@ -3579,14 +3579,14 @@ Sta::findElmore(Pin *drvr_pin, void Sta::setElmore(Pin *drvr_pin, Pin *load_pin, - const TransRiseFall *tr, + const RiseFall *rf, const MinMaxAll *min_max, float elmore) { Corner *corner = cmd_corner_; - for (auto mm : min_max->range()) { + for (MinMax *mm : min_max->range()) { const ParasiticAnalysisPt *ap = corner->findParasiticAnalysisPt(mm); - Parasitic *pi_elmore = parasitics_->findPiElmore(drvr_pin, tr, ap); + Parasitic *pi_elmore = parasitics_->findPiElmore(drvr_pin, rf, ap); if (pi_elmore) parasitics_->setElmore(pi_elmore, load_pin, elmore); } @@ -3840,7 +3840,7 @@ Sta::replaceCellPinInvalidate(LibertyPort *from_port, bool Sta::idealClockMode() { - for (auto clk : sdc_->clks()) { + for (Clock *clk : sdc_->clks()) { if (clk->isPropagated()) return false; } @@ -3851,14 +3851,14 @@ static bool libertyPortCapsEqual(LibertyPort *port1, LibertyPort *port2) { - return port1->capacitance(TransRiseFall::rise(), MinMax::min()) - == port2->capacitance(TransRiseFall::rise(), MinMax::min()) - && port1->capacitance(TransRiseFall::rise(), MinMax::max()) - == port2->capacitance(TransRiseFall::rise(), MinMax::max()) - && port1->capacitance(TransRiseFall::fall(), MinMax::min()) - == port2->capacitance(TransRiseFall::fall(), MinMax::min()) - && port1->capacitance(TransRiseFall::fall(), MinMax::max()) - == port2->capacitance(TransRiseFall::fall(), MinMax::max()); + return port1->capacitance(RiseFall::rise(), MinMax::min()) + == port2->capacitance(RiseFall::rise(), MinMax::min()) + && port1->capacitance(RiseFall::rise(), MinMax::max()) + == port2->capacitance(RiseFall::rise(), MinMax::max()) + && port1->capacitance(RiseFall::fall(), MinMax::min()) + == port2->capacitance(RiseFall::fall(), MinMax::min()) + && port1->capacitance(RiseFall::fall(), MinMax::max()) + == port2->capacitance(RiseFall::fall(), MinMax::max()); } void @@ -4271,52 +4271,52 @@ Sta::clocks(const Pin *pin, InstanceSet * Sta::findRegisterInstances(ClockSet *clks, - const TransRiseFallBoth *clk_tr, + const RiseFallBoth *clk_rf, bool edge_triggered, bool latches) { findRegisterPreamble(); - return findRegInstances(clks, clk_tr, edge_triggered, latches, this); + return findRegInstances(clks, clk_rf, edge_triggered, latches, this); } PinSet * Sta::findRegisterDataPins(ClockSet *clks, - const TransRiseFallBoth *clk_tr, + const RiseFallBoth *clk_rf, bool edge_triggered, bool latches) { findRegisterPreamble(); - return findRegDataPins(clks, clk_tr, edge_triggered, latches, this); + return findRegDataPins(clks, clk_rf, edge_triggered, latches, this); } PinSet * Sta::findRegisterClkPins(ClockSet *clks, - const TransRiseFallBoth *clk_tr, + const RiseFallBoth *clk_rf, bool edge_triggered, bool latches) { findRegisterPreamble(); - return findRegClkPins(clks, clk_tr, edge_triggered, latches, this); + return findRegClkPins(clks, clk_rf, edge_triggered, latches, this); } PinSet * Sta::findRegisterAsyncPins(ClockSet *clks, - const TransRiseFallBoth *clk_tr, + const RiseFallBoth *clk_rf, bool edge_triggered, bool latches) { findRegisterPreamble(); - return findRegAsyncPins(clks, clk_tr, edge_triggered, latches, this); + return findRegAsyncPins(clks, clk_rf, edge_triggered, latches, this); } PinSet * Sta::findRegisterOutputPins(ClockSet *clks, - const TransRiseFallBoth *clk_tr, + const RiseFallBoth *clk_rf, bool edge_triggered, bool latches) { findRegisterPreamble(); - return findRegOutputPins(clks, clk_tr, edge_triggered, latches, this); + return findRegOutputPins(clks, clk_rf, edge_triggered, latches, this); } void @@ -4730,9 +4730,9 @@ InstanceMaxSlewGreater::instMaxSlew(const Instance *inst) const Pin *pin = pin_iter->next(); if (network->isDriver(pin)) { Vertex *vertex = graph->pinDrvrVertex(pin); - for (auto tr : TransRiseFall::range()) { + for (RiseFall *rf : RiseFall::range()) { for (auto dcalc_ap : sta_->corners()->dcalcAnalysisPts()) { - Slew slew = graph->slew(vertex, tr, dcalc_ap->index()); + Slew slew = graph->slew(vertex, rf, dcalc_ap->index()); if (slew > max_slew) max_slew = slew; } @@ -4800,12 +4800,12 @@ Sta::reportSlewLimitShort(Pin *pin, const MinMax *min_max) { const Corner *corner1; - const TransRiseFall *tr; + const RiseFall *rf; Slew slew; float limit, slack; check_slew_limits_->checkSlews(pin, corner, min_max, - corner1, tr, slew, limit, slack); - report_path_->reportSlewLimitShort(pin, tr, slew, limit, slack); + corner1, rf, slew, limit, slack); + report_path_->reportSlewLimitShort(pin, rf, slew, limit, slack); } void @@ -4814,12 +4814,12 @@ Sta::reportSlewLimitVerbose(Pin *pin, const MinMax *min_max) { const Corner *corner1; - const TransRiseFall *tr; + const RiseFall *rf; Slew slew; float limit, slack; check_slew_limits_->checkSlews(pin, corner, min_max, - corner1, tr, slew, limit, slack); - report_path_->reportSlewLimitVerbose(pin, corner1, tr, slew, + corner1, rf, slew, limit, slack); + report_path_->reportSlewLimitVerbose(pin, corner1, rf, slew, limit, slack, min_max); } @@ -4829,7 +4829,7 @@ Sta::checkSlews(const Pin *pin, const MinMax *min_max, // Return values. const Corner *&corner1, - const TransRiseFall *&tr, + const RiseFall *&rf, Slew &slew, float &limit, float &slack) @@ -4837,7 +4837,7 @@ Sta::checkSlews(const Pin *pin, checkSlewLimitPreamble(); check_slew_limits_->init(min_max); check_slew_limits_->checkSlews(pin, corner, min_max, - corner1, tr, slew, limit, slack); + corner1, rf, slew, limit, slack); } ////////////////////////////////////////////////////////////////' diff --git a/search/Sta.hh b/search/Sta.hh index 927a21f5..76c4c691 100644 --- a/search/Sta.hh +++ b/search/Sta.hh @@ -39,8 +39,8 @@ using ::Tcl_Interp; // Don't include headers to minimize dependencies. class MinMax; class MinMaxAll; -class TransRiseFallBoth; -class TransRiseFall; +class RiseFallBoth; +class RiseFall; class ReportPath; class CheckTiming; class DcalcAnalysisPt; @@ -126,49 +126,49 @@ public: const MinMaxAll *min_max); void setTimingDerate(TimingDerateType type, PathClkOrData clk_data, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, const EarlyLate *early_late, float derate); // Delay type is always net for net derating. void setTimingDerate(const Net *net, PathClkOrData clk_data, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, const EarlyLate *early_late, float derate); void setTimingDerate(const Instance *inst, TimingDerateType type, PathClkOrData clk_data, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, const EarlyLate *early_late, float derate); void setTimingDerate(const LibertyCell *cell, TimingDerateType type, PathClkOrData clk_data, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, const EarlyLate *early_late, float derate); void unsetTimingDerate(); void setInputSlew(Port *port, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, const MinMaxAll *min_max, float slew); // Port external pin load. float portExtPinCap(Port *port, - const TransRiseFall *tr, + const RiseFall *rf, const MinMax *min_max); // Set port external pin load (set_load -pin port). void setPortExtPinCap(Port *port, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, const MinMaxAll *min_max, float cap); // Port external wire load. float portExtWireCap(Port *port, - const TransRiseFall *tr, + const RiseFall *rf, const MinMax *min_max); // Set port external wire load (set_load -wire port). void setPortExtWireCap(Port *port, bool subtract_pin_cap, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, const MinMaxAll *min_max, float cap); // Set net wire capacitance (set_load -wire net). @@ -189,13 +189,13 @@ public: // pin_cap = net pin capacitances + port external pin capacitance, // wire_cap = annotated net capacitance + port external wire capacitance. void connectedCap(Pin *drvr_pin, - const TransRiseFall *tr, + const RiseFall *rf, const Corner *corner, const MinMax *min_max, float &pin_cap, float &wire_cap) const; void connectedCap(Net *net, - const TransRiseFall *tr, + const RiseFall *rf, const Corner *corner, const MinMax *min_max, float &pin_cap, @@ -209,10 +209,10 @@ public: LibertyPort *from_port, float *from_slews, LibertyPort *to_port, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, const MinMaxAll *min_max); void setDriveResistance(Port *port, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, const MinMaxAll *min_max, float res); void setLatchBorrowLimit(Pin *pin, @@ -221,16 +221,16 @@ public: float limit); void setLatchBorrowLimit(Clock *clk, float limit); - void setMinPulseWidth(const TransRiseFallBoth *tr, + void setMinPulseWidth(const RiseFallBoth *rf, float min_width); void setMinPulseWidth(const Pin *pin, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, float min_width); void setMinPulseWidth(const Instance *inst, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, float min_width); void setMinPulseWidth(const Clock *clk, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, float min_width); void setWireload(Wireload *wireload, const MinMaxAll *min_max); @@ -238,7 +238,7 @@ public: void setWireloadSelection(WireloadSelection *selection, const MinMaxAll *min_max); void setSlewLimit(Clock *clk, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, const PathClkOrData clk_data, const MinMax *min_max, float slew); @@ -310,7 +310,7 @@ public: void setPropagatedClock(Pin *pin); void removePropagatedClock(Pin *pin); void setClockSlew(Clock *clock, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, const MinMaxAll *min_max, float slew); void removeClockSlew(Clock *clk); @@ -318,7 +318,7 @@ public: // Latency can be on a clk, pin, or clk/pin combination. void setClockLatency(Clock *clk, Pin *pin, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, const MinMaxAll *min_max, float delay); void removeClockLatency(const Clock *clk, @@ -326,7 +326,7 @@ public: // Clock insertion delay (source latency). void setClockInsertion(const Clock *clk, const Pin *pin, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, const MinMaxAll *min_max, const EarlyLateAll *early_late, float delay); @@ -345,15 +345,15 @@ public: const SetupHoldAll *setup_hold); // Inter-clock uncertainty. virtual void setClockUncertainty(Clock *from_clk, - const TransRiseFallBoth *from_tr, + const RiseFallBoth *from_rf, Clock *to_clk, - const TransRiseFallBoth *to_tr, + const RiseFallBoth *to_rf, const SetupHoldAll *setup_hold, float uncertainty); virtual void removeClockUncertainty(Clock *from_clk, - const TransRiseFallBoth *from_tr, + const RiseFallBoth *from_rf, Clock *to_clk, - const TransRiseFallBoth *to_tr, + const RiseFallBoth *to_rf, const SetupHoldAll *setup_hold); ClockGroups *makeClockGroups(const char *name, bool logically_exclusive, @@ -370,34 +370,34 @@ public: void setClockSense(PinSet *pins, ClockSet *clks, ClockSense sense); - void setClockGatingCheck(const TransRiseFallBoth *tr, + void setClockGatingCheck(const RiseFallBoth *rf, const SetupHold *setup_hold, float margin); void setClockGatingCheck(Clock *clk, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, const SetupHold *setup_hold, float margin); void setClockGatingCheck(Instance *inst, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, const SetupHold *setup_hold, float margin, LogicValue active_value); void setClockGatingCheck(Pin *pin, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, const SetupHold *setup_hold, float margin, LogicValue active_value); void setDataCheck(Pin *from, - const TransRiseFallBoth *from_tr, + const RiseFallBoth *from_rf, Pin *to, - const TransRiseFallBoth *to_tr, + const RiseFallBoth *to_rf, Clock *clk, const SetupHoldAll *setup_hold, float margin); void removeDataCheck(Pin *from, - const TransRiseFallBoth *from_tr, + const RiseFallBoth *from_rf, Pin *to, - const TransRiseFallBoth *to_tr, + const RiseFallBoth *to_rf, Clock *clk, const SetupHoldAll *setup_hold); // set_disable_timing cell [-from] [-to] @@ -470,9 +470,9 @@ public: LogicValue value); void removeCaseAnalysis(Pin *pin); void setInputDelay(Pin *pin, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, Clock *clk, - const TransRiseFall *clk_tr, + const RiseFall *clk_rf, Pin *ref_pin, bool source_latency_included, bool network_latency_included, @@ -480,14 +480,14 @@ public: bool add, float delay); void removeInputDelay(Pin *pin, - TransRiseFallBoth *tr, + RiseFallBoth *rf, Clock *clk, - TransRiseFall *clk_tr, + RiseFall *clk_rf, MinMaxAll *min_max); void setOutputDelay(Pin *pin, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, Clock *clk, - const TransRiseFall *clk_tr, + const RiseFall *clk_rf, Pin *ref_pin, bool source_latency_included, bool network_latency_included, @@ -495,9 +495,9 @@ public: bool add, float delay); void removeOutputDelay(Pin *pin, - TransRiseFallBoth *tr, + RiseFallBoth *rf, Clock *clk, - TransRiseFall *clk_tr, + RiseFall *clk_rf, MinMaxAll *min_max); void makeFalsePath(ExceptionFrom *from, ExceptionThruSeq *thrus, @@ -533,7 +533,7 @@ public: ExceptionFrom *makeExceptionFrom(PinSet *from_pins, ClockSet *from_clks, InstanceSet *from_insts, - const TransRiseFallBoth *from_tr); + const RiseFallBoth *from_rf); void checkExceptionFromPins(ExceptionFrom *from, const char *file, int line) const; @@ -543,35 +543,35 @@ public: ExceptionThru *makeExceptionThru(PinSet *pins, NetSet *nets, InstanceSet *insts, - const TransRiseFallBoth *tr); + const RiseFallBoth *rf); void deleteExceptionThru(ExceptionThru *thru); // Make an exception -to specification. ExceptionTo *makeExceptionTo(PinSet *to_pins, ClockSet *to_clks, InstanceSet *to_insts, - const TransRiseFallBoth *tr, - TransRiseFallBoth *end_tr); + const RiseFallBoth *rf, + RiseFallBoth *end_rf); void checkExceptionToPins(ExceptionTo *to, const char *file, int) const; void deleteExceptionTo(ExceptionTo *to); InstanceSet *findRegisterInstances(ClockSet *clks, - const TransRiseFallBoth *clk_tr, + const RiseFallBoth *clk_rf, bool edge_triggered, bool latches); PinSet *findRegisterDataPins(ClockSet *clks, - const TransRiseFallBoth *clk_tr, + const RiseFallBoth *clk_rf, bool registers, bool latches); PinSet *findRegisterClkPins(ClockSet *clks, - const TransRiseFallBoth *clk_tr, + const RiseFallBoth *clk_rf, bool registers, bool latches); PinSet *findRegisterAsyncPins(ClockSet *clks, - const TransRiseFallBoth *clk_tr, + const RiseFallBoth *clk_rf, bool registers, bool latches); PinSet *findRegisterOutputPins(ClockSet *clks, - const TransRiseFallBoth *clk_tr, + const RiseFallBoth *clk_rf, bool registers, bool latches); PinSet * @@ -632,7 +632,7 @@ public: const MinMax *min_max, // Return values. const Corner *&corner1, - const TransRiseFall *&tr, + const RiseFall *&tr, Slew &slew, float &limit, float &slack); @@ -711,7 +711,7 @@ public: void setAnnotatedSlew(Vertex *vertex, const Corner *corner, const MinMaxAll *min_max, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, float slew); void writeSdf(const char *filename, Corner *corner, @@ -935,14 +935,14 @@ public: Slack &worst_slack, Vertex *&worst_vertex); VertexPathIterator *vertexPathIterator(Vertex *vertex, - const TransRiseFall *tr, + const RiseFall *rf, const PathAnalysisPt *path_ap); VertexPathIterator *vertexPathIterator(Vertex *vertex, - const TransRiseFall *tr, + const RiseFall *rf, const MinMax *min_max); void vertexWorstArrivalPath(Vertex *vertex, - const TransRiseFall *tr, + const RiseFall *rf, const MinMax *min_max, // Return value. PathRef &worst_path); @@ -958,7 +958,7 @@ public: PathRef &worst_path); void vertexWorstSlackPath(Vertex *vertex, - const TransRiseFall *tr, + const RiseFall *rf, const MinMax *min_max, // Return value. PathRef &worst_path); @@ -968,52 +968,52 @@ public: // passes required propagate arrivals around latch loops. // See Sta::updateTiming() to propagate arrivals around latch loops. Arrival vertexArrival(Vertex *vertex, - const TransRiseFall *tr, + const RiseFall *rf, const ClockEdge *clk_edge, const PathAnalysisPt *path_ap); // Min/max across all clock tags. Arrival vertexArrival(Vertex *vertex, - const TransRiseFall *tr, + const RiseFall *rf, const PathAnalysisPt *path_ap); Required vertexRequired(Vertex *vertex, const MinMax *min_max); // Min/max across all clock tags. Required vertexRequired(Vertex *vertex, - const TransRiseFall *tr, + const RiseFall *rf, const PathAnalysisPt *path_ap); Required vertexRequired(Vertex *vertex, - const TransRiseFall *tr, + const RiseFall *rf, const ClockEdge *clk_edge, const PathAnalysisPt *path_ap); Slack netSlack(const Net *net, const MinMax *min_max); Slack pinSlack(const Pin *pin, - const TransRiseFall *tr, + const RiseFall *rf, const MinMax *min_max); Slack pinSlack(const Pin *pin, const MinMax *min_max); Slack vertexSlack(Vertex *vertex, const MinMax *min_max); Slack vertexSlack(Vertex *vertex, - const TransRiseFall *tr, + const RiseFall *rf, const MinMax *min_max); // Slack with respect to clk_edge. Slack vertexSlack(Vertex *vertex, - const TransRiseFall *tr, + const RiseFall *rf, const ClockEdge *clk_edge, const PathAnalysisPt *path_ap); // Min slack across all clock tags. Slack vertexSlack(Vertex *vertex, - const TransRiseFall *tr, + const RiseFall *rf, const PathAnalysisPt *path_ap); // Slew for one delay calc analysis pt(corner). Slew vertexSlew(Vertex *vertex, - const TransRiseFall *tr, + const RiseFall *rf, const DcalcAnalysisPt *dcalc_ap); // Slew across all corners. Slew vertexSlew(Vertex *vertex, - const TransRiseFall *tr, + const RiseFall *rf, const MinMax *min_max); ArcDelay arcDelay(Edge *edge, TimingArc *arc, @@ -1065,7 +1065,7 @@ public: bool quiet); // Parasitics. void findPiElmore(Pin *drvr_pin, - const TransRiseFall *tr, + const RiseFall *rf, const MinMax *min_max, float &c2, float &rpi, @@ -1073,19 +1073,19 @@ public: bool &exists) const; void findElmore(Pin *drvr_pin, Pin *load_pin, - const TransRiseFall *tr, + const RiseFall *rf, const MinMax *min_max, float &elmore, bool &exists) const; void makePiElmore(Pin *drvr_pin, - const TransRiseFall *tr, + const RiseFall *rf, const MinMaxAll *min_max, float c2, float rpi, float c1); void setElmore(Pin *drvr_pin, Pin *load_pin, - const TransRiseFall *tr, + const RiseFall *rf, const MinMaxAll *min_max, float elmore); @@ -1242,7 +1242,7 @@ protected: void delaysInvalidFromFanin(Port *port); void deleteEdge(Edge *edge); void netParasiticCaps(Net *net, - const TransRiseFall *tr, + const RiseFall *rf, const MinMax *min_max, float &pin_cap, float &wire_cap) const; @@ -1251,7 +1251,7 @@ protected: Instance *inst, PinSet *pins); Slack vertexSlack1(Vertex *vertex, - const TransRiseFall *tr, + const RiseFall *rf, const ClockEdge *clk_edge, const PathAnalysisPt *path_ap); void findRequired(Vertex *vertex); diff --git a/search/Tag.cc b/search/Tag.cc index 9ce71ecf..a6087176 100644 --- a/search/Tag.cc +++ b/search/Tag.cc @@ -100,10 +100,10 @@ Tag::asString(bool report_index, if (report_index) str += stringPrintTmp("%4d ", index_); - const TransRiseFall *tr = transition(); + const RiseFall *rf = transition(); PathAnalysisPt *path_ap = corners->findPathAnalysisPt(path_ap_index_); str += stringPrintTmp("%s %s/%d ", - tr->asString(), + rf->asString(), path_ap->pathMinMax()->asString(), path_ap_index_); @@ -174,10 +174,10 @@ Tag::asString(bool report_index, return result; } -const TransRiseFall * +const RiseFall * Tag::transition() const { - return TransRiseFall::find(tr_index_); + return RiseFall::find(tr_index_); } PathAnalysisPt * @@ -296,12 +296,12 @@ TagLess::operator()(const Tag *tag1, int tagCmp(const Tag *tag1, const Tag *tag2, - bool cmp_tr) + bool cmp_rf) { if (tag1 == tag2) return 0; - if (cmp_tr) { + if (cmp_rf) { int tr_index1 = tag1->trIndex(); int tr_index2 = tag2->trIndex(); if (tr_index1 < tr_index2) diff --git a/search/Tag.hh b/search/Tag.hh index ea522985..5a3202e5 100644 --- a/search/Tag.hh +++ b/search/Tag.hh @@ -65,7 +65,7 @@ public: Clock *clock() const; const Pin *clkSrc() const; int trIndex() const { return tr_index_; } - const TransRiseFall *transition() const; + const RiseFall *transition() const; PathAnalysisPt *pathAnalysisPt(const StaState *sta) const; PathAPIndex pathAPIndex() const { return path_ap_index_; } TagIndex index() const { return index_; } @@ -99,7 +99,7 @@ private: // Indicates that states_ is owned by the tag. bool own_states_:1; TagIndex index_:tag_index_bits; - unsigned int tr_index_:TransRiseFall::index_bit_count; + unsigned int tr_index_:RiseFall::index_bit_count; unsigned int path_ap_index_:path_ap_index_bit_count; }; @@ -133,7 +133,7 @@ public: int tagCmp(const Tag *tag1, const Tag *tag2, - bool cmp_tr); + bool cmp_rf); // Match tag clock edge, clock driver and exception states but not clk info. bool diff --git a/search/TagGroup.cc b/search/TagGroup.cc index 7135dce8..d0877b4d 100644 --- a/search/TagGroup.cc +++ b/search/TagGroup.cc @@ -138,7 +138,7 @@ arrivalMapReport(const ArrivalMap *arrival_map, TagGroupBldr::TagGroupBldr(bool match_crpr_clk_pin, const StaState *sta) : default_arrival_count_(sta->corners()->count() - * TransRiseFall::index_count + * RiseFall::index_count * MinMax::index_count), arrival_map_(default_arrival_count_, TagMatchHash(match_crpr_clk_pin, sta), diff --git a/search/VisitPathEnds.cc b/search/VisitPathEnds.cc index f598f637..5cd2907d 100644 --- a/search/VisitPathEnds.cc +++ b/search/VisitPathEnds.cc @@ -86,28 +86,28 @@ VisitPathEnds::visitClkedPathEnds(const Pin *pin, PathVertex *path = path_iter.next(); PathAnalysisPt *path_ap = path->pathAnalysisPt(this); const MinMax *path_min_max = path_ap->pathMinMax(); - const TransRiseFall *end_tr = path->transition(this); + const RiseFall *end_rf = path->transition(this); Tag *tag = path->tag(this); if ((corner == nullptr || path_ap->corner() == corner) && min_max->matches(path_min_max) // Ignore generated clock source paths. && !path->clkInfo(this)->isGenClkSrcPath() - && !falsePathTo(path, pin, end_tr, path_min_max) + && !falsePathTo(path, pin, end_rf, path_min_max) // Ignore segment startpoint paths. && (!is_segment_start || !tag->isSegmentStart())) { // set_output_delay to timing check has precidence. if (sdc_->hasOutputDelay(pin)) - visitOutputDelayEnd(pin, path, end_tr, path_ap, filtered, visitor, + visitOutputDelayEnd(pin, path, end_rf, path_ap, filtered, visitor, is_constrained); else if (vertex->hasChecks()) - visitCheckEnd(pin, vertex, path, end_tr, path_ap, filtered, visitor, + visitCheckEnd(pin, vertex, path, end_rf, path_ap, filtered, visitor, is_constrained); else if (!sdc_->exceptionToInvalid(pin) && (!filtered || search_->matchesFilter(path, nullptr))) { - PathDelay *path_delay = pathDelayTo(path, pin, end_tr, path_min_max); + PathDelay *path_delay = pathDelayTo(path, pin, end_rf, path_min_max); if (path_delay) { PathEndPathDelay path_end(path_delay, path, this); visitor->visit(&path_end); @@ -115,9 +115,9 @@ VisitPathEnds::visitClkedPathEnds(const Pin *pin, } } if (sdc_->gatedClkChecksEnabled()) - visitGatedClkEnd(pin, vertex, path, end_tr, path_ap, filtered, visitor, + visitGatedClkEnd(pin, vertex, path, end_rf, path_ap, filtered, visitor, is_constrained); - visitDataCheckEnd(pin, path, end_tr, path_ap, filtered, visitor, + visitDataCheckEnd(pin, path, end_rf, path_ap, filtered, visitor, is_constrained); } } @@ -127,7 +127,7 @@ void VisitPathEnds::visitCheckEnd(const Pin *pin, Vertex *vertex, Path *path, - const TransRiseFall *end_tr, + const RiseFall *end_rf, const PathAnalysisPt *path_ap, bool filtered, PathEndVisitor *visitor, @@ -149,10 +149,10 @@ VisitPathEnds::visitCheckEnd(const Pin *pin, TimingArcSetArcIterator arc_iter(arc_set); while (arc_iter.hasNext()) { TimingArc *check_arc = arc_iter.next(); - TransRiseFall *clk_tr = check_arc->fromTrans()->asRiseFall(); - if (check_arc->toTrans()->asRiseFall() == end_tr - && clk_tr) { - VertexPathIterator tgt_clk_path_iter(tgt_clk_vertex, clk_tr, + RiseFall *clk_rf = check_arc->fromTrans()->asRiseFall(); + if (check_arc->toTrans()->asRiseFall() == end_rf + && clk_rf) { + VertexPathIterator tgt_clk_path_iter(tgt_clk_vertex, clk_rf, tgt_clk_path_ap, this); while (tgt_clk_path_iter.hasNext()) { PathVertex *tgt_clk_path = tgt_clk_path_iter.next(); @@ -160,7 +160,7 @@ VisitPathEnds::visitCheckEnd(const Pin *pin, const ClockEdge *tgt_clk_edge = tgt_clk_path->clkEdge(this); const Clock *tgt_clk = tgt_clk_path->clock(this); const Pin *tgt_pin = tgt_clk_vertex->pin(); - ExceptionPath *exception = exceptionTo(path, pin, end_tr, + ExceptionPath *exception = exceptionTo(path, pin, end_rf, tgt_clk_edge, min_max); // Ignore generated clock source paths. if (!tgt_clk_info->isGenClkSrcPath() @@ -228,7 +228,7 @@ VisitPathEnds::visitCheckEnd(const Pin *pin, } if (!check_clked && !sdc_->exceptionToInvalid(pin)) - visitCheckEndUnclked(pin, vertex, path, end_tr, path_ap, filtered, + visitCheckEndUnclked(pin, vertex, path, end_rf, path_ap, filtered, visitor, is_constrained); } @@ -236,7 +236,7 @@ void VisitPathEnds::visitCheckEndUnclked(const Pin *pin, Vertex *vertex, Path *path, - const TransRiseFall *end_tr, + const RiseFall *end_rf, const PathAnalysisPt *path_ap, bool filtered, PathEndVisitor *visitor, @@ -253,12 +253,12 @@ VisitPathEnds::visitCheckEndUnclked(const Pin *pin, TimingArcSetArcIterator arc_iter(arc_set); while (arc_iter.hasNext()) { TimingArc *check_arc = arc_iter.next(); - TransRiseFall *clk_tr = check_arc->fromTrans()->asRiseFall(); - if (check_arc->toTrans()->asRiseFall() == end_tr - && clk_tr + RiseFall *clk_rf = check_arc->fromTrans()->asRiseFall(); + if (check_arc->toTrans()->asRiseFall() == end_rf + && clk_rf && (!filtered || search_->matchesFilter(path, nullptr))) { - ExceptionPath *exception = exceptionTo(path, pin, end_tr, + ExceptionPath *exception = exceptionTo(path, pin, end_rf, nullptr, min_max); // False paths and path delays override multicycle paths. if (exception @@ -292,7 +292,7 @@ VisitPathEnds::checkEdgeEnabled(Edge *edge) const void VisitPathEnds::visitOutputDelayEnd(const Pin *pin, Path *path, - const TransRiseFall *end_tr, + const RiseFall *end_rf, const PathAnalysisPt *path_ap, bool filtered, PathEndVisitor *visitor, @@ -304,7 +304,7 @@ VisitPathEnds::visitOutputDelayEnd(const Pin *pin, for (OutputDelay *output_delay : *output_delays) { float margin; bool exists; - output_delay->delays()->value(end_tr, min_max, margin, exists); + output_delay->delays()->value(end_rf, min_max, margin, exists); if (exists) { const Pin *ref_pin = output_delay->refPin(); ClockEdge *tgt_clk_edge = output_delay->clkEdge(); @@ -313,20 +313,20 @@ VisitPathEnds::visitOutputDelayEnd(const Pin *pin, if (ref_pin) { Clock *tgt_clk = output_delay->clock(); Vertex *ref_vertex = graph_->pinLoadVertex(ref_pin); - TransRiseFall *ref_tr = output_delay->refTransition(); - VertexPathIterator ref_path_iter(ref_vertex,ref_tr,path_ap,this); + RiseFall *ref_rf = output_delay->refTransition(); + VertexPathIterator ref_path_iter(ref_vertex,ref_rf,path_ap,this); while (ref_path_iter.hasNext()) { PathVertex *ref_path = ref_path_iter.next(); if (ref_path->isClock(this) && (tgt_clk == nullptr || ref_path->clock(this) == tgt_clk)) - visitOutputDelayEnd1(output_delay, pin, path, end_tr, + visitOutputDelayEnd1(output_delay, pin, path, end_rf, ref_path->clkEdge(this), ref_path, min_max, visitor, is_constrained); } } else - visitOutputDelayEnd1(output_delay, pin, path, end_tr, + visitOutputDelayEnd1(output_delay, pin, path, end_rf, tgt_clk_edge, nullptr, min_max, visitor, is_constrained); } @@ -339,7 +339,7 @@ void VisitPathEnds::visitOutputDelayEnd1(OutputDelay *output_delay, const Pin *pin, Path *path, - const TransRiseFall *end_tr, + const RiseFall *end_rf, const ClockEdge *tgt_clk_edge, PathVertex *ref_path, const MinMax *min_max, @@ -348,7 +348,7 @@ VisitPathEnds::visitOutputDelayEnd1(OutputDelay *output_delay, { // Target clk is not required for path delay, // but the exception may be -to clk. - ExceptionPath *exception = exceptionTo(path, pin, end_tr, tgt_clk_edge, + ExceptionPath *exception = exceptionTo(path, pin, end_rf, tgt_clk_edge, min_max); if (exception && exception->isPathDelay()) { @@ -378,7 +378,7 @@ void VisitPathEnds::visitGatedClkEnd(const Pin *pin, Vertex *vertex, Path *path, - const TransRiseFall *end_tr, + const RiseFall *end_rf, const PathAnalysisPt *path_ap, bool filtered, PathEndVisitor *visitor, @@ -399,13 +399,13 @@ VisitPathEnds::visitGatedClkEnd(const Pin *pin, Vertex *clk_vertex = graph_->pinLoadVertex(clk_pin); LogicValue active_value = sdc_->clockGatingActiveValue(clk_pin, pin); - TransRiseFall *clk_tr = + RiseFall *clk_rf = // Clock active value specified by set_clock_gating_check // overrides the library cell function active value. gated_clk->gatedClkActiveTrans((active_value == LogicValue::unknown) ? logic_active_value : active_value, min_max); - VertexPathIterator clk_path_iter(clk_vertex, clk_tr, clk_path_ap, this); + VertexPathIterator clk_path_iter(clk_vertex, clk_rf, clk_path_ap, this); while (clk_path_iter.hasNext()) { PathVertex *clk_path = clk_path_iter.next(); const ClockEdge *clk_edge = clk_path->clkEdge(this); @@ -423,8 +423,8 @@ VisitPathEnds::visitGatedClkEnd(const Pin *pin, ? TimingRole::gatedClockSetup() : TimingRole::gatedClockHold(); float margin = clockGatingMargin(clk, clk_pin, - pin, end_tr, min_max); - ExceptionPath *exception = exceptionTo(path, pin, end_tr, + pin, end_rf, min_max); + ExceptionPath *exception = exceptionTo(path, pin, end_rf, clk_edge, min_max); if (sdc_->sameClockGroup(src_clk, clk) // False paths and path delays override. @@ -453,29 +453,29 @@ float VisitPathEnds::clockGatingMargin(const Clock *clk, const Pin *clk_pin, const Pin *enable_pin, - const TransRiseFall *enable_tr, + const RiseFall *enable_rf, const SetupHold *setup_hold) { bool exists; float margin; - sdc_->clockGatingMarginEnablePin(enable_pin, enable_tr, + sdc_->clockGatingMarginEnablePin(enable_pin, enable_rf, setup_hold, exists, margin); if (exists) return margin; Instance *inst = network_->instance(enable_pin); - sdc_->clockGatingMarginInstance(inst, enable_tr, setup_hold, + sdc_->clockGatingMarginInstance(inst, enable_rf, setup_hold, exists, margin); if (exists) return margin; - sdc_->clockGatingMarginClkPin(clk_pin, enable_tr, setup_hold, + sdc_->clockGatingMarginClkPin(clk_pin, enable_rf, setup_hold, exists, margin); if (exists) return margin; - sdc_->clockGatingMarginClk(clk, enable_tr, setup_hold, + sdc_->clockGatingMarginClk(clk, enable_rf, setup_hold, exists, margin); if (exists) return margin; - sdc_->clockGatingMargin(enable_tr, setup_hold, + sdc_->clockGatingMargin(enable_rf, setup_hold, exists, margin); if (exists) return margin; @@ -488,7 +488,7 @@ VisitPathEnds::clockGatingMargin(const Clock *clk, void VisitPathEnds::visitDataCheckEnd(const Pin *pin, Path *path, - const TransRiseFall *end_tr, + const RiseFall *end_rf, const PathAnalysisPt *path_ap, bool filtered, PathEndVisitor *visitor, @@ -506,14 +506,14 @@ VisitPathEnds::visitDataCheckEnd(const Pin *pin, DataCheck *check = check_iter.next(); const Pin *from_pin = check->from(); Vertex *from_vertex = graph_->pinLoadVertex(from_pin); - for (auto from_tr : TransRiseFall::range()) { + for (auto from_rf : RiseFall::range()) { float margin; bool margin_exists; - check->margin(from_tr, end_tr, min_max, margin, margin_exists); + check->margin(from_rf, end_rf, min_max, margin, margin_exists); if (margin_exists) - visitDataCheckEnd1(check, pin, path, src_clk, end_tr, + visitDataCheckEnd1(check, pin, path, src_clk, end_rf, min_max, clk_ap, from_pin, from_vertex, - from_tr, filtered, visitor, is_constrained); + from_rf, filtered, visitor, is_constrained); } } } @@ -525,23 +525,23 @@ VisitPathEnds::visitDataCheckEnd1(DataCheck *check, const Pin *pin, Path *path, const Clock *src_clk, - const TransRiseFall *end_tr, + const RiseFall *end_rf, const MinMax *min_max, const PathAnalysisPt *clk_ap, const Pin *from_pin, Vertex *from_vertex, - TransRiseFall *from_tr, + RiseFall *from_rf, bool filtered, PathEndVisitor *visitor, bool &is_constrained) { bool found_from_path = false; - VertexPathIterator tgt_clk_path_iter(from_vertex,from_tr,clk_ap,this); + VertexPathIterator tgt_clk_path_iter(from_vertex,from_rf,clk_ap,this); while (tgt_clk_path_iter.hasNext()) { PathVertex *tgt_clk_path = tgt_clk_path_iter.next(); const ClockEdge *tgt_clk_edge = tgt_clk_path->clkEdge(this); const Clock *tgt_clk = tgt_clk_edge ? tgt_clk_edge->clock() : nullptr; - ExceptionPath *exception = exceptionTo(path, pin, end_tr, + ExceptionPath *exception = exceptionTo(path, pin, end_rf, tgt_clk_edge, min_max); // Ignore generated clock source paths. if (!tgt_clk_path->clkInfo(this)->isGenClkSrcPath() @@ -602,11 +602,11 @@ VisitPathEnds::visitUnconstrainedPathEnds(const Pin *pin, bool VisitPathEnds::falsePathTo(Path *path, const Pin *pin, - const TransRiseFall *tr, + const RiseFall *rf, const MinMax *min_max) { ExceptionPath *exception = search_->exceptionTo(ExceptionPathType::false_path, path, - pin, tr, nullptr, min_max, + pin, rf, nullptr, min_max, false, false); return exception != nullptr; } @@ -614,11 +614,11 @@ VisitPathEnds::falsePathTo(Path *path, PathDelay * VisitPathEnds::pathDelayTo(Path *path, const Pin *pin, - const TransRiseFall *tr, + const RiseFall *rf, const MinMax *min_max) { ExceptionPath *exception = search_->exceptionTo(ExceptionPathType::path_delay, - path, pin, tr, nullptr, + path, pin, rf, nullptr, min_max, false, // Register clk pins only // match with -to pin. @@ -629,11 +629,11 @@ VisitPathEnds::pathDelayTo(Path *path, ExceptionPath * VisitPathEnds::exceptionTo(const Path *path, const Pin *pin, - const TransRiseFall *tr, + const RiseFall *rf, const ClockEdge *clk_edge, const MinMax *min_max) const { - return search_->exceptionTo(ExceptionPathType::any, path, pin, tr, clk_edge, + return search_->exceptionTo(ExceptionPathType::any, path, pin, rf, clk_edge, min_max, false, false); } diff --git a/search/VisitPathEnds.hh b/search/VisitPathEnds.hh index 9a9cb7b8..7e6eb272 100644 --- a/search/VisitPathEnds.hh +++ b/search/VisitPathEnds.hh @@ -52,7 +52,7 @@ protected: virtual void visitCheckEnd(const Pin *pin, Vertex *vertex, Path *path, - const TransRiseFall *end_tr, + const RiseFall *end_rf, const PathAnalysisPt *path_ap, bool filtered, PathEndVisitor *visitor, @@ -60,14 +60,14 @@ protected: void visitCheckEndUnclked(const Pin *pin, Vertex *vertex, Path *path, - const TransRiseFall *end_tr, + const RiseFall *end_rf, const PathAnalysisPt *path_ap, bool filtered, PathEndVisitor *visitor, bool &is_constrained); void visitOutputDelayEnd(const Pin *pin, Path *path, - const TransRiseFall *end_tr, + const RiseFall *end_rf, const PathAnalysisPt *path_ap, bool filtered, PathEndVisitor *visitor, @@ -75,7 +75,7 @@ protected: virtual void visitOutputDelayEnd1(OutputDelay *output_delay, const Pin *pin, Path *path, - const TransRiseFall *end_tr, + const RiseFall *end_rf, const ClockEdge *tgt_clk_edge, PathVertex *ref_path, const MinMax *min_max, @@ -84,7 +84,7 @@ protected: virtual void visitGatedClkEnd(const Pin *pin, Vertex *vertex, Path *path, - const TransRiseFall *end_tr, + const RiseFall *end_rf, const PathAnalysisPt *path_ap, bool filtered, PathEndVisitor *visitor, @@ -92,11 +92,11 @@ protected: float clockGatingMargin(const Clock *clk, const Pin *clk_pin, const Pin *enable_pin, - const TransRiseFall *enable_tr, + const RiseFall *enable_rf, const SetupHold *setup_hold); void visitDataCheckEnd(const Pin *pin, Path *path, - const TransRiseFall *end_tr, + const RiseFall *end_rf, const PathAnalysisPt *path_ap, bool filtered, PathEndVisitor *visitor, @@ -105,12 +105,12 @@ protected: const Pin *pin, Path *path, const Clock *src_clk, - const TransRiseFall *end_tr, + const RiseFall *end_rf, const MinMax *min_max, const PathAnalysisPt *clk_ap, const Pin *from_pin, Vertex *from_vertex, - TransRiseFall *from_tr, + RiseFall *from_rf, bool filtered, PathEndVisitor *visitor, bool &is_constrained); @@ -122,15 +122,15 @@ protected: PathEndVisitor *visitor); bool falsePathTo(Path *path, const Pin *pin, - const TransRiseFall *tr, + const RiseFall *rf, const MinMax *min_max); PathDelay *pathDelayTo(Path *path, const Pin *pin, - const TransRiseFall *tr, + const RiseFall *rf, const MinMax *min_max); ExceptionPath *exceptionTo(const Path *path, const Pin *pin, - const TransRiseFall *tr, + const RiseFall *rf, const ClockEdge *clk_edge, const MinMax *min_max) const; }; diff --git a/search/VisitPathGroupVertices.cc b/search/VisitPathGroupVertices.cc index fae65a7b..348eb3fc 100644 --- a/search/VisitPathGroupVertices.cc +++ b/search/VisitPathGroupVertices.cc @@ -78,14 +78,14 @@ protected: // Return false to stop visiting. virtual bool visitFromToPath(const Pin *from_pin, Vertex *from_vertex, - const TransRiseFall *from_tr, + const RiseFall *from_rf, Tag *from_tag, PathVertex *from_path, Edge *edge, TimingArc *arc, ArcDelay arc_delay, Vertex *to_vertex, - const TransRiseFall *to_tr, + const RiseFall *to_rf, Tag *to_tag, Arrival &to_arrival, const MinMax *min_max, @@ -257,14 +257,14 @@ PathGroupPathVisitor::visit(Vertex *vertex) bool PathGroupPathVisitor::visitFromToPath(const Pin *, Vertex *from_vertex, - const TransRiseFall *, + const RiseFall *, Tag *from_tag, PathVertex *from_path, Edge *, TimingArc *, ArcDelay , Vertex *to_vertex, - const TransRiseFall *to_tr, + const RiseFall *to_rf, Tag *to_tag, Arrival &, const MinMax *, @@ -288,7 +288,7 @@ PathGroupPathVisitor::visitFromToPath(const Pin *, } } else { - VertexPathIterator to_iter(to_vertex, to_tr, path_ap, sta_); + VertexPathIterator to_iter(to_vertex, to_rf, path_ap, sta_); while (to_iter.hasNext()) { PathVertex *to_path = to_iter.next(); if (tagMatchNoCrpr(to_path->tag(sta_), to_tag) diff --git a/search/WritePathSpice.cc b/search/WritePathSpice.cc index 5b2dccd4..3a319af8 100644 --- a/search/WritePathSpice.cc +++ b/search/WritePathSpice.cc @@ -79,7 +79,7 @@ private: void writeStageInstances(); void writeInputSource(); void writeStepVoltSource(const Pin *pin, - const TransRiseFall *tr, + const RiseFall *rf, float slew, float time, int &volt_index); @@ -104,7 +104,7 @@ private: float maxTime(); const char *nodeName(ParasiticNode *node); void initNodeMap(const char *net_name); - const char *spiceTrans(const TransRiseFall *tr); + const char *spiceTrans(const RiseFall *rf); void writeMeasureDelayStmt(Stage stage, Path *from_path, Path *to_path); @@ -126,26 +126,26 @@ private: // Return values. LibertyPortLogicValues &port_values); void seqPortValues(Sequential *seq, - const TransRiseFall *tr, + const RiseFall *rf, // Return values. LibertyPortLogicValues &port_values); void writeInputWaveform(); void writeClkWaveform(); - void writeWaveformEdge(const TransRiseFall *tr, + void writeWaveformEdge(const RiseFall *rf, float time, float slew); void writeClkedStepSource(const Pin *pin, - const TransRiseFall *tr, + const RiseFall *rf, const Clock *clk, DcalcAPIndex dcalc_ap_index, int &volt_index); float clkWaveformTImeOffset(const Clock *clk); float findSlew(Path *path); float findSlew(Path *path, - const TransRiseFall *tr, + const RiseFall *rf, TimingArc *next_arc); float findSlew(Vertex *vertex, - const TransRiseFall *tr, + const RiseFall *rf, TimingArc *next_arc, DcalcAPIndex dcalc_ap_index); LibertyPort *onePort(FuncExpr *expr); @@ -465,13 +465,13 @@ WritePathSpice::writeInputWaveform() void WritePathSpice::writeStepVoltSource(const Pin *pin, - const TransRiseFall *tr, + const RiseFall *rf, float slew, float time, int &volt_index) { float volt0, volt1; - if (tr == TransRiseFall::rise()) { + if (rf == RiseFall::rise()) { volt0 = gnd_voltage_; volt1 = power_voltage_; } @@ -483,7 +483,7 @@ WritePathSpice::writeStepVoltSource(const Pin *pin, volt_index, network_->pathName(pin)); streamPrint(spice_stream_, "+%.3e %.3e\n", 0.0, volt0); - writeWaveformEdge(tr, time, slew); + writeWaveformEdge(rf, time, slew); streamPrint(spice_stream_, "+%.3e %.3e\n", maxTime(), volt1); streamPrint(spice_stream_, "+)\n"); volt_index++; @@ -499,28 +499,28 @@ WritePathSpice::writeClkWaveform() auto clk = clk_edge->clock(); auto period = clk->period(); float time_offset = clkWaveformTImeOffset(clk); - TransRiseFall *tr0, *tr1; + RiseFall *rf0, *rf1; float volt0; if (clk_edge->time() < period) { - tr0 = TransRiseFall::rise(); - tr1 = TransRiseFall::fall(); + rf0 = RiseFall::rise(); + rf1 = RiseFall::fall(); volt0 = gnd_voltage_; } else { - tr0 = TransRiseFall::fall(); - tr1 = TransRiseFall::rise(); + rf0 = RiseFall::fall(); + rf1 = RiseFall::rise(); volt0 = power_voltage_; } - auto slew0 = findSlew(input_path, tr0, next_arc); - auto slew1 = findSlew(input_path, tr1, next_arc); + auto slew0 = findSlew(input_path, rf0, next_arc); + auto slew1 = findSlew(input_path, rf1, next_arc); streamPrint(spice_stream_, "v1 %s 0 pwl(\n", stageDrvrPinName(input_stage)); streamPrint(spice_stream_, "+%.3e %.3e\n", 0.0, volt0); for (int cycle = 0; cycle < clk_cycle_count_; cycle++) { auto time0 = time_offset + cycle * period; auto time1 = time0 + period / 2.0; - writeWaveformEdge(tr0, time0, slew0); - writeWaveformEdge(tr1, time1, slew1); + writeWaveformEdge(rf0, time0, slew0); + writeWaveformEdge(rf1, time1, slew1); } streamPrint(spice_stream_, "+%.3e %.3e\n", maxTime(), volt0); streamPrint(spice_stream_, "+)\n"); @@ -535,29 +535,29 @@ WritePathSpice::clkWaveformTImeOffset(const Clock *clk) float WritePathSpice::findSlew(Path *path) { - auto vertex = path->vertex(this); - auto dcalc_ap_index = path->dcalcAnalysisPt(this)->index(); - auto tr = path->transition(this); - return findSlew(vertex, tr, nullptr, dcalc_ap_index); + Vertex *vertex = path->vertex(this); + DcalcAPIndex dcalc_ap_index = path->dcalcAnalysisPt(this)->index(); + const RiseFall *rf = path->transition(this); + return findSlew(vertex, rf, nullptr, dcalc_ap_index); } float WritePathSpice::findSlew(Path *path, - const TransRiseFall *tr, + const RiseFall *rf, TimingArc *next_arc) { - auto vertex = path->vertex(this); - auto dcalc_ap_index = path->dcalcAnalysisPt(this)->index(); - return findSlew(vertex, tr, next_arc, dcalc_ap_index); + Vertex *vertex = path->vertex(this); + DcalcAPIndex dcalc_ap_index = path->dcalcAnalysisPt(this)->index(); + return findSlew(vertex, rf, next_arc, dcalc_ap_index); } float WritePathSpice::findSlew(Vertex *vertex, - const TransRiseFall *tr, + const RiseFall *rf, TimingArc *next_arc, DcalcAPIndex dcalc_ap_index) { - auto slew = delayAsFloat(graph_->slew(vertex, tr, dcalc_ap_index)); + auto slew = delayAsFloat(graph_->slew(vertex, rf, dcalc_ap_index)); if (slew == 0.0 && next_arc) slew = slewAxisMinValue(next_arc); if (slew == 0.0) @@ -597,12 +597,12 @@ WritePathSpice::slewAxisMinValue(TimingArc *arc) // Write PWL rise/fall edge that crosses threshold at time. void -WritePathSpice::writeWaveformEdge(const TransRiseFall *tr, +WritePathSpice::writeWaveformEdge(const RiseFall *rf, float time, float slew) { float volt0, volt1; - if (tr == TransRiseFall::rise()) { + if (rf == RiseFall::rise()) { volt0 = gnd_voltage_; volt1 = power_voltage_; } @@ -610,9 +610,9 @@ WritePathSpice::writeWaveformEdge(const TransRiseFall *tr, volt0 = power_voltage_; volt1 = gnd_voltage_; } - auto threshold = default_library_->inputThreshold(tr); - auto lower = default_library_->slewLowerThreshold(tr); - auto upper = default_library_->slewUpperThreshold(tr); + auto threshold = default_library_->inputThreshold(rf); + auto lower = default_library_->slewLowerThreshold(rf); + auto upper = default_library_->slewUpperThreshold(rf); auto dt = slew / (upper - lower); auto time0 = time - dt * threshold; auto time1 = time0 + dt; @@ -629,7 +629,7 @@ WritePathSpice::writeMeasureStmts() streamPrint(spice_stream_, "* Measure statements\n"); streamPrint(spice_stream_, "********************\n\n"); - for (auto stage = stageFirst(); stage <= stageLast(); stage++) { + for (Stage stage = stageFirst(); stage <= stageLast(); stage++) { auto gate_input_path = stageGateInputPath(stage); auto drvr_path = stageDrvrPath(stage); auto load_path = stageLoadPath(stage); @@ -653,12 +653,12 @@ WritePathSpice::writeMeasureDelayStmt(Stage stage, Path *to_path) { auto from_pin_name = network_->pathName(from_path->pin(this)); - auto from_tr = from_path->transition(this); - auto from_threshold = power_voltage_ * default_library_->inputThreshold(from_tr); + auto from_rf = from_path->transition(this); + auto from_threshold = power_voltage_ * default_library_->inputThreshold(from_rf); auto to_pin_name = network_->pathName(to_path->pin(this)); - auto to_tr = to_path->transition(this); - auto to_threshold = power_voltage_ * default_library_->inputThreshold(to_tr); + auto to_rf = to_path->transition(this); + auto to_threshold = power_voltage_ * default_library_->inputThreshold(to_rf); streamPrint(spice_stream_, ".measure tran %s_%s_delay_%s\n", stageName(stage).c_str(), @@ -668,12 +668,12 @@ WritePathSpice::writeMeasureDelayStmt(Stage stage, "+trig v(%s) val=%.3f %s=last\n", from_pin_name, from_threshold, - spiceTrans(from_tr)); + spiceTrans(from_rf)); streamPrint(spice_stream_, "+targ v(%s) val=%.3f %s=last\n", to_pin_name, to_threshold, - spiceTrans(to_tr)); + spiceTrans(to_rf)); } void @@ -682,11 +682,11 @@ WritePathSpice::writeMeasureSlewStmt(Stage stage, { auto pin_name = network_->pathName(path->pin(this)); auto tr = path->transition(this); - auto spice_tr = spiceTrans(tr); + auto spice_rf = spiceTrans(tr); auto lower = power_voltage_ * default_library_->slewLowerThreshold(tr); auto upper = power_voltage_ * default_library_->slewUpperThreshold(tr); float threshold1, threshold2; - if (tr == TransRiseFall::rise()) { + if (tr == RiseFall::rise()) { threshold1 = lower; threshold2 = upper; } @@ -702,18 +702,18 @@ WritePathSpice::writeMeasureSlewStmt(Stage stage, "+trig v(%s) val=%.3f %s=last\n", pin_name, threshold1, - spice_tr); + spice_rf); streamPrint(spice_stream_, "+targ v(%s) val=%.3f %s=last\n", pin_name, threshold2, - spice_tr); + spice_rf); } const char * -WritePathSpice::spiceTrans(const TransRiseFall *tr) +WritePathSpice::spiceTrans(const RiseFall *rf) { - if (tr == TransRiseFall::rise()) + if (rf == RiseFall::rise()) return "RISE"; else return "FALL"; @@ -726,7 +726,7 @@ WritePathSpice::writeStageSubckts() streamPrint(spice_stream_, "* Stage subckts\n"); streamPrint(spice_stream_, "***************\n\n"); - for (auto stage = stageFirst(); stage <= stageLast(); stage++) { + for (Stage stage = stageFirst(); stage <= stageLast(); stage++) { if (stage == stageFirst()) writeInputStage(stage); else @@ -807,16 +807,16 @@ WritePathSpice::writeGateStage(Stage stage) void WritePathSpice::writeSubcktInst(const Pin *input_pin) { - auto inst = network_->instance(input_pin); - auto inst_name = network_->pathName(inst); - auto cell = network_->libertyCell(inst); - auto cell_name = cell->name(); - auto spice_port_names = cell_spice_port_names_[cell_name]; + const Instance *inst = network_->instance(input_pin); + const char *inst_name = network_->pathName(inst); + LibertyCell *cell = network_->libertyCell(inst); + const char *cell_name = cell->name(); + StringVector *spice_port_names = cell_spice_port_names_[cell_name]; streamPrint(spice_stream_, "x%s", inst_name); - for (auto subckt_port_name : *spice_port_names) { - auto subckt_port_cname = subckt_port_name.c_str(); - auto pin = network_->findPin(inst, subckt_port_cname); - auto pg_port = cell->findPgPort(subckt_port_cname); + for (string subckt_port_name : *spice_port_names) { + const char *subckt_port_cname = subckt_port_name.c_str(); + Pin *pin = network_->findPin(inst, subckt_port_cname); + LibertyPgPort *pg_port = cell->findPgPort(subckt_port_cname); const char *pin_name; if (pin) { pin_name = network_->pathName(pin); @@ -841,22 +841,22 @@ WritePathSpice::writeSubcktInstVoltSrcs(Stage stage, DcalcAPIndex dcalc_ap_index) { - auto inst = network_->instance(input_pin); - auto cell = network_->libertyCell(inst); - auto cell_name = cell->name(); - auto spice_port_names = cell_spice_port_names_[cell_name]; + const Instance *inst = network_->instance(input_pin); + LibertyCell *cell = network_->libertyCell(inst); + const char *cell_name = cell->name(); + StringVector *spice_port_names = cell_spice_port_names_[cell_name]; - auto drvr_pin = stageDrvrPin(stage); - auto input_port = network_->libertyPort(input_pin); - auto drvr_port = network_->libertyPort(drvr_pin); - auto input_port_name = input_port->name(); - auto drvr_port_name = drvr_port->name(); - auto inst_name = network_->pathName(inst); + const Pin *drvr_pin = stageDrvrPin(stage); + const LibertyPort *input_port = network_->libertyPort(input_pin); + const LibertyPort *drvr_port = network_->libertyPort(drvr_pin); + const char *input_port_name = input_port->name(); + const char *drvr_port_name = drvr_port->name(); + const char *inst_name = network_->pathName(inst); debugPrint1(debug_, "write_spice", 2, "subckt %s\n", cell->name()); - for (auto subckt_port_sname : *spice_port_names) { - auto subckt_port_name = subckt_port_sname.c_str(); - auto pg_port = cell->findPgPort(subckt_port_name); + for (string subckt_port_sname : *spice_port_names) { + const char *subckt_port_name = subckt_port_sname.c_str(); + LibertyPgPort *pg_port = cell->findPgPort(subckt_port_name); debugPrint2(debug_, "write_spice", 2, " port %s%s\n", subckt_port_name, pg_port ? " pwr/gnd" : ""); @@ -872,7 +872,7 @@ WritePathSpice::writeSubcktInstVoltSrcs(Stage stage, else if (!(stringEq(subckt_port_name, input_port_name) || stringEq(subckt_port_name, drvr_port_name))) { // Input voltage to sensitize path from gate input to output. - auto port = cell->findLibertyPort(subckt_port_name); + LibertyPort *port = cell->findLibertyPort(subckt_port_name); if (port && port->direction()->isAnyInput()) { const Pin *pin = network_->findPin(inst, port); @@ -900,11 +900,11 @@ WritePathSpice::writeSubcktInstVoltSrcs(Stage stage, volt_index); break; case LogicValue::rise: - writeClkedStepSource(pin, TransRiseFall::rise(), clk, + writeClkedStepSource(pin, RiseFall::rise(), clk, dcalc_ap_index, volt_index); break; case LogicValue::fall: - writeClkedStepSource(pin, TransRiseFall::fall(), clk, + writeClkedStepSource(pin, RiseFall::fall(), clk, dcalc_ap_index, volt_index); break; } @@ -916,15 +916,15 @@ WritePathSpice::writeSubcktInstVoltSrcs(Stage stage, // PWL voltage source that rises half way into the first clock cycle. void WritePathSpice::writeClkedStepSource(const Pin *pin, - const TransRiseFall *tr, + const RiseFall *rf, const Clock *clk, DcalcAPIndex dcalc_ap_index, int &volt_index) { - auto vertex = graph_->pinLoadVertex(pin); - auto slew = findSlew(vertex, tr, nullptr, dcalc_ap_index); - auto time = clkWaveformTImeOffset(clk) + clk->period() / 2.0; - writeStepVoltSource(pin, tr, slew, time, volt_index); + Vertex *vertex = graph_->pinLoadVertex(pin); + Slew slew = findSlew(vertex, rf, nullptr, dcalc_ap_index); + Delay time = clkWaveformTImeOffset(clk) + clk->period() / 2.0; + writeStepVoltSource(pin, rf, slew, time, volt_index); } void @@ -949,7 +949,7 @@ WritePathSpice::writeVoltageSource(LibertyCell *cell, int &volt_index) { if (pg_port_name) { - auto pg_port = cell->findPgPort(pg_port_name); + LibertyPgPort *pg_port = cell->findPgPort(pg_port_name); if (pg_port) voltage = pgPortVoltage(pg_port); else @@ -971,14 +971,14 @@ WritePathSpice::gatePortValues(Stage stage, clk = nullptr; dcalc_ap_index = 0; - auto gate_edge = stageGateEdge(stage); - auto drvr_port = stageDrvrPort(stage); + Edge *gate_edge = stageGateEdge(stage); + LibertyPort *drvr_port = stageDrvrPort(stage); if (gate_edge->role()->genericRole() == TimingRole::regClkToQ()) regPortValues(stage, port_values, clk, dcalc_ap_index); else if (drvr_port->function()) { - auto input_pin = stageGateInputPin(stage); - auto input_port = network_->libertyPort(input_pin); - auto inst = network_->instance(input_pin); + Pin *input_pin = stageGateInputPin(stage); + LibertyPort *input_port = network_->libertyPort(input_pin); + Instance *inst = network_->instance(input_pin); gatePortValues(inst, drvr_port->function(), input_port, port_values); } } @@ -990,19 +990,19 @@ WritePathSpice::regPortValues(Stage stage, const Clock *&clk, DcalcAPIndex &dcalc_ap_index) { - auto drvr_port = stageDrvrPort(stage); - auto drvr_expr = drvr_port->function(); + LibertyPort *drvr_port = stageDrvrPort(stage); + FuncExpr *drvr_expr = drvr_port->function(); if (drvr_expr) { - auto q_port = drvr_expr->port(); + LibertyPort *q_port = drvr_expr->port(); if (q_port) { // Drvr (register/latch output) function should be a reference // to an internal port like IQ or IQN. - auto cell = stageLibertyCell(stage); - auto seq = cell->outputPortSequential(q_port); + LibertyCell *cell = stageLibertyCell(stage); + Sequential *seq = cell->outputPortSequential(q_port); if (seq) { - auto drvr_path = stageDrvrPath(stage); - auto drvr_tr = drvr_path->transition(this); - seqPortValues(seq, drvr_tr, port_values); + PathRef *drvr_path = stageDrvrPath(stage); + const RiseFall *drvr_rf = drvr_path->transition(this); + seqPortValues(seq, drvr_rf, port_values); clk = drvr_path->clock(this); dcalc_ap_index = drvr_path->dcalcAnalysisPt(this)->index(); } @@ -1022,8 +1022,8 @@ WritePathSpice::gatePortValues(const Instance *inst, // Return values. LibertyPortLogicValues &port_values) { - auto left = expr->left(); - auto right = expr->right(); + FuncExpr *left = expr->left(); + FuncExpr *right = expr->right(); switch (expr->op()) { case FuncExpr::op_port: break; @@ -1095,23 +1095,23 @@ WritePathSpice::gatePortValues(const Instance *inst, void WritePathSpice::seqPortValues(Sequential *seq, - const TransRiseFall *tr, + const RiseFall *rf, // Return values. LibertyPortLogicValues &port_values) { - auto data = seq->data(); - auto port = onePort(data); + FuncExpr *data = seq->data(); + LibertyPort *port = onePort(data); if (port) { - auto sense = data->portTimingSense(port); + TimingSense sense = data->portTimingSense(port); switch (sense) { case TimingSense::positive_unate: - if (tr == TransRiseFall::rise()) + if (rf == RiseFall::rise()) port_values[port] = LogicValue::rise; else port_values[port] = LogicValue::fall; break; case TimingSense::negative_unate: - if (tr == TransRiseFall::rise()) + if (rf == RiseFall::rise()) port_values[port] = LogicValue::fall; else port_values[port] = LogicValue::rise; @@ -1129,8 +1129,8 @@ WritePathSpice::seqPortValues(Sequential *seq, LibertyPort * WritePathSpice::onePort(FuncExpr *expr) { - auto left = expr->left(); - auto right = expr->right(); + FuncExpr *left = expr->left(); + FuncExpr *right = expr->right(); LibertyPort *port; switch (expr->op()) { case FuncExpr::op_port: @@ -1162,15 +1162,15 @@ public: bool operator()(const ParasiticDevice *device1, const ParasiticDevice *device2) const { - auto node1 = parasitics_->node1(device1); - auto node2 = parasitics_->node1(device2); - auto name1 = parasitics_->name(node1); - auto name2 = parasitics_->name(node2); + ParasiticNode *node1 = parasitics_->node1(device1); + ParasiticNode *node2 = parasitics_->node1(device2); + const char *name1 = parasitics_->name(node1); + const char *name2 = parasitics_->name(node2); if (stringEq(name1, name2)) { - auto node12 = parasitics_->node2(device1); - auto node22 = parasitics_->node2(device2); - auto name12 = parasitics_->name(node12); - auto name22 = parasitics_->name(node22); + ParasiticNode *node12 = parasitics_->node2(device1); + ParasiticNode *node22 = parasitics_->node2(device2); + const char *name12 = parasitics_->name(node12); + const char *name22 = parasitics_->name(node22); return stringLess(name12, name22); } else @@ -1191,8 +1191,8 @@ public: bool operator()(const ParasiticNode *node1, const ParasiticNode *node2) const { - auto name1 = parasitics_->name(node1); - auto name2 = parasitics_->name(node2); + const char *name1 = parasitics_->name(node1); + const char *name2 = parasitics_->name(node2); return stringLess(name1, name2); } private: @@ -1202,17 +1202,17 @@ private: void WritePathSpice::writeStageParasitics(Stage stage) { - auto drvr_path = stageDrvrPath(stage); - auto drvr_pin = stageDrvrPin(stage); - auto dcalc_ap = drvr_path->dcalcAnalysisPt(this); - auto parasitic_ap = dcalc_ap->parasiticAnalysisPt(); - auto parasitic = parasitics_->findParasiticNetwork(drvr_pin, parasitic_ap); + PathRef *drvr_path = stageDrvrPath(stage); + Pin *drvr_pin = stageDrvrPin(stage); + DcalcAnalysisPt *dcalc_ap = drvr_path->dcalcAnalysisPt(this); + ParasiticAnalysisPt *parasitic_ap = dcalc_ap->parasiticAnalysisPt(); + Parasitic *parasitic = parasitics_->findParasiticNetwork(drvr_pin, parasitic_ap); Set reachable_pins; int res_index = 1; int cap_index = 1; if (parasitic) { - auto net = network_->net(drvr_pin); - auto net_name = net ? network_->pathName(net) : network_->pathName(drvr_pin); + Net *net = network_->net(drvr_pin); + const char *net_name = net ? network_->pathName(net) : network_->pathName(drvr_pin); initNodeMap(net_name); streamPrint(spice_stream_, "* Net %s\n", net_name); @@ -1220,7 +1220,7 @@ WritePathSpice::writeStageParasitics(Stage stage) Vector devices; ParasiticDeviceIterator *device_iter1 = parasitics_->deviceIterator(parasitic); while (device_iter1->hasNext()) { - auto device = device_iter1->next(); + ParasiticDevice *device = device_iter1->next(); devices.push_back(device); } delete device_iter1; @@ -1228,10 +1228,10 @@ WritePathSpice::writeStageParasitics(Stage stage) sort(devices, ParasiticDeviceLess(parasitics_)); for (auto device : devices) { - auto resistance = parasitics_->value(device, parasitic_ap); + float resistance = parasitics_->value(device, parasitic_ap); if (parasitics_->isResistor(device)) { - auto node1 = parasitics_->node1(device); - auto node2 = parasitics_->node2(device); + ParasiticNode *node1 = parasitics_->node1(device); + ParasiticNode *node2 = parasitics_->node2(device); streamPrint(spice_stream_, "R%d %s %s %.3e\n", res_index, nodeName(node1), @@ -1239,15 +1239,15 @@ WritePathSpice::writeStageParasitics(Stage stage) resistance); res_index++; - auto pin1 = parasitics_->connectionPin(node1); + const Pin *pin1 = parasitics_->connectionPin(node1); reachable_pins.insert(pin1); - auto pin2 = parasitics_->connectionPin(node2); + const Pin *pin2 = parasitics_->connectionPin(node2); reachable_pins.insert(pin2); } else if (parasitics_->isCouplingCap(device)) { // Ground coupling caps for now. ParasiticNode *node1 = parasitics_->node1(device); - auto cap = parasitics_->value(device, parasitic_ap); + float cap = parasitics_->value(device, parasitic_ap); streamPrint(spice_stream_, "C%d %s 0 %.3e\n", cap_index, nodeName(node1), @@ -1262,7 +1262,7 @@ WritePathSpice::writeStageParasitics(Stage stage) // Add resistors from drvr to load for missing parasitic connections. auto pin_iter = network_->connectedPinIterator(drvr_pin); while (pin_iter->hasNext()) { - auto pin = pin_iter->next(); + Pin *pin = pin_iter->next(); if (pin != drvr_pin && network_->isLoad(pin) && !network_->isHierarchical(pin) @@ -1282,14 +1282,14 @@ WritePathSpice::writeStageParasitics(Stage stage) Vector nodes; ParasiticNodeIterator *node_iter = parasitics_->nodeIterator(parasitic); while (node_iter->hasNext()) { - auto node = node_iter->next(); + ParasiticNode *node = node_iter->next(); nodes.push_back(node); } sort(nodes, ParasiticNodeLess(parasitics_)); - for (auto node : nodes) { - auto cap = parasitics_->nodeGndCap(node, parasitic_ap); + for (ParasiticNode *node : nodes) { + float cap = parasitics_->nodeGndCap(node, parasitic_ap); // Spice has a cow over zero value caps. if (cap > 0.0) { streamPrint(spice_stream_, "C%d %s 0 %.3e\n", @@ -1315,7 +1315,7 @@ WritePathSpice::initNodeMap(const char *net_name) const char * WritePathSpice::nodeName(ParasiticNode *node) { - auto pin = parasitics_->connectionPin(node); + const Pin *pin = parasitics_->connectionPin(node); if (pin) return parasitics_->name(node); else { @@ -1351,7 +1351,7 @@ WritePathSpice::writeSubckts() split(line, " \t", tokens); if (tokens.size() >= 2 && stringEqual(tokens[0].c_str(), ".subckt")) { - auto cell_name = tokens[1].c_str(); + const char *cell_name = tokens[1].c_str(); if (path_cell_names.hasKey(cell_name)) { subckts_stream << line << "\n"; bool found_ends = false; @@ -1376,7 +1376,7 @@ WritePathSpice::writeSubckts() if (!path_cell_names.empty()) { report_->error("The following subkcts are missing from %s\n", lib_subckt_filename_); - for (auto cell_name : path_cell_names) + for (const char *cell_name : path_cell_names) report_->printError(" %s\n", cell_name); } } @@ -1393,22 +1393,22 @@ void WritePathSpice::findPathCellnames(// Return values. StringSet &path_cell_names) { - for (auto stage = stageFirst(); stage <= stageLast(); stage++) { - auto arc = stageGateArc(stage); + for (Stage stage = stageFirst(); stage <= stageLast(); stage++) { + TimingArc *arc = stageGateArc(stage); if (arc) { - auto cell = arc->set()->libertyCell(); + LibertyCell *cell = arc->set()->libertyCell(); if (cell) { debugPrint1(debug_, "write_spice", 2, "cell %s\n", cell->name()); path_cell_names.insert(cell->name()); } // Include side receivers. - auto drvr_pin = stageDrvrPin(stage); + Pin *drvr_pin = stageDrvrPin(stage); auto pin_iter = network_->connectedPinIterator(drvr_pin); while (pin_iter->hasNext()) { - auto pin = pin_iter->next(); - auto port = network_->libertyPort(pin); + Pin *pin = pin_iter->next(); + LibertyPort *port = network_->libertyPort(pin); if (port) { - auto cell = port->libertyCell(); + LibertyCell *cell = port->libertyCell(); path_cell_names.insert(cell->name()); } } @@ -1421,13 +1421,13 @@ void WritePathSpice::recordSpicePortNames(const char *cell_name, StringVector &tokens) { - auto cell = network_->findLibertyCell(cell_name); + LibertyCell *cell = network_->findLibertyCell(cell_name); if (cell) { - auto spice_port_names = new StringVector; + StringVector *spice_port_names = new StringVector; for (size_t i = 2; i < tokens.size(); i++) { - auto port_name = tokens[i].c_str(); - auto port = cell->findLibertyPort(port_name); - auto pg_port = cell->findPgPort(port_name); + const char *port_name = tokens[i].c_str(); + LibertyPort *port = cell->findLibertyPort(port_name); + LibertyPgPort *pg_port = cell->findPgPort(port_name); if (port == nullptr && pg_port == nullptr && !stringEqual(port_name, power_name_) @@ -1483,28 +1483,28 @@ WritePathSpice::stageLoadPathIndex(Stage stage) PathRef * WritePathSpice::stageGateInputPath(Stage stage) { - auto path_index = stageGateInputPathIndex(stage); + int path_index = stageGateInputPathIndex(stage); return path_expanded_.path(path_index); } PathRef * WritePathSpice::stageDrvrPath(Stage stage) { - auto path_index = stageDrvrPathIndex(stage); + int path_index = stageDrvrPathIndex(stage); return path_expanded_.path(path_index); } PathRef * WritePathSpice::stageLoadPath(Stage stage) { - auto path_index = stageLoadPathIndex(stage); + int path_index = stageLoadPathIndex(stage); return path_expanded_.path(path_index); } TimingArc * WritePathSpice::stageGateArc(Stage stage) { - auto path_index = stageDrvrPathIndex(stage); + int path_index = stageDrvrPathIndex(stage); if (path_index >= 0) return path_expanded_.prevArc(path_index); else @@ -1514,93 +1514,93 @@ WritePathSpice::stageGateArc(Stage stage) TimingArc * WritePathSpice::stageWireArc(Stage stage) { - auto path_index = stageLoadPathIndex(stage); + int path_index = stageLoadPathIndex(stage); return path_expanded_.prevArc(path_index); } Edge * WritePathSpice::stageGateEdge(Stage stage) { - auto path = stageDrvrPath(stage); - auto arc = stageGateArc(stage); + PathRef *path = stageDrvrPath(stage); + TimingArc *arc = stageGateArc(stage); return path->prevEdge(arc, this); } Edge * WritePathSpice::stageWireEdge(Stage stage) { - auto path = stageLoadPath(stage); - auto arc = stageWireArc(stage); + PathRef *path = stageLoadPath(stage); + TimingArc *arc = stageWireArc(stage); return path->prevEdge(arc, this); } Pin * WritePathSpice::stageGateInputPin(Stage stage) { - auto path = stageGateInputPath(stage); + PathRef *path = stageGateInputPath(stage); return path->pin(this); } LibertyPort * WritePathSpice::stageGateInputPort(Stage stage) { - auto pin = stageGateInputPin(stage); + Pin *pin = stageGateInputPin(stage); return network_->libertyPort(pin); } Pin * WritePathSpice::stageDrvrPin(Stage stage) { - auto path = stageDrvrPath(stage); + PathRef *path = stageDrvrPath(stage); return path->pin(this); } LibertyPort * WritePathSpice::stageDrvrPort(Stage stage) { - auto pin = stageDrvrPin(stage); + Pin *pin = stageDrvrPin(stage); return network_->libertyPort(pin); } Pin * WritePathSpice::stageLoadPin(Stage stage) { - auto path = stageLoadPath(stage); + PathRef *path = stageLoadPath(stage); return path->pin(this); } const char * WritePathSpice::stageGateInputPinName(Stage stage) { - auto pin = stageGateInputPin(stage); + Pin *pin = stageGateInputPin(stage); return network_->pathName(pin); } const char * WritePathSpice::stageDrvrPinName(Stage stage) { - auto pin = stageDrvrPin(stage); + Pin *pin = stageDrvrPin(stage); return network_->pathName(pin); } const char * WritePathSpice::stageLoadPinName(Stage stage) { - auto pin = stageLoadPin(stage); + Pin *pin = stageLoadPin(stage); return network_->pathName(pin); } Instance * WritePathSpice::stageInstance(Stage stage) { - auto pin = stageDrvrPin(stage); + Pin *pin = stageDrvrPin(stage); return network_->instance(pin); } LibertyCell * WritePathSpice::stageLibertyCell(Stage stage) { - auto pin = stageDrvrPin(stage); + Pin *pin = stageDrvrPin(stage); return network_->libertyPort(pin)->libertyCell(); } diff --git a/tcl/Cmds.tcl b/tcl/Cmds.tcl index b80eb49c..c52eef7b 100644 --- a/tcl/Cmds.tcl +++ b/tcl/Cmds.tcl @@ -296,7 +296,7 @@ proc set_assigned_delay_cmd { cmd cmd_args } { check_argc_eq1 $cmd $cmd_args set corner [parse_corner keys] set min_max [parse_min_max_all_check_flags flags] - set to_tr [parse_rise_fall_flags flags] + set to_rf [parse_rise_fall_flags flags] if [info exists keys(-from)] { set from_pins [get_port_pins_error "from_pins" $keys(-from)] @@ -337,28 +337,28 @@ proc set_assigned_delay_cmd { cmd cmd_args } { foreach from_pin $from_pins { set from_vertices [$from_pin vertices] set_assigned_delay1 [lindex $from_vertices 0] \ - $to_pins $to_tr $corner $min_max $delay + $to_pins $to_rf $corner $min_max $delay if { [llength $from_vertices] == 2 } { set_assigned_delay1 [lindex $from_vertices 1] \ - $to_pins $to_tr $corner $min_max $delay + $to_pins $to_rf $corner $min_max $delay } } } -proc set_assigned_delay1 { from_vertex to_pins to_tr corner min_max delay } { +proc set_assigned_delay1 { from_vertex to_pins to_rf corner min_max delay } { foreach to_pin $to_pins { set to_vertices [$to_pin vertices] set_assigned_delay2 $from_vertex [lindex $to_vertices 0] \ - $to_tr $corner $min_max $delay + $to_rf $corner $min_max $delay if { [llength $to_vertices] == 2 } { # Bidirect driver. set_assigned_delay2 $from_vertex [lindex $to_vertices 1] \ - $to_tr $corner $min_max $delay + $to_rf $corner $min_max $delay } } } -proc set_assigned_delay2 {from_vertex to_vertex to_tr corner min_max delay} { +proc set_assigned_delay2 {from_vertex to_vertex to_rf corner min_max delay} { set edge_iter [$from_vertex out_edge_iterator] while {[$edge_iter has_next]} { set edge [$edge_iter next] @@ -367,8 +367,8 @@ proc set_assigned_delay2 {from_vertex to_vertex to_tr corner min_max delay} { set arc_iter [$edge timing_arc_iterator] while {[$arc_iter has_next]} { set arc [$arc_iter next] - if { $to_tr == "rise_fall" \ - || $to_tr eq [$arc to_trans_name] } { + if { $to_rf == "rise_fall" \ + || $to_rf eq [$arc to_trans_name] } { set_arc_delay $edge $arc $corner $min_max $delay } } @@ -392,12 +392,12 @@ proc set_assigned_check_cmd { cmd cmd_args } { } else { sta_error "$cmd missing -from argument." } - set from_tr "rise_fall" + set from_rf "rise_fall" if { [info exists keys(-clock)] } { set clk_arg $keys(-clock) if { $clk_arg eq "rise" \ || $clk_arg eq "fall" } { - set from_tr $clk_arg + set from_rf $clk_arg } else { sta_error "$cmd -clock must be rise or fall." } @@ -408,7 +408,7 @@ proc set_assigned_check_cmd { cmd cmd_args } { } else { sta_error "$cmd missing -to argument." } - set to_tr [parse_rise_fall_flags flags] + set to_rf [parse_rise_fall_flags flags] set corner [parse_corner keys] set min_max [parse_min_max_all_check_flags flags] @@ -435,31 +435,31 @@ proc set_assigned_check_cmd { cmd cmd_args } { foreach from_pin $from_pins { set from_vertices [$from_pin vertices] - set_assigned_check1 [lindex $from_vertices 0] $from_tr \ - $to_pins $to_tr $role $corner $min_max $cond $check_value + set_assigned_check1 [lindex $from_vertices 0] $from_rf \ + $to_pins $to_rf $role $corner $min_max $cond $check_value if { [llength $from_vertices] == 2 } { - set_assigned_check1 [lindex $from_vertices 1] $from_tr \ - $to_pins $to_tr $role $corner $min_max $cond $check_value + set_assigned_check1 [lindex $from_vertices 1] $from_rf \ + $to_pins $to_rf $role $corner $min_max $cond $check_value } } } -proc set_assigned_check1 { from_vertex from_tr to_pins to_tr \ +proc set_assigned_check1 { from_vertex from_rf to_pins to_rf \ role corner min_max cond check_value } { foreach to_pin $to_pins { set to_vertices [$to_pin vertices] - set_assigned_check2 $from_vertex $from_tr [lindex $to_vertices 0] \ - $to_tr $role $corner $min_max $cond $check_value + set_assigned_check2 $from_vertex $from_rf [lindex $to_vertices 0] \ + $to_rf $role $corner $min_max $cond $check_value if { [llength $to_vertices] == 2 } { # Bidirect driver. - set_assigned_check2 $from_vertex $from_tr \ - [lindex $to_vertices 1] $to_tr $role $corner $min_max \ + set_assigned_check2 $from_vertex $from_rf \ + [lindex $to_vertices 1] $to_rf $role $corner $min_max \ $cond $check_value } } } -proc set_assigned_check2 { from_vertex from_tr to_vertex to_tr \ +proc set_assigned_check2 { from_vertex from_rf to_vertex to_rf \ role corner min_max cond check_value } { set edge_iter [$from_vertex out_edge_iterator] while {[$edge_iter has_next]} { @@ -468,10 +468,10 @@ proc set_assigned_check2 { from_vertex from_tr to_vertex to_tr \ set arc_iter [$edge timing_arc_iterator] while {[$arc_iter has_next]} { set arc [$arc_iter next] - if { ($from_tr eq "rise_fall" \ - || $from_tr eq [$arc from_trans_name]) \ - && ($to_tr eq "rise_fall" \ - || $to_tr eq [$arc to_trans_name]) \ + if { ($from_rf eq "rise_fall" \ + || $from_rf eq [$arc from_trans_name]) \ + && ($to_rf eq "rise_fall" \ + || $to_rf eq [$arc to_trans_name]) \ && [$arc role] eq $role \ && ($cond eq "" || [$arc sdf_cond] eq $cond) } { set_arc_delay $edge $arc $corner $min_max $check_value @@ -602,26 +602,26 @@ proc unset_clk_uncertainty_cmd { cmd cmd_args } { if { [info exists keys(-from)] } { set from_key "-from" - set from_tr "rise_fall" + set from_rf "rise_fall" } elseif { [info exists keys(-rise_from)] } { set from_key "-rise_from" - set from_tr "rise" + set from_rf "rise" } elseif { [info exists keys(-fall_from)] } { set from_key "-fall_from" - set from_tr "fall" + set from_rf "fall" } else { set from_key "none" } if { [info exists keys(-to)] } { set to_key "-to" - set to_tr "rise_fall" + set to_rf "rise_fall" } elseif { [info exists keys(-rise_to)] } { set to_key "-rise_to" - set to_tr "rise" + set to_rf "rise" } elseif { [info exists keys(-fall_to)] } { set to_key "-fall_to" - set to_tr "fall" + set to_rf "fall" } else { set to_key "none" } @@ -639,8 +639,8 @@ proc unset_clk_uncertainty_cmd { cmd cmd_args } { foreach from_clk $from_clks { foreach to_clk $to_clks { - unset_inter_clock_uncertainty $from_clk $from_tr \ - $to_clk $to_tr $min_max + unset_inter_clock_uncertainty $from_clk $from_rf \ + $to_clk $to_rf $min_max } } } else { @@ -670,18 +670,18 @@ proc unset_data_checks_cmd { cmd cmd_args } { flags {-setup -hold} check_argc_eq0 $cmd $cmd_args - set from_tr "rise_fall" - set to_tr "rise_fall" + set from_rf "rise_fall" + set to_rf "rise_fall" set clk "NULL" set setup_hold "max" if [info exists keys(-from)] { set from [get_port_pin_error "from_pin" $keys(-from)] } elseif [info exists keys(-rise_from)] { set from [get_port_pin_error "from_pin" $keys(-rise_from)] - set from_tr "rise" + set from_rf "rise" } elseif [info exists keys(-fall_from)] { set from [get_port_pin_error "from_pin" $keys(-fall_from)] - set from_tr "fall" + set from_rf "fall" } else { sta_error "missing -from, -rise_from or -fall_from argument." } @@ -690,10 +690,10 @@ proc unset_data_checks_cmd { cmd cmd_args } { set to [get_port_pin_error "to_pin" $keys(-to)] } elseif [info exists keys(-rise_to)] { set to [get_port_pin_error "to_pin" $keys(-rise_to)] - set to_tr "rise" + set to_rf "rise" } elseif [info exists keys(-fall_to)] { set to [get_port_pin_error "to_pin" $keys(-fall_to)] - set to_tr "fall" + set to_rf "fall" } else { sta_error "missing -to, -rise_to or -fall_to argument." } @@ -710,7 +710,7 @@ proc unset_data_checks_cmd { cmd cmd_args } { set setup_hold "setup_hold" } - unset_data_check_cmd $from $from_tr $to $to_tr $clk $setup_hold + unset_data_check_cmd $from $from_rf $to $to_rf $clk $setup_hold } ################################################################ @@ -892,16 +892,16 @@ proc unset_port_delay { cmd swig_cmd cmd_args } { } if [info exists flags(-clock_fall)] { - set clk_tr "fall" + set clk_rf "fall" } else { - set clk_tr "rise" + set clk_rf "rise" } set tr [parse_rise_fall_flags flags] set min_max [parse_min_max_all_flags flags] foreach pin $pins { - $swig_cmd $pin $tr $clk $clk_tr $min_max + $swig_cmd $pin $tr $clk $clk_rf $min_max } } diff --git a/tcl/Sdc.tcl b/tcl/Sdc.tcl index 56ccea29..86428d34 100644 --- a/tcl/Sdc.tcl +++ b/tcl/Sdc.tcl @@ -383,17 +383,17 @@ proc all_registers { args } { check_argc_eq0 "all_registers" $args set clks {} - set clk_tr "rise_fall" + set clk_rf "rise_fall" if [info exists keys(-clock)] { set clks [get_clocks_warn "clocks" $keys(-clock)] } if [info exists keys(-rise_clock)] { set clks [get_clocks_warn "clocks" $keys(-rise_clock)] - set clk_tr "rise" + set clk_rf "rise" } if [info exists keys(-fall_clock)] { set clks [get_clocks_warn "clocks" $keys(-fall_clock)] - set clk_tr "fall" + set clk_rf "fall" } if {[info exists flags(-edge_triggered)] \ @@ -409,23 +409,23 @@ proc all_registers { args } { set level_sensitive 1 } if [info exists flags(-cells)] { - return [find_register_instances $clks $clk_tr \ + return [find_register_instances $clks $clk_rf \ $edge_triggered $level_sensitive] } elseif [info exists flags(-data_pins)] { - return [find_register_data_pins $clks $clk_tr \ + return [find_register_data_pins $clks $clk_rf \ $edge_triggered $level_sensitive] } elseif [info exists flags(-clock_pins)] { - return [find_register_clk_pins $clks $clk_tr \ + return [find_register_clk_pins $clks $clk_rf \ $edge_triggered $level_sensitive] } elseif [info exists flags(-async_pins)] { - return [find_register_async_pins $clks $clk_tr \ + return [find_register_async_pins $clks $clk_rf \ $edge_triggered $level_sensitive] } elseif [info exists flags(-output_pins)] { - return [find_register_output_pins $clks $clk_tr \ + return [find_register_output_pins $clks $clk_rf \ $edge_triggered $level_sensitive] } else { # -cells is the default. - return [find_register_instances $clks $clk_tr \ + return [find_register_instances $clks $clk_rf \ $edge_triggered $level_sensitive] } } @@ -1613,26 +1613,26 @@ proc set_clock_uncertainty { args } { if { [info exists keys(-from)] } { set from_key "-from" - set from_tr "rise_fall" + set from_rf "rise_fall" } elseif { [info exists keys(-rise_from)] } { set from_key "-rise_from" - set from_tr "rise" + set from_rf "rise" } elseif { [info exists keys(-fall_from)] } { set from_key "-fall_from" - set from_tr "fall" + set from_rf "fall" } else { set from_key "none" } if { [info exists keys(-to)] } { set to_key "-to" - set to_tr "rise_fall" + set to_rf "rise_fall" } elseif { [info exists keys(-rise_to)] } { set to_key "-rise_to" - set to_tr "rise" + set to_rf "rise" } elseif { [info exists keys(-fall_to)] } { set to_key "-fall_to" - set to_tr "fall" + set to_rf "fall" } else { set to_key "none" } @@ -1650,8 +1650,8 @@ proc set_clock_uncertainty { args } { foreach from_clk $from_clks { foreach to_clk $to_clks { - set_inter_clock_uncertainty $from_clk $from_tr \ - $to_clk $to_tr $min_max $uncertainty + set_inter_clock_uncertainty $from_clk $from_rf \ + $to_clk $to_rf $min_max $uncertainty } } } else { @@ -1687,18 +1687,18 @@ proc set_data_check { args } { check_argc_eq1 "set_data_check" $args set margin [time_ui_sta $args] - set from_tr "rise_fall" - set to_tr "rise_fall" + set from_rf "rise_fall" + set to_rf "rise_fall" set clk "NULL" if [info exists keys(-from)] { set from [get_port_pin_error "from_pin" $keys(-from)] } elseif [info exists keys(-rise_from)] { set from [get_port_pin_error "from_pin" $keys(-rise_from)] - set from_tr "rise" + set from_rf "rise" } elseif [info exists keys(-fall_from)] { set from [get_port_pin_error "from_pin" $keys(-fall_from)] - set from_tr "fall" + set from_rf "fall" } else { sta_error "missing -from, -rise_from or -fall_from argument." } @@ -1707,10 +1707,10 @@ proc set_data_check { args } { set to [get_port_pin_error "to_pin" $keys(-to)] } elseif [info exists keys(-rise_to)] { set to [get_port_pin_error "to_pin" $keys(-rise_to)] - set to_tr "rise" + set to_rf "rise" } elseif [info exists keys(-fall_to)] { set to [get_port_pin_error "to_pin" $keys(-fall_to)] - set to_tr "fall" + set to_rf "fall" } else { sta_error "missing -to, -rise_to or -fall_to argument." } @@ -1727,7 +1727,7 @@ proc set_data_check { args } { set setup_hold "setup_hold" } - set_data_check_cmd $from $from_tr $to $to_tr $clk $setup_hold $margin + set_data_check_cmd $from $from_rf $to $to_rf $clk $setup_hold $margin } ################################################################ @@ -1991,9 +1991,9 @@ proc set_port_delay { cmd sta_cmd cmd_args port_dirs } { } if [info exists flags(-clock_fall)] { - set clk_tr "fall" + set clk_rf "fall" } else { - set clk_tr "rise" + set clk_rf "rise" } set tr [parse_rise_fall_flags flags] @@ -2009,7 +2009,7 @@ proc set_port_delay { cmd sta_cmd cmd_args port_dirs } { } elseif { $clk != "NULL" && [lsearch [$clk sources] $pin] != -1 } { sta_warn "$cmd relative to a clock defined on the same port/pin not allowed." } else { - $sta_cmd $pin $tr $clk $clk_tr $ref_pin\ + $sta_cmd $pin $tr $clk $clk_rf $ref_pin\ $source_latency_included $network_latency_included \ $min_max $add $delay } @@ -2834,27 +2834,27 @@ proc parse_to_arg { keys_var flags_var arg_error_var } { upvar 1 $flags_var flags upvar 1 $arg_error_var arg_error - set end_tr [parse_rise_fall_flags flags] - return [parse_to_arg1 keys $end_tr arg_error] + set end_rf [parse_rise_fall_flags flags] + return [parse_to_arg1 keys $end_rf arg_error] } -proc parse_to_arg1 { keys_var end_tr arg_error_var } { +proc parse_to_arg1 { keys_var end_rf arg_error_var } { upvar 1 $keys_var keys upvar 1 $arg_error_var arg_error if [info exists keys(-to)] { set key "-to" - set to_tr "rise_fall" + set to_rf "rise_fall" } elseif [info exists keys(-rise_to)] { set key "-rise_to" - set to_tr "rise" + set to_rf "rise" } elseif [info exists keys(-fall_to)] { set key "-fall_to" - set to_tr "fall" + set to_rf "fall" } else { # -rise/-fall without -to/-rise_to/-fall_to (no objects). - if { $end_tr != "rise_fall" } { - return [make_exception_to {} {} {} "rise_fall" $end_tr] + if { $end_rf != "rise_fall" } { + return [make_exception_to {} {} {} "rise_fall" $end_rf] } else { return "NULL" } @@ -2866,7 +2866,7 @@ proc parse_to_arg1 { keys_var end_tr arg_error_var } { puts "Error: no valid objects specified for $key." return "NULL" } - return [make_exception_to $to_pins $to_clks $to_insts $to_tr $end_tr] + return [make_exception_to $to_pins $to_clks $to_insts $to_rf $end_rf] } proc delete_from_thrus_to { from thrus to } { diff --git a/tcl/Search.tcl b/tcl/Search.tcl index 0b6b1f19..e75b4911 100644 --- a/tcl/Search.tcl +++ b/tcl/Search.tcl @@ -45,17 +45,17 @@ proc report_delays_wrt_clks { pin_arg what } { } } -proc report_delays_wrt_clk { vertex what clk clk_tr } { +proc report_delays_wrt_clk { vertex what clk clk_rf } { global sta_report_default_digits - set rise [$vertex $what rise $clk $clk_tr $sta_report_default_digits] - set fall [$vertex $what fall $clk $clk_tr $sta_report_default_digits] + set rise [$vertex $what rise $clk $clk_rf $sta_report_default_digits] + set fall [$vertex $what fall $clk $clk_rf $sta_report_default_digits] # Filter INF/-INF arrivals. if { !([delays_are_inf $rise] && [delays_are_inf $fall]) } { set rise_fmt [format_delays $rise] set fall_fmt [format_delays $fall] if {$clk != "NULL"} { - set clk_str " ([get_name $clk] [rise_fall_short_name $clk_tr])" + set clk_str " ([get_name $clk] [rise_fall_short_name $clk_rf])" } else { set clk_str "" } @@ -80,17 +80,17 @@ proc report_wrt_clks { pin_arg what } { } } -proc report_wrt_clk { vertex what clk clk_tr } { +proc report_wrt_clk { vertex what clk clk_rf } { global sta_report_default_digits - set rise [$vertex $what rise $clk $clk_tr] - set fall [$vertex $what fall $clk $clk_tr] + set rise [$vertex $what rise $clk $clk_rf] + set fall [$vertex $what fall $clk $clk_rf] # Filter INF/-INF arrivals. if { !([times_are_inf $rise] && [times_are_inf $fall]) } { set rise_fmt [format_times $rise $sta_report_default_digits] set fall_fmt [format_times $fall $sta_report_default_digits] if {$clk != "NULL"} { - set clk_str " ([get_name $clk] [rise_fall_short_name $clk_tr])" + set clk_str " ([get_name $clk] [rise_fall_short_name $clk_rf])" } else { set clk_str "" } @@ -186,7 +186,7 @@ proc_redirect report_path { } $path_iter finish } else { - set worst_path [vertex_worst_arrival_path_tr $vertex $tr $min_max] + set worst_path [vertex_worst_arrival_path_rf $vertex $tr $min_max] if { $worst_path != "NULL" } { if { $report_tags } { puts "Tag: [$worst_path tag]" diff --git a/tcl/Sta.tcl b/tcl/Sta.tcl index 6dae23ad..34de9005 100644 --- a/tcl/Sta.tcl +++ b/tcl/Sta.tcl @@ -174,21 +174,21 @@ proc find_timing_paths_cmd { cmd args_var } { flags {-unconstrained -sort_by_slack -unique_paths_to_endpoint} 0 set min_max "max" - set end_tr "rise_fall" + set end_rf "rise_fall" if [info exists keys(-path_delay)] { set mm_key $keys(-path_delay) if { $mm_key == "max_rise" } { set min_max "max" - set end_tr "rise" + set end_rf "rise" } elseif { $mm_key == "max_fall" } { set min_max "max" - set end_tr "fall" + set end_rf "fall" } elseif { $mm_key == "min_rise" } { set min_max "min" - set end_tr "rise" + set end_rf "rise" } elseif { $mm_key == "min_fall" } { set min_max "min" - set end_tr "fall" + set end_rf "fall" } elseif { $mm_key == "min" || $mm_key == "max" || $mm_key == "min_max" } { set min_max $mm_key } else { @@ -199,7 +199,7 @@ proc find_timing_paths_cmd { cmd args_var } { set arg_error 0 set from [parse_from_arg keys arg_error] set thrus [parse_thrus_arg args arg_error] - set to [parse_to_arg1 keys $end_tr arg_error] + set to [parse_to_arg1 keys $end_rf arg_error] if { $arg_error } { delete_from_thrus_to $from $thrus $to sta_error "$cmd command failed." diff --git a/tcl/StaTcl.i b/tcl/StaTcl.i index 3d9afa8a..3a0c5089 100644 --- a/tcl/StaTcl.i +++ b/tcl/StaTcl.i @@ -605,10 +605,10 @@ using namespace sta; Tcl_SetResult(interp, const_cast(str), TCL_STATIC); } -%typemap(in) TransRiseFall* { +%typemap(in) RiseFall* { int length; const char *arg = Tcl_GetStringFromObj($input, &length); - TransRiseFall *tr = TransRiseFall::find(arg); + RiseFall *tr = RiseFall::find(arg); if (tr == nullptr) { Tcl_SetResult(interp,const_cast("Error: unknown transition name."), TCL_STATIC); @@ -617,18 +617,18 @@ using namespace sta; $1 = tr; } -%typemap(out) TransRiseFall* { - const TransRiseFall *tr = $1; +%typemap(out) RiseFall* { + const RiseFall *tr = $1; const char *str = ""; if (tr) str = tr->asString(); Tcl_SetResult(interp, const_cast(str), TCL_STATIC); } -%typemap(in) TransRiseFallBoth* { +%typemap(in) RiseFallBoth* { int length; const char *arg = Tcl_GetStringFromObj($input, &length); - TransRiseFallBoth *tr = TransRiseFallBoth::find(arg); + RiseFallBoth *tr = RiseFallBoth::find(arg); if (tr == nullptr) { Tcl_SetResult(interp,const_cast("Error: unknown transition name."), TCL_STATIC); @@ -637,8 +637,8 @@ using namespace sta; $1 = tr; } -%typemap(out) TransRiseFallBoth* { - TransRiseFallBoth *tr = $1; +%typemap(out) RiseFallBoth* { + RiseFallBoth *tr = $1; const char *str = ""; if (tr) str = tr->asString(); @@ -2010,11 +2010,11 @@ void set_rise_fall_short_names(const char *rise_short_name, const char *fall_short_name) { - TransRiseFall::rise()->setShortName(rise_short_name); - TransRiseFall::fall()->setShortName(fall_short_name); + RiseFall::rise()->setShortName(rise_short_name); + RiseFall::fall()->setShortName(fall_short_name); - TransRiseFallBoth::rise()->setShortName(rise_short_name); - TransRiseFallBoth::fall()->setShortName(fall_short_name); + RiseFallBoth::rise()->setShortName(rise_short_name); + RiseFallBoth::fall()->setShortName(fall_short_name); Transition::rise()->setName(rise_short_name); Transition::fall()->setName(fall_short_name); @@ -2023,13 +2023,13 @@ set_rise_fall_short_names(const char *rise_short_name, const char * rise_short_name() { - return TransRiseFall::rise()->shortName(); + return RiseFall::rise()->shortName(); } const char * fall_short_name() { - return TransRiseFall::fall()->shortName(); + return RiseFall::fall()->shortName(); } bool @@ -2386,7 +2386,7 @@ find_instances_hier_matching(const char *pattern, TmpInstanceSet * find_register_instances(ClockSet *clks, - const TransRiseFallBoth *clk_tr, + const RiseFallBoth *clk_tr, bool edge_triggered, bool latches) { @@ -2400,7 +2400,7 @@ find_register_instances(ClockSet *clks, TmpPinSet * find_register_data_pins(ClockSet *clks, - const TransRiseFallBoth *clk_tr, + const RiseFallBoth *clk_tr, bool edge_triggered, bool latches) { @@ -2413,7 +2413,7 @@ find_register_data_pins(ClockSet *clks, TmpPinSet * find_register_clk_pins(ClockSet *clks, - const TransRiseFallBoth *clk_tr, + const RiseFallBoth *clk_tr, bool edge_triggered, bool latches) { @@ -2426,7 +2426,7 @@ find_register_clk_pins(ClockSet *clks, TmpPinSet * find_register_async_pins(ClockSet *clks, - const TransRiseFallBoth *clk_tr, + const RiseFallBoth *clk_tr, bool edge_triggered, bool latches) { @@ -2439,7 +2439,7 @@ find_register_async_pins(ClockSet *clks, TmpPinSet * find_register_output_pins(ClockSet *clks, - const TransRiseFallBoth *clk_tr, + const RiseFallBoth *clk_tr, bool edge_triggered, bool latches) { @@ -2783,39 +2783,39 @@ set_instance_pvt(Instance *inst, float port_ext_pin_cap(Port *port, - const TransRiseFall *tr, + const RiseFall *rf, const MinMax *min_max) { cmdLinkedNetwork(); - return Sta::sta()->portExtPinCap(port, tr, min_max); + return Sta::sta()->portExtPinCap(port, rf, min_max); } void set_port_pin_cap(Port *port, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, const MinMaxAll *min_max, float cap) { - Sta::sta()->setPortExtPinCap(port, tr, min_max, cap); + Sta::sta()->setPortExtPinCap(port, rf, min_max, cap); } float port_ext_wire_cap(Port *port, - const TransRiseFall *tr, + const RiseFall *rf, const MinMax *min_max) { cmdLinkedNetwork(); - return Sta::sta()->portExtWireCap(port, tr, min_max); + return Sta::sta()->portExtWireCap(port, rf, min_max); } void set_port_wire_cap(Port *port, bool subtract_pin_cap, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, const MinMaxAll *min_max, float cap) { - Sta::sta()->setPortExtWireCap(port, subtract_pin_cap, tr, min_max, cap); + Sta::sta()->setPortExtWireCap(port, subtract_pin_cap, rf, min_max, cap); } int @@ -2950,12 +2950,12 @@ unset_propagated_clock_pin_cmd(Pin *pin) void set_clock_slew_cmd(Clock *clk, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, const MinMaxAll *min_max, float slew) { cmdLinkedNetwork(); - Sta::sta()->setClockSlew(clk, tr, min_max, slew); + Sta::sta()->setClockSlew(clk, rf, min_max, slew); } void @@ -2968,23 +2968,23 @@ unset_clock_slew_cmd(Clock *clk) void set_clock_latency_cmd(Clock *clk, Pin *pin, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, MinMaxAll *min_max, float delay) { cmdLinkedNetwork(); - Sta::sta()->setClockLatency(clk, pin, tr, min_max, delay); + Sta::sta()->setClockLatency(clk, pin, rf, min_max, delay); } void set_clock_insertion_cmd(Clock *clk, Pin *pin, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, const MinMaxAll *min_max, const EarlyLateAll *early_late, float delay) { cmdLinkedNetwork(); - Sta::sta()->setClockInsertion(clk, pin, tr, min_max, early_late, delay); + Sta::sta()->setClockInsertion(clk, pin, rf, min_max, early_late, delay); } void @@ -3039,9 +3039,9 @@ unset_clock_uncertainty_pin(Pin *pin, void set_inter_clock_uncertainty(Clock *from_clk, - const TransRiseFallBoth *from_tr, + const RiseFallBoth *from_tr, Clock *to_clk, - const TransRiseFallBoth *to_tr, + const RiseFallBoth *to_tr, const MinMaxAll *min_max, float uncertainty) { @@ -3052,9 +3052,9 @@ set_inter_clock_uncertainty(Clock *from_clk, void unset_inter_clock_uncertainty(Clock *from_clk, - const TransRiseFallBoth *from_tr, + const RiseFallBoth *from_tr, Clock *to_clk, - const TransRiseFallBoth *to_tr, + const RiseFallBoth *to_tr, const MinMaxAll *min_max) { cmdLinkedNetwork(); @@ -3062,59 +3062,59 @@ unset_inter_clock_uncertainty(Clock *from_clk, } void -set_clock_gating_check_cmd(const TransRiseFallBoth *tr, +set_clock_gating_check_cmd(const RiseFallBoth *rf, const SetupHold *setup_hold, float margin) { - Sta::sta()->setClockGatingCheck(tr, setup_hold, margin); + Sta::sta()->setClockGatingCheck(rf, setup_hold, margin); } void set_clock_gating_check_clk_cmd(Clock *clk, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, const SetupHold *setup_hold, float margin) { - Sta::sta()->setClockGatingCheck(clk, tr, setup_hold, margin); + Sta::sta()->setClockGatingCheck(clk, rf, setup_hold, margin); } void set_clock_gating_check_pin_cmd(Pin *pin, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, const SetupHold *setup_hold, float margin, LogicValue active_value) { - Sta::sta()->setClockGatingCheck(pin, tr, setup_hold, margin, active_value); + Sta::sta()->setClockGatingCheck(pin, rf, setup_hold, margin, active_value); } void set_clock_gating_check_instance_cmd(Instance *inst, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, const SetupHold *setup_hold, float margin, LogicValue active_value) { - Sta::sta()->setClockGatingCheck(inst, tr, setup_hold, margin, active_value); + Sta::sta()->setClockGatingCheck(inst, rf, setup_hold, margin, active_value); } void set_data_check_cmd(Pin *from, - const TransRiseFallBoth *from_tr, + const RiseFallBoth *from_rf, Pin *to, - const TransRiseFallBoth *to_tr, + const RiseFallBoth *to_rf, Clock *clk, const SetupHoldAll *setup_hold, float margin) { - Sta::sta()->setDataCheck(from, from_tr, to, to_tr, clk, setup_hold, margin); + Sta::sta()->setDataCheck(from, from_rf, to, to_rf, clk, setup_hold, margin); } void unset_data_check_cmd(Pin *from, - const TransRiseFallBoth *from_tr, + const RiseFallBoth *from_tr, Pin *to, - const TransRiseFallBoth *to_tr, + const RiseFallBoth *to_tr, Clock *clk, const SetupHoldAll *setup_hold) { @@ -3123,9 +3123,9 @@ unset_data_check_cmd(Pin *from, void set_input_delay_cmd(Pin *pin, - TransRiseFallBoth *tr, + RiseFallBoth *rf, Clock *clk, - TransRiseFall *clk_tr, + RiseFall *clk_rf, Pin *ref_pin, bool source_latency_included, bool network_latency_included, @@ -3134,27 +3134,27 @@ set_input_delay_cmd(Pin *pin, float delay) { cmdLinkedNetwork(); - Sta::sta()->setInputDelay(pin, tr, clk, clk_tr, ref_pin, + Sta::sta()->setInputDelay(pin, rf, clk, clk_rf, ref_pin, source_latency_included, network_latency_included, min_max, add, delay); } void unset_input_delay_cmd(Pin *pin, - TransRiseFallBoth *tr, + RiseFallBoth *rf, Clock *clk, - TransRiseFall *clk_tr, + RiseFall *clk_rf, MinMaxAll *min_max) { cmdLinkedNetwork(); - Sta::sta()->removeInputDelay(pin, tr, clk, clk_tr, min_max); + Sta::sta()->removeInputDelay(pin, rf, clk, clk_rf, min_max); } void set_output_delay_cmd(Pin *pin, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, Clock *clk, - const TransRiseFall *clk_tr, + const RiseFall *clk_rf, Pin *ref_pin, bool source_latency_included, bool network_latency_included, @@ -3163,20 +3163,20 @@ set_output_delay_cmd(Pin *pin, float delay) { cmdLinkedNetwork(); - Sta::sta()->setOutputDelay(pin, tr, clk, clk_tr, ref_pin, + Sta::sta()->setOutputDelay(pin, rf, clk, clk_rf, ref_pin, source_latency_included, network_latency_included, min_max, add, delay); } void unset_output_delay_cmd(Pin *pin, - TransRiseFallBoth *tr, + RiseFallBoth *rf, Clock *clk, - TransRiseFall *clk_tr, + RiseFall *clk_rf, MinMaxAll *min_max) { cmdLinkedNetwork(); - Sta::sta()->removeOutputDelay(pin, tr, clk, clk_tr, min_max); + Sta::sta()->removeOutputDelay(pin, rf, clk, clk_rf, min_max); } void @@ -3391,7 +3391,7 @@ ExceptionFrom * make_exception_from(PinSet *from_pins, ClockSet *from_clks, InstanceSet *from_insts, - const TransRiseFallBoth *from_tr) + const RiseFallBoth *from_tr) { cmdLinkedNetwork(); return Sta::sta()->makeExceptionFrom(from_pins, from_clks, from_insts, @@ -3416,10 +3416,10 @@ ExceptionThru * make_exception_thru(PinSet *pins, NetSet *nets, InstanceSet *insts, - const TransRiseFallBoth *tr) + const RiseFallBoth *rf) { cmdLinkedNetwork(); - return Sta::sta()->makeExceptionThru(pins, nets, insts, tr); + return Sta::sta()->makeExceptionThru(pins, nets, insts, rf); } void @@ -3432,11 +3432,11 @@ ExceptionTo * make_exception_to(PinSet *to_pins, ClockSet *to_clks, InstanceSet *to_insts, - const TransRiseFallBoth *tr, - TransRiseFallBoth *end_tr) + const RiseFallBoth *rf, + RiseFallBoth *end_rf) { cmdLinkedNetwork(); - return Sta::sta()->makeExceptionTo(to_pins, to_clks, to_insts, tr, end_tr); + return Sta::sta()->makeExceptionTo(to_pins, to_clks, to_insts, rf, end_rf); } void @@ -3455,12 +3455,12 @@ check_exception_to_pins(ExceptionTo *to, void set_input_slew_cmd(Port *port, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, const MinMaxAll *min_max, float slew) { cmdLinkedNetwork(); - Sta::sta()->setInputSlew(port, tr, min_max, slew); + Sta::sta()->setInputSlew(port, rf, min_max, slew); } void @@ -3471,35 +3471,35 @@ set_drive_cell_cmd(LibertyLibrary *library, float from_slew_rise, float from_slew_fall, LibertyPort *to_port, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, const MinMaxAll *min_max) { - float from_slews[TransRiseFall::index_count]; - from_slews[TransRiseFall::riseIndex()] = from_slew_rise; - from_slews[TransRiseFall::fallIndex()] = from_slew_fall; + float from_slews[RiseFall::index_count]; + from_slews[RiseFall::riseIndex()] = from_slew_rise; + from_slews[RiseFall::fallIndex()] = from_slew_fall; Sta::sta()->setDriveCell(library, cell, port, from_port, from_slews, - to_port, tr, min_max); + to_port, rf, min_max); } void set_drive_resistance_cmd(Port *port, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, const MinMaxAll *min_max, float res) { cmdLinkedNetwork(); - Sta::sta()->setDriveResistance(port, tr, min_max, res); + Sta::sta()->setDriveResistance(port, rf, min_max, res); } void set_slew_limit_clk(Clock *clk, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, PathClkOrData clk_data, const MinMax *min_max, float slew) { cmdLinkedNetwork(); - Sta::sta()->setSlewLimit(clk, tr, clk_data, min_max, slew); + Sta::sta()->setSlewLimit(clk, rf, clk_data, min_max, slew); } void @@ -3574,34 +3574,34 @@ set_latch_borrow_limit_clk(Clock *clk, float limit) } void -set_min_pulse_width_global(const TransRiseFallBoth *tr, +set_min_pulse_width_global(const RiseFallBoth *rf, float min_width) { - Sta::sta()->setMinPulseWidth(tr, min_width); + Sta::sta()->setMinPulseWidth(rf, min_width); } void set_min_pulse_width_pin(Pin *pin, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, float min_width) { - Sta::sta()->setMinPulseWidth(pin, tr, min_width); + Sta::sta()->setMinPulseWidth(pin, rf, min_width); } void set_min_pulse_width_clk(Clock *clk, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, float min_width) { - Sta::sta()->setMinPulseWidth(clk, tr, min_width); + Sta::sta()->setMinPulseWidth(clk, rf, min_width); } void set_min_pulse_width_inst(Instance *inst, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, float min_width) { - Sta::sta()->setMinPulseWidth(inst, tr, min_width); + Sta::sta()->setMinPulseWidth(inst, rf, min_width); } void @@ -3649,43 +3649,43 @@ unset_case_analysis_cmd(Pin *pin) void set_timing_derate_cmd(TimingDerateType type, PathClkOrData clk_data, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, const EarlyLate *early_late, float derate) { - Sta::sta()->setTimingDerate(type, clk_data, tr, early_late, derate); + Sta::sta()->setTimingDerate(type, clk_data, rf, early_late, derate); } void set_timing_derate_net_cmd(const Net *net, PathClkOrData clk_data, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, const EarlyLate *early_late, float derate) { - Sta::sta()->setTimingDerate(net, clk_data, tr, early_late, derate); + Sta::sta()->setTimingDerate(net, clk_data, rf, early_late, derate); } void set_timing_derate_inst_cmd(const Instance *inst, TimingDerateType type, PathClkOrData clk_data, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, const EarlyLate *early_late, float derate) { - Sta::sta()->setTimingDerate(inst, type, clk_data, tr, early_late, derate); + Sta::sta()->setTimingDerate(inst, type, clk_data, rf, early_late, derate); } void set_timing_derate_cell_cmd(const LibertyCell *cell, TimingDerateType type, PathClkOrData clk_data, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, const EarlyLate *early_late, float derate) { - Sta::sta()->setTimingDerate(cell, type, clk_data, tr, early_late, derate); + Sta::sta()->setTimingDerate(cell, type, clk_data, rf, early_late, derate); } void @@ -3976,11 +3976,11 @@ void set_annotated_slew(Vertex *vertex, const Corner *corner, const MinMaxAll *min_max, - const TransRiseFallBoth *tr, + const RiseFallBoth *rf, float slew) { cmdGraph(); - Sta::sta()->setAnnotatedSlew(vertex, corner, min_max, tr, slew); + Sta::sta()->setAnnotatedSlew(vertex, corner, min_max, rf, slew); } // Remove all delay and slew annotations. @@ -4565,13 +4565,13 @@ vertex_worst_arrival_path(Vertex *vertex, } PathRef * -vertex_worst_arrival_path_tr(Vertex *vertex, - const TransRiseFall *tr, +vertex_worst_arrival_path_rf(Vertex *vertex, + const RiseFall *rf, MinMax *min_max) { Sta *sta = Sta::sta(); PathRef path; - sta->vertexWorstArrivalPath(vertex, tr, min_max, path); + sta->vertexWorstArrivalPath(vertex, rf, min_max, path); if (!path.isNull()) return new PathRef(path); else @@ -5393,12 +5393,12 @@ tristate_enable() } float -capacitance(const TransRiseFall *tr, +capacitance(const RiseFall *rf, const MinMax *min_max) { Sta *sta = Sta::sta(); OperatingConditions *op_cond = sta->operatingConditions(min_max); - return self->capacitance(tr, min_max, op_cond, op_cond); + return self->capacitance(rf, min_max, op_cond, op_cond); } } // LibertyPort methods @@ -5534,35 +5534,35 @@ vertices() } float -capacitance(const TransRiseFall *tr, +capacitance(const RiseFall *rf, const Corner *corner, const MinMax *min_max) { cmdLinkedNetwork(); float pin_cap, wire_cap; - Sta::sta()->connectedCap(self, tr, corner, min_max, pin_cap, wire_cap); + Sta::sta()->connectedCap(self, rf, corner, min_max, pin_cap, wire_cap); return pin_cap + wire_cap; } float -pin_capacitance(const TransRiseFall *tr, +pin_capacitance(const RiseFall *rf, const Corner *corner, const MinMax *min_max) { cmdLinkedNetwork(); float pin_cap, wire_cap; - Sta::sta()->connectedCap(self, tr, corner, min_max, pin_cap, wire_cap); + Sta::sta()->connectedCap(self, rf, corner, min_max, pin_cap, wire_cap); return pin_cap; } float -wire_capacitance(const TransRiseFall *tr, +wire_capacitance(const RiseFall *rf, const Corner *corner, const MinMax *min_max) { cmdLinkedNetwork(); float pin_cap, wire_cap; - Sta::sta()->connectedCap(self, tr, corner, min_max, pin_cap, wire_cap); + Sta::sta()->connectedCap(self, rf, corner, min_max, pin_cap, wire_cap); return wire_cap; } @@ -5591,35 +5591,35 @@ bool is_power() { return cmdLinkedNetwork()->isPower(self);} bool is_ground() { return cmdLinkedNetwork()->isGround(self);} float -capacitance(const TransRiseFall *tr, +capacitance(const RiseFall *rf, const Corner *corner, const MinMax *min_max) { cmdLinkedNetwork(); float pin_cap, wire_cap; - Sta::sta()->connectedCap(self, tr, corner, min_max, pin_cap, wire_cap); + Sta::sta()->connectedCap(self, rf, corner, min_max, pin_cap, wire_cap); return pin_cap + wire_cap; } float -pin_capacitance(const TransRiseFall *tr, +pin_capacitance(const RiseFall *rf, const Corner *corner, const MinMax *min_max) { cmdLinkedNetwork(); float pin_cap, wire_cap; - Sta::sta()->connectedCap(self, tr, corner, min_max, pin_cap, wire_cap); + Sta::sta()->connectedCap(self, rf, corner, min_max, pin_cap, wire_cap); return pin_cap; } float -wire_capacitance(const TransRiseFall *tr, +wire_capacitance(const RiseFall *rf, const Corner *corner, const MinMax *min_max) { cmdLinkedNetwork(); float pin_cap, wire_cap; - Sta::sta()->connectedCap(self, tr, corner, min_max, pin_cap, wire_cap); + Sta::sta()->connectedCap(self, rf, corner, min_max, pin_cap, wire_cap); return wire_cap; } @@ -5663,7 +5663,7 @@ void finish() { delete self; } %extend Clock { float period() { return self->period(); } FloatSeq *waveform() { return self->waveform(); } -float time(TransRiseFall *tr) { return self->edge(tr)->time(); } +float time(RiseFall *rf) { return self->edge(rf)->time(); } bool is_generated() { return self->isGenerated(); } bool waveform_valid() { return self->waveformValid(); } bool is_virtual() { return self->isVirtual(); } @@ -5671,17 +5671,17 @@ bool is_propagated() { return self->isPropagated(); } PinSet &sources() { return self->pins(); } float -slew(const TransRiseFall *tr, +slew(const RiseFall *rf, const MinMax *min_max) { - return self->slew(tr, min_max); + return self->slew(rf, min_max); } } %extend ClockEdge { Clock *clock() { return self->clock(); } -TransRiseFall *transition() { return self->transition(); } +RiseFall *transition() { return self->transition(); } float time() { return self->time(); } } @@ -5698,24 +5698,24 @@ int level() { return Sta::sta()->vertexLevel(self); } int tag_group_index() { return self->tagGroupIndex(); } TmpFloatSeq * -slews(TransRiseFall *tr) +slews(RiseFall *rf) { Sta *sta = Sta::sta(); TmpFloatSeq *floats = new FloatSeq; DcalcAnalysisPtIterator ap_iter(sta); while (ap_iter.hasNext()) { DcalcAnalysisPt *dcalc_ap = ap_iter.next(); - floats->push_back(delayAsFloat(sta->vertexSlew(self, tr, dcalc_ap))); + floats->push_back(delayAsFloat(sta->vertexSlew(self, rf, dcalc_ap))); } return floats; } Slew -slew(const TransRiseFall *tr, +slew(const RiseFall *rf, const MinMax *min_max) { Sta *sta = Sta::sta(); - return sta->vertexSlew(self, tr, min_max); + return sta->vertexSlew(self, rf, min_max); } VertexOutEdgeIterator * @@ -5731,35 +5731,35 @@ in_edge_iterator() } TmpFloatSeq * -arrivals_clk(const TransRiseFall *tr, +arrivals_clk(const RiseFall *rf, Clock *clk, - const TransRiseFall *clk_tr) + const RiseFall *clk_rf) { Sta *sta = Sta::sta(); TmpFloatSeq *floats = new FloatSeq; const ClockEdge *clk_edge = nullptr; if (clk) - clk_edge = clk->edge(clk_tr); + clk_edge = clk->edge(clk_rf); for (auto path_ap : sta->corners()->pathAnalysisPts()) { - floats->push_back(delayAsFloat(sta->vertexArrival(self, tr, clk_edge, + floats->push_back(delayAsFloat(sta->vertexArrival(self, rf, clk_edge, path_ap))); } return floats; } TmpStringSeq * -arrivals_clk_delays(const TransRiseFall *tr, +arrivals_clk_delays(const RiseFall *rf, Clock *clk, - const TransRiseFall *clk_tr, + const RiseFall *clk_rf, int digits) { Sta *sta = Sta::sta(); StringSeq *arrivals = new StringSeq; const ClockEdge *clk_edge = nullptr; if (clk) - clk_edge = clk->edge(clk_tr); + clk_edge = clk->edge(clk_rf); for (auto path_ap : sta->corners()->pathAnalysisPts()) { - arrivals->push_back(delayAsString(sta->vertexArrival(self, tr, clk_edge, + arrivals->push_back(delayAsString(sta->vertexArrival(self, rf, clk_edge, path_ap), sta, digits)); } @@ -5767,35 +5767,35 @@ arrivals_clk_delays(const TransRiseFall *tr, } TmpFloatSeq * -requireds_clk(const TransRiseFall *tr, +requireds_clk(const RiseFall *rf, Clock *clk, - const TransRiseFall *clk_tr) + const RiseFall *clk_rf) { Sta *sta = Sta::sta(); TmpFloatSeq *floats = new FloatSeq; const ClockEdge *clk_edge = nullptr; if (clk) - clk_edge = clk->edge(clk_tr); + clk_edge = clk->edge(clk_rf); for (auto path_ap : sta->corners()->pathAnalysisPts()) { - floats->push_back(delayAsFloat(sta->vertexRequired(self, tr, clk_edge, + floats->push_back(delayAsFloat(sta->vertexRequired(self, rf, clk_edge, path_ap))); } return floats; } TmpStringSeq * -requireds_clk_delays(const TransRiseFall *tr, +requireds_clk_delays(const RiseFall *rf, Clock *clk, - const TransRiseFall *clk_tr, + const RiseFall *clk_rf, int digits) { Sta *sta = Sta::sta(); StringSeq *requireds = new StringSeq; const ClockEdge *clk_edge = nullptr; if (clk) - clk_edge = clk->edge(clk_tr); + clk_edge = clk->edge(clk_rf); for (auto path_ap : sta->corners()->pathAnalysisPts()) { - requireds->push_back(delayAsString(sta->vertexRequired(self, tr, clk_edge, + requireds->push_back(delayAsString(sta->vertexRequired(self, rf, clk_edge, path_ap), sta, digits)); } @@ -5803,47 +5803,47 @@ requireds_clk_delays(const TransRiseFall *tr, } TmpFloatSeq * -slacks(TransRiseFall *tr) +slacks(RiseFall *rf) { Sta *sta = Sta::sta(); TmpFloatSeq *floats = new FloatSeq; for (auto path_ap : sta->corners()->pathAnalysisPts()) { - floats->push_back(delayAsFloat(sta->vertexSlack(self, tr, path_ap))); + floats->push_back(delayAsFloat(sta->vertexSlack(self, rf, path_ap))); } return floats; } // Slack with respect to a clock rise/fall edge. TmpFloatSeq * -slacks_clk(const TransRiseFall *tr, +slacks_clk(const RiseFall *rf, Clock *clk, - const TransRiseFall *clk_tr) + const RiseFall *clk_rf) { Sta *sta = Sta::sta(); TmpFloatSeq *floats = new FloatSeq; const ClockEdge *clk_edge = nullptr; if (clk) - clk_edge = clk->edge(clk_tr); + clk_edge = clk->edge(clk_rf); for (auto path_ap : sta->corners()->pathAnalysisPts()) { - floats->push_back(delayAsFloat(sta->vertexSlack(self, tr, clk_edge, + floats->push_back(delayAsFloat(sta->vertexSlack(self, rf, clk_edge, path_ap))); } return floats; } TmpStringSeq * -slacks_clk_delays(const TransRiseFall *tr, +slacks_clk_delays(const RiseFall *rf, Clock *clk, - const TransRiseFall *clk_tr, + const RiseFall *clk_rf, int digits) { Sta *sta = Sta::sta(); StringSeq *slacks = new StringSeq; const ClockEdge *clk_edge = nullptr; if (clk) - clk_edge = clk->edge(clk_tr); + clk_edge = clk->edge(clk_rf); for (auto path_ap : sta->corners()->pathAnalysisPts()) { - slacks->push_back(delayAsString(sta->vertexSlack(self, tr, clk_edge, + slacks->push_back(delayAsString(sta->vertexSlack(self, rf, clk_edge, path_ap), sta, digits)); } @@ -5851,10 +5851,10 @@ slacks_clk_delays(const TransRiseFall *tr, } VertexPathIterator * -path_iterator(const TransRiseFall *tr, +path_iterator(const RiseFall *rf, const MinMax *min_max) { - return Sta::sta()->vertexPathIterator(self, tr, min_max); + return Sta::sta()->vertexPathIterator(self, rf, min_max); } bool @@ -5979,10 +5979,10 @@ latch_d_to_q_en() TimingArcSet *d_q_set = self->timingArcSet(); LibertyPort *enable_port; FuncExpr *enable_func; - TransRiseFall *enable_tr; - lib_cell->latchEnable(d_q_set, enable_port, enable_func, enable_tr); + RiseFall *enable_rf; + lib_cell->latchEnable(d_q_set, enable_port, enable_func, enable_rf); const char *en_name = enable_port->name(); - return stringPrintTmp("%s %s", en_name, enable_tr->asString()); + return stringPrintTmp("%s %s", en_name, enable_rf->asString()); } return ""; @@ -6018,8 +6018,8 @@ bool is_path_delay() { return self->isPathDelay(); } bool is_gated_clock() { return self->isGatedClock(); } Vertex *vertex() { return self->vertex(Sta::sta()); } PathRef *path() { return &self->pathRef(); } -TransRiseFall *end_transition() -{ return const_cast(self->path()->transition(Sta::sta())); } +RiseFall *end_transition() +{ return const_cast(self->path()->transition(Sta::sta())); } Slack slack() { return self->slack(Sta::sta()); } ArcDelay margin() { return self->margin(Sta::sta()); } Required data_required_time() { return self->requiredTimeOffset(Sta::sta()); } @@ -6048,8 +6048,8 @@ Arrival target_clk_arrival() { return self->targetClkArrival(Sta::sta()); } bool path_delay_margin_is_external() { return self->pathDelayMarginIsExternal();} Crpr common_clk_pessimism() { return self->commonClkPessimism(Sta::sta()); } -TransRiseFall *target_clk_end_trans() -{ return const_cast(self->targetClkEndTrans(Sta::sta())); } +RiseFall *target_clk_end_trans() +{ return const_cast(self->targetClkEndTrans(Sta::sta())); } }