slew limit check respect set_disable_timing [get_lib_ports]
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parent
7c02b7425a
commit
c8b2b65fe3
11
sdc/Sdc.cc
11
sdc/Sdc.cc
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@ -6128,6 +6128,17 @@ Sdc::annotateDisables(bool annotate)
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annotateGraphDisabled(pin, annotate);
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}
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if (!disabled_lib_ports_.empty()) {
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VertexIterator vertex_iter(graph_);
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while (vertex_iter.hasNext()) {
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Vertex *vertex = vertex_iter.next();
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Pin *pin = vertex->pin();
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LibertyPort *port = network_->libertyPort(pin);
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if (disabled_lib_ports_.hasKey(port))
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annotateGraphDisabled(pin, annotate);
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}
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}
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Instance *top_inst = network_->topInstance();
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PortSet::Iterator port_iter(disabled_ports_);
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while (port_iter.hasNext()) {
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@ -137,7 +137,8 @@ CheckSlewLimits::checkSlews1(const Pin *pin,
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{
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Vertex *vertex, *bidirect_drvr_vertex;
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sta_->graph()->pinVertices(pin, vertex, bidirect_drvr_vertex);
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if (!vertex->isDisabledConstraint())
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if (vertex
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&& !vertex->isDisabledConstraint())
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checkSlews1(vertex, corner, min_max,
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corner1, rf, slew, limit, slack);
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if (bidirect_drvr_vertex
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@ -5242,6 +5242,7 @@ find_cells_matching(const char *pattern,
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} // Library methods
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%extend LibertyLibrary {
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const char *name() { return self->name(); }
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LibertyCell *
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find_liberty_cell(const char *name)
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@ -5326,6 +5327,7 @@ find_ports_matching(const char *pattern,
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} // Cell methods
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%extend LibertyCell {
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const char *name() { return self->name(); }
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bool is_leaf() { return self->isLeaf(); }
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LibertyLibrary *liberty_library() { return self->libertyLibrary(); }
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Cell *cell() { return reinterpret_cast<Cell*>(self); }
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@ -5883,6 +5885,8 @@ is_clock()
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return search->isClock(self);
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}
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bool is_disabled_constraint() { return self->isDisabledConstraint(); }
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} // Vertex methods
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%extend Edge {
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