crpr clk path for reg clk zero min/max wire delay redo

Signed-off-by: James Cherry <[email protected]>
2026-09-07 03:43:29 +02:00 · 2025-03-21 13:09:29 -07:00
parent a34588e2c5
commit c6d8e3cf91
2 changed files with 27 additions and 13 deletions
@@ -258,6 +258,7 @@ public:
                  bool to_propagates_clk,
                  Edge *edge,
                  const RiseFall *to_rf,
+                  bool arc_delay_min_max_eq,
                  const MinMax *min_max,
                  const PathAnalysisPt *path_ap);
  ClkInfo *thruClkInfo(PathVertex *from_path,
@@ -268,6 +269,7 @@ public:
                       Vertex *to_vertex,
                       const Pin *to_pin,
                       bool to_is_clk,
+                       bool arc_delay_min_max_eq,
                       const MinMax *min_max,
                       const PathAnalysisPt *path_ap);
  ClkInfo *clkInfoWithCrprClkPath(ClkInfo *from_clk_info,