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crpr clk path for reg clk zero min/max wire delay 

Signed-off-by: James Cherry <cherry@parallaxsw.com>
This commit is contained in:
James Cherry 2025-03-18 21:14:09 -07:00
parent 2d52aea14f
commit a34588e2c5
1 changed files with 7 additions and 1 deletions
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8
search/Search.cc
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@ -2197,7 +2197,13 @@ PathVisitor::visitFromPath(const Pin *from_pin,
&& from_tag->isClock())) {
const RiseFall *clk_rf = clk_edge ? clk_edge->transition() : nullptr;
ClkInfo *to_clk_info = from_clk_info;
if (network_->direction(to_pin)->isInternal())
const PathAnalysisPt *path_ap_opp =
path_ap->corner()->findPathAnalysisPt(min_max->opposite());
Delay arc_delay_opp = search_->deratedDelay(from_vertex, arc, edge,
false, path_ap_opp);
bool delay_min_max_eq = fuzzyEqual(arc_delay, arc_delay_opp);
if (delay_min_max_eq
|| network_->direction(to_pin)->isInternal())
to_clk_info = search_->clkInfoWithCrprClkPath(from_clk_info,
from_path, path_ap);
to_tag = search_->fromRegClkTag(from_pin, from_rf, clk, clk_rf,