luke
/
OpenSTA
mirror of https://github.com/The-OpenROAD-Project/OpenSTA.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

rm Search::pathPropagatedToClkSrc 

Signed-off-by: James Cherry <cherry@parallaxsw.com>
This commit is contained in:
James Cherry 2022-08-11 12:45:31 -07:00
parent de39ab34b8
commit c43cd616db
3 changed files with 71 additions and 93 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
include/sta/Search.hh
View File

@ -340,8 +340,6 @@ public:
Vertex *vertex,
TagGroupBldr *tag_bldr);
void ensureDownstreamClkPins();
bool pathPropagatedToClkSrc(const Pin *pin,
Path *path);
// Check paths from inputs from the default arrival clock
// (missing set_input_delay).
virtual bool checkDefaultArrivalPaths() { return true; }

47
search/Search.cc
View File

@ -2029,20 +2029,16 @@ PathVisitor::visitEdge(const Pin *from_pin,
PathAnalysisPt *path_ap = from_path->pathAnalysisPt(sta_);
const MinMax *min_max = path_ap->pathMinMax();
const RiseFall *from_rf = from_path->transition(sta_);
// Do not propagate paths from a clock source unless they are
// defined on the from pin.
if (!search->pathPropagatedToClkSrc(from_pin, from_path)) {
TimingArc *arc1, *arc2;
arc_set->arcsFrom(from_rf, arc1, arc2);
if (!visitArc(from_pin, from_vertex, from_rf, from_path,
edge, arc1, to_pin, to_vertex,
min_max, path_ap))
return false;
if (!visitArc(from_pin, from_vertex, from_rf, from_path,
edge, arc2, to_pin, to_vertex,
min_max, path_ap))
return false;
}
TimingArc *arc1, *arc2;
arc_set->arcsFrom(from_rf, arc1, arc2);
if (!visitArc(from_pin, from_vertex, from_rf, from_path,
edge, arc1, to_pin, to_vertex,
min_max, path_ap))
return false;
if (!visitArc(from_pin, from_vertex, from_rf, from_path,
edge, arc2, to_pin, to_vertex,
min_max, path_ap))
return false;
}
}
return true;
@ -2070,22 +2066,6 @@ PathVisitor::visitArc(const Pin *from_pin,
return true;
}
bool
Search::pathPropagatedToClkSrc(const Pin *pin,
Path *path)
{
const Tag *tag = path->tag(this);
if (!tag->isGenClkSrcPath()
// Clock source can have input arrivals from unrelated clock.
&& tag->inputDelay() == nullptr) {
ClockSet *clks = sdc_->findLeafPinClocks(pin);
return clks
&& !clks->hasKey(tag->clock());
}
else
return false;
}
bool
PathVisitor::visitFromPath(const Pin *from_pin,
Vertex *from_vertex,
@ -2194,12 +2174,17 @@ PathVisitor::visitFromPath(const Pin *from_pin,
}
}
else if (from_tag->isClock()) {
ClockSet *clks = sdc->findLeafPinClocks(from_pin);
// Disable edges from hierarchical clock source pins that do
// not go thru the hierarchical pin and edges from clock source pins
// that traverse a hierarchical source pin of a different clock.
// Clock arrivals used as data also need to be disabled.
if (!(role == TimingRole::wire()
&& sdc->clkDisabledByHpinThru(clk, from_pin, to_pin))) {
&& sdc->clkDisabledByHpinThru(clk, from_pin, to_pin))
// Generated clock source pins have arrivals for the source clock.
// Do not propagate them past the generated clock source pin.
&& !(clks
&& !clks->hasKey(from_tag->clock()))) {
// Propagate arrival as non-clock at the end of the clock tree.
bool to_propagates_clk =
!sdc->clkStopPropagation(clk,from_pin,from_rf,to_pin,to_rf)

115
search/VisitPathEnds.cc
View File

@ -162,62 +162,60 @@ VisitPathEnds::visitCheckEnd(const Pin *pin,
tgt_clk_edge, min_max);
// Ignore generated clock source paths.
if (!tgt_clk_info->isGenClkSrcPath()
&& !search_->pathPropagatedToClkSrc(tgt_pin, tgt_clk_path)) {
if (tgt_clk_path->isClock(this)) {
check_clked = true;
if (!filtered
|| search_->matchesFilter(path, tgt_clk_edge)) {
if (src_clk_edge
&& tgt_clk != sdc_->defaultArrivalClock()
&& sdc_->sameClockGroup(src_clk, tgt_clk)
&& !sdc_->clkStopPropagation(tgt_pin, tgt_clk)
&& (search_->checkDefaultArrivalPaths()
|| src_clk_edge
!= sdc_->defaultArrivalClockEdge())
// False paths and path delays override
// paths.
&& (exception == nullptr
|| exception->isFilter()
|| exception->isGroupPath()
|| exception->isMultiCycle())) {
MultiCyclePath *mcp=dynamic_cast<MultiCyclePath*>(exception);
if (network_->isLatchData(pin)
&& check_role == TimingRole::setup()) {
PathEndLatchCheck path_end(path, check_arc, edge,
tgt_clk_path, mcp, nullptr,
this);
visitor->visit(&path_end);
is_constrained = true;
}
else {
PathEndCheck path_end(path, check_arc, edge,
tgt_clk_path, mcp, this);
visitor->visit(&path_end);
is_constrained = true;
}
}
else if (exception
&& exception->isPathDelay()
&& (src_clk == nullptr
|| sdc_->sameClockGroup(src_clk,
tgt_clk))) {
PathDelay *path_delay = dynamic_cast<PathDelay*>(exception);
if (network_->isLatchData(pin)
&& check_role == TimingRole::setup()) {
PathEndLatchCheck path_end(path, check_arc, edge,
tgt_clk_path, nullptr,
path_delay, this);
visitor->visit(&path_end);
}
else {
PathEndPathDelay path_end(path_delay, path, tgt_clk_path,
check_arc, edge, this);
visitor->visit(&path_end);
is_constrained = true;
}
}
}
}
&& tgt_clk_path->isClock(this)) {
check_clked = true;
if (!filtered
|| search_->matchesFilter(path, tgt_clk_edge)) {
if (src_clk_edge
&& tgt_clk != sdc_->defaultArrivalClock()
&& sdc_->sameClockGroup(src_clk, tgt_clk)
&& !sdc_->clkStopPropagation(tgt_pin, tgt_clk)
&& (search_->checkDefaultArrivalPaths()
|| src_clk_edge
!= sdc_->defaultArrivalClockEdge())
// False paths and path delays override
// paths.
&& (exception == nullptr
|| exception->isFilter()
|| exception->isGroupPath()
|| exception->isMultiCycle())) {
MultiCyclePath *mcp=dynamic_cast<MultiCyclePath*>(exception);
if (network_->isLatchData(pin)
&& check_role == TimingRole::setup()) {
PathEndLatchCheck path_end(path, check_arc, edge,
tgt_clk_path, mcp, nullptr,
this);
visitor->visit(&path_end);
is_constrained = true;
}
else {
PathEndCheck path_end(path, check_arc, edge,
tgt_clk_path, mcp, this);
visitor->visit(&path_end);
is_constrained = true;
}
}
else if (exception
&& exception->isPathDelay()
&& (src_clk == nullptr
|| sdc_->sameClockGroup(src_clk,
tgt_clk))) {
PathDelay *path_delay = dynamic_cast<PathDelay*>(exception);
if (network_->isLatchData(pin)
&& check_role == TimingRole::setup()) {
PathEndLatchCheck path_end(path, check_arc, edge,
tgt_clk_path, nullptr,
path_delay, this);
visitor->visit(&path_end);
}
else {
PathEndPathDelay path_end(path_delay, path, tgt_clk_path,
check_arc, edge, this);
visitor->visit(&path_end);
is_constrained = true;
}
}
}
}
}
}
@ -412,7 +410,6 @@ VisitPathEnds::visitGatedClkEnd(const Pin *pin,
&& clk_edge != sdc_->defaultArrivalClockEdge()
// Ignore generated clock source paths.
&& !path->clkInfo(this)->isGenClkSrcPath()
&& !search_->pathPropagatedToClkSrc(clk_pin, clk_path)
&& !sdc_->clkStopPropagation(pin, clk)
&& clk_vertex->hasDownstreamClkPin()) {
TimingRole *check_role = (min_max == MinMax::max())
@ -538,8 +535,7 @@ VisitPathEnds::visitDataCheckEnd1(DataCheck *check,
const ClockEdge *tgt_clk_edge = tgt_clk_path->clkEdge(this);
// Ignore generated clock source paths.
if (tgt_clk_edge
&& !tgt_clk_path->clkInfo(this)->isGenClkSrcPath()
&& !search_->pathPropagatedToClkSrc(from_pin, tgt_clk_path)) {
&& !tgt_clk_path->clkInfo(this)->isGenClkSrcPath()) {
found_from_path = true;
const Clock *tgt_clk = tgt_clk_edge->clock();
ExceptionPath *exception = exceptionTo(path, pin, end_rf,
@ -583,7 +579,6 @@ VisitPathEnds::visitUnconstrainedPathEnds(const Pin *pin,
&& min_max->matches(path_min_max)
// Ignore generated clock source paths.
&& !path->clkInfo(this)->isGenClkSrcPath()
&& !search_->pathPropagatedToClkSrc(pin, path)
&& (!filtered
|| search_->matchesFilter(path, nullptr))
&& !falsePathTo(path, pin, path->transition(this),