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liberty rm "pin" from port function names 

Signed-off-by: James Cherry <cherry@parallaxsw.com>
This commit is contained in:
James Cherry 2022-11-27 14:47:12 -08:00
parent fdba9eb279
commit b752018e27
4 changed files with 59 additions and 59 deletions
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48
include/sta/Liberty.hh
View File

@ -732,26 +732,26 @@ public:
float min_width);
bool isClock() const;
void setIsClock(bool is_clk);
bool isClockGateClockPin() const { return is_clk_gate_clk_pin_; }
void setIsClockGateClockPin(bool is_clk_gate_clk);
bool isClockGateEnablePin() const { return is_clk_gate_enable_pin_; }
void setIsClockGateEnablePin(bool is_clk_gate_enable);
bool isClockGateOutPin() const { return is_clk_gate_out_pin_; }
void setIsClockGateOutPin(bool is_clk_gate_out);
bool isPllFeedbackPin() const { return is_pll_feedback_pin_; }
void setIsPllFeedbackPin(bool is_pll_feedback_pin);
bool isClockGateClock() const { return is_clk_gate_clk_; }
void setIsClockGateClock(bool is_clk_gate_clk);
bool isClockGateEnable() const { return is_clk_gate_enable_; }
void setIsClockGateEnable(bool is_clk_gate_enable);
bool isClockGateOut() const { return is_clk_gate_out_; }
void setIsClockGateOut(bool is_clk_gate_out);
bool isPllFeedback() const { return is_pll_feedback_; }
void setIsPllFeedback(bool is_pll_feedback);
bool isolationCellDataPin() const { return isolation_cell_data_pin_; }
void setIsolationCellDataPin(bool isolation_cell_data_pin);
bool isolationCellData() const { return isolation_cell_data_; }
void setIsolationCellData(bool isolation_cell_data);
bool isolationCellEnablePin() const { return isolation_cell_enable_pin_; }
void setIsolationCellEnablePin(bool isolation_cell_enable_pin);
bool isolationCellEnable() const { return isolation_cell_enable_; }
void setIsolationCellEnable(bool isolation_cell_enable);
bool levelShifterDataPin() const { return level_shifter_data_pin_; }
void setLevelShifterDataPin(bool level_shifter_data_pin);
bool levelShifterData() const { return level_shifter_data_; }
void setLevelShifterData(bool level_shifter_data);
bool switchPin() const { return switch_pin_; }
void setSwitchPin(bool switch_pin);
bool isSwitch() const { return is_switch_; }
void setIsSwitch(bool is_switch);
// Has register/latch rise/fall edges from pin.
bool isRegClk() const { return is_reg_clk_; }
@ -825,14 +825,14 @@ protected:
bool is_clk_:1;
bool is_reg_clk_:1;
bool is_check_clk_:1;
bool is_clk_gate_clk_pin_:1;
bool is_clk_gate_enable_pin_:1;
bool is_clk_gate_out_pin_:1;
bool is_pll_feedback_pin_:1;
bool isolation_cell_data_pin_:1;
bool isolation_cell_enable_pin_:1;
bool level_shifter_data_pin_:1;
bool switch_pin_:1;
bool is_clk_gate_clk_:1;
bool is_clk_gate_enable_:1;
bool is_clk_gate_out_:1;
bool is_pll_feedback_:1;
bool isolation_cell_data_:1;
bool isolation_cell_enable_:1;
bool level_shifter_data_:1;
bool is_switch_:1;
bool is_disabled_constraint_:1;
private:

48
liberty/Liberty.cc
View File

@ -1922,14 +1922,14 @@ LibertyPort::LibertyPort(LibertyCell *cell,
is_clk_(false),
is_reg_clk_(false),
is_check_clk_(false),
is_clk_gate_clk_pin_(false),
is_clk_gate_enable_pin_(false),
is_clk_gate_out_pin_(false),
is_pll_feedback_pin_(false),
isolation_cell_data_pin_(false),
isolation_cell_enable_pin_(false),
level_shifter_data_pin_(false),
switch_pin_(false),
is_clk_gate_clk_(false),
is_clk_gate_enable_(false),
is_clk_gate_out_(false),
is_pll_feedback_(false),
isolation_cell_data_(false),
isolation_cell_enable_(false),
level_shifter_data_(false),
is_switch_(false),
is_disabled_constraint_(false)
{
liberty_port_ = this;
@ -2360,51 +2360,51 @@ LibertyPort::setIsCheckClk(bool is_clk)
}
void
LibertyPort::setIsClockGateClockPin(bool is_clk_gate_clk)
LibertyPort::setIsClockGateClock(bool is_clk_gate_clk)
{
is_clk_gate_clk_pin_ = is_clk_gate_clk;
is_clk_gate_clk_ = is_clk_gate_clk;
}
void
LibertyPort::setIsClockGateEnablePin(bool is_clk_gate_enable)
LibertyPort::setIsClockGateEnable(bool is_clk_gate_enable)
{
is_clk_gate_enable_pin_ = is_clk_gate_enable;
is_clk_gate_enable_ = is_clk_gate_enable;
}
void
LibertyPort::setIsClockGateOutPin(bool is_clk_gate_out)
LibertyPort::setIsClockGateOut(bool is_clk_gate_out)
{
is_clk_gate_out_pin_ = is_clk_gate_out;
is_clk_gate_out_ = is_clk_gate_out;
}
void
LibertyPort::setIsPllFeedbackPin(bool is_pll_feedback_pin)
LibertyPort::setIsPllFeedback(bool is_pll_feedback)
{
is_pll_feedback_pin_ = is_pll_feedback_pin;
is_pll_feedback_ = is_pll_feedback;
}
void
LibertyPort::setIsolationCellDataPin(bool isolation_cell_data_pin)
LibertyPort::setIsolationCellData(bool isolation_cell_data)
{
isolation_cell_data_pin_ = isolation_cell_data_pin;
isolation_cell_data_ = isolation_cell_data;
}
void
LibertyPort::setIsolationCellEnablePin(bool isolation_cell_enable_pin)
LibertyPort::setIsolationCellEnable(bool isolation_cell_enable)
{
isolation_cell_enable_pin_ = isolation_cell_enable_pin;
isolation_cell_enable_ = isolation_cell_enable;
}
void
LibertyPort::setLevelShifterDataPin(bool level_shifter_data_pin)
LibertyPort::setLevelShifterData(bool level_shifter_data)
{
level_shifter_data_pin_ = level_shifter_data_pin;
level_shifter_data_ = level_shifter_data;
}
void
LibertyPort::setSwitchPin(bool switch_pin)
LibertyPort::setIsSwitch(bool is_switch)
{
switch_pin_ = switch_pin;
is_switch_ = is_switch;
}
void

16
liberty/LibertyReader.cc
View File

@ -3291,25 +3291,25 @@ LibertyReader::visitPulseClock(LibertyAttr *attr)
void
LibertyReader::visitClockGateClockPin(LibertyAttr *attr)
{
visitPortBoolAttr(attr, &LibertyPort::setIsClockGateClockPin);
visitPortBoolAttr(attr, &LibertyPort::setIsClockGateClock);
}
void
LibertyReader::visitClockGateEnablePin(LibertyAttr *attr)
{
visitPortBoolAttr(attr, &LibertyPort::setIsClockGateEnablePin);
visitPortBoolAttr(attr, &LibertyPort::setIsClockGateEnable);
}
void
LibertyReader::visitClockGateOutPin(LibertyAttr *attr)
{
visitPortBoolAttr(attr, &LibertyPort::setIsClockGateOutPin);
visitPortBoolAttr(attr, &LibertyPort::setIsClockGateOut);
}
void
LibertyReader::visitIsPllFeedbackPin(LibertyAttr *attr)
{
visitPortBoolAttr(attr, &LibertyPort::setIsPllFeedbackPin);
visitPortBoolAttr(attr, &LibertyPort::setIsPllFeedback);
}
void
@ -3333,25 +3333,25 @@ LibertyReader::visitSignalType(LibertyAttr *attr)
void
LibertyReader::visitIsolationCellDataPin(LibertyAttr *attr)
{
visitPortBoolAttr(attr, &LibertyPort::setIsolationCellDataPin);
visitPortBoolAttr(attr, &LibertyPort::setIsolationCellData);
}
void
LibertyReader::visitIsolationCellEnablePin(LibertyAttr *attr)
{
visitPortBoolAttr(attr, &LibertyPort::setIsolationCellEnablePin);
visitPortBoolAttr(attr, &LibertyPort::setIsolationCellEnable);
}
void
LibertyReader::visitLevelShifterDataPin(LibertyAttr *attr)
{
visitPortBoolAttr(attr, &LibertyPort::setLevelShifterDataPin);
visitPortBoolAttr(attr, &LibertyPort::setLevelShifterData);
}
void
LibertyReader::visitSwitchPin(LibertyAttr *attr)
{
visitPortBoolAttr(attr, &LibertyPort::setSwitchPin);
visitPortBoolAttr(attr, &LibertyPort::setIsSwitch);
}
void

6
search/Sim.cc
View File

@ -958,7 +958,7 @@ Sim::evalInstance(const Instance *inst,
}
}
}
else if (port->isClockGateOutPin()) {
else if (port->isClockGateOut()) {
value = clockGateOutValue(inst);
debugPrint(debug_, "sim", 2, " %s gated_clk = %c",
port->name(),
@ -979,8 +979,8 @@ Sim::clockGateOutValue(const Instance *inst)
LibertyCellPortIterator port_iter(cell);
while (port_iter.hasNext()) {
LibertyPort *port = port_iter.next();
if (port->isClockGateClockPin()
|| port->isClockGateEnablePin()) {
if (port->isClockGateClock()
|| port->isClockGateEnable()) {
Pin *gclk_pin = network_->findPin(inst, port);
if (gclk_pin) {
Vertex *gclk_vertex = graph_->pinLoadVertex(gclk_pin);