compress example liberty files

Signed-off-by: James Cherry <cherry@parallaxsw.com>
2024-10-05 18:12:23 -07:00 · 2024-10-05 18:12:23 -07:00 · b04def2de0
parent f71405fb40
commit b04def2de0
16 changed files with 11 additions and 573035 deletions
--- a/examples/delay_calc.tcl
+++ b/examples/delay_calc.tcl
@ -1,5 +1,5 @@
 # delay calc example
-read_liberty nangate45_slow.lib
+read_liberty nangate45_slow.lib.gz
 read_verilog example1.v
 link_design top
 create_clock -name clk -period 10 {clk1 clk2 clk3}
--- a/examples/min_max_delays.tcl
+++ b/examples/min_max_delays.tcl
@ -1,6 +1,6 @@
 # min/max delay calc example
-read_liberty -max nangate45_slow.lib
-read_liberty -min nangate45_fast.lib
+read_liberty -max nangate45_slow.lib.gz
+read_liberty -min nangate45_fast.lib.gz
 read_verilog example1.v
 link_design top
 create_clock -name clk -period 10 {clk1 clk2 clk3}
--- a/examples/multi_corner.tcl
+++ b/examples/multi_corner.tcl
@ -1,8 +1,8 @@
 # 3 corners with +/- 10% derating example
 define_corners ss tt ff
-read_liberty -corner ss nangate45_slow.lib
-read_liberty -corner tt nangate45_typ.lib
-read_liberty -corner ff nangate45_fast.lib
+read_liberty -corner ss nangate45_slow.lib.gz
+read_liberty -corner tt nangate45_typ.lib.gz
+read_liberty -corner ff nangate45_fast.lib.gz
 read_verilog example1.v
 link_design top
 set_timing_derate -early 0.9
--- a/examples/nangate45_fast.lib
+++ b/examples/nangate45_fast.lib
--- a/examples/nangate45_fast.lib.gz
+++ b/examples/nangate45_fast.lib.gz
--- a/examples/nangate45_slow.lib
+++ b/examples/nangate45_slow.lib
--- a/examples/nangate45_slow.lib.gz
+++ b/examples/nangate45_slow.lib.gz
--- a/examples/nangate45_typ.lib
+++ b/examples/nangate45_typ.lib
--- a/examples/nangate45_typ.lib.gz
+++ b/examples/nangate45_typ.lib.gz
--- a/examples/power.tcl
+++ b/examples/power.tcl
@ -1,5 +1,5 @@
 # report_power gcd
-read_liberty sky130hd_tt.lib
+read_liberty sky130hd_tt.lib.gz
 read_verilog gcd_sky130hd.v
 link_design gcd

--- a/examples/power_vcd.tcl
+++ b/examples/power_vcd.tcl
@ -1,5 +1,5 @@
 # read_vcd_activities gcd
-read_liberty sky130hd_tt.lib
+read_liberty sky130hd_tt.lib.gz
 read_verilog gcd_sky130hd.v
 link_design gcd

--- a/examples/sdf_delays.tcl
+++ b/examples/sdf_delays.tcl
@ -1,5 +1,5 @@
 # sdf example
-read_liberty nangate45_slow.lib
+read_liberty nangate45_slow.lib.gz
 read_verilog example1.v
 link_design top
 read_sdf example1.sdf
--- a/examples/sky130hd_tt.lib
+++ b/examples/sky130hd_tt.lib
--- a/examples/sky130hd_tt.lib.gz
+++ b/examples/sky130hd_tt.lib.gz
--- a/examples/spef_parasitics.tcl
+++ b/examples/spef_parasitics.tcl
@ -1,5 +1,5 @@
 # delay calc with spef parasitics
-read_liberty nangate45_slow.lib
+read_liberty nangate45_slow.lib.gz
 read_verilog example1.v
 link_design top
 read_spef example1.dspef
--- a/test/verilog_attribute.tcl
+++ b/test/verilog_attribute.tcl
@ -1,5 +1,5 @@
 # Tests whether Verilog attributes can be parsed and retrieved correctly
-read_liberty ../examples/sky130hd_tt.lib
+read_liberty ../examples/sky130hd_tt.lib.gz
 read_verilog verilog_attribute.v
 link_design counter
 create_clock -name clk [get_ports clk] -period 50