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format fixes 

Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>
This commit is contained in:
Ethan Mahintorabi 2024-03-09 05:56:25 +00:00
parent 1fd97b479f
commit ad6f4cd3b1
No known key found for this signature in database
GPG Key ID: 824E41B920BEA252
9 changed files with 136 additions and 122 deletions
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3
include/sta/ConcreteLibrary.hh
View File

@ -106,7 +106,8 @@ public:
ConcreteCellPortBitIterator *portBitIterator() const; ConcreteCellPortBitIterator *portBitIterator() const;
bool isLeaf() const { return is_leaf_; } bool isLeaf() const { return is_leaf_; }
void setIsLeaf(bool is_leaf); void setIsLeaf(bool is_leaf);
void setAttribute(const char *key, const char *value); void setAttribute(const char *key,
const char *value);
const char *getAttribute(const char *key) const; const char *getAttribute(const char *key) const;
// Cell acts as port factory. // Cell acts as port factory.

17
include/sta/ConcreteNetwork.hh
View File

@ -75,7 +75,8 @@ public:
const PatternMatch *pattern) const override; const PatternMatch *pattern) const override;
const char *name(const Cell *cell) const override; const char *name(const Cell *cell) const override;
const char *getAttribute(const Cell *cell, const char *key) const override; const char *getAttribute(const Cell *cell,
const char *key) const override;
ObjectId id(const Cell *cell) const override; ObjectId id(const Cell *cell) const override;
Library *library(const Cell *cell) const override; Library *library(const Cell *cell) const override;
LibertyCell *libertyCell(Cell *cell) const override; LibertyCell *libertyCell(Cell *cell) const override;
@ -110,7 +111,8 @@ public:
PortMemberIterator *memberIterator(const Port *port) const override; PortMemberIterator *memberIterator(const Port *port) const override;
const char *name(const Instance *instance) const override; const char *name(const Instance *instance) const override;
const char *getAttribute(const Instance *inst, const char *key) const override; const char *getAttribute(const Instance *inst,
const char *key) const override;
ObjectId id(const Instance *instance) const override; ObjectId id(const Instance *instance) const override;
Cell *cell(const Instance *instance) const override; Cell *cell(const Instance *instance) const override;
Instance *parent(const Instance *instance) const override; Instance *parent(const Instance *instance) const override;
@ -179,8 +181,8 @@ public:
void setIsLeaf(Cell *cell, void setIsLeaf(Cell *cell,
bool is_leaf) override; bool is_leaf) override;
void setAttribute(Cell *cell, void setAttribute(Cell *cell,
const char *key, const char *key,
const char *value) override; const char *value) override;
Port *makePort(Cell *cell, Port *makePort(Cell *cell,
const char *name) override; const char *name) override;
Port *makeBusPort(Cell *cell, Port *makeBusPort(Cell *cell,
@ -213,8 +215,8 @@ public:
LibertyPort *port, LibertyPort *port,
Net *net) override; Net *net) override;
void setAttribute(Instance *inst, void setAttribute(Instance *inst,
const char *key, const char *key,
const char *value) override; const char *value) override;
void disconnectPin(Pin *pin) override; void disconnectPin(Pin *pin) override;
void deletePin(Pin *pin) override; void deletePin(Pin *pin) override;
Net *makeNet(const char *name, Net *makeNet(const char *name,
@ -294,7 +296,8 @@ public:
InstanceNetIterator *netIterator() const; InstanceNetIterator *netIterator() const;
Instance *findChild(const char *name) const; Instance *findChild(const char *name) const;
InstanceChildIterator *childIterator() const; InstanceChildIterator *childIterator() const;
void setAttribute(const char *key, const char *value); void setAttribute(const char *key,
const char *value);
const char *getAttribute(const char *key) const; const char *getAttribute(const char *key) const;
void addChild(ConcreteInstance *child); void addChild(ConcreteInstance *child);
void deleteChild(ConcreteInstance *child); void deleteChild(ConcreteInstance *child);

14
include/sta/Network.hh
View File

@ -145,7 +145,8 @@ public:
// Filename may return null. // Filename may return null.
virtual const char *filename(const Cell *cell) = 0; virtual const char *filename(const Cell *cell) = 0;
// Attributes can be null // Attributes can be null
virtual const char *getAttribute(const Cell *cell, const char *key) const = 0; virtual const char *getAttribute(const Cell *cell,
const char *key) const = 0;
// Name can be a simple, bundle, bus, or bus bit name. // Name can be a simple, bundle, bus, or bus bit name.
virtual Port *findPort(const Cell *cell, virtual Port *findPort(const Cell *cell,
const char *name) const = 0; const char *name) const = 0;
@ -208,7 +209,8 @@ public:
const PatternMatch *pattern) const; const PatternMatch *pattern) const;
virtual InstanceSeq findInstancesHierMatching(const Instance *instance, virtual InstanceSeq findInstancesHierMatching(const Instance *instance,
const PatternMatch *pattern) const; const PatternMatch *pattern) const;
virtual const char *getAttribute(const Instance *inst, const char *key) const = 0; virtual const char *getAttribute(const Instance *inst,
const char *key) const = 0;
// Hierarchical path name. // Hierarchical path name.
virtual const char *pathName(const Instance *instance) const; virtual const char *pathName(const Instance *instance) const;
bool pathNameLess(const Instance *inst1, bool pathNameLess(const Instance *inst1,
@ -548,11 +550,11 @@ public:
virtual void setIsLeaf(Cell *cell, virtual void setIsLeaf(Cell *cell,
bool is_leaf) = 0; bool is_leaf) = 0;
virtual void setAttribute(Cell *cell, virtual void setAttribute(Cell *cell,
const char *key, const char *key,
const char *value) = 0; const char *value) = 0;
virtual void setAttribute(Instance *instance, virtual void setAttribute(Instance *instance,
const char *key, const char *key,
const char *value) = 0; const char *value) = 0;
virtual Port *makePort(Cell *cell, virtual Port *makePort(Cell *cell,
const char *name) = 0; const char *name) = 0;
virtual Port *makeBusPort(Cell *cell, virtual Port *makeBusPort(Cell *cell,

6
include/sta/SdcNetwork.hh
View File

@ -45,7 +45,8 @@ public:
const PatternMatch *pattern) const override; const PatternMatch *pattern) const override;
const char *name(const Cell *cell) const override; const char *name(const Cell *cell) const override;
const char *getAttribute(const Cell *cell, const char* key) const override; const char *getAttribute(const Cell *cell,
const char* key) const override;
ObjectId id(const Cell *cell) const override; ObjectId id(const Cell *cell) const override;
Library *library(const Cell *cell) const override; Library *library(const Cell *cell) const override;
LibertyCell *libertyCell(Cell *cell) const override; LibertyCell *libertyCell(Cell *cell) const override;
@ -81,7 +82,8 @@ public:
bool hasMembers(const Port *port) const override; bool hasMembers(const Port *port) const override;
ObjectId id(const Instance *instance) const override; ObjectId id(const Instance *instance) const override;
const char *getAttribute(const Instance *inst, const char* key) const override; const char *getAttribute(const Instance *inst,
const char* key) const override;
Instance *topInstance() const override; Instance *topInstance() const override;
Cell *cell(const Instance *instance) const override; Cell *cell(const Instance *instance) const override;
Instance *parent(const Instance *instance) const override; Instance *parent(const Instance *instance) const override;

3
network/ConcreteLibrary.cc
View File

@ -270,7 +270,8 @@ ConcreteCell::setIsLeaf(bool is_leaf)
} }
void void
ConcreteCell::setAttribute(const char* key, const char* value) ConcreteCell::setAttribute(const char* key,
const char* value)
{ {
attribute_map_.insert(key, stringCopy(value)); attribute_map_.insert(key, stringCopy(value));
} }

17
network/ConcreteNetwork.cc
View File

@ -559,8 +559,8 @@ ConcreteNetwork::setIsLeaf(Cell *cell,
void void
ConcreteNetwork::setAttribute(Cell *cell, ConcreteNetwork::setAttribute(Cell *cell,
const char *key, const char *key,
const char *value) const char *value)
{ {
ConcreteCell *ccell = reinterpret_cast<ConcreteCell*>(cell); ConcreteCell *ccell = reinterpret_cast<ConcreteCell*>(cell);
ccell->setAttribute(key, value); ccell->setAttribute(key, value);
@ -607,7 +607,8 @@ ConcreteNetwork::filename(const Cell *cell)
} }
const char * const char *
ConcreteNetwork::getAttribute(const Cell *cell, const char *key) const ConcreteNetwork::getAttribute(const Cell *cell,
const char *key) const
{ {
const ConcreteCell *ccell = reinterpret_cast<const ConcreteCell*>(cell); const ConcreteCell *ccell = reinterpret_cast<const ConcreteCell*>(cell);
return ccell->getAttribute(key); return ccell->getAttribute(key);
@ -938,7 +939,8 @@ ConcreteNetwork::id(const Instance *instance) const
} }
const char * const char *
ConcreteNetwork::getAttribute(const Instance *inst, const char *key) const ConcreteNetwork::getAttribute(const Instance *inst,
const char *key) const
{ {
const ConcreteInstance *cinst = reinterpret_cast<const ConcreteInstance*>(inst); const ConcreteInstance *cinst = reinterpret_cast<const ConcreteInstance*>(inst);
return cinst->getAttribute(key); return cinst->getAttribute(key);
@ -1350,8 +1352,8 @@ ConcreteNetwork::connect(Instance *inst,
void void
ConcreteNetwork::setAttribute(Instance *inst, ConcreteNetwork::setAttribute(Instance *inst,
const char *key, const char *key,
const char *value) const char *value)
{ {
ConcreteInstance *cinst = reinterpret_cast<ConcreteInstance*>(inst); ConcreteInstance *cinst = reinterpret_cast<ConcreteInstance*>(inst);
cinst->setAttribute(key, value); cinst->setAttribute(key, value);
@ -1682,7 +1684,8 @@ ConcreteInstance::childIterator() const
} }
void void
ConcreteInstance::setAttribute(const char *key, const char *value) ConcreteInstance::setAttribute(const char *key,
const char *value)
{ {
attribute_map_.insert(key, stringCopy(value)); attribute_map_.insert(key, stringCopy(value));
} }

3
network/SdcNetwork.cc
View File

@ -123,7 +123,8 @@ NetworkNameAdapter::id(const Cell *cell) const
} }
const char * const char *
NetworkNameAdapter::getAttribute(const Cell *cell, const char *key) const NetworkNameAdapter::getAttribute(const Cell *cell,
const char *key) const
{ {
return network_->getAttribute(cell, key); return network_->getAttribute(cell, key);
} }

72
verilog/VerilogReader.cc
View File

@ -545,10 +545,10 @@ VerilogReader::makeAssign(VerilogNet *lhs,
VerilogInst * VerilogInst *
VerilogReader::makeModuleInst(const char *module_vname, VerilogReader::makeModuleInst(const char *module_vname,
const char *inst_vname, const char *inst_vname,
VerilogNetSeq *pins, VerilogNetSeq *pins,
VerilogAttributeStmtSeq* attribute_stmts, VerilogAttributeStmtSeq* attribute_stmts,
const int line) const int line)
{ {
string module_name = moduleVerilogToSta(module_vname); string module_name = moduleVerilogToSta(module_vname);
string inst_name = instanceVerilogToSta(inst_vname); string inst_name = instanceVerilogToSta(inst_vname);
@ -836,12 +836,12 @@ VerilogReader::netVerilogName(const char *net_name)
//////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////
VerilogModule::VerilogModule(const char *name, VerilogModule::VerilogModule(const char *name,
VerilogNetSeq *ports, VerilogNetSeq *ports,
VerilogStmtSeq *stmts, VerilogStmtSeq *stmts,
VerilogAttributeStmtSeq *attribute_stmts, VerilogAttributeStmtSeq *attribute_stmts,
const char *filename, const char *filename,
int line, int line,
VerilogReader *reader) : VerilogReader *reader) :
VerilogStmt(line), VerilogStmt(line),
name_(stringCopy(name)), name_(stringCopy(name)),
filename_(filename), filename_(filename),
@ -959,7 +959,7 @@ VerilogStmt::VerilogStmt(int line) :
} }
VerilogInst::VerilogInst(const char *inst_name, VerilogInst::VerilogInst(const char *inst_name,
VerilogAttributeStmtSeq* attribute_stmts, VerilogAttributeStmtSeq* attribute_stmts,
const int line) : const int line) :
VerilogStmt(line), VerilogStmt(line),
inst_name_(stringCopy(inst_name)), inst_name_(stringCopy(inst_name)),
@ -982,10 +982,10 @@ VerilogInst::setInstanceName(const char *inst_name)
} }
VerilogModuleInst::VerilogModuleInst(const char *module_name, VerilogModuleInst::VerilogModuleInst(const char *module_name,
const char *inst_name, const char *inst_name,
VerilogNetSeq *pins, VerilogNetSeq *pins,
VerilogAttributeStmtSeq* attribute_stmts, VerilogAttributeStmtSeq* attribute_stmts,
int line) : int line) :
VerilogInst(inst_name, attribute_stmts, line), VerilogInst(inst_name, attribute_stmts, line),
module_name_(stringCopy(module_name)), module_name_(stringCopy(module_name)),
pins_(pins) pins_(pins)
@ -1018,10 +1018,10 @@ VerilogModuleInst::namedPins()
} }
VerilogLibertyInst::VerilogLibertyInst(LibertyCell *cell, VerilogLibertyInst::VerilogLibertyInst(LibertyCell *cell,
const char *inst_name, const char *inst_name,
const char **net_names, const char **net_names,
VerilogAttributeStmtSeq* attribute_stmts, VerilogAttributeStmtSeq* attribute_stmts,
const int line) : const int line) :
VerilogInst(inst_name, attribute_stmts, line), VerilogInst(inst_name, attribute_stmts, line),
cell_(cell), cell_(cell),
net_names_(net_names) net_names_(net_names)
@ -1041,9 +1041,9 @@ VerilogLibertyInst::~VerilogLibertyInst()
} }
VerilogDcl::VerilogDcl(PortDirection *dir, VerilogDcl::VerilogDcl(PortDirection *dir,
VerilogDclArgSeq *args, VerilogDclArgSeq *args,
VerilogAttributeStmtSeq* attribute_stmts, VerilogAttributeStmtSeq* attribute_stmts,
int line) : int line) :
VerilogStmt(line), VerilogStmt(line),
dir_(dir), dir_(dir),
args_(args), args_(args),
@ -1052,9 +1052,9 @@ VerilogDcl::VerilogDcl(PortDirection *dir,
} }
VerilogDcl::VerilogDcl(PortDirection *dir, VerilogDcl::VerilogDcl(PortDirection *dir,
VerilogDclArg *arg, VerilogDclArg *arg,
VerilogAttributeStmtSeq* attribute_stmts, VerilogAttributeStmtSeq* attribute_stmts,
int line) : int line) :
VerilogStmt(line), VerilogStmt(line),
dir_(dir) dir_(dir)
{ {
@ -1084,11 +1084,11 @@ VerilogDcl::portName()
} }
VerilogDclBus::VerilogDclBus(PortDirection *dir, VerilogDclBus::VerilogDclBus(PortDirection *dir,
int from_index, int from_index,
int to_index, int to_index,
VerilogDclArgSeq *args, VerilogDclArgSeq *args,
VerilogAttributeStmtSeq* attribute_stmts, VerilogAttributeStmtSeq* attribute_stmts,
int line) : int line) :
VerilogDcl(dir, args, attribute_stmts, line), VerilogDcl(dir, args, attribute_stmts, line),
from_index_(from_index), from_index_(from_index),
to_index_(to_index) to_index_(to_index)
@ -1096,11 +1096,11 @@ VerilogDclBus::VerilogDclBus(PortDirection *dir,
} }
VerilogDclBus::VerilogDclBus(PortDirection *dir, VerilogDclBus::VerilogDclBus(PortDirection *dir,
int from_index, int from_index,
int to_index, int to_index,
VerilogDclArg *arg, VerilogDclArg *arg,
VerilogAttributeStmtSeq* attribute_stmts, VerilogAttributeStmtSeq* attribute_stmts,
int line) : int line) :
VerilogDcl(dir, arg, attribute_stmts, line), VerilogDcl(dir, arg, attribute_stmts, line),
from_index_(from_index), from_index_(from_index),
to_index_(to_index) to_index_(to_index)
@ -1740,7 +1740,7 @@ VerilogNetPortRefPart::name() const
} }
VerilogAttributeEntry::VerilogAttributeEntry(const char *key, VerilogAttributeEntry::VerilogAttributeEntry(const char *key,
const char * value) : const char * value) :
key_(key), key_(key),
value_(value) value_(value)
{ {

123
verilog/VerilogReaderPvt.hh
View File

@ -91,42 +91,42 @@ public:
int &result, int &result,
size_t max_size); size_t max_size);
void makeModule(const char *module_name, void makeModule(const char *module_name,
VerilogNetSeq *ports, VerilogNetSeq *ports,
VerilogStmtSeq *stmts, VerilogStmtSeq *stmts,
VerilogAttributeStmtSeq *attribute_stmts, VerilogAttributeStmtSeq *attribute_stmts,
int line); int line);
void makeModule(const char *module_name, void makeModule(const char *module_name,
VerilogStmtSeq *port_dcls, VerilogStmtSeq *port_dcls,
VerilogStmtSeq *stmts, VerilogStmtSeq *stmts,
VerilogAttributeStmtSeq *attribute_stmts, VerilogAttributeStmtSeq *attribute_stmts,
int line); int line);
VerilogDcl *makeDcl(PortDirection *dir, VerilogDcl *makeDcl(PortDirection *dir,
VerilogDclArgSeq *args, VerilogDclArgSeq *args,
VerilogAttributeStmtSeq* attribute_stmts, VerilogAttributeStmtSeq* attribute_stmts,
int line); int line);
VerilogDcl *makeDcl(PortDirection *dir, VerilogDcl *makeDcl(PortDirection *dir,
VerilogDclArg *arg, VerilogDclArg *arg,
VerilogAttributeStmtSeq* attribute_stmts, VerilogAttributeStmtSeq* attribute_stmts,
int line); int line);
VerilogDclArg *makeDclArg(const char *net_name); VerilogDclArg *makeDclArg(const char *net_name);
VerilogDclArg*makeDclArg(VerilogAssign *assign); VerilogDclArg*makeDclArg(VerilogAssign *assign);
VerilogDclBus *makeDclBus(PortDirection *dir, VerilogDclBus *makeDclBus(PortDirection *dir,
int from_index, int from_index,
int to_index, int to_index,
VerilogDclArg *arg, VerilogDclArg *arg,
VerilogAttributeStmtSeq* attribute_stmts, VerilogAttributeStmtSeq* attribute_stmts,
int line); int line);
VerilogDclBus *makeDclBus(PortDirection *dir, VerilogDclBus *makeDclBus(PortDirection *dir,
int from_index, int from_index,
int to_index, int to_index,
VerilogDclArgSeq *args, VerilogDclArgSeq *args,
VerilogAttributeStmtSeq* attribute_stmts, VerilogAttributeStmtSeq* attribute_stmts,
int line); int line);
VerilogInst *makeModuleInst(const char *module_name, VerilogInst *makeModuleInst(const char *module_name,
const char *inst_name, const char *inst_name,
VerilogNetSeq *pins, VerilogNetSeq *pins,
VerilogAttributeStmtSeq* attribute_stmts, VerilogAttributeStmtSeq* attribute_stmts,
const int line); const int line);
VerilogAssign *makeAssign(VerilogNet *lhs, VerilogAssign *makeAssign(VerilogNet *lhs,
VerilogNet *rhs, VerilogNet *rhs,
int line); int line);
@ -337,12 +337,12 @@ class VerilogModule : public VerilogStmt
{ {
public: public:
VerilogModule(const char *name, VerilogModule(const char *name,
VerilogNetSeq *ports, VerilogNetSeq *ports,
VerilogStmtSeq *stmts, VerilogStmtSeq *stmts,
VerilogAttributeStmtSeq *attribute_stmts, VerilogAttributeStmtSeq *attribute_stmts,
const char *filename, const char *filename,
int line, int line,
VerilogReader *reader); VerilogReader *reader);
virtual ~VerilogModule(); virtual ~VerilogModule();
const char *name() { return name_; } const char *name() { return name_; }
const char *filename() { return filename_; } const char *filename() { return filename_; }
@ -372,13 +372,13 @@ class VerilogDcl : public VerilogStmt
{ {
public: public:
VerilogDcl(PortDirection *dir, VerilogDcl(PortDirection *dir,
VerilogDclArgSeq *args, VerilogDclArgSeq *args,
VerilogAttributeStmtSeq *attribute_stmts, VerilogAttributeStmtSeq *attribute_stmts,
int line); int line);
VerilogDcl(PortDirection *dir, VerilogDcl(PortDirection *dir,
VerilogDclArg *arg, VerilogDclArg *arg,
VerilogAttributeStmtSeq *attribute_stmts, VerilogAttributeStmtSeq *attribute_stmts,
int line); int line);
virtual ~VerilogDcl(); virtual ~VerilogDcl();
const char *portName(); const char *portName();
virtual bool isBus() const { return false; } virtual bool isBus() const { return false; }
@ -399,17 +399,17 @@ class VerilogDclBus : public VerilogDcl
{ {
public: public:
VerilogDclBus(PortDirection *dir, VerilogDclBus(PortDirection *dir,
int from_index, int from_index,
int to_index, int to_index,
VerilogDclArgSeq *args, VerilogDclArgSeq *args,
VerilogAttributeStmtSeq* attribute_stmts, VerilogAttributeStmtSeq* attribute_stmts,
int line); int line);
VerilogDclBus(PortDirection *dir, VerilogDclBus(PortDirection *dir,
int from_index, int from_index,
int to_index, int to_index,
VerilogDclArg *arg, VerilogDclArg *arg,
VerilogAttributeStmtSeq* attribute_stmts, VerilogAttributeStmtSeq* attribute_stmts,
int line); int line);
virtual bool isBus() const { return true; } virtual bool isBus() const { return true; }
int fromIndex() const { return from_index_; } int fromIndex() const { return from_index_; }
int toIndex() const { return to_index_; } int toIndex() const { return to_index_; }
@ -456,8 +456,8 @@ class VerilogInst : public VerilogStmt
{ {
public: public:
VerilogInst(const char *inst_name, VerilogInst(const char *inst_name,
VerilogAttributeStmtSeq* attribute_stmts, VerilogAttributeStmtSeq* attribute_stmts,
const int line); const int line);
virtual ~VerilogInst(); virtual ~VerilogInst();
virtual bool isInstance() const { return true; } virtual bool isInstance() const { return true; }
const char *instanceName() const { return inst_name_; } const char *instanceName() const { return inst_name_; }
@ -473,10 +473,10 @@ class VerilogModuleInst : public VerilogInst
{ {
public: public:
VerilogModuleInst(const char *module_name, VerilogModuleInst(const char *module_name,
const char *inst_name, const char *inst_name,
VerilogNetSeq *pins, VerilogNetSeq *pins,
VerilogAttributeStmtSeq* attribute_stmts, VerilogAttributeStmtSeq* attribute_stmts,
const int line); const int line);
virtual ~VerilogModuleInst(); virtual ~VerilogModuleInst();
virtual bool isModuleInst() const { return true; } virtual bool isModuleInst() const { return true; }
const char *moduleName() const { return module_name_; } const char *moduleName() const { return module_name_; }
@ -496,10 +496,10 @@ class VerilogLibertyInst : public VerilogInst
{ {
public: public:
VerilogLibertyInst(LibertyCell *cell, VerilogLibertyInst(LibertyCell *cell,
const char *inst_name, const char *inst_name,
const char **net_names, const char **net_names,
VerilogAttributeStmtSeq* attribute_stmts, VerilogAttributeStmtSeq* attribute_stmts,
const int line); const int line);
virtual ~VerilogLibertyInst(); virtual ~VerilogLibertyInst();
virtual bool isLibertyInst() const { return true; } virtual bool isLibertyInst() const { return true; }
LibertyCell *cell() const { return cell_; } LibertyCell *cell() const { return cell_; }
@ -729,7 +729,8 @@ private:
class VerilogAttributeEntry class VerilogAttributeEntry
{ {
public: public:
VerilogAttributeEntry(const char *key, const char *value); VerilogAttributeEntry(const char *key,
const char *value);
virtual const char *key(); virtual const char *key();
virtual const char *value(); virtual const char *value();
virtual ~VerilogAttributeEntry(); virtual ~VerilogAttributeEntry();