diff --git a/include/sta/ConcreteLibrary.hh b/include/sta/ConcreteLibrary.hh index 78b3a596..ab196e65 100644 --- a/include/sta/ConcreteLibrary.hh +++ b/include/sta/ConcreteLibrary.hh @@ -106,7 +106,8 @@ public: ConcreteCellPortBitIterator *portBitIterator() const; bool isLeaf() const { return is_leaf_; } void setIsLeaf(bool is_leaf); - void setAttribute(const char *key, const char *value); + void setAttribute(const char *key, + const char *value); const char *getAttribute(const char *key) const; // Cell acts as port factory. diff --git a/include/sta/ConcreteNetwork.hh b/include/sta/ConcreteNetwork.hh index d8856611..60671780 100644 --- a/include/sta/ConcreteNetwork.hh +++ b/include/sta/ConcreteNetwork.hh @@ -75,7 +75,8 @@ public: const PatternMatch *pattern) const override; const char *name(const Cell *cell) const override; - const char *getAttribute(const Cell *cell, const char *key) const override; + const char *getAttribute(const Cell *cell, + const char *key) const override; ObjectId id(const Cell *cell) const override; Library *library(const Cell *cell) const override; LibertyCell *libertyCell(Cell *cell) const override; @@ -110,7 +111,8 @@ public: PortMemberIterator *memberIterator(const Port *port) const override; const char *name(const Instance *instance) const override; - const char *getAttribute(const Instance *inst, const char *key) const override; + const char *getAttribute(const Instance *inst, + const char *key) const override; ObjectId id(const Instance *instance) const override; Cell *cell(const Instance *instance) const override; Instance *parent(const Instance *instance) const override; @@ -179,8 +181,8 @@ public: void setIsLeaf(Cell *cell, bool is_leaf) override; void setAttribute(Cell *cell, - const char *key, - const char *value) override; + const char *key, + const char *value) override; Port *makePort(Cell *cell, const char *name) override; Port *makeBusPort(Cell *cell, @@ -213,8 +215,8 @@ public: LibertyPort *port, Net *net) override; void setAttribute(Instance *inst, - const char *key, - const char *value) override; + const char *key, + const char *value) override; void disconnectPin(Pin *pin) override; void deletePin(Pin *pin) override; Net *makeNet(const char *name, @@ -294,7 +296,8 @@ public: InstanceNetIterator *netIterator() const; Instance *findChild(const char *name) const; InstanceChildIterator *childIterator() const; - void setAttribute(const char *key, const char *value); + void setAttribute(const char *key, + const char *value); const char *getAttribute(const char *key) const; void addChild(ConcreteInstance *child); void deleteChild(ConcreteInstance *child); diff --git a/include/sta/Network.hh b/include/sta/Network.hh index da982c09..6b67f7dd 100644 --- a/include/sta/Network.hh +++ b/include/sta/Network.hh @@ -145,7 +145,8 @@ public: // Filename may return null. virtual const char *filename(const Cell *cell) = 0; // Attributes can be null - virtual const char *getAttribute(const Cell *cell, const char *key) const = 0; + virtual const char *getAttribute(const Cell *cell, + const char *key) const = 0; // Name can be a simple, bundle, bus, or bus bit name. virtual Port *findPort(const Cell *cell, const char *name) const = 0; @@ -208,7 +209,8 @@ public: const PatternMatch *pattern) const; virtual InstanceSeq findInstancesHierMatching(const Instance *instance, const PatternMatch *pattern) const; - virtual const char *getAttribute(const Instance *inst, const char *key) const = 0; + virtual const char *getAttribute(const Instance *inst, + const char *key) const = 0; // Hierarchical path name. virtual const char *pathName(const Instance *instance) const; bool pathNameLess(const Instance *inst1, @@ -548,11 +550,11 @@ public: virtual void setIsLeaf(Cell *cell, bool is_leaf) = 0; virtual void setAttribute(Cell *cell, - const char *key, - const char *value) = 0; + const char *key, + const char *value) = 0; virtual void setAttribute(Instance *instance, - const char *key, - const char *value) = 0; + const char *key, + const char *value) = 0; virtual Port *makePort(Cell *cell, const char *name) = 0; virtual Port *makeBusPort(Cell *cell, diff --git a/include/sta/SdcNetwork.hh b/include/sta/SdcNetwork.hh index fcc98f99..58abad29 100644 --- a/include/sta/SdcNetwork.hh +++ b/include/sta/SdcNetwork.hh @@ -45,7 +45,8 @@ public: const PatternMatch *pattern) const override; const char *name(const Cell *cell) const override; - const char *getAttribute(const Cell *cell, const char* key) const override; + const char *getAttribute(const Cell *cell, + const char* key) const override; ObjectId id(const Cell *cell) const override; Library *library(const Cell *cell) const override; LibertyCell *libertyCell(Cell *cell) const override; @@ -81,7 +82,8 @@ public: bool hasMembers(const Port *port) const override; ObjectId id(const Instance *instance) const override; - const char *getAttribute(const Instance *inst, const char* key) const override; + const char *getAttribute(const Instance *inst, + const char* key) const override; Instance *topInstance() const override; Cell *cell(const Instance *instance) const override; Instance *parent(const Instance *instance) const override; diff --git a/network/ConcreteLibrary.cc b/network/ConcreteLibrary.cc index 53402990..6195708e 100644 --- a/network/ConcreteLibrary.cc +++ b/network/ConcreteLibrary.cc @@ -270,7 +270,8 @@ ConcreteCell::setIsLeaf(bool is_leaf) } void -ConcreteCell::setAttribute(const char* key, const char* value) +ConcreteCell::setAttribute(const char* key, + const char* value) { attribute_map_.insert(key, stringCopy(value)); } diff --git a/network/ConcreteNetwork.cc b/network/ConcreteNetwork.cc index a8e580d4..7bd3e611 100644 --- a/network/ConcreteNetwork.cc +++ b/network/ConcreteNetwork.cc @@ -559,8 +559,8 @@ ConcreteNetwork::setIsLeaf(Cell *cell, void ConcreteNetwork::setAttribute(Cell *cell, - const char *key, - const char *value) + const char *key, + const char *value) { ConcreteCell *ccell = reinterpret_cast(cell); ccell->setAttribute(key, value); @@ -607,7 +607,8 @@ ConcreteNetwork::filename(const Cell *cell) } const char * -ConcreteNetwork::getAttribute(const Cell *cell, const char *key) const +ConcreteNetwork::getAttribute(const Cell *cell, + const char *key) const { const ConcreteCell *ccell = reinterpret_cast(cell); return ccell->getAttribute(key); @@ -938,7 +939,8 @@ ConcreteNetwork::id(const Instance *instance) const } const char * -ConcreteNetwork::getAttribute(const Instance *inst, const char *key) const +ConcreteNetwork::getAttribute(const Instance *inst, + const char *key) const { const ConcreteInstance *cinst = reinterpret_cast(inst); return cinst->getAttribute(key); @@ -1350,8 +1352,8 @@ ConcreteNetwork::connect(Instance *inst, void ConcreteNetwork::setAttribute(Instance *inst, - const char *key, - const char *value) + const char *key, + const char *value) { ConcreteInstance *cinst = reinterpret_cast(inst); cinst->setAttribute(key, value); @@ -1682,7 +1684,8 @@ ConcreteInstance::childIterator() const } void -ConcreteInstance::setAttribute(const char *key, const char *value) +ConcreteInstance::setAttribute(const char *key, + const char *value) { attribute_map_.insert(key, stringCopy(value)); } diff --git a/network/SdcNetwork.cc b/network/SdcNetwork.cc index b83beb21..7b0ae729 100644 --- a/network/SdcNetwork.cc +++ b/network/SdcNetwork.cc @@ -123,7 +123,8 @@ NetworkNameAdapter::id(const Cell *cell) const } const char * -NetworkNameAdapter::getAttribute(const Cell *cell, const char *key) const +NetworkNameAdapter::getAttribute(const Cell *cell, + const char *key) const { return network_->getAttribute(cell, key); } diff --git a/verilog/VerilogReader.cc b/verilog/VerilogReader.cc index b7e4a763..3d3cd76e 100644 --- a/verilog/VerilogReader.cc +++ b/verilog/VerilogReader.cc @@ -545,10 +545,10 @@ VerilogReader::makeAssign(VerilogNet *lhs, VerilogInst * VerilogReader::makeModuleInst(const char *module_vname, - const char *inst_vname, - VerilogNetSeq *pins, - VerilogAttributeStmtSeq* attribute_stmts, - const int line) + const char *inst_vname, + VerilogNetSeq *pins, + VerilogAttributeStmtSeq* attribute_stmts, + const int line) { string module_name = moduleVerilogToSta(module_vname); string inst_name = instanceVerilogToSta(inst_vname); @@ -836,12 +836,12 @@ VerilogReader::netVerilogName(const char *net_name) //////////////////////////////////////////////////////////////// VerilogModule::VerilogModule(const char *name, - VerilogNetSeq *ports, - VerilogStmtSeq *stmts, - VerilogAttributeStmtSeq *attribute_stmts, - const char *filename, - int line, - VerilogReader *reader) : + VerilogNetSeq *ports, + VerilogStmtSeq *stmts, + VerilogAttributeStmtSeq *attribute_stmts, + const char *filename, + int line, + VerilogReader *reader) : VerilogStmt(line), name_(stringCopy(name)), filename_(filename), @@ -959,7 +959,7 @@ VerilogStmt::VerilogStmt(int line) : } VerilogInst::VerilogInst(const char *inst_name, - VerilogAttributeStmtSeq* attribute_stmts, + VerilogAttributeStmtSeq* attribute_stmts, const int line) : VerilogStmt(line), inst_name_(stringCopy(inst_name)), @@ -982,10 +982,10 @@ VerilogInst::setInstanceName(const char *inst_name) } VerilogModuleInst::VerilogModuleInst(const char *module_name, - const char *inst_name, - VerilogNetSeq *pins, - VerilogAttributeStmtSeq* attribute_stmts, - int line) : + const char *inst_name, + VerilogNetSeq *pins, + VerilogAttributeStmtSeq* attribute_stmts, + int line) : VerilogInst(inst_name, attribute_stmts, line), module_name_(stringCopy(module_name)), pins_(pins) @@ -1018,10 +1018,10 @@ VerilogModuleInst::namedPins() } VerilogLibertyInst::VerilogLibertyInst(LibertyCell *cell, - const char *inst_name, - const char **net_names, - VerilogAttributeStmtSeq* attribute_stmts, - const int line) : + const char *inst_name, + const char **net_names, + VerilogAttributeStmtSeq* attribute_stmts, + const int line) : VerilogInst(inst_name, attribute_stmts, line), cell_(cell), net_names_(net_names) @@ -1041,9 +1041,9 @@ VerilogLibertyInst::~VerilogLibertyInst() } VerilogDcl::VerilogDcl(PortDirection *dir, - VerilogDclArgSeq *args, - VerilogAttributeStmtSeq* attribute_stmts, - int line) : + VerilogDclArgSeq *args, + VerilogAttributeStmtSeq* attribute_stmts, + int line) : VerilogStmt(line), dir_(dir), args_(args), @@ -1052,9 +1052,9 @@ VerilogDcl::VerilogDcl(PortDirection *dir, } VerilogDcl::VerilogDcl(PortDirection *dir, - VerilogDclArg *arg, - VerilogAttributeStmtSeq* attribute_stmts, - int line) : + VerilogDclArg *arg, + VerilogAttributeStmtSeq* attribute_stmts, + int line) : VerilogStmt(line), dir_(dir) { @@ -1084,11 +1084,11 @@ VerilogDcl::portName() } VerilogDclBus::VerilogDclBus(PortDirection *dir, - int from_index, - int to_index, - VerilogDclArgSeq *args, - VerilogAttributeStmtSeq* attribute_stmts, - int line) : + int from_index, + int to_index, + VerilogDclArgSeq *args, + VerilogAttributeStmtSeq* attribute_stmts, + int line) : VerilogDcl(dir, args, attribute_stmts, line), from_index_(from_index), to_index_(to_index) @@ -1096,11 +1096,11 @@ VerilogDclBus::VerilogDclBus(PortDirection *dir, } VerilogDclBus::VerilogDclBus(PortDirection *dir, - int from_index, - int to_index, - VerilogDclArg *arg, - VerilogAttributeStmtSeq* attribute_stmts, - int line) : + int from_index, + int to_index, + VerilogDclArg *arg, + VerilogAttributeStmtSeq* attribute_stmts, + int line) : VerilogDcl(dir, arg, attribute_stmts, line), from_index_(from_index), to_index_(to_index) @@ -1740,7 +1740,7 @@ VerilogNetPortRefPart::name() const } VerilogAttributeEntry::VerilogAttributeEntry(const char *key, - const char * value) : + const char * value) : key_(key), value_(value) { diff --git a/verilog/VerilogReaderPvt.hh b/verilog/VerilogReaderPvt.hh index 04e30a1f..5d88b55b 100644 --- a/verilog/VerilogReaderPvt.hh +++ b/verilog/VerilogReaderPvt.hh @@ -91,42 +91,42 @@ public: int &result, size_t max_size); void makeModule(const char *module_name, - VerilogNetSeq *ports, - VerilogStmtSeq *stmts, - VerilogAttributeStmtSeq *attribute_stmts, - int line); + VerilogNetSeq *ports, + VerilogStmtSeq *stmts, + VerilogAttributeStmtSeq *attribute_stmts, + int line); void makeModule(const char *module_name, - VerilogStmtSeq *port_dcls, - VerilogStmtSeq *stmts, - VerilogAttributeStmtSeq *attribute_stmts, - int line); + VerilogStmtSeq *port_dcls, + VerilogStmtSeq *stmts, + VerilogAttributeStmtSeq *attribute_stmts, + int line); VerilogDcl *makeDcl(PortDirection *dir, - VerilogDclArgSeq *args, - VerilogAttributeStmtSeq* attribute_stmts, - int line); + VerilogDclArgSeq *args, + VerilogAttributeStmtSeq* attribute_stmts, + int line); VerilogDcl *makeDcl(PortDirection *dir, - VerilogDclArg *arg, - VerilogAttributeStmtSeq* attribute_stmts, - int line); + VerilogDclArg *arg, + VerilogAttributeStmtSeq* attribute_stmts, + int line); VerilogDclArg *makeDclArg(const char *net_name); VerilogDclArg*makeDclArg(VerilogAssign *assign); VerilogDclBus *makeDclBus(PortDirection *dir, - int from_index, - int to_index, - VerilogDclArg *arg, - VerilogAttributeStmtSeq* attribute_stmts, - int line); + int from_index, + int to_index, + VerilogDclArg *arg, + VerilogAttributeStmtSeq* attribute_stmts, + int line); VerilogDclBus *makeDclBus(PortDirection *dir, - int from_index, - int to_index, - VerilogDclArgSeq *args, - VerilogAttributeStmtSeq* attribute_stmts, - int line); + int from_index, + int to_index, + VerilogDclArgSeq *args, + VerilogAttributeStmtSeq* attribute_stmts, + int line); VerilogInst *makeModuleInst(const char *module_name, - const char *inst_name, - VerilogNetSeq *pins, - VerilogAttributeStmtSeq* attribute_stmts, - const int line); + const char *inst_name, + VerilogNetSeq *pins, + VerilogAttributeStmtSeq* attribute_stmts, + const int line); VerilogAssign *makeAssign(VerilogNet *lhs, VerilogNet *rhs, int line); @@ -337,12 +337,12 @@ class VerilogModule : public VerilogStmt { public: VerilogModule(const char *name, - VerilogNetSeq *ports, - VerilogStmtSeq *stmts, - VerilogAttributeStmtSeq *attribute_stmts, - const char *filename, - int line, - VerilogReader *reader); + VerilogNetSeq *ports, + VerilogStmtSeq *stmts, + VerilogAttributeStmtSeq *attribute_stmts, + const char *filename, + int line, + VerilogReader *reader); virtual ~VerilogModule(); const char *name() { return name_; } const char *filename() { return filename_; } @@ -372,13 +372,13 @@ class VerilogDcl : public VerilogStmt { public: VerilogDcl(PortDirection *dir, - VerilogDclArgSeq *args, - VerilogAttributeStmtSeq *attribute_stmts, - int line); + VerilogDclArgSeq *args, + VerilogAttributeStmtSeq *attribute_stmts, + int line); VerilogDcl(PortDirection *dir, - VerilogDclArg *arg, - VerilogAttributeStmtSeq *attribute_stmts, - int line); + VerilogDclArg *arg, + VerilogAttributeStmtSeq *attribute_stmts, + int line); virtual ~VerilogDcl(); const char *portName(); virtual bool isBus() const { return false; } @@ -399,17 +399,17 @@ class VerilogDclBus : public VerilogDcl { public: VerilogDclBus(PortDirection *dir, - int from_index, - int to_index, - VerilogDclArgSeq *args, - VerilogAttributeStmtSeq* attribute_stmts, - int line); + int from_index, + int to_index, + VerilogDclArgSeq *args, + VerilogAttributeStmtSeq* attribute_stmts, + int line); VerilogDclBus(PortDirection *dir, - int from_index, - int to_index, - VerilogDclArg *arg, - VerilogAttributeStmtSeq* attribute_stmts, - int line); + int from_index, + int to_index, + VerilogDclArg *arg, + VerilogAttributeStmtSeq* attribute_stmts, + int line); virtual bool isBus() const { return true; } int fromIndex() const { return from_index_; } int toIndex() const { return to_index_; } @@ -456,8 +456,8 @@ class VerilogInst : public VerilogStmt { public: VerilogInst(const char *inst_name, - VerilogAttributeStmtSeq* attribute_stmts, - const int line); + VerilogAttributeStmtSeq* attribute_stmts, + const int line); virtual ~VerilogInst(); virtual bool isInstance() const { return true; } const char *instanceName() const { return inst_name_; } @@ -473,10 +473,10 @@ class VerilogModuleInst : public VerilogInst { public: VerilogModuleInst(const char *module_name, - const char *inst_name, - VerilogNetSeq *pins, - VerilogAttributeStmtSeq* attribute_stmts, - const int line); + const char *inst_name, + VerilogNetSeq *pins, + VerilogAttributeStmtSeq* attribute_stmts, + const int line); virtual ~VerilogModuleInst(); virtual bool isModuleInst() const { return true; } const char *moduleName() const { return module_name_; } @@ -496,10 +496,10 @@ class VerilogLibertyInst : public VerilogInst { public: VerilogLibertyInst(LibertyCell *cell, - const char *inst_name, - const char **net_names, - VerilogAttributeStmtSeq* attribute_stmts, - const int line); + const char *inst_name, + const char **net_names, + VerilogAttributeStmtSeq* attribute_stmts, + const int line); virtual ~VerilogLibertyInst(); virtual bool isLibertyInst() const { return true; } LibertyCell *cell() const { return cell_; } @@ -729,7 +729,8 @@ private: class VerilogAttributeEntry { public: - VerilogAttributeEntry(const char *key, const char *value); + VerilogAttributeEntry(const char *key, + const char *value); virtual const char *key(); virtual const char *value(); virtual ~VerilogAttributeEntry();