message ids

Signed-off-by: James Cherry <cherry@parallaxsw.com>

dcalc/LumpedCapDelayCalc.cc

@@ -142,8 +142,10 @@ LumpedCapDelayCalc::gateDelay(const Pin *drvr_pin,
     float gate_delay, drvr_slew;
     float in_slew1 = delayAsFloat(in_slew);
     // NaNs cause seg faults during table lookup.
-    if (std::isnan(load_cap) || std::isnan(in_slew.mean()))
-      report_->error(1350, "gate delay input variable is NaN");
+    if (std::isnan(load_cap))
+      report_->error(1350, "gate delay load cap is NaN");
+    if (std::isnan(in_slew.mean()))
+      report_->error(1351, "gate delay input slew is NaN");
     const Pvt *pvt = pinPvt(drvr_pin, scene, min_max);
     model->gateDelay(pvt, in_slew1, load_cap, gate_delay, drvr_slew);
 

search/MakeTimingModel.cc

@@ -231,7 +231,7 @@ MakeTimingModel::checkClock(Clock *clk)
 {
   for (const Pin *pin : clk->leafPins()) {
     if (!network_->isTopLevelPort(pin))
-      report_->warn(1355, "clock {} pin {} is inside model block.", clk->name(),
+      report_->warn(1380, "clock {} pin {} is inside model block.", clk->name(),
                     network_->pathName(pin));
   }
 }

search/TagGroup.cc

@@ -311,7 +311,7 @@ TagGroupBldr::copyPaths(TagGroup *tag_group,
     if (exists2)
       paths[path_index2] = paths_[path_index1];
     else
-      sta_->report()->critical(1351, "tag group missing tag");
+      sta_->report()->critical(1360, "tag group missing tag");
   }
 }
 

verilog/VerilogReader.cc

@@ -1490,12 +1490,12 @@ VerilogReader::linkNetwork(std::string_view top_cell_name,
         return top_instance;
     }
     else {
-      report_->error(1398, "{} is not a verilog module.", top_cell_name);
+      report_->error(1390, "{} is not a verilog module.", top_cell_name);
       return nullptr;
     }
   }
   else {
-    report_->error(1399, "{} is not a verilog module.", top_cell_name);
+    report_->error(1391, "{} is not a verilog module.", top_cell_name);
     return nullptr;
   }
 }