From a1c307713994379649f7673b8d51415b88cf64c2 Mon Sep 17 00:00:00 2001 From: James Cherry Date: Thu, 23 Apr 2026 18:12:40 -0700 Subject: [PATCH] message ids Signed-off-by: James Cherry --- dcalc/LumpedCapDelayCalc.cc | 6 ++++-- search/MakeTimingModel.cc | 2 +- search/TagGroup.cc | 2 +- verilog/VerilogReader.cc | 4 ++-- 4 files changed, 8 insertions(+), 6 deletions(-) diff --git a/dcalc/LumpedCapDelayCalc.cc b/dcalc/LumpedCapDelayCalc.cc index b245c1d6..41ef4250 100644 --- a/dcalc/LumpedCapDelayCalc.cc +++ b/dcalc/LumpedCapDelayCalc.cc @@ -142,8 +142,10 @@ LumpedCapDelayCalc::gateDelay(const Pin *drvr_pin, float gate_delay, drvr_slew; float in_slew1 = delayAsFloat(in_slew); // NaNs cause seg faults during table lookup. - if (std::isnan(load_cap) || std::isnan(in_slew.mean())) - report_->error(1350, "gate delay input variable is NaN"); + if (std::isnan(load_cap)) + report_->error(1350, "gate delay load cap is NaN"); + if (std::isnan(in_slew.mean())) + report_->error(1351, "gate delay input slew is NaN"); const Pvt *pvt = pinPvt(drvr_pin, scene, min_max); model->gateDelay(pvt, in_slew1, load_cap, gate_delay, drvr_slew); diff --git a/search/MakeTimingModel.cc b/search/MakeTimingModel.cc index 7e61d19c..6ca5f935 100644 --- a/search/MakeTimingModel.cc +++ b/search/MakeTimingModel.cc @@ -231,7 +231,7 @@ MakeTimingModel::checkClock(Clock *clk) { for (const Pin *pin : clk->leafPins()) { if (!network_->isTopLevelPort(pin)) - report_->warn(1355, "clock {} pin {} is inside model block.", clk->name(), + report_->warn(1380, "clock {} pin {} is inside model block.", clk->name(), network_->pathName(pin)); } } diff --git a/search/TagGroup.cc b/search/TagGroup.cc index e7afc9c5..6fbe4d93 100644 --- a/search/TagGroup.cc +++ b/search/TagGroup.cc @@ -311,7 +311,7 @@ TagGroupBldr::copyPaths(TagGroup *tag_group, if (exists2) paths[path_index2] = paths_[path_index1]; else - sta_->report()->critical(1351, "tag group missing tag"); + sta_->report()->critical(1360, "tag group missing tag"); } } diff --git a/verilog/VerilogReader.cc b/verilog/VerilogReader.cc index 263acb4a..5c6cd0f9 100644 --- a/verilog/VerilogReader.cc +++ b/verilog/VerilogReader.cc @@ -1490,12 +1490,12 @@ VerilogReader::linkNetwork(std::string_view top_cell_name, return top_instance; } else { - report_->error(1398, "{} is not a verilog module.", top_cell_name); + report_->error(1390, "{} is not a verilog module.", top_cell_name); return nullptr; } } else { - report_->error(1399, "{} is not a verilog module.", top_cell_name); + report_->error(1391, "{} is not a verilog module.", top_cell_name); return nullptr; } }