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OpenSTA
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Merge remote-tracking branch 'parallax/master' 

Signed-off-by: Matt Liberty <mliberty@precisioninno.com>
This commit is contained in:
Matt Liberty 2024-05-28 15:59:15 -07:00
parent b71b48ad16 2b0d0f9d23
commit 99276b89cf
9 changed files with 70 additions and 51 deletions
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4
include/sta/Sta.hh
View File

@ -911,7 +911,7 @@ public:
void reportPath(Path *path);
// Report clk skews for clks.
void reportClkSkew(ConstClockSeq clks,
void reportClkSkew(ConstClockSeq &clks,
const Corner *corner,
const SetupHold *setup_hold,
bool include_internal_latency,
@ -919,7 +919,7 @@ public:
float findWorstClkSkew(const SetupHold *setup_hold,
bool include_internal_latency);
void reportClkLatency(ConstClockSeq clks,
void reportClkLatency(ConstClockSeq &clks,
const Corner *corner,
bool include_internal_latency,
int digits);

4
search/ClkLatency.cc
View File

@ -51,7 +51,7 @@ ClkLatency::findClkDelays(const Clock *clk,
}
void
ClkLatency::reportClkLatency(ConstClockSeq clks,
ClkLatency::reportClkLatency(ConstClockSeq &clks,
const Corner *corner,
bool include_internal_latency,
int digits)
@ -134,7 +134,7 @@ ClkLatency::reportClkLatency(const Clock *clk,
}
ClkDelayMap
ClkLatency::findClkDelays(ConstClockSeq clks,
ClkLatency::findClkDelays(ConstClockSeq &clks,
const Corner *corner,
bool include_internal_latency)
{

4
search/ClkLatency.hh
View File

@ -35,7 +35,7 @@ class ClkLatency : public StaState
public:
ClkLatency(StaState *sta);
// Report clk latency for clks.
void reportClkLatency(ConstClockSeq clks,
void reportClkLatency(ConstClockSeq &clks,
const Corner *corner,
bool include_internal_latency,
int digits);
@ -44,7 +44,7 @@ public:
bool include_internal_latency);
protected:
ClkDelayMap findClkDelays(ConstClockSeq clks,
ClkDelayMap findClkDelays(ConstClockSeq &clks,
const Corner *corner,
bool include_internal_latency);
void reportClkLatency(const Clock *clk,

3
search/ClkSkew.cc
View File

@ -72,6 +72,7 @@ private:
};
ClkSkew::ClkSkew() :
include_internal_latency_(false),
skew_(0.0)
{
}
@ -178,7 +179,7 @@ ClkSkews::ClkSkews(StaState *sta) :
}
void
ClkSkews::reportClkSkew(ConstClockSeq clks,
ClkSkews::reportClkSkew(ConstClockSeq &clks,
const Corner *corner,
const SetupHold *setup_hold,
bool include_internal_latency,

2
search/ClkSkew.hh
View File

@ -36,7 +36,7 @@ class ClkSkews : public StaState
public:
ClkSkews(StaState *sta);
// Report clk skews for clks.
void reportClkSkew(ConstClockSeq clks,
void reportClkSkew(ConstClockSeq &clks,
const Corner *corner,
const SetupHold *setup_hold,
bool include_internal_latency,

51
search/Sim.cc
View File

@ -802,31 +802,38 @@ Sim::setPinValue(const Pin *pin,
Vertex *vertex, *bidirect_drvr_vertex;
graph_->pinVertices(pin, vertex, bidirect_drvr_vertex);
// Set vertex constant flags.
if (vertex)
bool value_changed = false;
if (vertex) {
value_changed |= value != vertex->simValue();
setSimValue(vertex, value);
if (bidirect_drvr_vertex)
setSimValue(bidirect_drvr_vertex, value);
Instance *inst = network_->instance(pin);
if (logicValueZeroOne(value))
instances_with_const_pins_.insert(inst);
instances_to_annotate_.insert(inst);
if (network_->isLeaf(inst)
&& network_->direction(pin)->isAnyInput()) {
if (eval_queue_.empty()
|| (eval_queue_.back() != inst))
eval_queue_.push(inst);
}
else if (network_->isDriver(pin)) {
// Enqueue instances with input pins connected to net.
PinConnectedPinIterator *pin_iter=network_->connectedPinIterator(pin);
while (pin_iter->hasNext()) {
const Pin *pin1 = pin_iter->next();
if (pin1 != pin
&& network_->isLoad(pin1))
setPinValue(pin1, value);
if (bidirect_drvr_vertex) {
value_changed |= value != bidirect_drvr_vertex->simValue();
setSimValue(bidirect_drvr_vertex, value);
}
if (value_changed) {
Instance *inst = network_->instance(pin);
if (logicValueZeroOne(value))
instances_with_const_pins_.insert(inst);
instances_to_annotate_.insert(inst);
if (network_->isLeaf(inst)
&& network_->direction(pin)->isAnyInput()) {
if (eval_queue_.empty()
|| (eval_queue_.back() != inst))
eval_queue_.push(inst);
}
else if (network_->isDriver(pin)) {
// Enqueue instances with input pins connected to net.
PinConnectedPinIterator *pin_iter=network_->connectedPinIterator(pin);
while (pin_iter->hasNext()) {
const Pin *pin1 = pin_iter->next();
if (pin1 != pin
&& network_->isLoad(pin1))
setPinValue(pin1, value);
}
delete pin_iter;
}
delete pin_iter;
}
}
}

4
search/Sta.cc
View File

@ -2601,7 +2601,7 @@ Sta::updateTiming(bool full)
////////////////////////////////////////////////////////////////
void
Sta::reportClkSkew(ConstClockSeq clks,
Sta::reportClkSkew(ConstClockSeq &clks,
const Corner *corner,
const SetupHold *setup_hold,
bool include_internal_latency,
@ -2632,7 +2632,7 @@ Sta::clkSkewPreamble()
////////////////////////////////////////////////////////////////
void
Sta::reportClkLatency(ConstClockSeq clks,
Sta::reportClkLatency(ConstClockSeq &clks,
const Corner *corner,
bool include_internal_latency,
int digits)

6
tcl/StaTcl.i
View File

@ -4303,6 +4303,12 @@ capacitance(Corner *corner,
return sta->capacitance(self, corner, min_max);
}
void
set_direction(const char *dir)
{
self->setDirection(PortDirection::find(dir));
}
} // LibertyPort methods
%extend OperatingConditions {

43
verilog/VerilogWriter.cc
View File

@ -37,7 +37,7 @@ class VerilogWriter
public:
VerilogWriter(const char *filename,
bool sort,
bool include_pwr_gnd_pins,
bool include_pwr_gnd,
CellSeq *remove_cells,
FILE *stream,
Network *network);
@ -82,14 +82,14 @@ protected:
void
writeVerilog(const char *filename,
bool sort,
bool include_pwr_gnd_pins,
bool include_pwr_gnd,
CellSeq *remove_cells,
Network *network)
{
if (network->topInstance()) {
FILE *stream = fopen(filename, "w");
if (stream) {
VerilogWriter writer(filename, sort, include_pwr_gnd_pins,
VerilogWriter writer(filename, sort, include_pwr_gnd,
remove_cells, stream, network);
writer.writeModule(network->topInstance());
fclose(stream);
@ -101,13 +101,13 @@ writeVerilog(const char *filename,
VerilogWriter::VerilogWriter(const char *filename,
bool sort,
bool include_pwr_gnd_pins,
bool include_pwr_gnd,
CellSeq *remove_cells,
FILE *stream,
Network *network) :
filename_(filename),
sort_(sort),
include_pwr_gnd_(include_pwr_gnd_pins),
include_pwr_gnd_(include_pwr_gnd),
remove_cells_(network),
stream_(stream),
network_(network),
@ -236,20 +236,23 @@ VerilogWriter::writeWireDcls(Instance *inst)
NetIterator *net_iter = network_->netIterator(inst);
while (net_iter->hasNext()) {
Net *net = net_iter->next();
const char *net_name = network_->name(net);
if (network_->findPort(cell, net_name) == nullptr) {
if (isBusName(net_name, '[', ']', escape)) {
bool is_bus;
string bus_name;
int index;
parseBusName(net_name, '[', ']', escape, is_bus, bus_name, index);
BusIndexRange &range = bus_ranges[bus_name];
range.first = max(range.first, index);
range.second = min(range.second, index);
}
else {
string net_vname = netVerilogName(net_name, network_->pathEscape());
fprintf(stream_, " wire %s;\n", net_vname.c_str());;
if (include_pwr_gnd_
|| !(network_->isPower(net) || network_->isGround(net))) {
const char *net_name = network_->name(net);
if (network_->findPort(cell, net_name) == nullptr) {
if (isBusName(net_name, '[', ']', escape)) {
bool is_bus;
string bus_name;
int index;
parseBusName(net_name, '[', ']', escape, is_bus, bus_name, index);
BusIndexRange &range = bus_ranges[bus_name];
range.first = max(range.first, index);
range.second = min(range.second, index);
}
else {
string net_vname = netVerilogName(net_name, network_->pathEscape());
fprintf(stream_, " wire %s;\n", net_vname.c_str());;
}
}
}
}
@ -412,6 +415,8 @@ VerilogWriter::writeAssigns(Instance *inst)
Net *net = network_->net(term);
Port *port = network_->port(pin);
if (port
&& (include_pwr_gnd_
|| !(network_->isPower(net) || network_->isGround(net)))
&& (network_->direction(port)->isAnyOutput()
|| network_->direction(port)->isPowerGround())
&& !stringEqual(network_->name(port), network_->name(net))) {