From 73470f403340ad97c434d291ff3c2844c1b89923 Mon Sep 17 00:00:00 2001 From: James Cherry Date: Mon, 20 May 2024 15:48:00 -0700 Subject: [PATCH 1/4] reportClkSkew, reportClkLatency use ref for clks Signed-off-by: James Cherry --- include/sta/Sta.hh | 4 ++-- search/ClkLatency.cc | 4 ++-- search/ClkLatency.hh | 4 ++-- search/ClkSkew.cc | 3 ++- search/ClkSkew.hh | 2 +- search/Sta.cc | 4 ++-- tcl/StaTcl.i | 4 ++-- 7 files changed, 13 insertions(+), 12 deletions(-) diff --git a/include/sta/Sta.hh b/include/sta/Sta.hh index 5568ac3f..b5aadae3 100644 --- a/include/sta/Sta.hh +++ b/include/sta/Sta.hh @@ -911,7 +911,7 @@ public: void reportPath(Path *path); // Report clk skews for clks. - void reportClkSkew(ConstClockSeq clks, + void reportClkSkew(ConstClockSeq &clks, const Corner *corner, const SetupHold *setup_hold, bool include_internal_latency, @@ -919,7 +919,7 @@ public: float findWorstClkSkew(const SetupHold *setup_hold, bool include_internal_latency); - void reportClkLatency(ConstClockSeq clks, + void reportClkLatency(ConstClockSeq &clks, const Corner *corner, bool include_internal_latency, int digits); diff --git a/search/ClkLatency.cc b/search/ClkLatency.cc index 724cf20e..0e42b583 100644 --- a/search/ClkLatency.cc +++ b/search/ClkLatency.cc @@ -51,7 +51,7 @@ ClkLatency::findClkDelays(const Clock *clk, } void -ClkLatency::reportClkLatency(ConstClockSeq clks, +ClkLatency::reportClkLatency(ConstClockSeq &clks, const Corner *corner, bool include_internal_latency, int digits) @@ -134,7 +134,7 @@ ClkLatency::reportClkLatency(const Clock *clk, } ClkDelayMap -ClkLatency::findClkDelays(ConstClockSeq clks, +ClkLatency::findClkDelays(ConstClockSeq &clks, const Corner *corner, bool include_internal_latency) { diff --git a/search/ClkLatency.hh b/search/ClkLatency.hh index e7614c8b..d7c2470f 100644 --- a/search/ClkLatency.hh +++ b/search/ClkLatency.hh @@ -35,7 +35,7 @@ class ClkLatency : public StaState public: ClkLatency(StaState *sta); // Report clk latency for clks. - void reportClkLatency(ConstClockSeq clks, + void reportClkLatency(ConstClockSeq &clks, const Corner *corner, bool include_internal_latency, int digits); @@ -44,7 +44,7 @@ public: bool include_internal_latency); protected: - ClkDelayMap findClkDelays(ConstClockSeq clks, + ClkDelayMap findClkDelays(ConstClockSeq &clks, const Corner *corner, bool include_internal_latency); void reportClkLatency(const Clock *clk, diff --git a/search/ClkSkew.cc b/search/ClkSkew.cc index 1e47247e..d26d380e 100644 --- a/search/ClkSkew.cc +++ b/search/ClkSkew.cc @@ -72,6 +72,7 @@ private: }; ClkSkew::ClkSkew() : + include_internal_latency_(false), skew_(0.0) { } @@ -178,7 +179,7 @@ ClkSkews::ClkSkews(StaState *sta) : } void -ClkSkews::reportClkSkew(ConstClockSeq clks, +ClkSkews::reportClkSkew(ConstClockSeq &clks, const Corner *corner, const SetupHold *setup_hold, bool include_internal_latency, diff --git a/search/ClkSkew.hh b/search/ClkSkew.hh index 36f3b6eb..288584ff 100644 --- a/search/ClkSkew.hh +++ b/search/ClkSkew.hh @@ -36,7 +36,7 @@ class ClkSkews : public StaState public: ClkSkews(StaState *sta); // Report clk skews for clks. - void reportClkSkew(ConstClockSeq clks, + void reportClkSkew(ConstClockSeq &clks, const Corner *corner, const SetupHold *setup_hold, bool include_internal_latency, diff --git a/search/Sta.cc b/search/Sta.cc index 4c9bb754..36dfacab 100644 --- a/search/Sta.cc +++ b/search/Sta.cc @@ -2601,7 +2601,7 @@ Sta::updateTiming(bool full) //////////////////////////////////////////////////////////////// void -Sta::reportClkSkew(ConstClockSeq clks, +Sta::reportClkSkew(ConstClockSeq &clks, const Corner *corner, const SetupHold *setup_hold, bool include_internal_latency, @@ -2632,7 +2632,7 @@ Sta::clkSkewPreamble() //////////////////////////////////////////////////////////////// void -Sta::reportClkLatency(ConstClockSeq clks, +Sta::reportClkLatency(ConstClockSeq &clks, const Corner *corner, bool include_internal_latency, int digits) diff --git a/tcl/StaTcl.i b/tcl/StaTcl.i index e36af43f..cd1fbbbb 100644 --- a/tcl/StaTcl.i +++ b/tcl/StaTcl.i @@ -3037,7 +3037,7 @@ report_path_cmd(PathRef *path) //////////////////////////////////////////////////////////////// void -report_clk_skew(ConstClockSeq clks, +report_clk_skew(ConstClockSeq &clks, const Corner *corner, const SetupHold *setup_hold, bool include_internal_latency, @@ -3049,7 +3049,7 @@ report_clk_skew(ConstClockSeq clks, } void -report_clk_latency(ConstClockSeq clks, +report_clk_latency(ConstClockSeq &clks, const Corner *corner, bool include_internal_latency, int digits) From 20ae641fcb59a9358fa420e7b0e93081fd7ebf38 Mon Sep 17 00:00:00 2001 From: James Cherry Date: Tue, 21 May 2024 08:45:55 -0700 Subject: [PATCH 2/4] report_clock_skew/latency Signed-off-by: James Cherry --- tcl/StaTcl.i | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tcl/StaTcl.i b/tcl/StaTcl.i index cd1fbbbb..e36af43f 100644 --- a/tcl/StaTcl.i +++ b/tcl/StaTcl.i @@ -3037,7 +3037,7 @@ report_path_cmd(PathRef *path) //////////////////////////////////////////////////////////////// void -report_clk_skew(ConstClockSeq &clks, +report_clk_skew(ConstClockSeq clks, const Corner *corner, const SetupHold *setup_hold, bool include_internal_latency, @@ -3049,7 +3049,7 @@ report_clk_skew(ConstClockSeq &clks, } void -report_clk_latency(ConstClockSeq &clks, +report_clk_latency(ConstClockSeq clks, const Corner *corner, bool include_internal_latency, int digits) From 8a6c4c6d8805312786d7b252662f774cbcf23ec9 Mon Sep 17 00:00:00 2001 From: James Cherry Date: Mon, 27 May 2024 19:33:08 -0700 Subject: [PATCH 3/4] set_logic_one/zero bidir loop Signed-off-by: James Cherry --- search/Sim.cc | 51 +++++++++++++++++++++++++++++---------------------- 1 file changed, 29 insertions(+), 22 deletions(-) diff --git a/search/Sim.cc b/search/Sim.cc index 6c46dabe..105d5d38 100644 --- a/search/Sim.cc +++ b/search/Sim.cc @@ -802,31 +802,38 @@ Sim::setPinValue(const Pin *pin, Vertex *vertex, *bidirect_drvr_vertex; graph_->pinVertices(pin, vertex, bidirect_drvr_vertex); // Set vertex constant flags. - if (vertex) + bool value_changed = false; + if (vertex) { + value_changed |= value != vertex->simValue(); setSimValue(vertex, value); - if (bidirect_drvr_vertex) - setSimValue(bidirect_drvr_vertex, value); - Instance *inst = network_->instance(pin); - if (logicValueZeroOne(value)) - instances_with_const_pins_.insert(inst); - instances_to_annotate_.insert(inst); - - if (network_->isLeaf(inst) - && network_->direction(pin)->isAnyInput()) { - if (eval_queue_.empty() - || (eval_queue_.back() != inst)) - eval_queue_.push(inst); } - else if (network_->isDriver(pin)) { - // Enqueue instances with input pins connected to net. - PinConnectedPinIterator *pin_iter=network_->connectedPinIterator(pin); - while (pin_iter->hasNext()) { - const Pin *pin1 = pin_iter->next(); - if (pin1 != pin - && network_->isLoad(pin1)) - setPinValue(pin1, value); + if (bidirect_drvr_vertex) { + value_changed |= value != bidirect_drvr_vertex->simValue(); + setSimValue(bidirect_drvr_vertex, value); + } + if (value_changed) { + Instance *inst = network_->instance(pin); + if (logicValueZeroOne(value)) + instances_with_const_pins_.insert(inst); + instances_to_annotate_.insert(inst); + + if (network_->isLeaf(inst) + && network_->direction(pin)->isAnyInput()) { + if (eval_queue_.empty() + || (eval_queue_.back() != inst)) + eval_queue_.push(inst); + } + else if (network_->isDriver(pin)) { + // Enqueue instances with input pins connected to net. + PinConnectedPinIterator *pin_iter=network_->connectedPinIterator(pin); + while (pin_iter->hasNext()) { + const Pin *pin1 = pin_iter->next(); + if (pin1 != pin + && network_->isLoad(pin1)) + setPinValue(pin1, value); + } + delete pin_iter; } - delete pin_iter; } } } From 2b0d0f9d23cb43166e4186dfaa8965619f406922 Mon Sep 17 00:00:00 2001 From: James Cherry Date: Mon, 27 May 2024 19:33:43 -0700 Subject: [PATCH 4/4] write_verilog wire dcls respect -include_pwr_gnd Signed-off-by: James Cherry --- tcl/StaTcl.i | 6 ++++++ verilog/VerilogWriter.cc | 43 ++++++++++++++++++++++------------------ 2 files changed, 30 insertions(+), 19 deletions(-) diff --git a/tcl/StaTcl.i b/tcl/StaTcl.i index e36af43f..272251e1 100644 --- a/tcl/StaTcl.i +++ b/tcl/StaTcl.i @@ -4303,6 +4303,12 @@ capacitance(Corner *corner, return sta->capacitance(self, corner, min_max); } +void +set_direction(const char *dir) +{ + self->setDirection(PortDirection::find(dir)); +} + } // LibertyPort methods %extend OperatingConditions { diff --git a/verilog/VerilogWriter.cc b/verilog/VerilogWriter.cc index 799495e5..e6037a94 100644 --- a/verilog/VerilogWriter.cc +++ b/verilog/VerilogWriter.cc @@ -37,7 +37,7 @@ class VerilogWriter public: VerilogWriter(const char *filename, bool sort, - bool include_pwr_gnd_pins, + bool include_pwr_gnd, CellSeq *remove_cells, FILE *stream, Network *network); @@ -82,14 +82,14 @@ protected: void writeVerilog(const char *filename, bool sort, - bool include_pwr_gnd_pins, + bool include_pwr_gnd, CellSeq *remove_cells, Network *network) { if (network->topInstance()) { FILE *stream = fopen(filename, "w"); if (stream) { - VerilogWriter writer(filename, sort, include_pwr_gnd_pins, + VerilogWriter writer(filename, sort, include_pwr_gnd, remove_cells, stream, network); writer.writeModule(network->topInstance()); fclose(stream); @@ -101,13 +101,13 @@ writeVerilog(const char *filename, VerilogWriter::VerilogWriter(const char *filename, bool sort, - bool include_pwr_gnd_pins, + bool include_pwr_gnd, CellSeq *remove_cells, FILE *stream, Network *network) : filename_(filename), sort_(sort), - include_pwr_gnd_(include_pwr_gnd_pins), + include_pwr_gnd_(include_pwr_gnd), remove_cells_(network), stream_(stream), network_(network), @@ -236,20 +236,23 @@ VerilogWriter::writeWireDcls(Instance *inst) NetIterator *net_iter = network_->netIterator(inst); while (net_iter->hasNext()) { Net *net = net_iter->next(); - const char *net_name = network_->name(net); - if (network_->findPort(cell, net_name) == nullptr) { - if (isBusName(net_name, '[', ']', escape)) { - bool is_bus; - string bus_name; - int index; - parseBusName(net_name, '[', ']', escape, is_bus, bus_name, index); - BusIndexRange &range = bus_ranges[bus_name]; - range.first = max(range.first, index); - range.second = min(range.second, index); - } - else { - string net_vname = netVerilogName(net_name, network_->pathEscape()); - fprintf(stream_, " wire %s;\n", net_vname.c_str());; + if (include_pwr_gnd_ + || !(network_->isPower(net) || network_->isGround(net))) { + const char *net_name = network_->name(net); + if (network_->findPort(cell, net_name) == nullptr) { + if (isBusName(net_name, '[', ']', escape)) { + bool is_bus; + string bus_name; + int index; + parseBusName(net_name, '[', ']', escape, is_bus, bus_name, index); + BusIndexRange &range = bus_ranges[bus_name]; + range.first = max(range.first, index); + range.second = min(range.second, index); + } + else { + string net_vname = netVerilogName(net_name, network_->pathEscape()); + fprintf(stream_, " wire %s;\n", net_vname.c_str());; + } } } } @@ -412,6 +415,8 @@ VerilogWriter::writeAssigns(Instance *inst) Net *net = network_->net(term); Port *port = network_->port(pin); if (port + && (include_pwr_gnd_ + || !(network_->isPower(net) || network_->isGround(net))) && (network_->direction(port)->isAnyOutput() || network_->direction(port)->isPowerGround()) && !stringEqual(network_->name(port), network_->name(net))) {