indsentation

Signed-off-by: James Cherry <cherry@parallaxsw.com>

include/sta/ConcreteNetwork.hh

@@ -76,7 +76,7 @@ public:
 
   const char *name(const Cell *cell) const override;
   string getAttribute(const Cell *cell,
-                           const string &key) const override;
+                      const string &key) const override;
   ObjectId id(const Cell *cell) const override;
   Library *library(const Cell *cell) const override;
   LibertyCell *libertyCell(Cell *cell) const override;
@@ -112,7 +112,7 @@ public:
 
   const char *name(const Instance *instance) const override;
   string getAttribute(const Instance *inst,
-                           const string &key) const override;
+                      const string &key) const override;
   ObjectId id(const Instance *instance) const override;
   Cell *cell(const Instance *instance) const override;
   Instance *parent(const Instance *instance) const override;

include/sta/Network.hh

@@ -146,7 +146,7 @@ public:
   virtual const char *filename(const Cell *cell) = 0;
   // Attributes can be null
   virtual string getAttribute(const Cell *cell,
-                                   const string &key) const = 0;
+                              const string &key) const = 0;
   // Name can be a simple, bundle, bus, or bus bit name.
   virtual Port *findPort(const Cell *cell,
 			 const char *name) const = 0;
@@ -210,7 +210,7 @@ public:
   virtual InstanceSeq findInstancesHierMatching(const Instance *instance,
                                                 const PatternMatch *pattern) const;
   virtual string getAttribute(const Instance *inst,
-                                   const string &key) const = 0;
+                              const string &key) const = 0;
   // Hierarchical path name.
   virtual const char *pathName(const Instance *instance) const;
   bool pathNameLess(const Instance *inst1,

include/sta/SdcNetwork.hh

@@ -83,7 +83,7 @@ public:
 
   ObjectId id(const Instance *instance) const override;
   string getAttribute(const Instance *inst,
-                           const string &key) const override;
+                      const string &key) const override;
   Instance *topInstance() const override;
   Cell *cell(const Instance *instance) const override;
   Instance *parent(const Instance *instance) const override;

test/regression_vars.tcl

@@ -122,7 +122,7 @@ record_example_tests {
 }
 
 record_sta_tests {
-  attribute_parsing
+  verilog_attribute
 }
 
 define_test_group fast [group_tests all]

test/verilog_attribute.tcl

@@ -1,5 +1,5 @@
 read_liberty ../examples/sky130hd_tt.lib
-read_verilog attribute_parsing.v
+read_verilog verilog_attribute.v
 link_design counter
 create_clock -name clk [get_ports clk] -period 50
 
@@ -11,4 +11,4 @@ puts "top_instance:\"$cell_name\" attribute \"src\" = $src_location"
 
 set instance_name "_1415_"
 set instance_src_location [[sta::find_instance $instance_name] get_attribute "src"]
-puts "instance: $instance_name attribute \"src\" = $instance_src_location"
+puts "instance: $instance_name attribute \"src\" = $instance_src_location"

verilog/VerilogParse.yy

@@ -35,7 +35,7 @@ int VerilogLex_lex();
   int ival;
   const char *string;
   const char *constant;
-	const char *attribute_spec_value;
+  const char *attribute_spec_value;
   sta::VerilogModule *module;
   sta::VerilogStmt *stmt;
   sta::VerilogStmtSeq *stmt_seq;

verilog/VerilogReader.cc

@@ -254,7 +254,7 @@ void
 VerilogReader::makeModule(const char *module_vname,
 			  VerilogNetSeq *ports,
 			  VerilogStmtSeq *stmts,
-        VerilogAttributeStmtSeq *attribute_stmts,
+                          VerilogAttributeStmtSeq *attribute_stmts,
 			  int line)
 {
   string module_name = moduleVerilogToSta(module_vname);
@@ -286,7 +286,7 @@ void
 VerilogReader::makeModule(const char *module_name,
 			  VerilogStmtSeq *port_dcls,
 			  VerilogStmtSeq *stmts,
-        VerilogAttributeStmtSeq *attribute_stmts,
+                          VerilogAttributeStmtSeq *attribute_stmts,
 			  int line)
 {
   VerilogNetSeq *ports = new VerilogNetSeq;
@@ -402,7 +402,7 @@ VerilogReader::checkModuleDcls(VerilogModule *module,
 VerilogDcl *
 VerilogReader::makeDcl(PortDirection *dir,
 		       VerilogDclArgSeq *args,
-           VerilogAttributeStmtSeq* attribute_stmts,
+                       VerilogAttributeStmtSeq* attribute_stmts,
 		       int line)
 {
   if (dir->isInternal()) {
@@ -436,7 +436,7 @@ VerilogReader::makeDcl(PortDirection *dir,
 VerilogDcl *
 VerilogReader::makeDcl(PortDirection *dir,
 		       VerilogDclArg *arg,
-           VerilogAttributeStmtSeq* attribute_stmts,
+                       VerilogAttributeStmtSeq* attribute_stmts,
 		       int line)
 {
   dcl_count_++;
@@ -448,7 +448,7 @@ VerilogReader::makeDclBus(PortDirection *dir,
 			  int from_index,
 			  int to_index,
 			  VerilogDclArg *arg,
-        VerilogAttributeStmtSeq* attribute_stmts,
+                          VerilogAttributeStmtSeq* attribute_stmts,
 			  int line)
 {
   dcl_bus_count_++;
@@ -461,7 +461,7 @@ VerilogReader::makeDclBus(PortDirection *dir,
 			  int from_index,
 			  int to_index,
 			  VerilogDclArgSeq *args,
-        VerilogAttributeStmtSeq* attribute_stmts,
+                          VerilogAttributeStmtSeq* attribute_stmts,
 			  int line)
 {
   dcl_bus_count_++;