From 8b5f0caa8551f5c707f3b37f91c6afa42359997e Mon Sep 17 00:00:00 2001 From: James Cherry Date: Sat, 16 Mar 2024 09:55:39 -0700 Subject: [PATCH] indsentation Signed-off-by: James Cherry --- include/sta/ConcreteNetwork.hh | 4 ++-- include/sta/Network.hh | 4 ++-- include/sta/SdcNetwork.hh | 2 +- test/regression_vars.tcl | 2 +- test/{attribute_parsing.ok => verilog_attribute.ok} | 0 .../{attribute_parsing.tcl => verilog_attribute.tcl} | 4 ++-- test/{attribute_parsing.v => verilog_attribute.v} | 0 verilog/VerilogParse.yy | 2 +- verilog/VerilogReader.cc | 12 ++++++------ 9 files changed, 15 insertions(+), 15 deletions(-) rename test/{attribute_parsing.ok => verilog_attribute.ok} (100%) rename test/{attribute_parsing.tcl => verilog_attribute.tcl} (91%) rename test/{attribute_parsing.v => verilog_attribute.v} (100%) diff --git a/include/sta/ConcreteNetwork.hh b/include/sta/ConcreteNetwork.hh index 06528214..7c62a4f7 100644 --- a/include/sta/ConcreteNetwork.hh +++ b/include/sta/ConcreteNetwork.hh @@ -76,7 +76,7 @@ public: const char *name(const Cell *cell) const override; string getAttribute(const Cell *cell, - const string &key) const override; + const string &key) const override; ObjectId id(const Cell *cell) const override; Library *library(const Cell *cell) const override; LibertyCell *libertyCell(Cell *cell) const override; @@ -112,7 +112,7 @@ public: const char *name(const Instance *instance) const override; string getAttribute(const Instance *inst, - const string &key) const override; + const string &key) const override; ObjectId id(const Instance *instance) const override; Cell *cell(const Instance *instance) const override; Instance *parent(const Instance *instance) const override; diff --git a/include/sta/Network.hh b/include/sta/Network.hh index 001826ac..5f0f1e21 100644 --- a/include/sta/Network.hh +++ b/include/sta/Network.hh @@ -146,7 +146,7 @@ public: virtual const char *filename(const Cell *cell) = 0; // Attributes can be null virtual string getAttribute(const Cell *cell, - const string &key) const = 0; + const string &key) const = 0; // Name can be a simple, bundle, bus, or bus bit name. virtual Port *findPort(const Cell *cell, const char *name) const = 0; @@ -210,7 +210,7 @@ public: virtual InstanceSeq findInstancesHierMatching(const Instance *instance, const PatternMatch *pattern) const; virtual string getAttribute(const Instance *inst, - const string &key) const = 0; + const string &key) const = 0; // Hierarchical path name. virtual const char *pathName(const Instance *instance) const; bool pathNameLess(const Instance *inst1, diff --git a/include/sta/SdcNetwork.hh b/include/sta/SdcNetwork.hh index 6f6a2e1f..66c42026 100644 --- a/include/sta/SdcNetwork.hh +++ b/include/sta/SdcNetwork.hh @@ -83,7 +83,7 @@ public: ObjectId id(const Instance *instance) const override; string getAttribute(const Instance *inst, - const string &key) const override; + const string &key) const override; Instance *topInstance() const override; Cell *cell(const Instance *instance) const override; Instance *parent(const Instance *instance) const override; diff --git a/test/regression_vars.tcl b/test/regression_vars.tcl index f6a9ad8c..444cab71 100644 --- a/test/regression_vars.tcl +++ b/test/regression_vars.tcl @@ -122,7 +122,7 @@ record_example_tests { } record_sta_tests { - attribute_parsing + verilog_attribute } define_test_group fast [group_tests all] diff --git a/test/attribute_parsing.ok b/test/verilog_attribute.ok similarity index 100% rename from test/attribute_parsing.ok rename to test/verilog_attribute.ok diff --git a/test/attribute_parsing.tcl b/test/verilog_attribute.tcl similarity index 91% rename from test/attribute_parsing.tcl rename to test/verilog_attribute.tcl index e771c6d2..1ae001ca 100644 --- a/test/attribute_parsing.tcl +++ b/test/verilog_attribute.tcl @@ -1,5 +1,5 @@ read_liberty ../examples/sky130hd_tt.lib -read_verilog attribute_parsing.v +read_verilog verilog_attribute.v link_design counter create_clock -name clk [get_ports clk] -period 50 @@ -11,4 +11,4 @@ puts "top_instance:\"$cell_name\" attribute \"src\" = $src_location" set instance_name "_1415_" set instance_src_location [[sta::find_instance $instance_name] get_attribute "src"] -puts "instance: $instance_name attribute \"src\" = $instance_src_location" \ No newline at end of file +puts "instance: $instance_name attribute \"src\" = $instance_src_location" diff --git a/test/attribute_parsing.v b/test/verilog_attribute.v similarity index 100% rename from test/attribute_parsing.v rename to test/verilog_attribute.v diff --git a/verilog/VerilogParse.yy b/verilog/VerilogParse.yy index e70b74e8..37515d81 100644 --- a/verilog/VerilogParse.yy +++ b/verilog/VerilogParse.yy @@ -35,7 +35,7 @@ int VerilogLex_lex(); int ival; const char *string; const char *constant; - const char *attribute_spec_value; + const char *attribute_spec_value; sta::VerilogModule *module; sta::VerilogStmt *stmt; sta::VerilogStmtSeq *stmt_seq; diff --git a/verilog/VerilogReader.cc b/verilog/VerilogReader.cc index 0b7c7fcc..dbb602ac 100644 --- a/verilog/VerilogReader.cc +++ b/verilog/VerilogReader.cc @@ -254,7 +254,7 @@ void VerilogReader::makeModule(const char *module_vname, VerilogNetSeq *ports, VerilogStmtSeq *stmts, - VerilogAttributeStmtSeq *attribute_stmts, + VerilogAttributeStmtSeq *attribute_stmts, int line) { string module_name = moduleVerilogToSta(module_vname); @@ -286,7 +286,7 @@ void VerilogReader::makeModule(const char *module_name, VerilogStmtSeq *port_dcls, VerilogStmtSeq *stmts, - VerilogAttributeStmtSeq *attribute_stmts, + VerilogAttributeStmtSeq *attribute_stmts, int line) { VerilogNetSeq *ports = new VerilogNetSeq; @@ -402,7 +402,7 @@ VerilogReader::checkModuleDcls(VerilogModule *module, VerilogDcl * VerilogReader::makeDcl(PortDirection *dir, VerilogDclArgSeq *args, - VerilogAttributeStmtSeq* attribute_stmts, + VerilogAttributeStmtSeq* attribute_stmts, int line) { if (dir->isInternal()) { @@ -436,7 +436,7 @@ VerilogReader::makeDcl(PortDirection *dir, VerilogDcl * VerilogReader::makeDcl(PortDirection *dir, VerilogDclArg *arg, - VerilogAttributeStmtSeq* attribute_stmts, + VerilogAttributeStmtSeq* attribute_stmts, int line) { dcl_count_++; @@ -448,7 +448,7 @@ VerilogReader::makeDclBus(PortDirection *dir, int from_index, int to_index, VerilogDclArg *arg, - VerilogAttributeStmtSeq* attribute_stmts, + VerilogAttributeStmtSeq* attribute_stmts, int line) { dcl_bus_count_++; @@ -461,7 +461,7 @@ VerilogReader::makeDclBus(PortDirection *dir, int from_index, int to_index, VerilogDclArgSeq *args, - VerilogAttributeStmtSeq* attribute_stmts, + VerilogAttributeStmtSeq* attribute_stmts, int line) { dcl_bus_count_++;