From 759348402df2cde1f9e326960cdba6e197d1ea56 Mon Sep 17 00:00:00 2001 From: Matt Liberty Date: Tue, 18 Nov 2025 22:20:00 +0000 Subject: [PATCH] Get the pin count from the Liberty cell not the Cell (#334) The Cell may come from LEF which doesn't have internal pins that Liberty does. This used to work by dumb luck where the extra two power pins in LEF happened to align to the extra two internal pins from Liberty. With the change to pg_pins this no longer works. Signed-off-by: Matt Liberty --- verilog/VerilogReader.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/verilog/VerilogReader.cc b/verilog/VerilogReader.cc index b7e0260f..166021e6 100644 --- a/verilog/VerilogReader.cc +++ b/verilog/VerilogReader.cc @@ -534,7 +534,7 @@ VerilogReader::makeModuleInst(const string *module_vname, // to reduce the memory footprint of the verilog parser. if (liberty_cell && hasScalarNamedPortRefs(liberty_cell, pins)) { - int port_count = network_->portBitCount(cell); + const int port_count = liberty_cell->portBitCount(); StdStringSeq net_names(port_count); for (VerilogNet *vnet : *pins) { VerilogNetPortRefScalarNet *vpin =