regolden tests for constant disabled arc slew fix

Update goldens for "dcalc no slew merge for constant disabled arcs".

dcalc_case_analysis_leak: arrival spread across the wire-load sweep on the
constant net drops from 46.38 ps to 0.00 ps, which is the point of the test.
Rewrite the header comment to describe the fix rather than the open bug.

graph_modify: with set_case_analysis 0 on d4, inv2 drives n4=1 and or1
drives n6=1, so nand1/A2 is constant. 1 is non-controlling for a NAND, so
nand1/ZN stays live and the A2->ZN arc is dead. Its slew no longer merges
into nand1/ZN, so buf4/Z falls from 0.07 to 0.06. The following report,
after unset_case_analysis, still shows 0.07 as expected.

sdc_port_delay_advanced: in1=0, in2=1 and case analysis 0 on in3 make
nor1/ZN constant, so it is no longer reported as the worst max slew pin;
reg1/QN takes its place.

Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>

dcalc/test/dcalc_case_analysis_leak.ok

@@ -1,10 +1,10 @@
 
 load on constant net cn (ff)    arrival at z (ps)
-0                               159.19
+0                               158.79
-50                              159.71
+50                              158.79
-200                             167.60
+200                             158.79
-500                             181.63
+500                             158.79
-1000                            205.57
+1000                            158.79
 
-arrival spread across the sweep: 46.38 ps (expected 0.00)
+arrival spread across the sweep: 0.00 ps (expected 0.00)
 

dcalc/test/dcalc_case_analysis_leak.tcl

@@ -1,21 +1,22 @@
-# Delay calculation ignores set_case_analysis constants.
+# Delay calculation must not merge slew from set_case_analysis constants.
 #
-# GraphDelayCalc uses DcalcPred (dcalc/GraphDelayCalc.cc), whose searchFrom
+# Regression guard for "dcalc no slew merge for constant disabled arcs".
-# stops only at power/ground nets:
+#
+# GraphDelayCalc uses DcalcPred (dcalc/GraphDelayCalc.cc).  Its searchFrom
+# used to stop only at power/ground nets:
 #
 #   return !(sdc->isDisabledConstraint(from_pin)
 #            || (net && (network->isPower(net) || network->isGround(net))));
 #
-# SearchPred0::searchFrom (search/SearchPred.cc) instead stops at
+# SearchPred0::searchFrom (search/SearchPred.cc) stops at
-# sim->isConstant(from_vertex).  DcalcPred::searchTo returns true
+# sim->isConstant(from_vertex); DcalcPred did not, so in
-# unconditionally where SearchPred0::searchTo returns !sim->isConstant, and
+# findDriverEdgeDelays an arc whose source pin is an SDC constant still
-# DcalcPred::searchThru omits sim->isDisabledCond and the
+# passed searchFrom/searchThru and had its delay and slew merged into the
-# simTimingSense == none test.  GraphDelayCalc.cc never references Sim at all.
+# driver vertex -- including when that driver is a live, non-constant pin.
 #
-# Consequence: in findDriverEdgeDelays (GraphDelayCalc.cc:1011) an arc whose
+# The fix adds sim->isConstant(from_vertex) to DcalcPred::searchFrom, and
-# source pin is an SDC constant still passes searchFrom/searchThru, so its
+# makes Sta::delayCalcPreamble propagate constants before delay calculation
-# delay and slew are computed and merged into the driver vertex -- including
+# so the predicate sees them.
-# when that driver is a live, non-constant pin.
 #
 # Circuit (dcalc_case_analysis_leak.v):
 #
@@ -27,9 +28,10 @@
 # AND, so n1 and z stay live and the A2->ZN arc is dead.  The reported path is
 # a -> u1 -> u2 -> z, which never traverses cn.
 #
-# Sweeping the wire load on cn must not change anything on that path.  It
+# Sweeping the wire load on cn must not change anything on that path.  Before
-# does: cn's slew rides the dead A2->ZN arc into n1, and n1's slew sets u2's
+# the fix it did: cn's slew rode the dead A2->ZN arc into n1, and n1's slew
-# delay.  The arrival column below should be flat and is not.
+# set u2's delay, so the arrival spread was 46.38 ps.  The arrival column
+# below must now be flat.
 
 read_liberty ../../examples/nangate45_slow.lib.gz
 read_verilog dcalc_case_analysis_leak.v

graph/test/graph_modify.ok

@@ -2415,7 +2415,7 @@ Corner: slow
    0.14    1.14 v buf1/Z (BUF_X1)
    0.09    1.23 v and1/ZN (AND2_X1)
    0.09    1.32 ^ nand1/ZN (NAND2_X1)
-   0.07    1.38 ^ buf4/Z (BUF_X4)
+   0.06    1.38 ^ buf4/Z (BUF_X4)
    0.00    1.38 ^ q3 (out)
            1.38   data arrival time
 

sdc/test/sdc_port_delay_advanced.ok

@@ -111,7 +111,7 @@ max slew
 
 Pin                                    Limit    Slew   Slack
 ------------------------------------------------------------
-nor1/ZN                                 0.20    0.01    0.18 (MET)
+reg1/QN                                 0.20    0.01    0.19 (MET)
 
 max fanout