mirror of
https://github.com/The-OpenROAD-Project/OpenSTA.git
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One-to-one mismatched widths: partial timing arc creation
This commit is contained in:
Akash Levy
@@ -0,0 +1,133 @@
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library (one_to_one_mismatched_width_test) {
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delay_model : "table_lookup";
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simulation : false;
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capacitive_load_unit (1,pF);
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leakage_power_unit : "1pW";
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current_unit : "1A";
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pulling_resistance_unit : "1kohm";
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time_unit : "1ns";
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voltage_unit : "1v";
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library_features : "report_delay_calculation";
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input_threshold_pct_rise : 50;
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input_threshold_pct_fall : 50;
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output_threshold_pct_rise : 50;
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output_threshold_pct_fall : 50;
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slew_lower_threshold_pct_rise : 30;
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slew_lower_threshold_pct_fall : 30;
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slew_upper_threshold_pct_rise : 70;
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slew_upper_threshold_pct_fall : 70;
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slew_derate_from_library : 1.0;
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nom_process : 1.0;
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nom_temperature : 85.0;
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nom_voltage : 0.75;
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type (bus20) {
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base_type : "array";
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data_type : "bit";
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bit_width : 20;
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bit_from : 19;
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bit_to : 0;
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}
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type (bus32) {
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base_type : "array";
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data_type : "bit";
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bit_width : 32;
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bit_from : 31;
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bit_to : 0;
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}
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cell (or_32_to_20) {
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bus (A) {
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capacitance : 1;
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bus_type : "bus32";
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direction : "input";
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}
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bus (B) {
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capacitance : 1;
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bus_type : "bus32";
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direction : "input";
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}
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bus (Y) {
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function : "A | B";
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bus_type : "bus20";
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direction : "output";
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timing () {
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related_pin : "A";
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cell_rise (scalar) {
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values ("1");
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}
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cell_fall (scalar) {
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values ("1");
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}
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rise_transition (scalar) {
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values ("1");
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}
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fall_transition (scalar) {
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values ("1");
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}
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}
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timing () {
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related_pin : "B";
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cell_rise (scalar) {
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values ("1");
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}
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cell_fall (scalar) {
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values ("1");
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}
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rise_transition (scalar) {
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values ("1");
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}
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fall_transition (scalar) {
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values ("1");
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}
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}
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}
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}
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cell (or_20_to_32) {
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bus (A) {
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capacitance : 1;
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bus_type : "bus20";
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direction : "input";
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}
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bus (B) {
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capacitance : 1;
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bus_type : "bus20";
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direction : "input";
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}
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bus (Y) {
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function : "A | B";
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bus_type : "bus32";
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direction : "output";
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timing () {
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related_pin : "A";
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cell_rise (scalar) {
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values ("1");
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}
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cell_fall (scalar) {
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values ("1");
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}
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rise_transition (scalar) {
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values ("1");
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}
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fall_transition (scalar) {
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values ("1");
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}
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}
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timing () {
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related_pin : "B";
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cell_rise (scalar) {
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values ("1");
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}
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cell_fall (scalar) {
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values ("1");
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}
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rise_transition (scalar) {
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values ("1");
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}
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fall_transition (scalar) {
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values ("1");
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}
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}
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}
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}
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}
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+168
@@ -0,0 +1,168 @@
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Warning: one2one.lib line 53, timing port A and related port Y are different sizes.
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Warning: one2one.lib line 68, timing port B and related port Y are different sizes.
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Warning: one2one.lib line 101, timing port A and related port Y are different sizes.
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Warning: one2one.lib line 116, timing port B and related port Y are different sizes.
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TEST 1:
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Startpoint: a[0] (input port clocked by clk)
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Endpoint: y[0] (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v a[0] (in)
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1.00 1.00 ^ partial_wide_or_cell/Y[0] (or_32_to_20)
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0.00 1.00 ^ y[0] (out)
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1.00 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 0.00 output external delay
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0.00 data required time
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---------------------------------------------------------
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0.00 data required time
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-1.00 data arrival time
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---------------------------------------------------------
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-1.00 slack (VIOLATED)
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Startpoint: a[10] (input port clocked by clk)
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Endpoint: y[10] (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v a[10] (in)
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1.00 1.00 ^ partial_wide_or_cell/Y[10] (or_32_to_20)
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0.00 1.00 ^ y[10] (out)
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1.00 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 0.00 output external delay
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0.00 data required time
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---------------------------------------------------------
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0.00 data required time
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-1.00 data arrival time
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---------------------------------------------------------
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-1.00 slack (VIOLATED)
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Startpoint: a[11] (input port clocked by clk)
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Endpoint: y[11] (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v a[11] (in)
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1.00 1.00 ^ partial_wide_or_cell/Y[11] (or_32_to_20)
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0.00 1.00 ^ y[11] (out)
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1.00 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 0.00 output external delay
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0.00 data required time
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---------------------------------------------------------
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0.00 data required time
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-1.00 data arrival time
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---------------------------------------------------------
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-1.00 slack (VIOLATED)
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TEST 2:
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Startpoint: a[0] (input port clocked by clk)
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Endpoint: y[0] (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v a[0] (in)
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1.00 1.00 ^ wide_or_cell/Y[0] (or_20_to_32)
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0.00 1.00 ^ y[0] (out)
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1.00 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 0.00 output external delay
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0.00 data required time
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---------------------------------------------------------
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0.00 data required time
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-1.00 data arrival time
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---------------------------------------------------------
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-1.00 slack (VIOLATED)
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Startpoint: a[10] (input port clocked by clk)
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Endpoint: y[10] (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v a[10] (in)
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1.00 1.00 ^ wide_or_cell/Y[10] (or_20_to_32)
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0.00 1.00 ^ y[10] (out)
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1.00 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 0.00 output external delay
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0.00 data required time
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---------------------------------------------------------
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0.00 data required time
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-1.00 data arrival time
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---------------------------------------------------------
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-1.00 slack (VIOLATED)
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Startpoint: a[11] (input port clocked by clk)
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Endpoint: y[11] (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v a[11] (in)
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1.00 1.00 ^ wide_or_cell/Y[11] (or_20_to_32)
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0.00 1.00 ^ y[11] (out)
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1.00 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 0.00 output external delay
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0.00 data required time
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---------------------------------------------------------
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0.00 data required time
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-1.00 data arrival time
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---------------------------------------------------------
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-1.00 slack (VIOLATED)
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@@ -0,0 +1,17 @@
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read_liberty one2one.lib
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puts "TEST 1:"
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read_verilog one2one_test1.v
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link_design one2one_test1
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create_clock -name clk -period 0
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set_input_delay -clock clk 0 [all_inputs]
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set_output_delay -clock clk 0 [all_outputs]
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report_checks -group_count 3
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puts "TEST 2:"
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read_verilog one2one_test2.v
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link_design one2one_test2
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create_clock -name clk -period 0
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set_input_delay -clock clk 0 [all_inputs]
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set_output_delay -clock clk 0 [all_outputs]
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report_checks -group_count 3
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@@ -0,0 +1,14 @@
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// Liberty file test: one-to-one mapping with mismatched bit widths
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// Should generate warning but still create timing arcs between bits with same index
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module one2one_test1 (
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input wire [31:0] a,
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output wire [19:0] y
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);
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or_32_to_20 partial_wide_or_cell (
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.A(a),
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.B(32'b0),
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.Y(y)
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);
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endmodule
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@@ -0,0 +1,14 @@
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// Liberty file test: one-to-one mapping with mismatched bit widths
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// Should generate warning but still create timing arcs between bits with same index
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module one2one_test2 (
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input wire [19:0] a,
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output wire [31:0] y
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);
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or_20_to_32 partial_wide_or_cell (
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.A(a),
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.B(20'b0),
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.Y(y)
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);
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endmodule
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@@ -124,6 +124,7 @@ record_example_tests {
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record_sta_tests {
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prima3
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verilog_attribute
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one2one
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}
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define_test_group fast [group_tests all]
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