ssta compile errors
Signed-off-by: James Cherry <cherry@parallaxsw.com>
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@ -54,7 +54,7 @@ ArcDcalcWaveforms::inputWaveform(ArcDcalcArg &dcalc_arg,
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library->supplyVoltage("VDD", vdd, vdd_exists);
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if (!vdd_exists)
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report->error(1751, "VDD not defined in library %s", library->name());
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Waveform in_waveform = driver_waveform->waveform(in_slew);
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Waveform in_waveform = driver_waveform->waveform(delayAsFloat(in_slew));
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// Delay time axis.
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FloatSeq *time_values = new FloatSeq;
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for (float time : *in_waveform.axis1()->values())
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@ -212,7 +212,7 @@ PrimaDelayCalc::gateDelays(ArcDcalcArgSeq &dcalc_args,
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GateTableModel *table_model = dcalc_arg.arc()->gateTableModel(dcalc_ap);
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if (table_model && dcalc_arg.parasitic()) {
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OutputWaveforms *output_waveforms = table_model->outputWaveforms();
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Slew in_slew = dcalc_arg.inSlew();
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float in_slew = dcalc_arg.inSlewFlt();
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if (output_waveforms
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// Bounds check because extrapolating waveforms does not work for shit.
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&& output_waveforms->slewAxis()->inBounds(in_slew)
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@ -323,7 +323,7 @@ PrimaDelayCalc::simulate1(const MatrixSd &G,
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v_ = v_prev_ = x_to_v * x_init;
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// voltageTime is always for a rising waveform so 0.0v is initial voltage.
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double time_begin = output_waveforms_[0]->voltageTime((*dcalc_args_)[0].inSlew(),
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double time_begin = output_waveforms_[0]->voltageTime((*dcalc_args_)[0].inSlewFlt(),
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ceff_[0], 0.0);
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// Limit in case load voltage waveforms don't get to final value.
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double time_end = time_begin + maxTime();
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@ -370,7 +370,7 @@ PrimaDelayCalc::timeStep()
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double
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PrimaDelayCalc::maxTime()
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{
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return (*dcalc_args_)[0].inSlew()
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return (*dcalc_args_)[0].inSlewFlt()
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+ (driverResistance() + resistance_sum_) * load_cap_ * 4;
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}
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@ -486,7 +486,7 @@ PrimaDelayCalc::initCeffIdrvr()
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ceff_[drvr_idx] = load_cap_;
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// voltageTime is always for a rising waveform so 0.0v is initial voltage.
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drvr_current_[drvr_idx] =
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output_waveforms_[drvr_idx]->voltageCurrent(dcalc_arg.inSlew(),
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output_waveforms_[drvr_idx]->voltageCurrent(dcalc_arg.inSlewFlt(),
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ceff_[drvr_idx], 0.0);
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}
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}
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@ -617,7 +617,7 @@ PrimaDelayCalc::updateCeffIdrvr()
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drvr_current_[drvr_idx] = 0.0;
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else
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drvr_current_[drvr_idx] =
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output_waveforms_[drvr_idx]->voltageCurrent(dcalc_arg.inSlew(),
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output_waveforms_[drvr_idx]->voltageCurrent(dcalc_arg.inSlewFlt(),
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ceff_[drvr_idx], v1);
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}
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else {
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@ -633,7 +633,7 @@ PrimaDelayCalc::updateCeffIdrvr()
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}
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else
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drvr_current_[drvr_idx] =
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output_waveforms_[drvr_idx]->voltageCurrent(dcalc_arg.inSlew(),
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output_waveforms_[drvr_idx]->voltageCurrent(dcalc_arg.inSlewFlt(),
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ceff_[drvr_idx],
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vdd_ - v1);
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}
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@ -710,7 +710,7 @@ PrimaDelayCalc::dcalcResults()
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const LibertyLibrary *drvr_library = dcalc_arg.drvrLibrary();
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size_t drvr_node = pin_node_map_[drvr_pin];
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ThresholdTimes &drvr_times = threshold_times_[drvr_node];
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float ref_time = output_waveforms_[drvr_idx]->referenceTime(dcalc_arg.inSlew());
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float ref_time = output_waveforms_[drvr_idx]->referenceTime(dcalc_arg.inSlewFlt());
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ArcDelay gate_delay = drvr_times[threshold_vth] - ref_time;
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Slew drvr_slew = abs(drvr_times[threshold_vh] - drvr_times[threshold_vl]);
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dcalc_result.setGateDelay(gate_delay);
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