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read_verilog pin { pin ( seg fault 

Signed-off-by: James Cherry <cherry@parallaxsw.com>
This commit is contained in:
James Cherry 2023-08-24 15:52:28 -07:00
parent 7c0d252fc1
commit 451831edd7
1 changed files with 14 additions and 12 deletions
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26
liberty/LibertyReader.cc
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@ -2977,21 +2977,23 @@ LibertyReader::endPorts()
{
// Capacitances default based on direction so wait until the end
// of the pin group to set them.
for (LibertyPort *port : *ports_) {
if (in_bus_ || in_bundle_) {
// Do not clobber member port capacitances by setting the capacitance
// on a bus or bundle.
LibertyPortMemberIterator member_iter(port);
while (member_iter.hasNext()) {
LibertyPort *member = member_iter.next();
setPortCapDefault(member);
if (ports_) {
for (LibertyPort *port : *ports_) {
if (in_bus_ || in_bundle_) {
// Do not clobber member port capacitances by setting the capacitance
// on a bus or bundle.
LibertyPortMemberIterator member_iter(port);
while (member_iter.hasNext()) {
LibertyPort *member = member_iter.next();
setPortCapDefault(member);
}
}
else
setPortCapDefault(port);
}
else
setPortCapDefault(port);
ports_ = nullptr;
port_group_ = nullptr;
}
ports_ = nullptr;
port_group_ = nullptr;
}
void