mirror of
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Network::id for maps/sets
commit be70d30ae05665021254b0d7e69fb8d2f0a82890 Author: James Cherry <[email protected]> Date: Tue Jan 17 17:04:49 2023 -0700 cmp Signed-off-by: James Cherry <[email protected]> commit 4d4ef96948afe3d6a00c4521aeb5bc74274f5737 Author: James Cherry <[email protected]> Date: Tue Jan 17 16:08:50 2023 -0700 rvo, const Signed-off-by: James Cherry <[email protected]> commit bb584e4264af2bea867b17d07e8d38c0e9eb0025 Author: James Cherry <[email protected]> Date: Tue Jan 17 15:05:00 2023 -0700 const Signed-off-by: James Cherry <[email protected]> commit a08fe558bca6b769b2728882258bd85aed990a27 Author: James Cherry <[email protected]> Date: Tue Jan 17 14:57:33 2023 -0700 LibertyPortPair no ptrs Signed-off-by: James Cherry <[email protected]> commit 4d3bd60c109d1ce9d0589d746f4968fa7bebd90d Author: James Cherry <[email protected]> Date: Tue Jan 17 14:13:07 2023 -0700 cleanup Signed-off-by: James Cherry <[email protected]> commit dc25ff77771cfbe26f9318bad2b3c45879614783 Author: James Cherry <[email protected]> Date: Tue Jan 17 14:06:13 2023 -0700 const Signed-off-by: James Cherry <[email protected]> commit 06e81586ce11a0cc06948ed78fef99353077d69e Author: James Cherry <[email protected]> Date: Tue Jan 17 14:01:10 2023 -0700 sortByName Signed-off-by: James Cherry <[email protected]> commit 9d8592aff5b246f83e47e1b94490e3cef8d8e119 Author: James Cherry <[email protected]> Date: Tue Jan 17 11:57:17 2023 -0700 sort pred Signed-off-by: James Cherry <[email protected]> commit 462a8e14df8b561ddfc842addc62c4b8435b6347 Author: James Cherry <[email protected]> Date: Tue Jan 17 11:09:57 2023 -0700 const Signed-off-by: James Cherry <[email protected]> commit 69f71505b684e88b22d395510429497e87bf1015 Author: James Cherry <[email protected]> Date: Tue Jan 17 10:45:14 2023 -0700 flush ConstPortSeq Signed-off-by: James Cherry <[email protected]> commit 6429d578b78eac3fe7e99fcd67a120789932b2eb Author: James Cherry <[email protected]> Date: Tue Jan 17 09:19:15 2023 -0700 rm ConstNetSet Signed-off-by: James Cherry <[email protected]> commit f247930b16e40560b957a36af68947249ed1ef04 Author: James Cherry <[email protected]> Date: Tue Jan 17 08:50:50 2023 -0700 sortPathNames Signed-off-by: James Cherry <[email protected]> commit 4ca2b0e0af7252c7bcbc65cf141d0ce40634d329 Author: James Cherry <[email protected]> Date: Mon Jan 16 10:14:05 2023 -0700 const Signed-off-by: James Cherry <[email protected]> commit 3d18640d2ebc4aae3098c7e7242a554fcb64fd42 Author: James Cherry <[email protected]> Date: Mon Jan 16 09:41:27 2023 -0700 set_input/ouput_delay -reference_pin Signed-off-by: James Cherry <[email protected]> commit d4a0854dd2102f46f96a94fb9eb8749f1593a85f Author: James Cherry <[email protected]> Date: Mon Jan 16 09:13:46 2023 -0700 PinPairSet no malloc Signed-off-by: James Cherry <[email protected]> commit a6f1583fc6a856c5ecc0dcb15a1d8b1f61e30718 Author: James Cherry <[email protected]> Date: Mon Jan 16 08:53:33 2023 -0700 no malloc for EdgePins Signed-off-by: James Cherry <[email protected]> commit c8e4b92e8b619109d6aa3c141c720646067ccb4b Author: James Cherry <[email protected]> Date: Mon Jan 16 06:31:08 2023 +0000 leak commit abab99e0fc3e466d914f6c1705aa08cdc204df51 Author: James Cherry <[email protected]> Date: Mon Jan 16 06:07:36 2023 +0000 leaks commit d1913b554bb6e98b89673d80d2295f552eb4ffca Author: James Cherry <[email protected]> Date: Sun Jan 15 19:48:39 2023 -0700 LibertyCell::checkCornerCell Signed-off-by: James Cherry <[email protected]> commit bcc172237d48deed647374f9592bac70bd2d5425 Author: James Cherry <[email protected]> Date: Sun Jan 15 18:19:47 2023 -0700 rvo Signed-off-by: James Cherry <[email protected]> commit 8ef9800b87f5e5548055a13afc21397f28a6bcf7 Author: James Cherry <[email protected]> Date: Sun Jan 15 18:07:46 2023 -0700 sdc net id Signed-off-by: James Cherry <[email protected]> commit d7235abed04ced4e2d84e91bf9968e621268567d Author: James Cherry <[email protected]> Date: Sun Jan 15 16:00:27 2023 -0700 range iter Signed-off-by: James Cherry <[email protected]> commit a22f91a3c54c644574339d1126821d9bc8045bd6 Author: James Cherry <[email protected]> Date: Sun Jan 15 15:52:50 2023 -0700 range iter Signed-off-by: James Cherry <[email protected]> commit 762615ce3de91d950eeaaa4680549a45b13e0e0a Author: James Cherry <[email protected]> Date: Sun Jan 15 15:42:19 2023 -0700 range iter Signed-off-by: James Cherry <[email protected]> commit 7e0c531613d343d23f064c24873bf5a498f6f4ce Author: James Cherry <[email protected]> Date: Sun Jan 15 12:26:49 2023 -0700 rm removeLoadCaps, removeNetLoadCaps Signed-off-by: James Cherry <[email protected]> commit f2e88c6082e2d4605e9849348008bf4065401fc8 Author: James Cherry <[email protected]> Date: Sun Jan 15 12:21:03 2023 -0700 sdc rm map ptrs Signed-off-by: James Cherry <[email protected]> commit b5939666188c0b94dfe957e22bbd8a92f4786125 Author: James Cherry <[email protected]> Date: Sun Jan 15 11:36:16 2023 -0700 sdc rm map ptrs Signed-off-by: James Cherry <[email protected]> commit a435081bafe10260743319f53a59cbe2ed0388b7 Author: James Cherry <[email protected]> Date: Sun Jan 15 08:43:37 2023 -0700 sdc rm map ptrs Signed-off-by: James Cherry <[email protected]> commit acfb247559db7b726d47f203613488df0f7add53 Author: James Cherry <[email protected]> Date: Sun Jan 15 08:38:07 2023 -0700 sdc rm map ptrs Signed-off-by: James Cherry <[email protected]> commit 7541b71da92ea15085615988a1e6ea1d4d53d8d6 Author: James Cherry <[email protected]> Date: Sun Jan 15 08:00:55 2023 -0700 sdc rm map ptrs Signed-off-by: James Cherry <[email protected]> commit d033210132656ea68fa834228575b9def1d02d90 Author: James Cherry <[email protected]> Date: Sun Jan 15 07:52:03 2023 -0700 sdc rm map ptrs Signed-off-by: James Cherry <[email protected]> commit ca6e9ecb7821b83ab024c4fee6df8f7fc8fc2ce2 Author: James Cherry <[email protected]> Date: Sun Jan 15 07:38:12 2023 -0700 instance_pvt_maps_ Signed-off-by: James Cherry <[email protected]> commit 631e4209b596386f5818045d521784db5239f58d Author: James Cherry <[email protected]> Date: Sun Jan 15 07:26:42 2023 -0700 rm GroupPathIterator Signed-off-by: James Cherry <[email protected]> commit 059c32afa87617fff530c9afa1ef8005a136739d Author: James Cherry <[email protected]> Date: Sat Jan 14 20:07:44 2023 -0700 rm ClockIterator Signed-off-by: James Cherry <[email protected]> commit c65fe873a6a6696220bbb44c4ecac87d5ca978ac Author: James Cherry <[email protected]> Date: Sat Jan 14 19:45:58 2023 -0700 rvo Signed-off-by: James Cherry <[email protected]> commit ce15c9a0cc78915acddc2f03749573d989ae96d6 Author: James Cherry <[email protected]> Date: Sun Jan 15 01:04:03 2023 +0000 leaks commit f97955a0c7e70b65ceb3f697ff47c0524a9b3cd4 Author: James Cherry <[email protected]> Date: Sat Jan 14 01:17:58 2023 +0000 leaks commit 7cdd65684adeb14e02827f5d93e7fab3b19af5dd Author: James Cherry <[email protected]> Date: Fri Jan 13 16:07:47 2023 -0700 leaks Signed-off-by: James Cherry <[email protected]> commit ee97c7e50394a3927458e7ef09c5dbeb27719d15 Author: James Cherry <[email protected]> Date: Fri Jan 13 11:52:48 2023 -0700 swig rm Tmp collections Signed-off-by: James Cherry <[email protected]> commit c49935da8704e41459280971b7645fccd97e3d13 Author: James Cherry <[email protected]> Date: Fri Jan 13 11:18:36 2023 -0700 swig rm Tmp types Signed-off-by: James Cherry <[email protected]> commit 4320b00ce700914843006f592126cd8cc1c4657a Author: James Cherry <[email protected]> Date: Fri Jan 13 10:55:10 2023 -0700 swig rm TmpPinSet, TmpPinSeq Signed-off-by: James Cherry <[email protected]> commit ff6004910980c9b09b41f63a553a4481404cc539 Author: James Cherry <[email protected]> Date: Fri Jan 13 10:45:06 2023 -0700 swig rm Tmp collections Signed-off-by: James Cherry <[email protected]> commit 9a5bf5c1a3e5a6d2996b3ab327fa2f3015f2ff20 Author: James Cherry <[email protected]> Date: Fri Jan 13 10:15:29 2023 -0700 swig rm one TmpPinSet Signed-off-by: James Cherry <[email protected]> commit f441116b56e23849485b2393b30e7086c33165a8 Author: James Cherry <[email protected]> Date: Fri Jan 13 09:16:56 2023 -0700 leak Signed-off-by: James Cherry <[email protected]> commit 050b08df8618340b568d9cd41fd3d5f052e2c680 Author: James Cherry <[email protected]> Date: Fri Jan 13 09:10:53 2023 -0700 leak Signed-off-by: James Cherry <[email protected]> commit be8c17f3a715ab53140748dc1d94698209965cf9 Author: James Cherry <[email protected]> Date: Fri Jan 13 08:59:06 2023 -0700 leak Signed-off-by: James Cherry <[email protected]> commit e43b82f8fb52eaeda90e3c7e76cf350ae6735ebd Author: James Cherry <[email protected]> Date: Thu Jan 12 18:57:49 2023 -0700 range iter Signed-off-by: James Cherry <[email protected]> commit 8db56209de7805ac2574fd2f76170bf68afd156d Author: James Cherry <[email protected]> Date: Thu Jan 12 18:08:54 2023 -0700 GroupPathSet net id Signed-off-by: James Cherry <[email protected]> commit cb7917f9827c2ea3afebd735cd4508405a0d77d4 Author: James Cherry <[email protected]> Date: Thu Jan 12 12:00:15 2023 -0700 DataCheckLess net id Signed-off-by: James Cherry <[email protected]> commit d9da3c62d7a76699c6ad62cebb1f5c39f89722fa Author: James Cherry <[email protected]> Date: Thu Jan 12 11:42:27 2023 -0700 rm hashPtr uses Signed-off-by: James Cherry <[email protected]> commit 5bbea162bb1e023aba813598c7992c740ddf9d0b Author: James Cherry <[email protected]> Date: Thu Jan 12 11:30:12 2023 -0700 EdgePins has use net id Signed-off-by: James Cherry <[email protected]> commit df38405e2ebaabdd7bbf99f3b19d78b25bd95720 Author: James Cherry <[email protected]> Date: Thu Jan 12 09:51:38 2023 -0700 ExceptionPath hash use net id Signed-off-by: James Cherry <[email protected]> commit 9a6dcfa54c54c9f50b14248a2449c70c20a0d977 Author: James Cherry <[email protected]> Date: Thu Jan 12 08:56:49 2023 -0700 ClockInsertion, ClockLatency net id Signed-off-by: James Cherry <[email protected]> commit dbb6dc0b8c93812458df31e93f08e0dbd74e8105 Author: James Cherry <[email protected]> Date: Thu Jan 12 08:34:03 2023 -0700 ExceptionStateSet obj id Signed-off-by: James Cherry <[email protected]> commit 70b8721c48ec0816289ee09b664c332ee095875f Author: James Cherry <[email protected]> Date: Thu Jan 12 08:14:37 2023 -0700 ClockGroups cmp Signed-off-by: James Cherry <[email protected]> commit 4c6c4ca191a99cd8541e106fec3202ee14968f39 Author: James Cherry <[email protected]> Date: Thu Jan 12 07:38:17 2023 -0700 ClockGroup typedef to ClockSet Signed-off-by: James Cherry <[email protected]> commit 66f425315e16deee5f00b05c0a505766e7afbf01 Author: James Cherry <[email protected]> Date: Wed Jan 11 20:32:38 2023 -0700 set cmps Signed-off-by: James Cherry <[email protected]> commit a94866c7828af5b6714e3e4fffc13bdaf5155c0e Author: James Cherry <[email protected]> Date: Wed Jan 11 19:08:09 2023 -0700 net use id Signed-off-by: James Cherry <[email protected]> commit 6348320908f42ebb5262117182e13d0024f65537 Author: James Cherry <[email protected]> Date: Wed Jan 11 11:52:13 2023 -0700 exception id cmp Signed-off-by: James Cherry <[email protected]> commit 0edfca41b6d6408ac17f8dfe10e697c55146c1ef Author: James Cherry <[email protected]> Date: Wed Jan 11 10:47:02 2023 -0700 range iter Signed-off-by: James Cherry <[email protected]> commit 44ad77985da9f0b9e7f4780e3f233c8d94fa7db7 Author: James Cherry <[email protected]> Date: Wed Jan 11 08:27:58 2023 -0700 non-ptr set cmp Signed-off-by: James Cherry <[email protected]> commit 36de7d88c3fa683465604a9e16b2fc1f6bc5fdd0 Author: James Cherry <[email protected]> Date: Wed Jan 11 08:00:54 2023 -0700 range iteration Signed-off-by: James Cherry <[email protected]> commit 4a31a2c8d9bdae58b09af8c05a64702ea3ac6c15 Author: James Cherry <[email protected]> Date: Tue Jan 10 16:43:54 2023 -0700 tcl types Signed-off-by: James Cherry <[email protected]> commit 056a7447b494a4c8ecc9764650d78a5bed3d87e8 Author: James Cherry <[email protected]> Date: Tue Jan 10 16:10:36 2023 -0700 tcl types Signed-off-by: James Cherry <[email protected]> commit 97239554c7625ba50ee729260f08eda7dec02365 Author: James Cherry <[email protected]> Date: Tue Jan 10 13:10:42 2023 -0700 use RVO Signed-off-by: James Cherry <[email protected]> commit c3247d8937d483102e3e1f2b69d7ac1d331ba9d4 Author: James Cherry <[email protected]> Date: Mon Jan 9 22:41:20 2023 -0700 swig template seq's Signed-off-by: James Cherry <[email protected]> commit 5431c06feb256adb46858819fcf5d513cfa6b5ec Author: James Cherry <[email protected]> Date: Mon Jan 9 20:50:24 2023 -0700 swig set in template Signed-off-by: James Cherry <[email protected]> commit 592ad641bf01d3beb862314a0d8986f66e258642 Author: James Cherry <[email protected]> Date: Mon Jan 9 17:27:25 2023 -0700 network return containers Signed-off-by: James Cherry <[email protected]> commit c95f8b77e0d6bd5ffa5ba8102413c70883c756e1 Author: James Cherry <[email protected]> Date: Mon Jan 9 12:15:37 2023 -0700 PinSeq const Signed-off-by: James Cherry <[email protected]> commit 702e7f9ba2f901066a38f32e67b35602b6c7bbdf Author: James Cherry <[email protected]> Date: Mon Jan 9 12:02:29 2023 -0700 InstanceSeq const Signed-off-by: James Cherry <[email protected]> commit 44fc25ba4a15e4ae570d74af27c9435872a126e0 Author: James Cherry <[email protected]> Date: Mon Jan 9 12:01:45 2023 -0700 NetSeq const Signed-off-by: James Cherry <[email protected]> commit 03b2725c81f5d52c33c875b55056c11d482144f1 Author: James Cherry <[email protected]> Date: Mon Jan 9 11:33:18 2023 -0700 rm PortPair Signed-off-by: James Cherry <[email protected]> commit 3fb82a7344dc053171c9883a113764ba691ab827 Author: James Cherry <[email protected]> Date: Mon Jan 9 11:20:53 2023 -0700 PinSet id Signed-off-by: James Cherry <[email protected]> commit 3dd31f027e15d40d62a11d0a88ef2a115f01fb73 Author: James Cherry <[email protected]> Date: Sun Jan 8 15:03:33 2023 -0700 InstanceSet id Signed-off-by: James Cherry <[email protected]> commit a91dea5cc0af3bede36b3faed13adb05239ff907 Author: James Cherry <[email protected]> Date: Sun Jan 8 11:40:15 2023 -0700 NetSet id Signed-off-by: James Cherry <[email protected]> commit b91e4b6410134eccae7969ddcfb0b27933b2e746 Author: James Cherry <[email protected]> Date: Sun Jan 8 10:44:47 2023 -0700 CellSet, PortSet id Signed-off-by: James Cherry <[email protected]> commit 6f891f77fae5a6b19c1454a1a4b4e3dfae0b5c50 Author: James Cherry <[email protected]> Date: Sun Jan 8 10:29:25 2023 -0700 network object sets Signed-off-by: James Cherry <[email protected]> commit eb8c627a57ecc6e7c5846a01d62b090ff91c08bf Author: James Cherry <[email protected]> Date: Sun Jan 8 10:09:00 2023 -0700 PinSet1 Signed-off-by: James Cherry <[email protected]> commit 8e864ecbdf87000fbb3c3097c39f06173c941e35 Author: James Cherry <[email protected]> Date: Sat Jan 7 17:13:03 2023 -0700 concrete network object id Signed-off-by: James Cherry <[email protected]> Signed-off-by: James Cherry <[email protected]>
This commit is contained in:
James Cherry
+12
-12
@@ -60,16 +60,16 @@ public:
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virtual void inputPortDelay(const Pin *port_pin,
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float in_slew,
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const RiseFall *rf,
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Parasitic *parasitic,
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const Parasitic *parasitic,
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const DcalcAnalysisPt *dcalc_ap) = 0;
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// Find the delay and slew for arc driving drvr_pin.
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virtual void gateDelay(const LibertyCell *drvr_cell,
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TimingArc *arc,
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const TimingArc *arc,
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const Slew &in_slew,
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// Pass in load_cap or drvr_parasitic.
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float load_cap,
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Parasitic *drvr_parasitic,
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const Parasitic *drvr_parasitic,
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float related_out_cap,
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const Pvt *pvt,
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const DcalcAnalysisPt *dcalc_ap,
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@@ -85,10 +85,10 @@ public:
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virtual void setMultiDrvrSlewFactor(float factor) = 0;
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// Ceff for parasitics with pi models.
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virtual float ceff(const LibertyCell *drvr_cell,
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TimingArc *arc,
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const TimingArc *arc,
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const Slew &in_slew,
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float load_cap,
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Parasitic *drvr_parasitic,
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const Parasitic *drvr_parasitic,
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float related_out_cap,
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const Pvt *pvt,
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const DcalcAnalysisPt *dcalc_ap) = 0;
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@@ -96,7 +96,7 @@ public:
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// Find the delay for a timing check arc given the arc's
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// from/clock, to/data slews and related output pin parasitic.
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virtual void checkDelay(const LibertyCell *drvr_cell,
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TimingArc *arc,
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const TimingArc *arc,
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const Slew &from_slew,
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const Slew &to_slew,
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float related_out_cap,
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@@ -106,11 +106,11 @@ public:
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ArcDelay &margin) = 0;
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// Report delay and slew calculation.
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virtual void reportGateDelay(const LibertyCell *drvr_cell,
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TimingArc *arc,
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const TimingArc *arc,
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const Slew &in_slew,
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// Pass in load_cap or drvr_parasitic.
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float load_cap,
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Parasitic *drvr_parasitic,
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const Parasitic *drvr_parasitic,
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float related_out_cap,
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const Pvt *pvt,
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const DcalcAnalysisPt *dcalc_ap,
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@@ -118,7 +118,7 @@ public:
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string *result) = 0;
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// Report timing check delay calculation.
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virtual void reportCheckDelay(const LibertyCell *cell,
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TimingArc *arc,
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const TimingArc *arc,
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const Slew &from_slew,
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const char *from_slew_annotation,
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const Slew &to_slew,
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@@ -130,11 +130,11 @@ public:
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virtual void finishDrvrPin() = 0;
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protected:
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GateTimingModel *gateModel(TimingArc *arc,
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GateTimingModel *gateModel(const TimingArc *arc,
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const DcalcAnalysisPt *dcalc_ap) const;
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CheckTimingModel *checkModel(TimingArc *arc,
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CheckTimingModel *checkModel(const TimingArc *arc,
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const DcalcAnalysisPt *dcalc_ap) const;
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TimingModel *model(TimingArc *arc,
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TimingModel *model(const TimingArc *arc,
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const DcalcAnalysisPt *dcalc_ap) const;
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};
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@@ -26,7 +26,7 @@
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namespace sta {
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typedef Map<const Pin*, ClockSet> PinClksMap;
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typedef Map<const Clock *, PinSet> ClkPinsMap;
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typedef Map<const Clock *, PinSet*> ClkPinsMap;
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class Sta;
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@@ -36,6 +36,7 @@ class ClkNetwork : public StaState
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{
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public:
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ClkNetwork(StaState *sta);
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~ClkNetwork();
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void ensureClkNetwork();
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void clear();
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bool isClock(const Pin *pin) const;
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+18
-15
@@ -34,7 +34,6 @@ public:
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float period() const { return period_; }
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// Virtual clocks have no pins.
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bool isVirtual() const;
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PinSet &pins() { return pins_; }
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const PinSet &pins() const { return pins_; }
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// The clock source pin's leaf pins.
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// If the source pin is hierarchical, the leaf pins are:
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@@ -44,7 +43,7 @@ public:
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const PinSet &leafPins() const { return leaf_pins_; }
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// Clock pin used by input/output delay for propagated generated
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// clock insertion delay.
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Pin *defaultPin() const;
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const Pin *defaultPin() const;
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bool addToPins() const { return add_to_pins_; }
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void setAddToPins(bool add_to_pins);
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FloatSeq *waveform() { return waveform_; }
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@@ -69,7 +68,7 @@ public:
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const MinMaxAll *min_max,
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float slew);
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void removeSlew();
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RiseFallMinMax *slews() { return &slews_; }
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const RiseFallMinMax &slews() const { return slews_; }
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void setSlewLimit(const RiseFallBoth *rf,
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const PathClkOrData clk_data,
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const MinMax *min_max,
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@@ -94,8 +93,8 @@ public:
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void setPeriod(float period);
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void setWaveform(FloatSeq *waveform);
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void addPin(Pin *pin);
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void deletePin(Pin *pin);
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void addPin(const Pin *pin);
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void deletePin(const Pin *pin);
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void makeLeafPins(const Network *network);
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bool isGenerated() const;
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@@ -123,9 +122,10 @@ public:
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void waveformInvalid();
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protected:
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// Private to Constraints::makeClock.
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// Private to Sdc::makeClock.
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Clock(const char *name,
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int index);
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int index,
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const Network *network);
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void initClk(PinSet *pins,
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bool add_to_pins,
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float period,
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@@ -218,16 +218,17 @@ int
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clkCmp(const Clock *clk1,
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const Clock *clk2);
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int
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clkEdgeCmp(ClockEdge *clk_edge1,
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ClockEdge *clk_edge2);
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clkEdgeCmp(const ClockEdge *clk_edge1,
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const ClockEdge *clk_edge2);
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bool
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clkEdgeLess(ClockEdge *clk_edge1,
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ClockEdge *clk_edge2);
|
||||
clkEdgeLess(const ClockEdge *clk_edge1,
|
||||
const ClockEdge *clk_edge2);
|
||||
|
||||
class ClockNameLess
|
||||
{
|
||||
public:
|
||||
bool operator()(const Clock *clk1, const Clock *clk2);
|
||||
bool operator()(const Clock *clk1,
|
||||
const Clock *clk2);
|
||||
};
|
||||
|
||||
////////////////////////////////////////////////////////////////
|
||||
@@ -278,8 +279,10 @@ public:
|
||||
}
|
||||
};
|
||||
|
||||
void
|
||||
sortClockSet(ClockSet * set,
|
||||
ClockSeq &clks);
|
||||
ClockSeq
|
||||
sortByName(ClockSet *set);
|
||||
int
|
||||
compare(const ClockSet *set1,
|
||||
const ClockSet *set2);
|
||||
|
||||
} // namespace
|
||||
|
||||
@@ -21,18 +21,6 @@
|
||||
|
||||
namespace sta {
|
||||
|
||||
class ClockGroup
|
||||
{
|
||||
public:
|
||||
ClockGroup(ClockSet *clks);
|
||||
~ClockGroup();
|
||||
bool isMember(const Clock *clk);
|
||||
ClockSet *clks() const { return clks_; }
|
||||
|
||||
private:
|
||||
ClockSet *clks_;
|
||||
};
|
||||
|
||||
class ClockGroups : public SdcCmdComment
|
||||
{
|
||||
public:
|
||||
@@ -43,7 +31,7 @@ public:
|
||||
bool allow_paths,
|
||||
const char *comment);
|
||||
~ClockGroups();
|
||||
ClockGroup *makeClockGroup(ClockSet *clks);
|
||||
void makeClockGroup(ClockSet *clks);
|
||||
const char *name() const { return name_; }
|
||||
ClockGroupSet *groups() { return &groups_; }
|
||||
bool logicallyExclusive() const { return logically_exclusive_; }
|
||||
|
||||
@@ -53,6 +53,7 @@ public:
|
||||
virtual ~ConcreteLibrary();
|
||||
const char *name() const { return name_; }
|
||||
void setName(const char *name);
|
||||
ObjectId id() const { return id_; }
|
||||
bool isLiberty() const { return is_liberty_; }
|
||||
const char *filename() const { return filename_; }
|
||||
void addCell(ConcreteCell *cell);
|
||||
@@ -62,8 +63,7 @@ public:
|
||||
void deleteCell(ConcreteCell *cell);
|
||||
ConcreteLibraryCellIterator *cellIterator() const;
|
||||
ConcreteCell *findCell(const char *name) const;
|
||||
void findCellsMatching(const PatternMatch *pattern,
|
||||
CellSeq *cells) const;
|
||||
CellSeq findCellsMatching(const PatternMatch *pattern) const;
|
||||
char busBrktLeft() const { return bus_brkt_left_; }
|
||||
char busBrktRight() const { return bus_brkt_right_; }
|
||||
void setBusBrkts(char left,
|
||||
@@ -74,6 +74,7 @@ protected:
|
||||
const char *cell_name);
|
||||
|
||||
const char *name_;
|
||||
ObjectId id_;
|
||||
const char *filename_;
|
||||
bool is_liberty_;
|
||||
char bus_brkt_left_;
|
||||
@@ -89,17 +90,17 @@ class ConcreteCell
|
||||
public:
|
||||
// Use ConcreteLibrary::deleteCell.
|
||||
virtual ~ConcreteCell();
|
||||
ConcreteLibrary *library() const { return library_; }
|
||||
const char *name() const { return name_; }
|
||||
ObjectId id() const { return id_; }
|
||||
const char *filename() const { return filename_; }
|
||||
ConcreteLibrary *library() const { return library_; }
|
||||
LibertyCell *libertyCell() const { return liberty_cell_; }
|
||||
void setLibertyCell(LibertyCell *cell);
|
||||
void *extCell() const { return ext_cell_; }
|
||||
void setExtCell(void *ext_cell);
|
||||
int portBitCount() const { return port_bit_count_; }
|
||||
ConcretePort *findPort(const char *name) const;
|
||||
void findPortsMatching(const PatternMatch *pattern,
|
||||
PortSeq *ports) const;
|
||||
PortSeq findPortsMatching(const PatternMatch *pattern) const;
|
||||
ConcreteCellPortIterator *portIterator() const;
|
||||
ConcreteCellPortBitIterator *portBitIterator() const;
|
||||
bool isLeaf() const { return is_leaf_; }
|
||||
@@ -124,10 +125,10 @@ public:
|
||||
void addPortBit(ConcretePort *port);
|
||||
|
||||
protected:
|
||||
ConcreteCell(ConcreteLibrary *library,
|
||||
const char *name,
|
||||
bool is_leaf,
|
||||
const char *filename);
|
||||
ConcreteCell(const char *name,
|
||||
const char *filename,
|
||||
bool is_leaf,
|
||||
ConcreteLibrary *library);
|
||||
ConcretePort *makeBusPort(const char *name,
|
||||
int from_index,
|
||||
int to_index,
|
||||
@@ -143,10 +144,11 @@ protected:
|
||||
const char *name,
|
||||
int index);
|
||||
|
||||
ConcreteLibrary *library_;
|
||||
const char *name_;
|
||||
ObjectId id_;
|
||||
// Filename is optional.
|
||||
const char *filename_;
|
||||
ConcreteLibrary *library_;
|
||||
LibertyCell *liberty_cell_;
|
||||
// External application cell.
|
||||
void *ext_cell_;
|
||||
@@ -167,6 +169,7 @@ class ConcretePort
|
||||
public:
|
||||
virtual ~ConcretePort();
|
||||
const char *name() const { return name_; }
|
||||
ObjectId id() const { return id_; }
|
||||
const char *busName() const;
|
||||
Cell *cell() const;
|
||||
ConcreteLibrary *library() const { return cell_->library(); }
|
||||
@@ -212,15 +215,16 @@ public:
|
||||
|
||||
protected:
|
||||
// Constructors for factory in cell class.
|
||||
ConcretePort(ConcreteCell *cell,
|
||||
const char *name,
|
||||
bool is_bus,
|
||||
ConcretePort(const char *name,
|
||||
bool is_bus,
|
||||
int from_index,
|
||||
int to_index,
|
||||
bool is_bundle,
|
||||
ConcretePortSeq *member_ports);
|
||||
ConcretePortSeq *member_ports,
|
||||
ConcreteCell *cell);
|
||||
|
||||
const char *name_;
|
||||
ObjectId id_;
|
||||
ConcreteCell *cell_;
|
||||
PortDirection *direction_;
|
||||
LibertyPort *liberty_port_;
|
||||
|
||||
@@ -60,20 +60,21 @@ public:
|
||||
Report *report);
|
||||
virtual Instance *topInstance() const;
|
||||
|
||||
virtual const char *name(const Library *library) const;
|
||||
virtual ObjectId id(const Library *library) const;
|
||||
virtual LibraryIterator *libraryIterator() const;
|
||||
virtual LibertyLibraryIterator *libertyLibraryIterator() const ;
|
||||
virtual Library *findLibrary(const char *name);
|
||||
virtual const char *name(const Library *library) const;
|
||||
virtual LibertyLibrary *findLiberty(const char *name);
|
||||
virtual LibertyLibrary *libertyLibrary(Library *library) const;
|
||||
virtual Cell *findCell(const Library *library,
|
||||
const char *name) const;
|
||||
virtual Cell *findAnyCell(const char *name);
|
||||
virtual void findCellsMatching(const Library *library,
|
||||
const PatternMatch *pattern,
|
||||
CellSeq *cells) const;
|
||||
virtual CellSeq findCellsMatching(const Library *library,
|
||||
const PatternMatch *pattern) const;
|
||||
|
||||
virtual const char *name(const Cell *cell) const;
|
||||
virtual ObjectId id(const Cell *cell) const;
|
||||
virtual Library *library(const Cell *cell) const;
|
||||
virtual LibertyCell *libertyCell(Cell *cell) const;
|
||||
virtual const LibertyCell *libertyCell(const Cell *cell) const;
|
||||
@@ -82,15 +83,15 @@ public:
|
||||
virtual const char *filename(const Cell *cell);
|
||||
virtual Port *findPort(const Cell *cell,
|
||||
const char *name) const;
|
||||
virtual void findPortsMatching(const Cell *cell,
|
||||
const PatternMatch *pattern,
|
||||
PortSeq *ports) const;
|
||||
virtual PortSeq findPortsMatching(const Cell *cell,
|
||||
const PatternMatch *pattern) const;
|
||||
virtual bool isLeaf(const Cell *cell) const;
|
||||
virtual CellPortIterator *portIterator(const Cell *cell) const;
|
||||
virtual CellPortBitIterator *portBitIterator(const Cell *cell) const;
|
||||
virtual int portBitCount(const Cell *cell) const;
|
||||
|
||||
virtual const char *name(const Port *port) const;
|
||||
virtual ObjectId id(const Port *port) const;
|
||||
virtual Cell *cell(const Port *port) const;
|
||||
virtual LibertyPort *libertyPort(const Port *port) const;
|
||||
virtual PortDirection *direction(const Port *port) const;
|
||||
@@ -109,6 +110,7 @@ public:
|
||||
virtual PortMemberIterator *memberIterator(const Port *port) const;
|
||||
|
||||
virtual const char *name(const Instance *instance) const;
|
||||
virtual ObjectId id(const Instance *instance) const;
|
||||
virtual Cell *cell(const Instance *instance) const;
|
||||
virtual Instance *parent(const Instance *instance) const;
|
||||
virtual bool isLeaf(const Instance *instance) const;
|
||||
@@ -126,6 +128,7 @@ public:
|
||||
virtual InstanceNetIterator *
|
||||
netIterator(const Instance *instance) const;
|
||||
|
||||
virtual ObjectId id(const Pin *pin) const;
|
||||
virtual Instance *instance(const Pin *pin) const;
|
||||
virtual Net *net(const Pin *pin) const;
|
||||
virtual Term *term(const Pin *pin) const;
|
||||
@@ -135,15 +138,17 @@ public:
|
||||
virtual void setVertexId(Pin *pin,
|
||||
VertexId id);
|
||||
|
||||
virtual ObjectId id(const Term *term) const;
|
||||
virtual Net *net(const Term *term) const;
|
||||
virtual Pin *pin(const Term *term) const;
|
||||
|
||||
virtual const char *name(const Net *net) const;
|
||||
virtual ObjectId id(const Net *net) const;
|
||||
virtual Net *findNet(const Instance *instance,
|
||||
const char *net_name) const;
|
||||
virtual void findInstNetsMatching(const Instance *instance,
|
||||
const PatternMatch *pattern,
|
||||
NetSeq *nets) const;
|
||||
virtual const char *name(const Net *net) const;
|
||||
const PatternMatch *pattern,
|
||||
NetSeq &matches) const;
|
||||
virtual Instance *instance(const Net *net) const;
|
||||
virtual bool isPower(const Net *net) const;
|
||||
virtual bool isGround(const Net *net) const;
|
||||
@@ -227,6 +232,8 @@ public:
|
||||
virtual void setLinkFunc(LinkNetworkFunc *link);
|
||||
void setTopInstance(Instance *top_inst);
|
||||
|
||||
static ObjectId nextObjectId();
|
||||
|
||||
using Network::netIterator;
|
||||
using Network::findPin;
|
||||
using Network::findNet;
|
||||
@@ -242,7 +249,7 @@ protected:
|
||||
void clearConstantNets();
|
||||
virtual void visitConnectedPins(const Net *net,
|
||||
PinVisitor &visitor,
|
||||
ConstNetSet &visited_nets) const;
|
||||
NetSet &visited_nets) const;
|
||||
Instance *makeConcreteInstance(ConcreteCell *cell,
|
||||
const char *name,
|
||||
Instance *parent);
|
||||
@@ -258,6 +265,7 @@ protected:
|
||||
NetSet constant_nets_[2]; // LogicValue::zero/one
|
||||
LinkNetworkFunc *link_func_;
|
||||
CellNetworkViewMap cell_network_view_map_;
|
||||
static ObjectId object_id_;
|
||||
|
||||
private:
|
||||
friend class ConcreteLibertyLibraryIterator;
|
||||
@@ -267,13 +275,14 @@ class ConcreteInstance
|
||||
{
|
||||
public:
|
||||
const char *name() const { return name_; }
|
||||
ObjectId id() const { return id_; }
|
||||
Cell *cell() const;
|
||||
ConcreteInstance *parent() const { return parent_; }
|
||||
ConcretePin *findPin(const char *port_name) const;
|
||||
ConcretePin *findPin(const Port *port) const;
|
||||
ConcreteNet *findNet(const char *net_name) const;
|
||||
void findNetsMatching(const PatternMatch *pattern,
|
||||
NetSeq *nets) const;
|
||||
NetSeq &matches) const;
|
||||
InstanceNetIterator *netIterator() const;
|
||||
Instance *findChild(const char *name) const;
|
||||
InstanceChildIterator *childIterator() const;
|
||||
@@ -289,13 +298,14 @@ public:
|
||||
void initPins();
|
||||
|
||||
protected:
|
||||
ConcreteInstance(ConcreteCell *cell,
|
||||
const char *name,
|
||||
ConcreteInstance *parent);
|
||||
ConcreteInstance(const char *name,
|
||||
ConcreteCell *cell,
|
||||
ConcreteInstance *parent);
|
||||
~ConcreteInstance();
|
||||
|
||||
ConcreteCell *cell_;
|
||||
const char *name_;
|
||||
ObjectId id_;
|
||||
ConcreteCell *cell_;
|
||||
ConcreteInstance *parent_;
|
||||
// Array of pins indexed by pin->port->index().
|
||||
ConcretePin **pins_;
|
||||
@@ -315,6 +325,7 @@ public:
|
||||
ConcreteNet *net() const { return net_; }
|
||||
ConcretePort *port() const { return port_; }
|
||||
ConcreteTerm *term() const { return term_; }
|
||||
ObjectId id() const { return id_; }
|
||||
VertexId vertexId() const { return vertex_id_; }
|
||||
void setVertexId(VertexId id);
|
||||
|
||||
@@ -328,6 +339,7 @@ protected:
|
||||
ConcretePort *port_;
|
||||
ConcreteNet *net_;
|
||||
ConcreteTerm *term_;
|
||||
ObjectId id_;
|
||||
// Doubly linked list of net pins.
|
||||
ConcretePin *net_next_;
|
||||
ConcretePin *net_prev_;
|
||||
@@ -343,6 +355,7 @@ class ConcreteTerm
|
||||
{
|
||||
public:
|
||||
const char *name() const;
|
||||
ObjectId id() const { return id_; }
|
||||
ConcreteNet *net() const { return net_; }
|
||||
ConcretePin *pin() const { return pin_; }
|
||||
|
||||
@@ -353,6 +366,7 @@ protected:
|
||||
|
||||
ConcretePin *pin_;
|
||||
ConcreteNet *net_;
|
||||
ObjectId id_;
|
||||
// Linked list of net terms.
|
||||
ConcreteTerm *net_next_;
|
||||
|
||||
@@ -366,6 +380,7 @@ class ConcreteNet
|
||||
{
|
||||
public:
|
||||
const char *name() const { return name_; }
|
||||
ObjectId id() const { return id_; }
|
||||
ConcreteInstance *instance() const { return instance_; }
|
||||
void addPin(ConcretePin *pin);
|
||||
void deletePin(ConcretePin *pin);
|
||||
@@ -379,6 +394,7 @@ protected:
|
||||
ConcreteInstance *instance);
|
||||
~ConcreteNet();
|
||||
const char *name_;
|
||||
ObjectId id_;
|
||||
ConcreteInstance *instance_;
|
||||
// Pointer to head of linked list of pins.
|
||||
ConcretePin *pins_;
|
||||
|
||||
@@ -25,8 +25,6 @@
|
||||
|
||||
namespace sta {
|
||||
|
||||
class PinPathNameLess;
|
||||
|
||||
class DataCheck
|
||||
{
|
||||
public:
|
||||
@@ -65,12 +63,12 @@ private:
|
||||
class DataCheckLess
|
||||
{
|
||||
public:
|
||||
explicit DataCheckLess(const Network *network);
|
||||
DataCheckLess(const Network *network);
|
||||
bool operator()(const DataCheck *check1,
|
||||
const DataCheck *check2) const;
|
||||
|
||||
private:
|
||||
PinPathNameLess pin_less_;
|
||||
const Network *network_;
|
||||
};
|
||||
|
||||
} // namespace
|
||||
|
||||
@@ -34,8 +34,7 @@ registerDelayCalc(const char *name,
|
||||
MakeArcDelayCalc maker);
|
||||
bool
|
||||
isDelayCalcName(const char *name);
|
||||
// Caller owns return value.
|
||||
StringSeq *
|
||||
StringSeq
|
||||
delayCalcNames();
|
||||
void
|
||||
deleteDelayCalcs();
|
||||
|
||||
@@ -29,7 +29,7 @@ class DisabledInstancePorts;
|
||||
|
||||
typedef Vector<DisabledInstancePorts*> DisabledInstancePortsSeq;
|
||||
typedef Vector<DisabledCellPorts*> DisabledCellPortsSeq;
|
||||
typedef Vector<LibertyPortPair*> LibertyPortPairSeq;
|
||||
typedef Vector<LibertyPortPair> LibertyPortPairSeq;
|
||||
typedef Set<TimingArcSet*> TimingArcSetSet;
|
||||
|
||||
// Base class for disabled cell and instance ports.
|
||||
@@ -93,15 +93,12 @@ private:
|
||||
Instance *inst_;
|
||||
};
|
||||
|
||||
void
|
||||
sortDisabledCellPortsMap(DisabledCellPortsMap *cell_map,
|
||||
DisabledCellPortsSeq &disables);
|
||||
void
|
||||
sortDisabledInstancePortsMap(DisabledInstancePortsMap *inst_map,
|
||||
Network *network,
|
||||
DisabledInstancePortsSeq &disables);
|
||||
void
|
||||
sortLibertyPortPairSet(LibertyPortPairSet *sets,
|
||||
LibertyPortPairSeq &pairs);
|
||||
DisabledCellPortsSeq
|
||||
sortByName(DisabledCellPortsMap *cell_map);
|
||||
DisabledInstancePortsSeq
|
||||
sortByPathName(const DisabledInstancePortsMap *inst_map,
|
||||
const Network *network);
|
||||
LibertyPortPairSeq
|
||||
sortByName(const LibertyPortPairSet *set);
|
||||
|
||||
} // namespace
|
||||
|
||||
@@ -314,22 +314,28 @@ public:
|
||||
virtual NetSet *nets() = 0;
|
||||
virtual EdgePinsSet *edges() = 0;
|
||||
size_t hash() const;
|
||||
virtual int nameCmp(ExceptionPt *pt, const Network *network) const = 0;
|
||||
virtual void mergeInto(ExceptionPt *pt) = 0;
|
||||
virtual int compare(ExceptionPt *pt,
|
||||
const Network *network) const = 0;
|
||||
virtual void mergeInto(ExceptionPt *pt,
|
||||
const Network *network) = 0;
|
||||
// All pins and instance/net pins.
|
||||
virtual void allPins(const Network *network,
|
||||
PinSet *pins) = 0;
|
||||
virtual int typePriority() const = 0;
|
||||
virtual const char *asString(const Network *network) const = 0;
|
||||
virtual size_t objectCount() const = 0;
|
||||
virtual void addPin(Pin *pin) = 0;
|
||||
virtual void addPin(const Pin *pin,
|
||||
const Network *network) = 0;
|
||||
virtual void addClock(Clock *clk) = 0;
|
||||
virtual void addInstance(Instance *inst) = 0;
|
||||
virtual void addNet(Net *net) = 0;
|
||||
virtual void addEdge(EdgePins *edge) = 0;
|
||||
virtual void addInstance(const Instance *inst,
|
||||
const Network *network) = 0;
|
||||
virtual void addNet(const Net *net,
|
||||
const Network *network) = 0;
|
||||
virtual void addEdge(const EdgePins &edge,
|
||||
const Network *network) = 0;
|
||||
virtual void connectPinAfter(PinSet *,
|
||||
Network *network) = 0;
|
||||
virtual void disconnectPinBefore(Pin *pin,
|
||||
virtual void disconnectPinBefore(const Pin *pin,
|
||||
Network *network) = 0;
|
||||
|
||||
protected:
|
||||
@@ -351,10 +357,12 @@ protected:
|
||||
class ExceptionFromTo : public ExceptionPt
|
||||
{
|
||||
public:
|
||||
ExceptionFromTo(PinSet *pins, ClockSet *clks,
|
||||
ExceptionFromTo(PinSet *pins,
|
||||
ClockSet *clks,
|
||||
InstanceSet *insts,
|
||||
const RiseFallBoth *rf,
|
||||
bool own_pts);
|
||||
bool own_pts,
|
||||
const Network *network);
|
||||
~ExceptionFromTo();
|
||||
virtual PinSet *pins() { return pins_; }
|
||||
bool hasPins() const;
|
||||
@@ -365,31 +373,39 @@ public:
|
||||
virtual NetSet *nets() { return nullptr; }
|
||||
virtual EdgePinsSet *edges() { return nullptr; }
|
||||
bool hasObjects() const;
|
||||
void deleteObjects(ExceptionFromTo *pt);
|
||||
void deleteObjects(ExceptionFromTo *pt,
|
||||
const Network *network);
|
||||
virtual void allPins(const Network *network,
|
||||
PinSet *pins);
|
||||
bool equal(ExceptionFromTo *from_to) const;
|
||||
virtual int nameCmp(ExceptionPt *pt,
|
||||
virtual int compare(ExceptionPt *pt,
|
||||
const Network *network) const;
|
||||
virtual void mergeInto(ExceptionPt *pt);
|
||||
virtual void mergeInto(ExceptionPt *pt,
|
||||
const Network *network);
|
||||
virtual const char *asString(const Network *network) const;
|
||||
virtual size_t objectCount() const;
|
||||
void deleteClock(Clock *clk);
|
||||
virtual void addPin(Pin *pin);
|
||||
virtual void addPin(const Pin *pin,
|
||||
const Network *network);
|
||||
virtual void addClock(Clock *clk);
|
||||
virtual void addInstance(Instance *inst);
|
||||
virtual void addNet(Net *) {}
|
||||
virtual void addEdge(EdgePins *) {}
|
||||
virtual void addInstance(const Instance *inst,
|
||||
const Network *network);
|
||||
virtual void addNet(const Net *,
|
||||
const Network *) {}
|
||||
virtual void addEdge(const EdgePins &,
|
||||
const Network *) {}
|
||||
virtual void connectPinAfter(PinSet *,
|
||||
Network *) {}
|
||||
virtual void disconnectPinBefore(Pin *,
|
||||
virtual void disconnectPinBefore(const Pin *,
|
||||
Network *) {}
|
||||
|
||||
protected:
|
||||
virtual void findHash();
|
||||
virtual void findHash(const Network *network);
|
||||
|
||||
void deletePin(Pin *pin);
|
||||
void deleteInstance(Instance *inst);
|
||||
void deletePin(const Pin *pin,
|
||||
const Network *network);
|
||||
void deleteInstance(const Instance *inst,
|
||||
const Network *network);
|
||||
virtual const char *cmdKeyword() const = 0;
|
||||
|
||||
PinSet *pins_;
|
||||
@@ -404,15 +420,16 @@ public:
|
||||
ClockSet *clks,
|
||||
InstanceSet *insts,
|
||||
const RiseFallBoth *rf,
|
||||
bool own_pts);
|
||||
ExceptionFrom *clone();
|
||||
bool own_pts,
|
||||
const Network *network);
|
||||
ExceptionFrom *clone(const Network *network);
|
||||
virtual bool isFrom() const { return true; }
|
||||
bool intersectsPts(ExceptionFrom *from) const;
|
||||
virtual int typePriority() const { return 0; }
|
||||
|
||||
protected:
|
||||
virtual const char *cmdKeyword() const;
|
||||
virtual void findHash();
|
||||
virtual void findHash(const Network *network);
|
||||
};
|
||||
|
||||
class ExceptionTo : public ExceptionFromTo
|
||||
@@ -425,8 +442,9 @@ public:
|
||||
const RiseFallBoth *rf,
|
||||
// -rise|-fall endpoint transition.
|
||||
const RiseFallBoth *end_rf,
|
||||
bool own_pts);
|
||||
ExceptionTo *clone();
|
||||
bool own_pts,
|
||||
const Network *network);
|
||||
ExceptionTo *clone(const Network *network);
|
||||
virtual bool isTo() const { return true; }
|
||||
const char *asString(const Network *network) const;
|
||||
const RiseFallBoth *endTransition() { return end_rf_; }
|
||||
@@ -446,7 +464,8 @@ public:
|
||||
const ClockEdge *clk_edge,
|
||||
const RiseFall *end_rf,
|
||||
const Network *network) const;
|
||||
virtual int nameCmp(ExceptionPt *pt, const Network *network) const;
|
||||
virtual int compare(ExceptionPt *pt,
|
||||
const Network *network) const;
|
||||
|
||||
protected:
|
||||
bool matches(const Pin *pin,
|
||||
@@ -479,7 +498,8 @@ public:
|
||||
InstanceSet *instances() { return insts_; }
|
||||
virtual ClockSet *clks() { return nullptr; }
|
||||
bool hasObjects() const;
|
||||
void deleteObjects(ExceptionThru *pt);
|
||||
void deleteObjects(ExceptionThru *pt,
|
||||
const Network *network);
|
||||
virtual void allPins(const Network *network,
|
||||
PinSet *pins);
|
||||
bool matches(const Pin *from_pin,
|
||||
@@ -487,41 +507,49 @@ public:
|
||||
const RiseFall *to_rf,
|
||||
const Network *network);
|
||||
bool equal(ExceptionThru *thru) const;
|
||||
virtual int nameCmp(ExceptionPt *pt,
|
||||
virtual int compare(ExceptionPt *pt,
|
||||
const Network *network) const;
|
||||
virtual void mergeInto(ExceptionPt *pt);
|
||||
virtual void mergeInto(ExceptionPt *pt,
|
||||
const Network *network);
|
||||
bool intersectsPts(ExceptionThru *thru) const;
|
||||
virtual int typePriority() const { return 2; }
|
||||
virtual size_t objectCount() const;
|
||||
virtual void connectPinAfter(PinSet *drvrs,
|
||||
Network *network);
|
||||
virtual void disconnectPinBefore(Pin *pin,
|
||||
virtual void disconnectPinBefore(const Pin *pin,
|
||||
Network *network);
|
||||
|
||||
protected:
|
||||
void findHash();
|
||||
virtual void addPin(Pin *pin);
|
||||
virtual void addEdge(EdgePins *edge);
|
||||
virtual void addNet(Net *net);
|
||||
virtual void addInstance(Instance *inst);
|
||||
void findHash(const Network *network);
|
||||
virtual void addPin(const Pin *pin,
|
||||
const Network *network);
|
||||
virtual void addEdge(const EdgePins &edge,
|
||||
const Network *network);
|
||||
virtual void addNet(const Net *net,
|
||||
const Network *network);
|
||||
virtual void addInstance(const Instance *inst,
|
||||
const Network *network);
|
||||
virtual void addClock(Clock *) {}
|
||||
void deletePin(Pin *pin);
|
||||
void deleteEdge(EdgePins *edge);
|
||||
void deleteNet(Net *net);
|
||||
void deleteInstance(Instance *inst);
|
||||
void deletePin(const Pin *pin,
|
||||
const Network *network);
|
||||
void deleteEdge(const EdgePins &edge);
|
||||
void deleteNet(const Net *net,
|
||||
const Network *network);
|
||||
void deleteInstance(const Instance *inst,
|
||||
const Network *network);
|
||||
void makeAllEdges(const Network *network);
|
||||
void makePinEdges(const Network *network);
|
||||
void makeNetEdges(const Network *network);
|
||||
void makeInstEdges(const Network *network);
|
||||
void makeHpinEdges(const Pin *pin,
|
||||
const Network *network);
|
||||
void makePinEdges(Pin *pin,
|
||||
void makePinEdges(const Pin *pin,
|
||||
const Network *network);
|
||||
void makeNetEdges(Net *net,
|
||||
void makeNetEdges(const Net *net,
|
||||
const Network *network);
|
||||
void makeInstEdges(Instance *inst,
|
||||
Network *network);
|
||||
void deletePinEdges(Pin *pin,
|
||||
void deletePinEdges(const Pin *pin,
|
||||
Network *network);
|
||||
void deleteNetEdges(Net *net,
|
||||
const Network *network);
|
||||
@@ -598,6 +626,7 @@ public:
|
||||
ExceptionThru *next_thru,
|
||||
int index);
|
||||
ExceptionPath *exception() { return exception_; }
|
||||
const ExceptionPath *exception() const { return exception_; }
|
||||
bool matchesNextThru(const Pin *from_pin,
|
||||
const Pin *to_pin,
|
||||
const RiseFall *to_rf,
|
||||
@@ -607,6 +636,7 @@ public:
|
||||
ExceptionThru *nextThru() const { return next_thru_; }
|
||||
ExceptionState *nextState() const { return next_state_; }
|
||||
void setNextState(ExceptionState *next_state);
|
||||
int index() const { return index_; }
|
||||
size_t hash() const;
|
||||
|
||||
private:
|
||||
@@ -623,22 +653,21 @@ public:
|
||||
virtual const char *what() const noexcept;
|
||||
};
|
||||
|
||||
class ExceptionPathLess
|
||||
{
|
||||
public:
|
||||
ExceptionPathLess(const Network *network);
|
||||
bool operator()(const ExceptionPath *except1,
|
||||
const ExceptionPath *except2) const;
|
||||
|
||||
private:
|
||||
const Network *network_;
|
||||
};
|
||||
|
||||
// Throws EmptyExpceptionPt it finds an empty exception point.
|
||||
void
|
||||
checkFromThrusTo(ExceptionFrom *from,
|
||||
ExceptionThruSeq *thrus,
|
||||
ExceptionTo *to);
|
||||
|
||||
void
|
||||
sortExceptions(ExceptionPathSet *set,
|
||||
ExceptionPathSeq &exceptions,
|
||||
Network *network);
|
||||
|
||||
bool
|
||||
intersects(PinSet *set1,
|
||||
PinSet *set2);
|
||||
bool
|
||||
intersects(ClockSet *set1,
|
||||
ClockSet *set2);
|
||||
|
||||
} // namespace
|
||||
|
||||
@@ -133,13 +133,13 @@ public:
|
||||
virtual Edge *makeEdge(Vertex *from,
|
||||
Vertex *to,
|
||||
TimingArcSet *arc_set);
|
||||
virtual void makeWireEdge(Pin *from_pin,
|
||||
Pin *to_pin);
|
||||
void makePinInstanceEdges(Pin *pin);
|
||||
virtual void makeWireEdge(const Pin *from_pin,
|
||||
const Pin *to_pin);
|
||||
void makePinInstanceEdges(const Pin *pin);
|
||||
void makeInstanceEdges(const Instance *inst);
|
||||
void makeWireEdgesToPin(Pin *to_pin);
|
||||
void makeWireEdgesThruPin(Pin *hpin);
|
||||
virtual void makeWireEdgesFromPin(Pin *drvr_pin);
|
||||
void makeWireEdgesToPin(const Pin *to_pin);
|
||||
void makeWireEdgesThruPin(const Pin *hpin);
|
||||
virtual void makeWireEdgesFromPin(const Pin *drvr_pin);
|
||||
virtual void deleteEdge(Edge *edge);
|
||||
virtual ArcDelay arcDelay(const Edge *edge,
|
||||
const TimingArc *arc,
|
||||
@@ -211,10 +211,10 @@ protected:
|
||||
bool is_reg_clk);
|
||||
virtual void makeEdgeArcDelays(Edge *edge);
|
||||
void makePinVertices(const Instance *inst);
|
||||
void makeWireEdgesFromPin(Pin *drvr_pin,
|
||||
void makeWireEdgesFromPin(const Pin *drvr_pin,
|
||||
PinSet &visited_drvrs);
|
||||
void makeWireEdges();
|
||||
virtual void makeInstDrvrWireEdges(Instance *inst,
|
||||
virtual void makeInstDrvrWireEdges(const Instance *inst,
|
||||
PinSet &visited_drvrs);
|
||||
virtual void makePortInstanceEdges(const Instance *inst,
|
||||
LibertyCell *cell,
|
||||
|
||||
@@ -52,6 +52,8 @@ nextMersenne(size_t n)
|
||||
size_t
|
||||
hashString(const char *str);
|
||||
|
||||
// Pointer hashing is strongly discouraged because it causes results to change
|
||||
// from run to run. Use Network::id functions instead.
|
||||
#if __WORDSIZE == 64
|
||||
#define hashPtr(ptr) (reinterpret_cast<intptr_t>(ptr) >> 3)
|
||||
#else
|
||||
|
||||
@@ -48,23 +48,23 @@ public:
|
||||
class HpinDrvrLoad
|
||||
{
|
||||
public:
|
||||
HpinDrvrLoad(Pin *drvr,
|
||||
Pin *load,
|
||||
HpinDrvrLoad(const Pin *drvr,
|
||||
const Pin *load,
|
||||
PinSet *hpins_from_drvr,
|
||||
PinSet *hpins_to_load);
|
||||
~HpinDrvrLoad();
|
||||
void report(const Network *network);
|
||||
HpinDrvrLoad(Pin *drvr,
|
||||
Pin *load);
|
||||
Pin *drvr() const { return drvr_; }
|
||||
Pin *load() const { return load_; }
|
||||
HpinDrvrLoad(const Pin *drvr,
|
||||
const Pin *load);
|
||||
const Pin *drvr() const { return drvr_; }
|
||||
const Pin *load() const { return load_; }
|
||||
PinSet *hpinsFromDrvr() { return hpins_from_drvr_; }
|
||||
PinSet *hpinsToLoad() { return hpins_to_load_; }
|
||||
void setDrvr(Pin *drvr);
|
||||
void setDrvr(const Pin *drvr);
|
||||
|
||||
private:
|
||||
Pin *drvr_;
|
||||
Pin *load_;
|
||||
const Pin *drvr_;
|
||||
const Pin *load_;
|
||||
PinSet *hpins_from_drvr_;
|
||||
PinSet *hpins_to_load_;
|
||||
};
|
||||
|
||||
+24
-24
@@ -47,20 +47,20 @@ public:
|
||||
bool hasDriveResistance(const RiseFall *rf,
|
||||
const MinMax *min_max);
|
||||
bool driveResistanceMinMaxEqual(const RiseFall *rf);
|
||||
void setDriveCell(LibertyLibrary *library,
|
||||
LibertyCell *cell,
|
||||
LibertyPort *from_port,
|
||||
void setDriveCell(const LibertyLibrary *library,
|
||||
const LibertyCell *cell,
|
||||
const LibertyPort *from_port,
|
||||
float *from_slews,
|
||||
LibertyPort *to_port,
|
||||
const LibertyPort *to_port,
|
||||
const RiseFallBoth *rf,
|
||||
const MinMaxAll *min_max);
|
||||
void driveCell(const RiseFall *rf,
|
||||
const MinMax *min_max,
|
||||
// Return values.
|
||||
LibertyCell *&cell,
|
||||
LibertyPort *&from_port,
|
||||
const LibertyCell *&cell,
|
||||
const LibertyPort *&from_port,
|
||||
float *&from_slews,
|
||||
LibertyPort *&to_port);
|
||||
const LibertyPort *&to_port);
|
||||
InputDriveCell *driveCell(const RiseFall *rf,
|
||||
const MinMax *min_max);
|
||||
bool hasDriveCell(const RiseFall *rf,
|
||||
@@ -83,29 +83,29 @@ private:
|
||||
class InputDriveCell
|
||||
{
|
||||
public:
|
||||
InputDriveCell(LibertyLibrary *library,
|
||||
LibertyCell *cell,
|
||||
LibertyPort *from_port,
|
||||
InputDriveCell(const LibertyLibrary *library,
|
||||
const LibertyCell *cell,
|
||||
const LibertyPort *from_port,
|
||||
float *from_slews,
|
||||
LibertyPort *to_port);
|
||||
LibertyLibrary *library() const { return library_; }
|
||||
void setLibrary(LibertyLibrary *library);
|
||||
LibertyCell *cell() const { return cell_; }
|
||||
void setCell(LibertyCell *cell);
|
||||
LibertyPort *fromPort() const { return from_port_; }
|
||||
void setFromPort(LibertyPort *from_port);
|
||||
const LibertyPort *to_port);
|
||||
const LibertyLibrary *library() const { return library_; }
|
||||
void setLibrary(const LibertyLibrary *library);
|
||||
const LibertyCell *cell() const { return cell_; }
|
||||
void setCell(const LibertyCell *cell);
|
||||
const LibertyPort *fromPort() const { return from_port_; }
|
||||
void setFromPort(const LibertyPort *from_port);
|
||||
float *fromSlews() { return from_slews_; }
|
||||
void setFromSlews(float *from_slews);
|
||||
LibertyPort *toPort() const { return to_port_; }
|
||||
void setToPort(LibertyPort *to_port);
|
||||
bool equal(InputDriveCell *drive) const;
|
||||
const LibertyPort *toPort() const { return to_port_; }
|
||||
void setToPort(const LibertyPort *to_port);
|
||||
bool equal(const InputDriveCell *drive) const;
|
||||
|
||||
private:
|
||||
LibertyLibrary *library_;
|
||||
LibertyCell *cell_;
|
||||
LibertyPort *from_port_;
|
||||
const LibertyLibrary *library_;
|
||||
const LibertyCell *cell_;
|
||||
const LibertyPort *from_port_;
|
||||
float from_slews_[RiseFall::index_count];
|
||||
LibertyPort *to_port_;
|
||||
const LibertyPort *to_port_;
|
||||
};
|
||||
|
||||
} // namespace
|
||||
|
||||
@@ -132,8 +132,7 @@ public:
|
||||
const char *filename);
|
||||
virtual ~LibertyLibrary();
|
||||
LibertyCell *findLibertyCell(const char *name) const;
|
||||
void findLibertyCellsMatching(PatternMatch *pattern,
|
||||
LibertyCellSeq *cells);
|
||||
LibertyCellSeq findLibertyCellsMatching(PatternMatch *pattern);
|
||||
// Liberty cells that are buffers.
|
||||
LibertyCellSeq *buffers();
|
||||
|
||||
@@ -398,8 +397,7 @@ public:
|
||||
LibertyLibrary *libertyLibrary() const { return liberty_library_; }
|
||||
LibertyLibrary *libertyLibrary() { return liberty_library_; }
|
||||
LibertyPort *findLibertyPort(const char *name) const;
|
||||
void findLibertyPortsMatching(PatternMatch *pattern,
|
||||
LibertyPortSeq *ports) const;
|
||||
LibertyPortSeq findLibertyPortsMatching(PatternMatch *pattern) const;
|
||||
bool hasInternalPorts() const { return has_internal_ports_; }
|
||||
LibertyPgPort *findPgPort(const char *name) const;
|
||||
size_t pgPortCount() const { return pg_port_map_.size(); }
|
||||
@@ -842,9 +840,8 @@ private:
|
||||
friend class LibertyReader;
|
||||
};
|
||||
|
||||
void
|
||||
sortLibertyPortSet(LibertyPortSet *set,
|
||||
LibertyPortSeq &ports);
|
||||
LibertyPortSeq
|
||||
sortByName(const LibertyPortSet *set);
|
||||
|
||||
class LibertyPortMemberIterator : public Iterator<LibertyPort*>
|
||||
{
|
||||
|
||||
@@ -151,8 +151,6 @@ public:
|
||||
class LibertyPortPairLess
|
||||
{
|
||||
public:
|
||||
bool operator()(const LibertyPortPair *pair1,
|
||||
const LibertyPortPair *pair2) const;
|
||||
bool operator()(const LibertyPortPair &pair1,
|
||||
const LibertyPortPair &pair2) const;
|
||||
};
|
||||
|
||||
@@ -98,6 +98,17 @@ public:
|
||||
delete iter.next();
|
||||
}
|
||||
|
||||
void
|
||||
deleteKeysContents()
|
||||
{
|
||||
for (auto key_value : this) {
|
||||
KEY key = key_value.first;
|
||||
VALUE value = key_value.second;
|
||||
delete key;
|
||||
delete value;
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
deleteArrayContents()
|
||||
{
|
||||
|
||||
+71
-71
@@ -31,7 +31,6 @@ class Report;
|
||||
class PatternMatch;
|
||||
class PinVisitor;
|
||||
|
||||
typedef Set<const Net*> ConstNetSet;
|
||||
typedef Map<const char*, LibertyLibrary*, CharPtrLess> LibertyLibraryMap;
|
||||
// Link network function returns top level instance.
|
||||
// Return nullptr if link fails.
|
||||
@@ -103,20 +102,19 @@ public:
|
||||
|
||||
////////////////////////////////////////////////////////////////
|
||||
// Library functions.
|
||||
virtual const char *name(const Library *library) const = 0;
|
||||
virtual ObjectId id(const Library *library) const = 0;
|
||||
virtual LibraryIterator *libraryIterator() const = 0;
|
||||
virtual LibertyLibraryIterator *libertyLibraryIterator() const = 0;
|
||||
virtual Library *findLibrary(const char *name) = 0;
|
||||
virtual LibertyLibrary *findLiberty(const char *name) = 0;
|
||||
// Find liberty library by filename.
|
||||
virtual LibertyLibrary *findLibertyFilename(const char *filename);
|
||||
virtual const char *name(const Library *library) const = 0;
|
||||
virtual Cell *findCell(const Library *library,
|
||||
const char *name) const = 0;
|
||||
// Search the design (non-liberty) libraries for cells matching pattern.
|
||||
virtual void findCellsMatching(const Library *library,
|
||||
const PatternMatch *pattern,
|
||||
// Return value.
|
||||
CellSeq *cells) const = 0;
|
||||
virtual CellSeq findCellsMatching(const Library *library,
|
||||
const PatternMatch *pattern) const = 0;
|
||||
// Search liberty libraries for cell name.
|
||||
virtual LibertyCell *findLibertyCell(const char *name) const;
|
||||
virtual LibertyLibrary *makeLibertyLibrary(const char *name,
|
||||
@@ -136,6 +134,7 @@ public:
|
||||
////////////////////////////////////////////////////////////////
|
||||
// Cell functions.
|
||||
virtual const char *name(const Cell *cell) const = 0;
|
||||
virtual ObjectId id(const Cell *cell) const = 0;
|
||||
virtual Library *library(const Cell *cell) const = 0;
|
||||
virtual LibertyLibrary *libertyLibrary(const Cell *cell) const;
|
||||
// Find the corresponding liberty cell.
|
||||
@@ -148,10 +147,8 @@ public:
|
||||
// Name can be a simple, bundle, bus, or bus bit name.
|
||||
virtual Port *findPort(const Cell *cell,
|
||||
const char *name) const = 0;
|
||||
virtual void findPortsMatching(const Cell *cell,
|
||||
const PatternMatch *pattern,
|
||||
// Return value.
|
||||
PortSeq *ports) const = 0;
|
||||
virtual PortSeq findPortsMatching(const Cell *cell,
|
||||
const PatternMatch *pattern) const = 0;
|
||||
virtual bool isLeaf(const Cell *cell) const = 0;
|
||||
virtual CellPortIterator *portIterator(const Cell *cell) const = 0;
|
||||
// Iterate over port bits (expanded buses).
|
||||
@@ -162,6 +159,7 @@ public:
|
||||
////////////////////////////////////////////////////////////////
|
||||
// Port functions
|
||||
virtual const char *name(const Port *port) const = 0;
|
||||
virtual ObjectId id(const Port *port) const = 0;
|
||||
virtual Cell *cell(const Port *port) const = 0;
|
||||
virtual LibertyPort *libertyPort(const Port *port) const = 0;
|
||||
virtual PortDirection *direction(const Port *port) const = 0;
|
||||
@@ -193,6 +191,9 @@ public:
|
||||
|
||||
////////////////////////////////////////////////////////////////
|
||||
// Instance functions
|
||||
// Name local to containing cell/instance.
|
||||
virtual const char *name(const Instance *instance) const = 0;
|
||||
virtual ObjectId id(const Instance *instance) const = 0;
|
||||
// Top level instance of the design (defined after link).
|
||||
virtual Instance *topInstance() const = 0;
|
||||
virtual bool isTopInstance(const Instance *inst) const;
|
||||
@@ -201,16 +202,10 @@ public:
|
||||
Instance *findInstanceRelative(const Instance *inst,
|
||||
const char *path_name) const;
|
||||
// Default implementation uses linear search.
|
||||
virtual void findInstancesMatching(const Instance *context,
|
||||
const PatternMatch *pattern,
|
||||
// Return value.
|
||||
InstanceSeq *insts) const;
|
||||
virtual void findInstancesHierMatching(const Instance *instance,
|
||||
const PatternMatch *pattern,
|
||||
// Return value.
|
||||
InstanceSeq *insts) const;
|
||||
// Name local to containing cell/instance.
|
||||
virtual const char *name(const Instance *instance) const = 0;
|
||||
virtual InstanceSeq findInstancesMatching(const Instance *context,
|
||||
const PatternMatch *pattern) const;
|
||||
virtual InstanceSeq findInstancesHierMatching(const Instance *instance,
|
||||
const PatternMatch *pattern) const;
|
||||
// Hierarchical path name.
|
||||
virtual const char *pathName(const Instance *instance) const;
|
||||
bool pathNameLess(const Instance *inst1,
|
||||
@@ -220,7 +215,7 @@ public:
|
||||
// Path from instance up to top level (last in the sequence).
|
||||
void path(const Instance *inst,
|
||||
// Return value.
|
||||
ConstInstanceSeq &path) const;
|
||||
InstanceSeq &path) const;
|
||||
virtual Cell *cell(const Instance *instance) const = 0;
|
||||
virtual const char *cellName(const Instance *instance) const;
|
||||
virtual LibertyLibrary *libertyLibrary(const Instance *instance) const;
|
||||
@@ -232,8 +227,8 @@ public:
|
||||
const char *name) const = 0;
|
||||
virtual void findChildrenMatching(const Instance *parent,
|
||||
const PatternMatch *pattern,
|
||||
// Return value.
|
||||
InstanceSeq *insts) const;
|
||||
// Return value.
|
||||
InstanceSeq &matches) const;
|
||||
// Is inst inside of hier_inst?
|
||||
bool isInside(const Instance *inst,
|
||||
const Instance *hier_inst) const;
|
||||
@@ -260,6 +255,9 @@ public:
|
||||
|
||||
////////////////////////////////////////////////////////////////
|
||||
// Pin functions
|
||||
// Name is instance_name/port_name (the same as path name).
|
||||
virtual const char *name(const Pin *pin) const;
|
||||
virtual ObjectId id(const Pin *pin) const = 0;
|
||||
virtual Pin *findPin(const char *path_name) const;
|
||||
virtual Pin *findPin(const Instance *instance,
|
||||
const char *port_name) const = 0;
|
||||
@@ -271,18 +269,12 @@ public:
|
||||
Pin *findPinRelative(const Instance *inst,
|
||||
const char *path_name) const;
|
||||
// Default implementation uses linear search.
|
||||
virtual void findPinsMatching(const Instance *instance,
|
||||
const PatternMatch *pattern,
|
||||
// Return value.
|
||||
PinSeq *pins) const;
|
||||
virtual PinSeq findPinsMatching(const Instance *instance,
|
||||
const PatternMatch *pattern) const;
|
||||
// Traverse the hierarchy from instance down and find pins matching
|
||||
// pattern of the form instance_name/port_name.
|
||||
virtual void findPinsHierMatching(const Instance *instance,
|
||||
const PatternMatch *pattern,
|
||||
// Return value.
|
||||
PinSeq *pins) const;
|
||||
// Name is instance_name/port_name (the same as path name).
|
||||
virtual const char *name(const Pin *pin) const;
|
||||
virtual PinSeq findPinsHierMatching(const Instance *instance,
|
||||
const PatternMatch *pattern) const;
|
||||
virtual const char *portName(const Pin *pin) const;
|
||||
// Path name is instance_name/port_name.
|
||||
virtual const char *pathName(const Pin *pin) const;
|
||||
@@ -317,7 +309,7 @@ public:
|
||||
// and child nets it is hierarchically connected to (port, leaf and
|
||||
// hierarchical pins).
|
||||
virtual PinConnectedPinIterator *connectedPinIterator(const Pin *pin) const;
|
||||
virtual void visitConnectedPins(Pin *pin,
|
||||
virtual void visitConnectedPins(const Pin *pin,
|
||||
PinVisitor &visitor) const;
|
||||
|
||||
// Find driver pins for the net connected to pin.
|
||||
@@ -344,6 +336,7 @@ public:
|
||||
// Terminal functions
|
||||
// Name is instance_name/port_name (the same as path name).
|
||||
virtual const char *name(const Term *term) const;
|
||||
virtual ObjectId id(const Term *term) const = 0;
|
||||
virtual const char *portName(const Term *term) const;
|
||||
// Path name is instance_name/port_name (pin name).
|
||||
virtual const char *pathName(const Term *term) const;
|
||||
@@ -352,28 +345,25 @@ public:
|
||||
|
||||
////////////////////////////////////////////////////////////////
|
||||
// Net functions
|
||||
virtual const char *name(const Net *net) const = 0; // no hierarchy prefix
|
||||
virtual ObjectId id(const Net *net) const = 0;
|
||||
virtual Net *findNet(const char *path_name) const;
|
||||
// Find net relative to hierarchical instance.
|
||||
Net *findNetRelative(const Instance *inst,
|
||||
const char *path_name) const;
|
||||
// Default implementation uses linear search.
|
||||
virtual void findNetsMatching(const Instance *context,
|
||||
const PatternMatch *pattern,
|
||||
// Return value.
|
||||
NetSeq *nets) const;
|
||||
virtual NetSeq findNetsMatching(const Instance *context,
|
||||
const PatternMatch *pattern) const;
|
||||
virtual Net *findNet(const Instance *instance,
|
||||
const char *net_name) const = 0;
|
||||
// Traverse the hierarchy from instance down and find nets matching
|
||||
// pattern of the form instance_name/net_name.
|
||||
virtual void findNetsHierMatching(const Instance *instance,
|
||||
const PatternMatch *pattern,
|
||||
// Return value.
|
||||
NetSeq *nets) const;
|
||||
virtual NetSeq findNetsHierMatching(const Instance *instance,
|
||||
const PatternMatch *pattern) const;
|
||||
// Primitive used by findNetsMatching.
|
||||
virtual void findInstNetsMatching(const Instance *instance,
|
||||
const PatternMatch *pattern,
|
||||
// Return value.
|
||||
NetSeq *nets) const = 0;
|
||||
virtual const char *name(const Net *net) const = 0; // no hierarchy prefix
|
||||
const PatternMatch *pattern,
|
||||
NetSeq &matches) const = 0;
|
||||
virtual const char *pathName(const Net *net) const;
|
||||
bool pathNameLess(const Net *net1,
|
||||
const Net *net2) const;
|
||||
@@ -390,7 +380,7 @@ public:
|
||||
virtual bool isConnected(const Net *net1,
|
||||
const Net *net2) const;
|
||||
virtual Net *highestNetAbove(Net *net) const;
|
||||
virtual Net *highestConnectedNet(Net *net) const;
|
||||
virtual const Net *highestConnectedNet(Net *net) const;
|
||||
virtual void connectedNets(Net *net,
|
||||
NetSet *nets) const;
|
||||
virtual void connectedNets(const Pin *pin,
|
||||
@@ -445,35 +435,45 @@ protected:
|
||||
void findInstancesMatching1(const Instance *context,
|
||||
size_t context_name_length,
|
||||
const PatternMatch *pattern,
|
||||
// Return value.
|
||||
InstanceSeq *insts) const;
|
||||
InstanceSeq &insts) const;
|
||||
void findInstancesHierMatching1(const Instance *instance,
|
||||
const PatternMatch *pattern,
|
||||
InstanceSeq &matches) const;
|
||||
void findNetsMatching(const Instance *context,
|
||||
const PatternMatch *pattern,
|
||||
NetSeq &matches) const;
|
||||
void findNetsHierMatching(const Instance *instance,
|
||||
const PatternMatch *pattern,
|
||||
NetSeq &matches) const;
|
||||
void findPinsHierMatching(const Instance *instance,
|
||||
const PatternMatch *pattern,
|
||||
// Return value.
|
||||
PinSeq &matches) const;
|
||||
bool isConnected(const Net *net,
|
||||
const Pin *pin,
|
||||
ConstNetSet &nets) const;
|
||||
NetSet &nets) const;
|
||||
bool isConnected(const Net *net1,
|
||||
const Net *net2,
|
||||
ConstNetSet &nets) const;
|
||||
NetSet &nets) const;
|
||||
int hierarchyLevel(const Net *net) const;
|
||||
virtual void visitConnectedPins(const Net *net,
|
||||
PinVisitor &visitor,
|
||||
ConstNetSet &visited_nets) const;
|
||||
NetSet &visited_nets) const;
|
||||
// Default implementation uses linear search.
|
||||
virtual void findInstPinsMatching(const Instance *instance,
|
||||
const PatternMatch *pattern,
|
||||
// Return value.
|
||||
PinSeq *pins) const;
|
||||
const PatternMatch *pattern,
|
||||
// Return value.
|
||||
PinSeq &matches) const;
|
||||
void findInstPinsHierMatching(const Instance *parent,
|
||||
const PatternMatch *pattern,
|
||||
// Return value.
|
||||
PinSeq *pins) const;
|
||||
const PatternMatch *pattern,
|
||||
// Return value.
|
||||
PinSeq &matches) const;
|
||||
// findNet using linear search.
|
||||
Net *findNetLinear(const Instance *instance,
|
||||
const char *net_name) const;
|
||||
// findNetsMatching using linear search.
|
||||
void findNetsMatchingLinear(const Instance *instance,
|
||||
const PatternMatch *pattern,
|
||||
// Return value.
|
||||
NetSeq *nets) const;
|
||||
NetSeq findNetsMatchingLinear(const Instance *instance,
|
||||
const PatternMatch *pattern) const;
|
||||
// Connect/disconnect net/pins should clear the net->drvrs map.
|
||||
// Incrementally maintaining the map is expensive because
|
||||
// nets may be connected across hierarchy levels.
|
||||
@@ -588,7 +588,7 @@ public:
|
||||
ConstantPinIterator() {}
|
||||
virtual ~ConstantPinIterator() {}
|
||||
virtual bool hasNext() = 0;
|
||||
virtual void next(Pin *&pin,
|
||||
virtual void next(const Pin *&pin,
|
||||
LogicValue &value) = 0;
|
||||
};
|
||||
|
||||
@@ -601,7 +601,7 @@ public:
|
||||
NetSet &one_nets);
|
||||
~NetworkConstantPinIterator();
|
||||
virtual bool hasNext();
|
||||
virtual void next(Pin *&pin, LogicValue &value);
|
||||
virtual void next(const Pin *&pin, LogicValue &value);
|
||||
|
||||
private:
|
||||
void findConstantPins(NetSet &nets,
|
||||
@@ -619,29 +619,29 @@ class HierPinThruVisitor
|
||||
public:
|
||||
HierPinThruVisitor() {}
|
||||
virtual ~HierPinThruVisitor() {}
|
||||
virtual void visit(Pin *drvr,
|
||||
Pin *load) = 0;
|
||||
virtual void visit(const Pin *drvr,
|
||||
const Pin *load) = 0;
|
||||
};
|
||||
|
||||
class PinVisitor
|
||||
{
|
||||
public:
|
||||
virtual ~PinVisitor() {}
|
||||
virtual void operator()(Pin *pin) = 0;
|
||||
virtual void operator()(const Pin *pin) = 0;
|
||||
};
|
||||
|
||||
class FindNetDrvrLoads : public PinVisitor
|
||||
{
|
||||
public:
|
||||
FindNetDrvrLoads(Pin *drvr_pin,
|
||||
FindNetDrvrLoads(const Pin *drvr_pin,
|
||||
PinSet &visited_drvrs,
|
||||
PinSeq &loads,
|
||||
PinSeq &drvrs,
|
||||
const Network *network);
|
||||
virtual void operator()(Pin *pin);
|
||||
virtual void operator()(const Pin *pin);
|
||||
|
||||
protected:
|
||||
Pin *drvr_pin_;
|
||||
const Pin *drvr_pin_;
|
||||
PinSet &visited_drvrs_;
|
||||
PinSeq &loads_;
|
||||
PinSeq &drvrs_;
|
||||
@@ -654,7 +654,7 @@ visitDrvrLoadsThruHierPin(const Pin *hpin,
|
||||
const Network *network,
|
||||
HierPinThruVisitor *visitor);
|
||||
void
|
||||
visitDrvrLoadsThruNet(Net *net,
|
||||
visitDrvrLoadsThruNet(const Net *net,
|
||||
const Network *network,
|
||||
HierPinThruVisitor *visitor);
|
||||
|
||||
|
||||
+112
-21
@@ -16,6 +16,7 @@
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <cstdint>
|
||||
#include "Set.hh"
|
||||
#include "Vector.hh"
|
||||
#include "Iterator.hh"
|
||||
@@ -40,40 +41,130 @@ class LibertyLibrary;
|
||||
typedef Iterator<Library*> LibraryIterator;
|
||||
typedef Iterator<LibertyLibrary*> LibertyLibraryIterator;
|
||||
typedef Vector<Cell*> CellSeq;
|
||||
typedef Set<Cell*> CellSet;
|
||||
typedef Vector<Port*> PortSeq;
|
||||
typedef Set<Port*> PortSet;
|
||||
typedef Vector<const Port*> PortSeq;
|
||||
typedef Iterator<Port*> CellPortIterator;
|
||||
typedef Iterator<Port*> CellPortBitIterator;
|
||||
typedef Iterator<Port*> PortMemberIterator;
|
||||
typedef std::pair<Port*, Port*> PortPair;
|
||||
|
||||
typedef Vector<Pin*> PinSeq;
|
||||
typedef Vector<const Pin*> ConstPinSeq;
|
||||
typedef Vector<Instance*> InstanceSeq;
|
||||
typedef Vector<const Instance*> ConstInstanceSeq;
|
||||
typedef Vector<Net*> NetSeq;
|
||||
typedef Set<Pin*> PinSet;
|
||||
typedef Set<Instance*> InstanceSet;
|
||||
typedef Set<Net*> NetSet;
|
||||
typedef Vector<const Pin*> PinSeq;
|
||||
typedef Vector<const Instance*> InstanceSeq;
|
||||
typedef Vector<const Net*> NetSeq;
|
||||
typedef Iterator<Instance*> InstanceChildIterator;
|
||||
typedef Iterator<Pin*> InstancePinIterator;
|
||||
typedef Iterator<Net*> InstanceNetIterator;
|
||||
typedef Iterator<Instance*> LeafInstanceIterator;
|
||||
typedef Iterator<Net*> NetIterator;
|
||||
typedef Iterator<Pin*> NetPinIterator;
|
||||
typedef Iterator<const Pin*> NetPinIterator;
|
||||
typedef Iterator<Term*> NetTermIterator;
|
||||
typedef Iterator<Pin*> ConnectedPinIterator;
|
||||
typedef Iterator<const Pin*> ConnectedPinIterator;
|
||||
typedef ConnectedPinIterator NetConnectedPinIterator;
|
||||
typedef ConnectedPinIterator PinConnectedPinIterator;
|
||||
|
||||
class PortPairLess
|
||||
{
|
||||
public:
|
||||
bool operator()(const PortPair *pair1,
|
||||
const PortPair *pair2) const;
|
||||
};
|
||||
typedef uint32_t ObjectId;
|
||||
|
||||
enum class LogicValue : unsigned { zero, one, unknown, rise, fall };
|
||||
|
||||
class CellIdLess
|
||||
{
|
||||
public:
|
||||
CellIdLess(const Network *network);
|
||||
bool operator()(const Cell *cell1,
|
||||
const Cell *cell2) const;
|
||||
private:
|
||||
const Network *network_;
|
||||
};
|
||||
|
||||
class PortIdLess
|
||||
{
|
||||
public:
|
||||
PortIdLess(const Network *network);
|
||||
bool operator()(const Port *port1,
|
||||
const Port *port2) const;
|
||||
private:
|
||||
const Network *network_;
|
||||
};
|
||||
|
||||
class InstanceIdLess
|
||||
{
|
||||
public:
|
||||
InstanceIdLess(const Network *network);
|
||||
bool operator()(const Instance *inst1,
|
||||
const Instance *inst2) const;
|
||||
private:
|
||||
const Network *network_;
|
||||
};
|
||||
|
||||
class PinIdLess
|
||||
{
|
||||
public:
|
||||
PinIdLess(const Network *network);
|
||||
bool operator()(const Pin *pin1,
|
||||
const Pin *pin2) const;
|
||||
private:
|
||||
const Network *network_;
|
||||
};
|
||||
|
||||
class PinIdHash
|
||||
{
|
||||
public:
|
||||
PinIdHash(const Network *network);
|
||||
size_t operator()(const Pin *pin) const;
|
||||
|
||||
private:
|
||||
const Network *network_;
|
||||
};
|
||||
|
||||
class NetIdLess
|
||||
{
|
||||
public:
|
||||
NetIdLess(const Network *network);
|
||||
bool operator()(const Net *net1,
|
||||
const Net *net2) const;
|
||||
private:
|
||||
const Network *network_;
|
||||
};
|
||||
|
||||
////////////////////////////////////////////////////////////////
|
||||
|
||||
class CellSet : public Set<const Cell*, CellIdLess>
|
||||
{
|
||||
public:
|
||||
CellSet(const Network *network);
|
||||
};
|
||||
|
||||
class PortSet : public Set<const Port*, PortIdLess>
|
||||
{
|
||||
public:
|
||||
PortSet(const Network *network);
|
||||
};
|
||||
|
||||
class InstanceSet : public Set<const Instance*, InstanceIdLess>
|
||||
{
|
||||
public:
|
||||
InstanceSet();
|
||||
InstanceSet(const Network *network);
|
||||
static int compare(const InstanceSet *set1,
|
||||
const InstanceSet *set2,
|
||||
const Network *network);
|
||||
};
|
||||
|
||||
class PinSet : public Set<const Pin*, PinIdLess>
|
||||
{
|
||||
public:
|
||||
PinSet();
|
||||
PinSet(const Network *network);
|
||||
static int compare(const PinSet *set1,
|
||||
const PinSet *set2,
|
||||
const Network *network);
|
||||
};
|
||||
|
||||
class NetSet : public Set<const Net*, NetIdLess>
|
||||
{
|
||||
public:
|
||||
NetSet();
|
||||
NetSet(const Network *network);
|
||||
static int compare(const NetSet *set1,
|
||||
const NetSet *set2,
|
||||
const Network *network);
|
||||
};
|
||||
|
||||
} // namespace
|
||||
|
||||
+13
-17
@@ -21,7 +21,7 @@
|
||||
|
||||
namespace sta {
|
||||
|
||||
// Comparison operators for sorting network objects.
|
||||
// Comparison operators for network objects.
|
||||
|
||||
class PortNameLess
|
||||
{
|
||||
@@ -67,21 +67,17 @@ private:
|
||||
const Network *network_;
|
||||
};
|
||||
|
||||
void
|
||||
sortPinSet(PinSet *set,
|
||||
const Network *network,
|
||||
PinSeq &pins);
|
||||
void
|
||||
sortPortSet(PortSet *set,
|
||||
const Network *network,
|
||||
PortSeq &ports);
|
||||
void
|
||||
sortInstanceSet(InstanceSet *set,
|
||||
const Network *network,
|
||||
InstanceSeq &insts);
|
||||
void
|
||||
sortNetSet(NetSet *set,
|
||||
const Network *network,
|
||||
NetSeq &nets);
|
||||
PinSeq
|
||||
sortByPathName(const PinSet *set,
|
||||
const Network *network);
|
||||
PortSeq
|
||||
sortByName(const PortSet *set,
|
||||
const Network *network);
|
||||
InstanceSeq
|
||||
sortByPathName(InstanceSet *set,
|
||||
const Network *network);
|
||||
NetSeq
|
||||
sortByPathName(NetSet *set,
|
||||
const Network *network);
|
||||
|
||||
} // namespace
|
||||
|
||||
@@ -47,23 +47,31 @@ public:
|
||||
virtual Parasitic *makePiElmore(const Pin *drvr_pin,
|
||||
const RiseFall *rf,
|
||||
const ParasiticAnalysisPt *ap,
|
||||
float c2, float rpi, float c1);
|
||||
virtual bool isPiElmore(Parasitic *parasitic) const;
|
||||
float c2,
|
||||
float rpi,
|
||||
float c1);
|
||||
virtual bool isPiElmore(const Parasitic *parasitic) const;
|
||||
virtual bool
|
||||
isReducedParasiticNetwork(Parasitic *parasitic) const;
|
||||
isReducedParasiticNetwork(const Parasitic *parasitic) const;
|
||||
virtual void setIsReducedParasiticNetwork(Parasitic *parasitic,
|
||||
bool is_reduced);
|
||||
virtual void piModel(Parasitic *parasitic, float &c2, float &rpi,
|
||||
virtual void piModel(const Parasitic *parasitic,
|
||||
float &c2,
|
||||
float &rpi,
|
||||
float &c1) const;
|
||||
virtual void setPiModel(Parasitic *parasitic, float c2, float rpi,
|
||||
virtual void setPiModel(Parasitic *parasitic,
|
||||
float c2,
|
||||
float rpi,
|
||||
float c1);
|
||||
virtual void findElmore(Parasitic *parasitic, const Pin *load_pin,
|
||||
float &elmore, bool &exists) const;
|
||||
virtual void findElmore(const Parasitic *parasitic,
|
||||
const Pin *load_pin,
|
||||
float &elmore,
|
||||
bool &exists) const;
|
||||
virtual void setElmore(Parasitic *parasitic, const Pin *load_pin,
|
||||
float elmore);
|
||||
|
||||
virtual bool isPiModel(Parasitic* parasitic) const;
|
||||
virtual bool isPiPoleResidue(Parasitic* parasitic) const;
|
||||
virtual bool isPiModel(const Parasitic* parasitic) const;
|
||||
virtual bool isPiPoleResidue(const Parasitic* parasitic) const;
|
||||
virtual Parasitic *
|
||||
findPiPoleResidue(const Pin *drvr_pin,
|
||||
const RiseFall *rf,
|
||||
|
||||
@@ -64,7 +64,7 @@ public:
|
||||
const ParasiticAnalysisPt *ap) = 0;
|
||||
virtual void deleteDrvrReducedParasitics(const Pin *drvr_pin) = 0;
|
||||
|
||||
virtual bool isReducedParasiticNetwork(Parasitic *parasitic) const = 0;
|
||||
virtual bool isReducedParasiticNetwork(const Parasitic *parasitic) const = 0;
|
||||
// Flag this parasitic as reduced from a parasitic network.
|
||||
virtual void setIsReducedParasiticNetwork(Parasitic *parasitic,
|
||||
bool is_reduced) = 0;
|
||||
@@ -76,7 +76,7 @@ public:
|
||||
// Pi model driver load with elmore delays to load pins (RSPF).
|
||||
// This follows the SPEF documentation of c2/c1, with c2 being the
|
||||
// capacitor on the driver pin.
|
||||
virtual bool isPiElmore(Parasitic *parasitic) const = 0;
|
||||
virtual bool isPiElmore(const Parasitic *parasitic) const = 0;
|
||||
virtual Parasitic *findPiElmore(const Pin *drvr_pin,
|
||||
const RiseFall *rf,
|
||||
const ParasiticAnalysisPt *ap) const = 0;
|
||||
@@ -89,8 +89,8 @@ public:
|
||||
|
||||
////////////////////////////////////////////////////////////////
|
||||
// Pi models are common to PiElmore and PiPoleResidue.
|
||||
virtual bool isPiModel(Parasitic *parasitic) const = 0;
|
||||
virtual void piModel(Parasitic *parasitic,
|
||||
virtual bool isPiModel(const Parasitic *parasitic) const = 0;
|
||||
virtual void piModel(const Parasitic *parasitic,
|
||||
float &c2,
|
||||
float &rpi,
|
||||
float &c1) const = 0;
|
||||
@@ -103,7 +103,7 @@ public:
|
||||
////////////////////////////////////////////////////////////////
|
||||
// Elmore driver to load delay.
|
||||
// Common to LumpedElmore and PiElmore parasitics.
|
||||
virtual void findElmore(Parasitic *parasitic,
|
||||
virtual void findElmore(const Parasitic *parasitic,
|
||||
const Pin *load_pin,
|
||||
float &elmore,
|
||||
bool &exists) const = 0;
|
||||
@@ -114,7 +114,7 @@ public:
|
||||
|
||||
////////////////////////////////////////////////////////////////
|
||||
// Pi model driver load with pole/residue interconnect model to load pins.
|
||||
virtual bool isPiPoleResidue(Parasitic* parasitic) const = 0;
|
||||
virtual bool isPiPoleResidue(const Parasitic* parasitic) const = 0;
|
||||
virtual Parasitic *findPiPoleResidue(const Pin *drvr_pin,
|
||||
const RiseFall *rf,
|
||||
const ParasiticAnalysisPt *ap) const=0;
|
||||
@@ -310,7 +310,7 @@ protected:
|
||||
float fanout,
|
||||
const ParasiticAnalysisPt *ap);
|
||||
|
||||
Net *findParasiticNet(const Pin *pin) const;
|
||||
const Net *findParasiticNet(const Pin *pin) const;
|
||||
};
|
||||
|
||||
// Managed by the Corner class.
|
||||
|
||||
+2
-2
@@ -47,8 +47,8 @@ public:
|
||||
virtual Tag *tag(const StaState *sta) const = 0;
|
||||
virtual TagIndex tagIndex(const StaState *sta) const;
|
||||
virtual ClkInfo *clkInfo(const StaState *sta) const;
|
||||
virtual ClockEdge *clkEdge(const StaState *sta) const;
|
||||
virtual Clock *clock(const StaState *sta) const;
|
||||
virtual const ClockEdge *clkEdge(const StaState *sta) const;
|
||||
virtual const Clock *clock(const StaState *sta) const;
|
||||
virtual bool isClock(const StaState *sta) const;
|
||||
virtual const RiseFall *transition(const StaState *sta) const = 0;
|
||||
virtual int rfIndex(const StaState *sta) const;
|
||||
|
||||
@@ -104,7 +104,7 @@ public:
|
||||
virtual Slack slack(const StaState *sta) const = 0;
|
||||
virtual Slack slackNoCrpr(const StaState *sta) const = 0;
|
||||
virtual Arrival borrow(const StaState *sta) const;
|
||||
ClockEdge *sourceClkEdge(const StaState *sta) const;
|
||||
const ClockEdge *sourceClkEdge(const StaState *sta) const;
|
||||
// Time offset for the path start so the path begins in the correct
|
||||
// source cycle.
|
||||
virtual float sourceClkOffset(const StaState *sta) const = 0;
|
||||
@@ -112,8 +112,8 @@ public:
|
||||
virtual Delay sourceClkInsertionDelay(const StaState *sta) const;
|
||||
virtual PathVertex *targetClkPath();
|
||||
virtual const PathVertex *targetClkPath() const;
|
||||
virtual Clock *targetClk(const StaState *sta) const;
|
||||
virtual ClockEdge *targetClkEdge(const StaState *sta) const;
|
||||
virtual const Clock *targetClk(const StaState *sta) const;
|
||||
virtual const ClockEdge *targetClkEdge(const StaState *sta) const;
|
||||
const RiseFall *targetClkEndTrans(const StaState *sta) const;
|
||||
// Target clock with cycle accounting and source clock offsets.
|
||||
virtual float targetClkTime(const StaState *sta) const;
|
||||
@@ -232,8 +232,8 @@ public:
|
||||
virtual float sourceClkOffset(const StaState *sta) const;
|
||||
virtual Delay sourceClkLatency(const StaState *sta) const;
|
||||
virtual Delay sourceClkInsertionDelay(const StaState *sta) const;
|
||||
virtual Clock *targetClk(const StaState *sta) const;
|
||||
virtual ClockEdge *targetClkEdge(const StaState *sta) const;
|
||||
virtual const Clock *targetClk(const StaState *sta) const;
|
||||
virtual const ClockEdge *targetClkEdge(const StaState *sta) const;
|
||||
virtual PathVertex *targetClkPath();
|
||||
virtual const PathVertex *targetClkPath() const;
|
||||
virtual float targetClkTime(const StaState *sta) const;
|
||||
@@ -420,7 +420,7 @@ public:
|
||||
virtual bool isOutputDelay() const { return true; }
|
||||
virtual ArcDelay margin(const StaState *sta) const;
|
||||
virtual TimingRole *checkRole(const StaState *sta) const;
|
||||
virtual ClockEdge *targetClkEdge(const StaState *sta) const;
|
||||
virtual const ClockEdge *targetClkEdge(const StaState *sta) const;
|
||||
virtual Arrival targetClkArrivalNoCrpr(const StaState *sta) const;
|
||||
virtual Delay targetClkDelay(const StaState *sta) const;
|
||||
virtual Delay targetClkInsertionDelay(const StaState *sta) const;
|
||||
@@ -496,7 +496,7 @@ public:
|
||||
virtual void reportShort(ReportPath *report) const;
|
||||
virtual void reportFull(ReportPath *report) const;
|
||||
virtual bool isDataCheck() const { return true; }
|
||||
virtual ClockEdge *targetClkEdge(const StaState *sta) const;
|
||||
virtual const ClockEdge *targetClkEdge(const StaState *sta) const;
|
||||
virtual TimingRole *checkRole(const StaState *sta) const;
|
||||
virtual ArcDelay margin(const StaState *sta) const;
|
||||
virtual int exceptPathCmp(const PathEnd *path_end,
|
||||
@@ -553,7 +553,7 @@ public:
|
||||
virtual PathDelay *pathDelay() const { return path_delay_; }
|
||||
virtual ArcDelay margin(const StaState *sta) const;
|
||||
virtual float sourceClkOffset(const StaState *sta) const;
|
||||
virtual ClockEdge *targetClkEdge(const StaState *sta) const;
|
||||
virtual const ClockEdge *targetClkEdge(const StaState *sta) const;
|
||||
virtual float targetClkTime(const StaState *sta) const;
|
||||
virtual Arrival targetClkArrivalNoCrpr(const StaState *sta) const;
|
||||
virtual float targetClkOffset(const StaState *sta) const;
|
||||
|
||||
+20
-7
@@ -22,28 +22,41 @@
|
||||
|
||||
namespace sta {
|
||||
|
||||
typedef std::pair<Pin*, Pin*> PinPair;
|
||||
typedef std::pair<const Pin*, const Pin*> PinPair;
|
||||
|
||||
class PinPairLess
|
||||
{
|
||||
public:
|
||||
bool operator()(const PinPair *pair1,
|
||||
const PinPair *pair2) const;
|
||||
PinPairLess(const Network *network);
|
||||
bool operator()(const PinPair &pair1,
|
||||
const PinPair &pair2) const;
|
||||
|
||||
private:
|
||||
const Network *network_;
|
||||
};
|
||||
|
||||
typedef Set<PinPair*, PinPairLess> PinPairSet;
|
||||
|
||||
class PinPairSet : public Set<PinPair, PinPairLess>
|
||||
{
|
||||
public:
|
||||
PinPairSet(const Network *network);
|
||||
};
|
||||
|
||||
class PinPairHash
|
||||
{
|
||||
public:
|
||||
size_t operator()(const PinPair *pair) const;
|
||||
PinPairHash(const Network *network);
|
||||
size_t operator()(const PinPair &pair) const;
|
||||
|
||||
private:
|
||||
const Network *network_;
|
||||
};
|
||||
|
||||
class PinPairEqual
|
||||
{
|
||||
public:
|
||||
bool operator()(const PinPair *pair1,
|
||||
const PinPair *pair2) const;
|
||||
bool operator()(const PinPair &pair1,
|
||||
const PinPair &pair2) const;
|
||||
};
|
||||
|
||||
} // namespace
|
||||
|
||||
+16
-17
@@ -30,27 +30,28 @@ class PortDelay
|
||||
{
|
||||
public:
|
||||
RiseFallMinMax *delays() { return &delays_; }
|
||||
Pin *pin() const { return pin_; }
|
||||
const Pin *pin() const { return pin_; }
|
||||
PinSet &leafPins() { return leaf_pins_; }
|
||||
Clock *clock() const;
|
||||
ClockEdge *clkEdge() const { return clk_edge_; }
|
||||
const ClockEdge *clkEdge() const { return clk_edge_; }
|
||||
bool sourceLatencyIncluded() const;
|
||||
void setSourceLatencyIncluded(bool included);
|
||||
bool networkLatencyIncluded() const;
|
||||
void setNetworkLatencyIncluded(bool included);
|
||||
Pin *refPin() const { return ref_pin_; }
|
||||
const Pin *refPin() const { return ref_pin_; }
|
||||
void setRefPin(const Pin *ref_pin);
|
||||
RiseFall *refTransition() const;
|
||||
|
||||
protected:
|
||||
PortDelay(Pin *pin,
|
||||
ClockEdge *clk_edge,
|
||||
Pin *ref_pin);
|
||||
PortDelay(const Pin *pin,
|
||||
const ClockEdge *clk_edge,
|
||||
const Network *network);
|
||||
|
||||
Pin *pin_;
|
||||
ClockEdge *clk_edge_;
|
||||
const Pin *pin_;
|
||||
const ClockEdge *clk_edge_;
|
||||
bool source_latency_included_;
|
||||
bool network_latency_included_;
|
||||
Pin *ref_pin_;
|
||||
const Pin *ref_pin_;
|
||||
RiseFallMinMax delays_;
|
||||
PinSet leaf_pins_;
|
||||
};
|
||||
@@ -61,11 +62,10 @@ public:
|
||||
int index() const { return index_; }
|
||||
|
||||
protected:
|
||||
InputDelay(Pin *pin,
|
||||
ClockEdge *clk_edge,
|
||||
Pin *ref_pin,
|
||||
InputDelay(const Pin *pin,
|
||||
const ClockEdge *clk_edge,
|
||||
int index,
|
||||
Network *network);
|
||||
const Network *network);
|
||||
|
||||
private:
|
||||
int index_;
|
||||
@@ -78,10 +78,9 @@ class OutputDelay : public PortDelay
|
||||
public:
|
||||
|
||||
protected:
|
||||
OutputDelay(Pin *pin,
|
||||
ClockEdge *clk_edge,
|
||||
Pin *ref_pin,
|
||||
Network *network);
|
||||
OutputDelay(const Pin *pin,
|
||||
const ClockEdge *clk_edge,
|
||||
const Network *network);
|
||||
|
||||
private:
|
||||
friend class Sdc;
|
||||
|
||||
@@ -30,12 +30,13 @@ typedef MinMaxIntValues FanoutValues;
|
||||
class PortExtCap
|
||||
{
|
||||
public:
|
||||
explicit PortExtCap(Port *port);
|
||||
Port *port() { return port_; }
|
||||
PortExtCap(const Port *port);
|
||||
const Port *port() { return port_; }
|
||||
void pinCap(const RiseFall *rf,
|
||||
const MinMax *min_max,
|
||||
// Return values.
|
||||
float &cap, bool &exists);
|
||||
float &cap,
|
||||
bool &exists);
|
||||
RiseFallMinMax *pinCap() { return &pin_cap_; }
|
||||
void setPinCap(float cap,
|
||||
const RiseFall *rf,
|
||||
@@ -43,7 +44,8 @@ public:
|
||||
void wireCap(const RiseFall *rf,
|
||||
const MinMax *min_max,
|
||||
// Return values.
|
||||
float &cap, bool &exists);
|
||||
float &cap,
|
||||
bool &exists);
|
||||
RiseFallMinMax *wireCap() { return &wire_cap_; }
|
||||
void setWireCap(float cap,
|
||||
const RiseFall *rf,
|
||||
@@ -57,7 +59,7 @@ public:
|
||||
FanoutValues *fanout() { return &fanout_; }
|
||||
|
||||
private:
|
||||
Port *port_;
|
||||
const Port *port_;
|
||||
RiseFallMinMax pin_cap_;
|
||||
RiseFallMinMax wire_cap_;
|
||||
FanoutValues fanout_;
|
||||
|
||||
+31
-30
@@ -54,18 +54,19 @@ public:
|
||||
PropertyValue(float value,
|
||||
const Unit *unit);
|
||||
explicit PropertyValue(bool value);
|
||||
PropertyValue(Library *value);
|
||||
PropertyValue(Cell *value);
|
||||
PropertyValue(Port *value);
|
||||
PropertyValue(LibertyLibrary *value);
|
||||
PropertyValue(LibertyCell *value);
|
||||
PropertyValue(LibertyPort *value);
|
||||
PropertyValue(Instance *value);
|
||||
PropertyValue(Pin *value);
|
||||
PropertyValue(const Library *value);
|
||||
PropertyValue(const Cell *value);
|
||||
PropertyValue(const Port *value);
|
||||
PropertyValue(const LibertyLibrary *value);
|
||||
PropertyValue(const LibertyCell *value);
|
||||
PropertyValue(const LibertyPort *value);
|
||||
PropertyValue(const Instance *value);
|
||||
PropertyValue(const Pin *value);
|
||||
PropertyValue(PinSeq *value);
|
||||
PropertyValue(PinSet *value);
|
||||
PropertyValue(Net *value);
|
||||
PropertyValue(Clock *value);
|
||||
PropertyValue(const PinSet &value);
|
||||
PropertyValue(const Net *value);
|
||||
PropertyValue(const Clock *value);
|
||||
PropertyValue(ClockSeq *value);
|
||||
PropertyValue(ClockSet *value);
|
||||
PropertyValue(PathRefSeq *value);
|
||||
@@ -81,17 +82,17 @@ public:
|
||||
const char *stringValue() const { return string_; }
|
||||
float floatValue() const { return float_; }
|
||||
bool boolValue() const { return bool_; }
|
||||
LibertyLibrary *libertyLibrary() const { return liberty_library_; }
|
||||
LibertyCell *libertyCell() const { return liberty_cell_; }
|
||||
LibertyPort *libertyPort() const { return liberty_port_; }
|
||||
Library *library() const { return library_; }
|
||||
Cell *cell() const { return cell_; }
|
||||
Port *port() const { return port_; }
|
||||
Instance *instance() const { return inst_; }
|
||||
Pin *pin() const { return pin_; }
|
||||
const LibertyLibrary *libertyLibrary() const { return liberty_library_; }
|
||||
const LibertyCell *libertyCell() const { return liberty_cell_; }
|
||||
const LibertyPort *libertyPort() const { return liberty_port_; }
|
||||
const Library *library() const { return library_; }
|
||||
const Cell *cell() const { return cell_; }
|
||||
const Port *port() const { return port_; }
|
||||
const Instance *instance() const { return inst_; }
|
||||
const Pin *pin() const { return pin_; }
|
||||
PinSeq *pins() const { return pins_; }
|
||||
Net *net() const { return net_; }
|
||||
Clock *clock() const { return clk_; }
|
||||
const Net *net() const { return net_; }
|
||||
const Clock *clock() const { return clk_; }
|
||||
ClockSeq *clocks() const { return clks_; }
|
||||
PathRefSeq *pathRefs() const { return path_refs_; }
|
||||
PwrActivity pwrActivity() const { return pwr_activity_; }
|
||||
@@ -107,17 +108,17 @@ private:
|
||||
const char *string_;
|
||||
float float_;
|
||||
bool bool_;
|
||||
Library *library_;
|
||||
Cell *cell_;
|
||||
Port *port_;
|
||||
LibertyLibrary *liberty_library_;
|
||||
LibertyCell *liberty_cell_;
|
||||
LibertyPort *liberty_port_;
|
||||
Instance *inst_;
|
||||
Pin *pin_;
|
||||
const Library *library_;
|
||||
const Cell *cell_;
|
||||
const Port *port_;
|
||||
const LibertyLibrary *liberty_library_;
|
||||
const LibertyCell *liberty_cell_;
|
||||
const LibertyPort *liberty_port_;
|
||||
const Instance *inst_;
|
||||
const Pin *pin_;
|
||||
PinSeq *pins_;
|
||||
Net *net_;
|
||||
Clock *clk_;
|
||||
const Net *net_;
|
||||
const Clock *clk_;
|
||||
ClockSeq *clks_;
|
||||
PathRefSeq *path_refs_;
|
||||
PwrActivity pwr_activity_;
|
||||
|
||||
+185
-195
@@ -32,6 +32,7 @@
|
||||
#include "Clock.hh"
|
||||
#include "DataCheck.hh"
|
||||
#include "CycleAccting.hh"
|
||||
#include "ExceptionPath.hh"
|
||||
|
||||
namespace sta {
|
||||
|
||||
@@ -50,24 +51,33 @@ class FindNetCaps;
|
||||
class ClkHpinDisable;
|
||||
class FindClkHpinDisables;
|
||||
class Corner;
|
||||
class GroupPathIterator;
|
||||
class ClockPinIterator;
|
||||
class ClockIterator;
|
||||
|
||||
using std::vector;
|
||||
|
||||
typedef std::pair<const Pin*, const Clock*> PinClockPair;
|
||||
|
||||
class ClockInsertionPinClkLess
|
||||
class ClockInsertionkLess
|
||||
{
|
||||
public:
|
||||
ClockInsertionkLess(const Network *network);
|
||||
bool operator()(const ClockInsertion *insert1,
|
||||
const ClockInsertion *insert2) const;
|
||||
|
||||
private:
|
||||
const Network *network_;
|
||||
};
|
||||
|
||||
class ClockLatencyPinClkLess
|
||||
class ClockLatencyLess
|
||||
{
|
||||
public:
|
||||
ClockLatencyLess(const Network *network);
|
||||
bool operator()(const ClockLatency *latency1,
|
||||
const ClockLatency *latency2) const;
|
||||
|
||||
private:
|
||||
const Network *network_;
|
||||
};
|
||||
|
||||
// This is symmetric with respect to the clocks
|
||||
@@ -94,53 +104,55 @@ protected:
|
||||
class ClkHpinDisableLess
|
||||
{
|
||||
public:
|
||||
ClkHpinDisableLess(const Network *network);
|
||||
bool operator()(const ClkHpinDisable *disable1,
|
||||
const ClkHpinDisable *disable2) const;
|
||||
|
||||
private:
|
||||
const Network *network_;
|
||||
};
|
||||
|
||||
typedef Map<const char*,Clock*, CharPtrLess> ClockNameMap;
|
||||
typedef UnorderedMap<const Pin*, ClockSet*> ClockPinMap;
|
||||
typedef UnorderedMap<const Pin*, ClockSet*, PinIdHash> ClockPinMap;
|
||||
typedef Set<InputDelay*> InputDelaySet;
|
||||
typedef Map<const Pin*,InputDelaySet*> InputDelaysPinMap;
|
||||
typedef Map<const Pin*, InputDelaySet*, PinIdLess> InputDelaysPinMap;
|
||||
typedef Set<OutputDelay*> OutputDelaySet;
|
||||
typedef Map<const Pin*,OutputDelaySet*> OutputDelaysPinMap;
|
||||
typedef Set<Instance*> InstanceSet;
|
||||
typedef Map<const Pin*,OutputDelaySet*, PinIdLess> OutputDelaysPinMap;
|
||||
typedef UnorderedMap<const Pin*,ExceptionPathSet*> PinExceptionsMap;
|
||||
typedef Map<const Clock*,ExceptionPathSet*> ClockExceptionsMap;
|
||||
typedef Map<const Instance*,ExceptionPathSet*> InstanceExceptionsMap;
|
||||
typedef Map<const Net*,ExceptionPathSet*> NetExceptionsMap;
|
||||
typedef UnorderedMap<const EdgePins*,ExceptionPathSet*,
|
||||
typedef UnorderedMap<EdgePins, ExceptionPathSet*,
|
||||
PinPairHash, PinPairEqual> EdgeExceptionsMap;
|
||||
typedef Vector<ExceptionThru*> ExceptionThruSeq;
|
||||
typedef Map<const Port*,InputDrive*> InputDriveMap;
|
||||
typedef Map<int, ExceptionPathSet*, std::less<int> > ExceptionPathPtHash;
|
||||
typedef Set<ClockLatency*, ClockLatencyPinClkLess> ClockLatencies;
|
||||
typedef Set<ClockLatency*, ClockLatencyLess> ClockLatencies;
|
||||
typedef Map<const Pin*, ClockUncertainties*> PinClockUncertaintyMap;
|
||||
typedef Set<InterClockUncertainty*,
|
||||
InterClockUncertaintyLess> InterClockUncertaintySet;
|
||||
typedef Set<InterClockUncertainty*, InterClockUncertaintyLess> InterClockUncertaintySet;
|
||||
typedef Map<const Clock*, ClockGatingCheck*> ClockGatingCheckMap;
|
||||
typedef Map<const Instance*, ClockGatingCheck*> InstanceClockGatingCheckMap;
|
||||
typedef Map<const Pin*, ClockGatingCheck*> PinClockGatingCheckMap;
|
||||
typedef Set<ClockInsertion*, ClockInsertionPinClkLess> ClockInsertions;
|
||||
typedef Set<ClockInsertion*, ClockInsertionkLess> ClockInsertions;
|
||||
typedef Map<const Pin*, float> PinLatchBorrowLimitMap;
|
||||
typedef Map<const Instance*, float> InstLatchBorrowLimitMap;
|
||||
typedef Map<const Clock*, float> ClockLatchBorrowLimitMap;
|
||||
typedef Set<DataCheck*, DataCheckLess> DataCheckSet;
|
||||
typedef Map<const Pin*, DataCheckSet*> DataChecksMap;
|
||||
typedef Map<Port*, PortExtCap*> PortExtCapMap;
|
||||
typedef Map<Net*, MinMaxFloatValues> NetResistanceMap;
|
||||
typedef Map<Port*, MinMaxFloatValues> PortSlewLimitMap;
|
||||
typedef Map<const Net*, MinMaxFloatValues> NetResistanceMap;
|
||||
typedef Map<const Port*, MinMaxFloatValues> PortSlewLimitMap;
|
||||
typedef Map<const Pin*, MinMaxFloatValues> PinSlewLimitMap;
|
||||
typedef Map<Cell*, MinMaxFloatValues> CellSlewLimitMap;
|
||||
typedef Map<Cell*, MinMaxFloatValues> CellCapLimitMap;
|
||||
typedef Map<Port*, MinMaxFloatValues> PortCapLimitMap;
|
||||
typedef Map<Pin*, MinMaxFloatValues> PinCapLimitMap;
|
||||
typedef Map<Port*, MinMaxFloatValues> PortFanoutLimitMap;
|
||||
typedef Map<Cell*, MinMaxFloatValues> CellFanoutLimitMap;
|
||||
typedef Map<Net*, MinMaxFloatValues> NetWireCapMap;
|
||||
typedef Map<Pin*, MinMaxFloatValues*> PinWireCapMap;
|
||||
typedef Map<Instance*, Pvt*> InstancePvtMap;
|
||||
typedef Map<Edge*, ClockLatency*> EdgeClockLatencyMap;
|
||||
typedef Map<const Cell*, MinMaxFloatValues> CellSlewLimitMap;
|
||||
typedef Map<const Cell*, MinMaxFloatValues> CellCapLimitMap;
|
||||
typedef Map<const Port*, MinMaxFloatValues> PortCapLimitMap;
|
||||
typedef Map<const Pin*, MinMaxFloatValues> PinCapLimitMap;
|
||||
typedef Map<const Port*, MinMaxFloatValues> PortFanoutLimitMap;
|
||||
typedef Map<const Cell*, MinMaxFloatValues> CellFanoutLimitMap;
|
||||
typedef Map<const Port*, PortExtCap*, PortIdLess> PortExtCapMap;
|
||||
typedef Map<const Net*, MinMaxFloatValues, NetIdLess> NetWireCapMap;
|
||||
typedef Map<const Pin*, MinMaxFloatValues*, PinIdLess> PinWireCapMap;
|
||||
typedef Map<const Instance*, Pvt*> InstancePvtMap;
|
||||
typedef Map<const Edge*, ClockLatency*> EdgeClockLatencyMap;
|
||||
typedef Map<const Pin*, RiseFallValues*> PinMinPulseWidthMap;
|
||||
typedef Map<const Clock*, RiseFallValues*> ClockMinPulseWidthMap;
|
||||
typedef Map<const Instance*, RiseFallValues*> InstMinPulseWidthMap;
|
||||
@@ -152,16 +164,16 @@ typedef Map<const Clock*, ClockGroupsSet*> ClockGroupsClkMap;
|
||||
typedef Map<const char*, ClockGroups*, CharPtrLess> ClockGroupsNameMap;
|
||||
typedef Map<PinClockPair, ClockSense, PinClockPairLess> ClockSenseMap;
|
||||
typedef Set<ClkHpinDisable*, ClkHpinDisableLess> ClkHpinDisables;
|
||||
typedef Set<GroupPath*> GroupPathSet;
|
||||
typedef Set<GroupPath*, ExceptionPathLess> GroupPathSet;
|
||||
typedef Map<const char*, GroupPathSet*, CharPtrLess> GroupPathMap;
|
||||
typedef Set<ClockPair, ClockPairLess> ClockPairSet;
|
||||
|
||||
void
|
||||
findLeafLoadPins(Pin *pin,
|
||||
findLeafLoadPins(const Pin *pin,
|
||||
const Network *network,
|
||||
PinSet *leaf_pins);
|
||||
void
|
||||
findLeafDriverPins(Pin *pin,
|
||||
findLeafDriverPins(const Pin *pin,
|
||||
const Network *network,
|
||||
PinSet *leaf_pins);
|
||||
|
||||
@@ -172,6 +184,7 @@ public:
|
||||
~Sdc();
|
||||
// Note that Search may reference a Filter exception removed by clear().
|
||||
void clear();
|
||||
void makeCornersAfter(Corners *corners);
|
||||
// Return true if pin is referenced by any constraint.
|
||||
bool isConstrained(const Pin *pin) const;
|
||||
// Return true if inst is referenced by any constraint.
|
||||
@@ -182,7 +195,7 @@ public:
|
||||
bool isConstrained(const Net *net) const;
|
||||
// Build data structures for search.
|
||||
void searchPreamble();
|
||||
void deleteNetBefore(Net *net);
|
||||
void deleteNetBefore(const Net *net);
|
||||
|
||||
// SWIG sdc interface.
|
||||
AnalysisType analysisType() { return analysis_type_; }
|
||||
@@ -227,34 +240,36 @@ public:
|
||||
static void moveDeratingFactors(Sdc *from,
|
||||
Sdc *to);
|
||||
|
||||
void setInputSlew(Port *port, const RiseFallBoth *rf,
|
||||
const MinMaxAll *min_max, float slew);
|
||||
void setInputSlew(const Port *port,
|
||||
const RiseFallBoth *rf,
|
||||
const MinMaxAll *min_max,
|
||||
float slew);
|
||||
// Set the rise/fall drive resistance on design port.
|
||||
void setDriveResistance(Port *port,
|
||||
void setDriveResistance(const Port *port,
|
||||
const RiseFallBoth *rf,
|
||||
const MinMaxAll *min_max,
|
||||
float res);
|
||||
// Set the drive on design port using external cell timing arcs of
|
||||
// cell driven by from_slews between from_port and to_port.
|
||||
void setDriveCell(LibertyLibrary *library,
|
||||
LibertyCell *cell,
|
||||
Port *port,
|
||||
LibertyPort *from_port,
|
||||
void setDriveCell(const LibertyLibrary *library,
|
||||
const LibertyCell *cell,
|
||||
const Port *port,
|
||||
const LibertyPort *from_port,
|
||||
float *from_slews,
|
||||
LibertyPort *to_port,
|
||||
const LibertyPort *to_port,
|
||||
const RiseFallBoth *rf,
|
||||
const MinMaxAll *min_max);
|
||||
void setLatchBorrowLimit(Pin *pin,
|
||||
void setLatchBorrowLimit(const Pin *pin,
|
||||
float limit);
|
||||
void setLatchBorrowLimit(Instance *inst,
|
||||
void setLatchBorrowLimit(const Instance *inst,
|
||||
float limit);
|
||||
void setLatchBorrowLimit(Clock *clk,
|
||||
void setLatchBorrowLimit(const Clock *clk,
|
||||
float limit);
|
||||
// Return the latch borrow limit respecting precidence if multiple
|
||||
// limits apply.
|
||||
void latchBorrowLimit(Pin *data_pin,
|
||||
Pin *enable_pin,
|
||||
Clock *clk,
|
||||
void latchBorrowLimit(const Pin *data_pin,
|
||||
const Pin *enable_pin,
|
||||
const Clock *clk,
|
||||
// Return values.
|
||||
float &limit,
|
||||
bool &exists);
|
||||
@@ -442,7 +457,7 @@ public:
|
||||
// Return values.
|
||||
float &insertion,
|
||||
bool &exists) const;
|
||||
ClockInsertions *clockInsertions() { return clk_insertions_; }
|
||||
const ClockInsertions &clockInsertions() const { return clk_insertions_; }
|
||||
// Clock uncertainty.
|
||||
virtual void setClockUncertainty(Pin *pin,
|
||||
const SetupHoldAll *setup_hold,
|
||||
@@ -520,44 +535,47 @@ public:
|
||||
const SetupHoldAll *setup_hold);
|
||||
DataCheckSet *dataChecksFrom(const Pin *from) const;
|
||||
DataCheckSet *dataChecksTo(const Pin *to) const;
|
||||
void setInputDelay(Pin *pin,
|
||||
void setInputDelay(const Pin *pin,
|
||||
const RiseFallBoth *rf,
|
||||
Clock *clk,
|
||||
const Clock *clk,
|
||||
const RiseFall *clk_rf,
|
||||
Pin *ref_pin,
|
||||
const Pin *ref_pin,
|
||||
bool source_latency_included,
|
||||
bool network_latency_included,
|
||||
const MinMaxAll *min_max,
|
||||
bool add, float delay);
|
||||
void removeInputDelay(Pin *pin,
|
||||
bool add,
|
||||
float delay);
|
||||
void removeInputDelay(const Pin *pin,
|
||||
const RiseFallBoth *rf,
|
||||
Clock *clk,
|
||||
RiseFall *clk_rf,
|
||||
MinMaxAll *min_max);
|
||||
void setOutputDelay(Pin *pin,
|
||||
const Clock *clk,
|
||||
const RiseFall *clk_rf,
|
||||
const MinMaxAll *min_max);
|
||||
void setOutputDelay(const Pin *pin,
|
||||
const RiseFallBoth *rf,
|
||||
Clock *clk,
|
||||
const Clock *clk,
|
||||
const RiseFall *clk_tr,
|
||||
Pin *ref_pin,
|
||||
const Pin *ref_pin,
|
||||
bool source_latency_included,
|
||||
bool network_latency_included,
|
||||
const MinMaxAll *min_max,
|
||||
bool add, float delay);
|
||||
void removeOutputDelay(Pin *pin,
|
||||
RiseFallBoth *rf,
|
||||
Clock *clk,
|
||||
RiseFall *clk_rf,
|
||||
MinMaxAll *min_max);
|
||||
bool add,
|
||||
float delay);
|
||||
void removeOutputDelay(const Pin *pin,
|
||||
const RiseFallBoth *rf,
|
||||
const Clock *clk,
|
||||
const RiseFall *clk_rf,
|
||||
const MinMaxAll *min_max);
|
||||
static void movePortDelays(Sdc *from,
|
||||
Sdc *to);
|
||||
|
||||
// Set port external pin load (set_load -pin_load port).
|
||||
void setPortExtPinCap(Port *port,
|
||||
void setPortExtPinCap(const Port *port,
|
||||
const RiseFall *rf,
|
||||
const Corner *corner,
|
||||
const MinMax *min_max,
|
||||
float cap);
|
||||
// Set port external wire load (set_load -wire port).
|
||||
void setPortExtWireCap(Port *port,
|
||||
void setPortExtWireCap(const Port *port,
|
||||
bool subtract_pin_cap,
|
||||
const RiseFall *rf,
|
||||
const Corner *corner,
|
||||
@@ -565,18 +583,15 @@ public:
|
||||
float cap);
|
||||
static void movePortExtCaps(Sdc *from,
|
||||
Sdc *to);
|
||||
// Remove all "set_load" and "set_fanout_load" annotations.
|
||||
void removeLoadCaps();
|
||||
// Remove all "set_load net" annotations.
|
||||
void removeNetLoadCaps();
|
||||
void setNetWireCap(Net *net,
|
||||
void setNetWireCap(const Net *net,
|
||||
bool subtract_pin_cap,
|
||||
const Corner *corner,
|
||||
const MinMax *min_max,
|
||||
float cap);
|
||||
bool hasNetWireCap(Net *net) const;
|
||||
bool hasNetWireCap(const Net *net) const;
|
||||
// True if driver pin net has wire capacitance.
|
||||
bool drvrPinHasWireCap(const Pin *pin);
|
||||
bool drvrPinHasWireCap(const Pin *pin,
|
||||
const Corner *corner);
|
||||
// Net wire capacitance (set_load -wire net).
|
||||
void drvrPinWireCap(const Pin *drvr_pin,
|
||||
const Corner *corner,
|
||||
@@ -590,15 +605,16 @@ public:
|
||||
const OperatingConditions *op_cond,
|
||||
const Corner *corner,
|
||||
const MinMax *min_max);
|
||||
void setResistance(Net *net,
|
||||
void setResistance(const Net *net,
|
||||
const MinMaxAll *min_max,
|
||||
float res);
|
||||
void resistance(Net *net,
|
||||
void resistance(const Net *net,
|
||||
const MinMax *min_max,
|
||||
float &res,
|
||||
bool &exists);
|
||||
NetResistanceMap *netResistances() { return &net_res_map_; }
|
||||
void setPortExtFanout(Port *port,
|
||||
NetResistanceMap &netResistances() { return net_res_map_; }
|
||||
void setPortExtFanout(const Port *port,
|
||||
const Corner *corner,
|
||||
const MinMax *min_max,
|
||||
int fanout);
|
||||
// set_disable_timing cell [-from] [-to]
|
||||
@@ -628,7 +644,7 @@ public:
|
||||
LibertyPort *from,
|
||||
LibertyPort *to);
|
||||
// set_disable_timing pin
|
||||
void disable(Pin *pin);
|
||||
void disable(const Pin *pin);
|
||||
void removeDisable(Pin *pin);
|
||||
// set_disable_timing [get_timing_arc -of_objects instance]]
|
||||
void disable(Edge *edge);
|
||||
@@ -652,11 +668,11 @@ public:
|
||||
bool isDisabled(Edge *edge);
|
||||
bool isDisabled(TimingArcSet *arc_set) const;
|
||||
DisabledCellPortsMap *disabledCellPorts();
|
||||
DisabledInstancePortsMap *disabledInstancePorts();
|
||||
PinSet *disabledPins() { return &disabled_pins_; }
|
||||
PortSet *disabledPorts() { return &disabled_ports_; }
|
||||
LibertyPortSet *disabledLibPorts() { return &disabled_lib_ports_; }
|
||||
EdgeSet *disabledEdges() { return &disabled_edges_; }
|
||||
const DisabledInstancePortsMap *disabledInstancePorts() const;
|
||||
const PinSet *disabledPins() const { return &disabled_pins_; }
|
||||
const PortSet *disabledPorts() const { return &disabled_ports_; }
|
||||
const LibertyPortSet *disabledLibPorts() const { return &disabled_lib_ports_; }
|
||||
const EdgeSet *disabledEdges() const { return &disabled_edges_; }
|
||||
void disableClockGatingCheck(Instance *inst);
|
||||
void disableClockGatingCheck(Pin *pin);
|
||||
void removeDisableClockGatingCheck(Instance *inst);
|
||||
@@ -664,16 +680,18 @@ public:
|
||||
bool isDisableClockGatingCheck(const Pin *pin);
|
||||
bool isDisableClockGatingCheck(const Instance *inst);
|
||||
// set_LogicValue::zero, set_LogicValue::one, set_logic_dc
|
||||
void setLogicValue(Pin *pin,
|
||||
void setLogicValue(const Pin *pin,
|
||||
LogicValue value);
|
||||
// set_case_analysis
|
||||
void setCaseAnalysis(Pin *pin,
|
||||
void setCaseAnalysis(const Pin *pin,
|
||||
LogicValue value);
|
||||
void removeCaseAnalysis(Pin *pin);
|
||||
void removeCaseAnalysis(const Pin *pin);
|
||||
void logicValue(const Pin *pin,
|
||||
LogicValue &value,
|
||||
bool &exists);
|
||||
void caseLogicValue(const Pin *pin, LogicValue &value, bool &exists);
|
||||
void caseLogicValue(const Pin *pin,
|
||||
LogicValue &value,
|
||||
bool &exists);
|
||||
// Pin has set_case_analysis or set_logic constant value.
|
||||
bool hasLogicValue(const Pin *pin);
|
||||
// The from/thrus/to arguments passed into the following functions
|
||||
@@ -716,8 +734,8 @@ public:
|
||||
ExceptionThruSeq *thrus,
|
||||
ExceptionTo *to,
|
||||
const char *comment);
|
||||
GroupPathIterator *groupPathIterator();
|
||||
bool isGroupPathName(const char *group_name);
|
||||
GroupPathMap &groupPaths() { return group_path_map_; }
|
||||
void addException(ExceptionPath *exception);
|
||||
// The pin/clk/instance/net set arguments passed into the following
|
||||
// functions that make exception from/thru/to's are owned by the
|
||||
@@ -741,9 +759,6 @@ public:
|
||||
FilterPath *makeFilterPath(ExceptionFrom *from,
|
||||
ExceptionThruSeq *thrus,
|
||||
ExceptionTo *to);
|
||||
Clock *findClock(const char *name) const;
|
||||
virtual void findClocksMatching(PatternMatch *pattern,
|
||||
ClockSeq *clks) const;
|
||||
Wireload *wireload(const MinMax *min_max);
|
||||
void setWireload(Wireload *wireload,
|
||||
const MinMaxAll *min_max);
|
||||
@@ -803,17 +818,19 @@ public:
|
||||
|
||||
// STA interface.
|
||||
InputDelaySet *refPinInputDelays(const Pin *ref_pin) const;
|
||||
LogicValueMap *logicValues() { return &logic_value_map_; }
|
||||
LogicValueMap *caseLogicValues() { return &case_value_map_; }
|
||||
LogicValueMap &logicValues() { return logic_value_map_; }
|
||||
LogicValueMap &caseLogicValues() { return case_value_map_; }
|
||||
// Returns nullptr if set_operating_conditions has not been called.
|
||||
OperatingConditions *operatingConditions(const MinMax *min_max);
|
||||
// Instance specific process/voltage/temperature.
|
||||
Pvt *pvt(Instance *inst, const MinMax *min_max) const;
|
||||
const Pvt *pvt(Instance *inst, const MinMax *min_max) const;
|
||||
// Pvt may be shared among multiple instances.
|
||||
void setPvt(Instance *inst,
|
||||
void setPvt(const Instance *inst,
|
||||
const MinMaxAll *min_max,
|
||||
Pvt *pvt);
|
||||
const Pvt &pvt);
|
||||
InputDrive *findInputDrive(Port *port);
|
||||
Clock *findClock(const char *name) const;
|
||||
virtual ClockSeq findClocksMatching(PatternMatch *pattern) const;
|
||||
// True if pin is defined as a clock source (pin may be hierarchical).
|
||||
bool isClock(const Pin *pin) const;
|
||||
// True if pin is a clock source vertex.
|
||||
@@ -882,15 +899,17 @@ public:
|
||||
|
||||
const OutputDelaySet &outputDelays() const { return output_delays_; }
|
||||
// Pin -> output delays.
|
||||
const OutputDelaysPinMap &outputDelayPinMap() const { return output_delay_pin_map_; }
|
||||
const OutputDelaysPinMap &outputDelaysPinMap() const { return output_delay_pin_map_; }
|
||||
// Output delays on leaf_pin.
|
||||
OutputDelaySet *outputDelaysLeafPin(const Pin *leaf_pin);
|
||||
bool hasOutputDelay(const Pin *leaf_pin) const;
|
||||
|
||||
PortExtCap *portExtCap(Port *port) const;
|
||||
bool hasPortExtCap(Port *port) const;
|
||||
void portExtCap(Port *port,
|
||||
PortExtCap *portExtCap(const Port *port,
|
||||
const Corner *corner) const;
|
||||
bool hasPortExtCap(const Port *port) const;
|
||||
void portExtCap(const Port *port,
|
||||
const RiseFall *rf,
|
||||
const Corner *corner,
|
||||
const MinMax *min_max,
|
||||
// Return values.
|
||||
float &pin_cap,
|
||||
@@ -899,8 +918,9 @@ public:
|
||||
bool &has_wire_cap,
|
||||
int &fanout,
|
||||
bool &has_fanout) const;
|
||||
float portExtCap(Port *port,
|
||||
float portExtCap(const Port *port,
|
||||
const RiseFall *rf,
|
||||
const Corner *corner,
|
||||
const MinMax *min_max) const;
|
||||
// Connected total capacitance.
|
||||
// pin_cap = pin capacitance + port external pin
|
||||
@@ -914,12 +934,14 @@ public:
|
||||
float &wire_cap,
|
||||
float &fanout,
|
||||
bool &has_set_load) const;
|
||||
void portExtFanout(Port *port,
|
||||
void portExtFanout(const Port *port,
|
||||
const Corner *corner,
|
||||
const MinMax *min_max,
|
||||
// Return values.
|
||||
int &fanout,
|
||||
bool &exists);
|
||||
int portExtFanout(Port *port,
|
||||
const Corner *corner,
|
||||
const MinMax *min_max);
|
||||
// Return true if search should proceed from pin/clk (no false paths
|
||||
// start at pin/clk). When thru is true, consider -thru exceptions
|
||||
@@ -984,7 +1006,7 @@ public:
|
||||
const RiseFall *rf,
|
||||
const MinMax *min_max) const;
|
||||
bool isPathDelayInternalStartpoint(const Pin *pin) const;
|
||||
PinSet *pathDelayInternalStartpoints() const;
|
||||
const PinSet &pathDelayInternalStartpoints() const;
|
||||
bool isPathDelayInternalEndpoint(const Pin *pin) const;
|
||||
ExceptionPathSet *exceptions() { return &exceptions_; }
|
||||
void deleteExceptions();
|
||||
@@ -995,12 +1017,12 @@ public:
|
||||
void removeGraphAnnotations();
|
||||
|
||||
// Network edit before/after methods.
|
||||
void disconnectPinBefore(Pin *pin);
|
||||
void connectPinAfter(Pin *pin);
|
||||
void clkHpinDisablesChanged(Pin *pin);
|
||||
void makeClkHpinDisable(Clock *clk,
|
||||
Pin *drvr,
|
||||
Pin *load);
|
||||
void disconnectPinBefore(const Pin *pin);
|
||||
void connectPinAfter(const Pin *pin);
|
||||
void clkHpinDisablesChanged(const Pin *pin);
|
||||
void makeClkHpinDisable(const Clock *clk,
|
||||
const Pin *drvr,
|
||||
const Pin *load);
|
||||
void ensureClkHpinDisables();
|
||||
bool bidirectDrvrSlewFromLoad(const Pin *pin) const;
|
||||
|
||||
@@ -1008,11 +1030,6 @@ protected:
|
||||
void initVariables();
|
||||
void clearCycleAcctings();
|
||||
void removeLibertyAnnotations();
|
||||
void deleteExceptionMap(PinExceptionsMap *&exception_map);
|
||||
void deleteExceptionMap(InstanceExceptionsMap *&exception_map);
|
||||
void deleteExceptionMap(NetExceptionsMap *&exception_map);
|
||||
void deleteExceptionMap(ClockExceptionsMap *&exception_map);
|
||||
void deleteExceptionMap(EdgeExceptionsMap *&exception_map);
|
||||
void deleteExceptionsReferencing(Clock *clk);
|
||||
void deleteClkPinMappings(Clock *clk);
|
||||
void deleteExceptionPtHashMapSets(ExceptionPathPtHash &map);
|
||||
@@ -1020,8 +1037,9 @@ protected:
|
||||
virtual void deletePinClocks(Clock *defining_clk,
|
||||
PinSet *pins);
|
||||
void makeDefaultArrivalClock();
|
||||
InputDrive *ensureInputDrive(Port *port);
|
||||
PortExtCap *ensurePortExtPinCap(Port *port);
|
||||
InputDrive *ensureInputDrive(const Port *port);
|
||||
PortExtCap *ensurePortExtPinCap(const Port *port,
|
||||
const Corner *corner);
|
||||
ExceptionPath *findMergeMatch(ExceptionPath *exception);
|
||||
void addException1(ExceptionPath *exception);
|
||||
void addException2(ExceptionPath *exception);
|
||||
@@ -1044,15 +1062,15 @@ protected:
|
||||
ExceptionPathSet &matches);
|
||||
void findMatchingExceptionsClks(ExceptionPath *exception,
|
||||
ClockSet *clks,
|
||||
ClockExceptionsMap *exception_map,
|
||||
ClockExceptionsMap &exception_map,
|
||||
ExceptionPathSet &matches);
|
||||
void findMatchingExceptionsPins(ExceptionPath *exception,
|
||||
PinSet *pins,
|
||||
PinExceptionsMap *exception_map,
|
||||
PinExceptionsMap &exception_map,
|
||||
ExceptionPathSet &matches);
|
||||
void findMatchingExceptionsInsts(ExceptionPath *exception,
|
||||
InstanceSet *insts,
|
||||
InstanceExceptionsMap *exception_map,
|
||||
InstanceExceptionsMap &exception_map,
|
||||
ExceptionPathSet &matches);
|
||||
void findMatchingExceptions(ExceptionPath *exception,
|
||||
ExceptionPathSet *potential_matches,
|
||||
@@ -1067,43 +1085,43 @@ protected:
|
||||
void recordExceptionFirstTo(ExceptionPath *exception);
|
||||
void recordExceptionClks(ExceptionPath *exception,
|
||||
ClockSet *clks,
|
||||
ClockExceptionsMap *&exception_map);
|
||||
ClockExceptionsMap &exception_map);
|
||||
void recordExceptionInsts(ExceptionPath *exception,
|
||||
InstanceSet *insts,
|
||||
InstanceExceptionsMap *&exception_map);
|
||||
InstanceExceptionsMap &exception_map);
|
||||
void recordExceptionPins(ExceptionPath *exception,
|
||||
PinSet *pins,
|
||||
PinExceptionsMap *&exception_map);
|
||||
PinExceptionsMap &exception_map);
|
||||
void recordExceptionNets(ExceptionPath *exception,
|
||||
NetSet *nets,
|
||||
NetExceptionsMap *&exception_map);
|
||||
NetExceptionsMap &exception_map);
|
||||
void recordExceptionHpin(ExceptionPath *exception,
|
||||
Pin *pin,
|
||||
PinExceptionsMap *&exception_map);
|
||||
PinExceptionsMap &exception_map);
|
||||
void recordExceptionEdges(ExceptionPath *exception,
|
||||
EdgePinsSet *edges,
|
||||
EdgeExceptionsMap *&exception_map);
|
||||
EdgeExceptionsMap &exception_map);
|
||||
void recordMergeHash(ExceptionPath *exception, ExceptionPt *missing_pt);
|
||||
void recordMergeHashes(ExceptionPath *exception);
|
||||
void unrecordExceptionFirstPts(ExceptionPath *exception);
|
||||
void unrecordExceptionClks(ExceptionPath *exception,
|
||||
ClockSet *clks,
|
||||
ClockExceptionsMap *exception_map);
|
||||
ClockExceptionsMap &exception_map);
|
||||
void unrecordExceptionPins(ExceptionPath *exception,
|
||||
PinSet *pins,
|
||||
PinExceptionsMap *exception_map);
|
||||
PinExceptionsMap &exception_map);
|
||||
void unrecordExceptionInsts(ExceptionPath *exception,
|
||||
InstanceSet *insts,
|
||||
InstanceExceptionsMap *exception_map);
|
||||
InstanceExceptionsMap &exception_map);
|
||||
void unrecordExceptionEdges(ExceptionPath *exception,
|
||||
EdgePinsSet *edges,
|
||||
EdgeExceptionsMap *exception_map);
|
||||
EdgeExceptionsMap &exception_map);
|
||||
void unrecordExceptionNets(ExceptionPath *exception,
|
||||
NetSet *nets,
|
||||
NetExceptionsMap *exception_map);
|
||||
NetExceptionsMap &exception_map);
|
||||
void unrecordExceptionHpin(ExceptionPath *exception,
|
||||
Pin *pin,
|
||||
PinExceptionsMap *&exception_map);
|
||||
PinExceptionsMap &exception_map);
|
||||
void unrecordMergeHashes(ExceptionPath *exception);
|
||||
void unrecordMergeHash(ExceptionPath *exception,
|
||||
ExceptionPt *missing_pt);
|
||||
@@ -1142,33 +1160,29 @@ protected:
|
||||
ExceptionPath *&hi_priority_exception,
|
||||
int &hi_priority) const;
|
||||
void makeLoopPath(ExceptionThruSeq *thrus);
|
||||
void makeLoopException(Pin *loop_input_pin,
|
||||
Pin *loop_pin,
|
||||
Pin *loop_prev_pin);
|
||||
void makeLoopExceptionThru(Pin *pin,
|
||||
void makeLoopException(const Pin *loop_input_pin,
|
||||
const Pin *loop_pin,
|
||||
const Pin *loop_prev_pin);
|
||||
void makeLoopExceptionThru(const Pin *pin,
|
||||
ExceptionThruSeq *thrus);
|
||||
void deleteLoopExceptions();
|
||||
void deleteConstraints();
|
||||
InputDelay *findInputDelay(const Pin *pin,
|
||||
ClockEdge *clk_edge,
|
||||
Pin *ref_pin);
|
||||
InputDelay *makeInputDelay(Pin *pin,
|
||||
ClockEdge *clk_edge,
|
||||
Pin *ref_pin);
|
||||
void deleteInputDelays(Pin *pin,
|
||||
const ClockEdge *clk_edge);
|
||||
InputDelay *makeInputDelay(const Pin *pin,
|
||||
const ClockEdge *clk_edge);
|
||||
void deleteInputDelays(const Pin *pin,
|
||||
InputDelay *except);
|
||||
void deleteInputDelaysReferencing(Clock *clk);
|
||||
void deleteInputDelaysReferencing(const Clock *clk);
|
||||
void deleteInputDelay(InputDelay *input_delay);
|
||||
OutputDelay *findOutputDelay(const Pin *pin,
|
||||
ClockEdge *clk_edge,
|
||||
Pin *ref_pin);
|
||||
OutputDelay *makeOutputDelay(Pin *pin,
|
||||
ClockEdge *clk_edge,
|
||||
Pin *ref_pin);
|
||||
void deleteOutputDelays(Pin *pin, OutputDelay *except);
|
||||
void deleteOutputDelaysReferencing(Clock *clk);
|
||||
const ClockEdge *clk_edge);
|
||||
OutputDelay *makeOutputDelay(const Pin *pin,
|
||||
const ClockEdge *clk_edge);
|
||||
void deleteOutputDelays(const Pin *pin,
|
||||
OutputDelay *except);
|
||||
void deleteOutputDelaysReferencing(const Clock *clk);
|
||||
void deleteOutputDelay(OutputDelay *output_delay);
|
||||
void deleteInstancePvts();
|
||||
void deleteClockInsertion(ClockInsertion *insertion);
|
||||
void deleteClockInsertionsReferencing(Clock *clk);
|
||||
void deleteInterClockUncertainty(InterClockUncertainty *uncertainties);
|
||||
@@ -1198,7 +1212,6 @@ protected:
|
||||
void annotateHierClkLatency();
|
||||
void annotateHierClkLatency(const Pin *hpin,
|
||||
ClockLatency *latency);
|
||||
void initInstancePvtMaps();
|
||||
void pinCaps(const Pin *pin,
|
||||
const RiseFall *rf,
|
||||
const OperatingConditions *op_cond,
|
||||
@@ -1244,18 +1257,18 @@ protected:
|
||||
const Clock *clk,
|
||||
const RiseFall *from_rf,
|
||||
const RiseFall *to_rf) const;
|
||||
void disconnectPinBefore(Pin *pin,
|
||||
void disconnectPinBefore(const Pin *pin,
|
||||
ExceptionPathSet *exceptions);
|
||||
void clockGroupsDeleteClkRefs(Clock *clk);
|
||||
void clearGroupPathMap();
|
||||
|
||||
AnalysisType analysis_type_;
|
||||
OperatingConditions *operating_conditions_[MinMax::index_count];
|
||||
InstancePvtMap *instance_pvt_maps_[MinMax::index_count];
|
||||
InstancePvtMap instance_pvt_maps_[MinMax::index_count];
|
||||
DeratingFactorsGlobal *derating_factors_;
|
||||
NetDeratingFactorsMap *net_derating_factors_;
|
||||
InstDeratingFactorsMap *inst_derating_factors_;
|
||||
CellDeratingFactorsMap *cell_derating_factors_;
|
||||
NetDeratingFactorsMap net_derating_factors_;
|
||||
InstDeratingFactorsMap inst_derating_factors_;
|
||||
CellDeratingFactorsMap cell_derating_factors_;
|
||||
// Clock sequence retains clock definition order.
|
||||
// This is important for getting consistent regression results,
|
||||
// which iterating over the name map can't provide.
|
||||
@@ -1273,15 +1286,15 @@ protected:
|
||||
bool clk_hpin_disables_valid_;
|
||||
PinSet propagated_clk_pins_;
|
||||
ClockLatencies clk_latencies_;
|
||||
ClockInsertions *clk_insertions_;
|
||||
ClockInsertions clk_insertions_;
|
||||
PinClockUncertaintyMap pin_clk_uncertainty_map_;
|
||||
InterClockUncertaintySet inter_clk_uncertainties_;
|
||||
// clk_groups name -> clk_groups
|
||||
ClockGroupsNameMap clk_groups_name_map_;
|
||||
// clk to clk paths excluded by clock groups.
|
||||
ClockPairSet *clk_group_exclusions_;
|
||||
ClockPairSet clk_group_exclusions_;
|
||||
// clks in the same set_clock_group set.
|
||||
ClockPairSet *clk_group_same_;
|
||||
ClockPairSet clk_group_same_;
|
||||
ClockSenseMap clk_sense_map_;
|
||||
ClockGatingCheck *clk_gating_check_;
|
||||
ClockGatingCheckMap clk_gating_check_map_;
|
||||
@@ -1294,11 +1307,11 @@ protected:
|
||||
|
||||
InputDelaySet input_delays_;
|
||||
InputDelaysPinMap input_delay_pin_map_;
|
||||
int input_delay_index_;
|
||||
InputDelaysPinMap input_delay_ref_pin_map_;
|
||||
// Input delays on hierarchical pins are indexed by the load pins.
|
||||
InputDelaysPinMap input_delay_leaf_pin_map_;
|
||||
InputDelaysPinMap input_delay_internal_pin_map_;
|
||||
int input_delay_index_;
|
||||
|
||||
OutputDelaySet output_delays_;
|
||||
OutputDelaysPinMap output_delay_pin_map_;
|
||||
@@ -1318,12 +1331,12 @@ protected:
|
||||
// set_load port
|
||||
// set_fanout_load port
|
||||
// Indexed by corner_index.
|
||||
PortExtCapMap *port_cap_map_;
|
||||
vector<PortExtCapMap> port_ext_cap_maps_;
|
||||
// set_load net
|
||||
// Indexed by corner_index.
|
||||
NetWireCapMap *net_wire_cap_map_;
|
||||
vector<NetWireCapMap> net_wire_cap_maps_;
|
||||
// Indexed by corner_index.
|
||||
PinWireCapMap *drvr_pin_wire_cap_map_;
|
||||
vector<PinWireCapMap> drvr_pin_wire_cap_maps_;
|
||||
NetResistanceMap net_res_map_;
|
||||
PinSet disabled_pins_;
|
||||
PortSet disabled_ports_;
|
||||
@@ -1338,25 +1351,24 @@ protected:
|
||||
|
||||
bool have_thru_hpin_exceptions_;
|
||||
// First pin/clock/instance/net/edge exception point to exception set map.
|
||||
PinExceptionsMap *first_from_pin_exceptions_;
|
||||
ClockExceptionsMap *first_from_clk_exceptions_;
|
||||
InstanceExceptionsMap *first_from_inst_exceptions_;
|
||||
PinExceptionsMap *first_thru_pin_exceptions_;
|
||||
InstanceExceptionsMap *first_thru_inst_exceptions_;
|
||||
PinExceptionsMap first_from_pin_exceptions_;
|
||||
ClockExceptionsMap first_from_clk_exceptions_;
|
||||
InstanceExceptionsMap first_from_inst_exceptions_;
|
||||
PinExceptionsMap first_thru_pin_exceptions_;
|
||||
InstanceExceptionsMap first_thru_inst_exceptions_;
|
||||
// Nets that have exception -thru nets.
|
||||
NetExceptionsMap *first_thru_net_exceptions_;
|
||||
PinExceptionsMap *first_to_pin_exceptions_;
|
||||
ClockExceptionsMap *first_to_clk_exceptions_;
|
||||
InstanceExceptionsMap *first_to_inst_exceptions_;
|
||||
NetExceptionsMap first_thru_net_exceptions_;
|
||||
PinExceptionsMap first_to_pin_exceptions_;
|
||||
ClockExceptionsMap first_to_clk_exceptions_;
|
||||
InstanceExceptionsMap first_to_inst_exceptions_;
|
||||
// Edges that traverse hierarchical exception pins.
|
||||
EdgeExceptionsMap *first_thru_edge_exceptions_;
|
||||
|
||||
EdgeExceptionsMap first_thru_edge_exceptions_;
|
||||
// Exception hash with one missing from/thru/to point, used for merging.
|
||||
ExceptionPathPtHash exception_merge_hash_;
|
||||
// Path delay -from pin internal startpoints.
|
||||
PinSet *path_delay_internal_startpoints_;
|
||||
PinSet path_delay_internal_startpoints_;
|
||||
// Path delay -to pin internal endpoints.
|
||||
PinSet *path_delay_internal_endpoints_;
|
||||
PinSet path_delay_internal_endpoints_;
|
||||
// There is a path delay exception without a -to.
|
||||
bool path_delays_without_to_;
|
||||
// Group path exception names.
|
||||
@@ -1401,26 +1413,4 @@ private:
|
||||
friend class GroupPathIterator;
|
||||
};
|
||||
|
||||
class ClockIterator : public ClockSeq::Iterator
|
||||
{
|
||||
public:
|
||||
ClockIterator(Sdc *sdc);
|
||||
|
||||
private:
|
||||
ClockIterator(ClockSeq &clocks);
|
||||
|
||||
friend class Sdc;
|
||||
};
|
||||
|
||||
class GroupPathIterator : public GroupPathMap::Iterator
|
||||
{
|
||||
public:
|
||||
GroupPathIterator(Sdc *sdc);
|
||||
|
||||
private:
|
||||
GroupPathIterator(GroupPathMap &group_path_map);
|
||||
|
||||
friend class Sdc;
|
||||
};
|
||||
|
||||
} // namespace
|
||||
|
||||
+34
-7
@@ -53,7 +53,6 @@ class DataCheck;
|
||||
class Wireload;
|
||||
class ClockLatency;
|
||||
class ClockInsertion;
|
||||
class ClockGroup;
|
||||
class ClockGroups;
|
||||
class PortDelay;
|
||||
|
||||
@@ -66,28 +65,56 @@ enum class ClockSense { positive, negative, stop };
|
||||
|
||||
typedef std::pair<const Clock*, const Clock*> ClockPair;
|
||||
|
||||
class ClockIndexLess
|
||||
{
|
||||
public:
|
||||
bool operator()(const Clock *clk1,
|
||||
const Clock *clk2) const;
|
||||
};
|
||||
|
||||
typedef Vector<float> FloatSeq;
|
||||
typedef Vector<int> IntSeq;
|
||||
typedef Vector<Clock*> ClockSeq;
|
||||
typedef Set<Clock*> ClockSet;
|
||||
typedef Set<Clock*, ClockIndexLess> ClockSet;
|
||||
typedef ClockSet ClockGroup;
|
||||
typedef Vector<PinSet*> PinSetSeq;
|
||||
typedef MinMax SetupHold;
|
||||
typedef MinMaxAll SetupHoldAll;
|
||||
typedef Vector<ExceptionThru*> ExceptionThruSeq;
|
||||
typedef Set<LibertyPortPair*, LibertyPortPairLess> LibertyPortPairSet;
|
||||
typedef Map<Instance*, DisabledInstancePorts*> DisabledInstancePortsMap;
|
||||
typedef Map<LibertyCell*, DisabledCellPorts*> DisabledCellPortsMap;
|
||||
typedef Set<LibertyPortPair, LibertyPortPairLess> LibertyPortPairSet;
|
||||
typedef Map<const Instance*, DisabledInstancePorts*> DisabledInstancePortsMap;
|
||||
typedef Map<const LibertyCell*, DisabledCellPorts*> DisabledCellPortsMap;
|
||||
typedef MinMaxValues<float> ClockUncertainties;
|
||||
typedef Set<ExceptionPath*> ExceptionPathSet;
|
||||
typedef PinPair EdgePins;
|
||||
typedef PinPairSet EdgePinsSet;
|
||||
typedef Map<const Pin*, LogicValue> LogicValueMap;
|
||||
typedef Set<ClockGroup*> ClockGroupSet;
|
||||
|
||||
class ClockSetLess
|
||||
{
|
||||
public:
|
||||
bool operator()(const ClockSet *set1,
|
||||
const ClockSet *set2) const;
|
||||
};
|
||||
|
||||
typedef Set<ClockGroup*, ClockSetLess> ClockGroupSet;
|
||||
|
||||
// For Search.
|
||||
class ExceptionState;
|
||||
|
||||
class ExceptionStateLess
|
||||
{
|
||||
public:
|
||||
ExceptionStateLess(const Network *network);
|
||||
bool operator()(const ExceptionState *state1,
|
||||
const ExceptionState *state2) const;
|
||||
|
||||
private:
|
||||
const Network *network_;
|
||||
};
|
||||
|
||||
class ExceptionPath;
|
||||
typedef Set<ExceptionState*> ExceptionStateSet;
|
||||
typedef Set<ExceptionState*, ExceptionStateLess> ExceptionStateSet;
|
||||
|
||||
enum class CrprMode { same_pin, same_transition };
|
||||
|
||||
|
||||
+28
-21
@@ -32,19 +32,20 @@ public:
|
||||
bool make_black_boxes,
|
||||
Report *report);
|
||||
|
||||
virtual const char *name(const Library *library) const;
|
||||
virtual ObjectId id(const Library *library) const;
|
||||
virtual LibraryIterator *libraryIterator() const;
|
||||
virtual LibertyLibraryIterator *libertyLibraryIterator() const;
|
||||
virtual Library *findLibrary(const char *name);
|
||||
virtual LibertyLibrary *findLibertyFilename(const char *filename);
|
||||
virtual LibertyLibrary *findLiberty(const char *name);
|
||||
virtual const char *name(const Library *library) const;
|
||||
virtual Cell *findCell(const Library *library,
|
||||
const char *name) const;
|
||||
virtual void findCellsMatching(const Library *library,
|
||||
const PatternMatch *pattern,
|
||||
CellSeq *cells) const;
|
||||
virtual CellSeq findCellsMatching(const Library *library,
|
||||
const PatternMatch *pattern) const;
|
||||
|
||||
virtual const char *name(const Cell *cell) const;
|
||||
virtual ObjectId id(const Cell *cell) const;
|
||||
virtual Library *library(const Cell *cell) const;
|
||||
virtual LibertyCell *libertyCell(Cell *cell) const;
|
||||
virtual const LibertyCell *libertyCell(const Cell *cell) const;
|
||||
@@ -53,15 +54,15 @@ public:
|
||||
virtual const char *filename(const Cell *cell);
|
||||
virtual Port *findPort(const Cell *cell,
|
||||
const char *name) const;
|
||||
virtual void findPortsMatching(const Cell *cell,
|
||||
const PatternMatch *pattern,
|
||||
PortSeq *ports) const;
|
||||
virtual PortSeq findPortsMatching(const Cell *cell,
|
||||
const PatternMatch *pattern) const;
|
||||
virtual bool isLeaf(const Cell *cell) const;
|
||||
virtual CellPortIterator *portIterator(const Cell *cell) const;
|
||||
virtual CellPortBitIterator *portBitIterator(const Cell *cell) const;
|
||||
virtual int portBitCount(const Cell *cell) const;
|
||||
|
||||
virtual const char *name(const Port *port) const;
|
||||
virtual ObjectId id(const Port *port) const;
|
||||
virtual Cell *cell(const Port *port) const;
|
||||
virtual LibertyPort *libertyPort(const Port *port) const;
|
||||
virtual PortDirection *direction(const Port *port) const;
|
||||
@@ -78,6 +79,7 @@ public:
|
||||
virtual PortMemberIterator *memberIterator(const Port *port) const;
|
||||
virtual bool hasMembers(const Port *port) const;
|
||||
|
||||
virtual ObjectId id(const Instance *instance) const;
|
||||
virtual Instance *topInstance() const;
|
||||
virtual Cell *cell(const Instance *instance) const;
|
||||
virtual Instance *parent(const Instance *instance) const;
|
||||
@@ -94,6 +96,7 @@ public:
|
||||
virtual InstanceNetIterator *
|
||||
netIterator(const Instance *instance) const;
|
||||
|
||||
virtual ObjectId id(const Pin *pin) const;
|
||||
virtual Port *port(const Pin *pin) const;
|
||||
virtual Instance *instance(const Pin *pin) const;
|
||||
virtual Net *net(const Pin *pin) const;
|
||||
@@ -108,9 +111,11 @@ public:
|
||||
double &y,
|
||||
bool &exists) const;
|
||||
|
||||
virtual ObjectId id(const Term *term) const;
|
||||
virtual Net *net(const Term *term) const;
|
||||
virtual Pin *pin(const Term *term) const;
|
||||
|
||||
virtual ObjectId id(const Net *net) const;
|
||||
virtual Instance *instance(const Net *net) const;
|
||||
virtual bool isPower(const Net *net) const;
|
||||
virtual bool isGround(const Net *net) const;
|
||||
@@ -151,6 +156,7 @@ public:
|
||||
|
||||
// Any overloaded functions from the base class must be listed here.
|
||||
using Network::name;
|
||||
using Network::id;
|
||||
using Network::isLeaf;
|
||||
using Network::netIterator;
|
||||
using Network::findPin;
|
||||
@@ -175,9 +181,8 @@ public:
|
||||
|
||||
virtual Port *findPort(const Cell *cell,
|
||||
const char *name) const;
|
||||
virtual void findPortsMatching(const Cell *cell,
|
||||
const PatternMatch *pattern,
|
||||
PortSeq *ports) const;
|
||||
virtual PortSeq findPortsMatching(const Cell *cell,
|
||||
const PatternMatch *pattern) const;
|
||||
virtual const char *name(const Port *port) const;
|
||||
virtual const char *busName(const Port *port) const;
|
||||
|
||||
@@ -185,30 +190,28 @@ public:
|
||||
virtual const char *pathName(const Instance *instance) const;
|
||||
virtual const char *pathName(const Pin *pin) const;
|
||||
virtual const char *portName(const Pin *pin) const;
|
||||
|
||||
virtual const char *name(const Net *net) const;
|
||||
virtual const char *pathName(const Net *net) const;
|
||||
|
||||
virtual Instance *findInstance(const char *path_name) const;
|
||||
virtual void findInstancesMatching(const Instance *context,
|
||||
const PatternMatch *pattern,
|
||||
InstanceSeq *insts) const;
|
||||
virtual InstanceSeq findInstancesMatching(const Instance *context,
|
||||
const PatternMatch *pattern) const;
|
||||
virtual Net *findNet(const char *path_name) const;
|
||||
virtual Net *findNet(const Instance *instance,
|
||||
const char *net_name) const;
|
||||
virtual void findNetsMatching(const Instance *parent,
|
||||
const PatternMatch *pattern,
|
||||
NetSeq *nets) const;
|
||||
virtual NetSeq findNetsMatching(const Instance *parent,
|
||||
const PatternMatch *pattern) const;
|
||||
virtual void findInstNetsMatching(const Instance *instance,
|
||||
const PatternMatch *pattern,
|
||||
NetSeq *nets) const;
|
||||
NetSeq &nets) const;
|
||||
virtual Instance *findChild(const Instance *parent,
|
||||
const char *name) const;
|
||||
virtual Pin *findPin(const char *path_name) const;
|
||||
virtual Pin *findPin(const Instance *instance,
|
||||
const char *port_name) const;
|
||||
virtual void findPinsMatching(const Instance *instance,
|
||||
const PatternMatch *pattern,
|
||||
PinSeq *pins) const;
|
||||
virtual PinSeq findPinsMatching(const Instance *instance,
|
||||
const PatternMatch *pattern) const;
|
||||
|
||||
virtual Instance *makeInstance(LibertyCell *cell,
|
||||
const char *name,
|
||||
@@ -221,6 +224,7 @@ public:
|
||||
// findInstPinsMatching(instance, pattern)
|
||||
|
||||
using Network::name;
|
||||
using Network::id;
|
||||
using Network::findPin;
|
||||
|
||||
protected:
|
||||
@@ -246,7 +250,10 @@ protected:
|
||||
visit_tail) const;
|
||||
bool visitPinTail(const Instance *instance,
|
||||
const PatternMatch *tail,
|
||||
PinSeq *pins) const;
|
||||
PinSeq &matches) const;
|
||||
void findInstancesMatching1(const Instance *context,
|
||||
const PatternMatch *pattern,
|
||||
InstanceSeq &matches) const;
|
||||
|
||||
const char *staToSdc(const char *sta_name) const;
|
||||
};
|
||||
|
||||
+21
-22
@@ -114,7 +114,7 @@ public:
|
||||
void requiredsInvalid();
|
||||
// Invalidate vertex required time.
|
||||
void requiredInvalid(Vertex *vertex);
|
||||
void requiredInvalid(Instance *inst);
|
||||
void requiredInvalid(const Instance *inst);
|
||||
void requiredInvalid(const Pin *pin);
|
||||
// Vertex will be deleted.
|
||||
void deleteVertexBefore(Vertex *vertex);
|
||||
@@ -150,7 +150,7 @@ public:
|
||||
Arrival clkPathArrival(const Path *clk_path) const;
|
||||
Arrival clkPathArrival(const Path *clk_path,
|
||||
ClkInfo *clk_info,
|
||||
ClockEdge *clk_edge,
|
||||
const ClockEdge *clk_edge,
|
||||
const MinMax *min_max,
|
||||
const PathAnalysisPt *path_ap) const;
|
||||
// Clock arrival at the path source/launch point.
|
||||
@@ -179,12 +179,8 @@ public:
|
||||
// Vertices on propagated generated clock source paths.
|
||||
bool isGenClkSrc(const Vertex *vertex) const;
|
||||
// The set of clocks that arrive at vertex.
|
||||
void clocks(const Vertex *vertex,
|
||||
// Return value.
|
||||
ClockSet &clks) const;
|
||||
void clocks(const Pin *pin,
|
||||
// Return value.
|
||||
ClockSet &clks) const;
|
||||
ClockSet clocks(const Vertex *vertex) const;
|
||||
ClockSet clocks(const Pin *pin) const;
|
||||
void visitStartpoints(VertexVisitor *visitor);
|
||||
void visitEndpoints(VertexVisitor *visitor);
|
||||
bool havePathGroups() const;
|
||||
@@ -222,7 +218,7 @@ public:
|
||||
bool require_exception);
|
||||
Tag *fromRegClkTag(const Pin *from_pin,
|
||||
const RiseFall *from_rf,
|
||||
Clock *clk,
|
||||
const Clock *clk,
|
||||
const RiseFall *clk_rf,
|
||||
ClkInfo *clk_info,
|
||||
const Pin *to_pin,
|
||||
@@ -305,7 +301,7 @@ public:
|
||||
bool own_states);
|
||||
void reportTags() const;
|
||||
void reportClkInfos() const;
|
||||
virtual ClkInfo *findClkInfo(ClockEdge *clk_edge,
|
||||
virtual ClkInfo *findClkInfo(const ClockEdge *clk_edge,
|
||||
const Pin *clk_src,
|
||||
bool is_propagated,
|
||||
const Pin *gen_clk_src,
|
||||
@@ -316,7 +312,7 @@ public:
|
||||
ClockUncertainties *uncertainties,
|
||||
const PathAnalysisPt *path_ap,
|
||||
PathVertex *crpr_clk_path);
|
||||
ClkInfo *findClkInfo(ClockEdge *clk_edge,
|
||||
ClkInfo *findClkInfo(const ClockEdge *clk_edge,
|
||||
const Pin *clk_src,
|
||||
bool is_propagated,
|
||||
Arrival insertion,
|
||||
@@ -368,24 +364,24 @@ protected:
|
||||
void findClockVertices(VertexSet &vertices);
|
||||
void seedClkDataArrival(const Pin *pin,
|
||||
const RiseFall *rf,
|
||||
Clock *clk,
|
||||
ClockEdge *clk_edge,
|
||||
const Clock *clk,
|
||||
const ClockEdge *clk_edge,
|
||||
const MinMax *min_max,
|
||||
const PathAnalysisPt *path_ap,
|
||||
Arrival insertion,
|
||||
TagGroupBldr *tag_bldr);
|
||||
void seedClkArrival(const Pin *pin,
|
||||
const RiseFall *rf,
|
||||
Clock *clk,
|
||||
ClockEdge *clk_edge,
|
||||
const Clock *clk,
|
||||
const ClockEdge *clk_edge,
|
||||
const MinMax *min_max,
|
||||
const PathAnalysisPt *path_ap,
|
||||
Arrival insertion,
|
||||
TagGroupBldr *tag_bldr);
|
||||
Tag *clkDataTag(const Pin *pin,
|
||||
Clock *clk,
|
||||
const Clock *clk,
|
||||
const RiseFall *rf,
|
||||
ClockEdge *clk_edge,
|
||||
const ClockEdge *clk_edge,
|
||||
Arrival insertion,
|
||||
const MinMax *min_max,
|
||||
const PathAnalysisPt *path_ap);
|
||||
@@ -402,7 +398,7 @@ protected:
|
||||
ClockSet *wrt_clks);
|
||||
void seedInputDelayArrival(const Pin *pin,
|
||||
InputDelay *input_delay,
|
||||
ClockEdge *clk_edge,
|
||||
const ClockEdge *clk_edge,
|
||||
float clk_arrival,
|
||||
float clk_insertion,
|
||||
float clk_latency,
|
||||
@@ -414,7 +410,7 @@ protected:
|
||||
const RiseFall *rf,
|
||||
float arrival,
|
||||
InputDelay *input_delay,
|
||||
ClockEdge *clk_edge,
|
||||
const ClockEdge *clk_edge,
|
||||
float clk_insertion,
|
||||
float clk_latency,
|
||||
bool is_segment_start,
|
||||
@@ -422,7 +418,7 @@ protected:
|
||||
PathAnalysisPt *path_ap,
|
||||
TagGroupBldr *tag_bldr);
|
||||
void inputDelayClkArrival(InputDelay *input_delay,
|
||||
ClockEdge *clk_edge,
|
||||
const ClockEdge *clk_edge,
|
||||
const MinMax *min_max,
|
||||
const PathAnalysisPt *path_ap,
|
||||
// Return values.
|
||||
@@ -430,7 +426,7 @@ protected:
|
||||
float &clk_insertion,
|
||||
float &clk_latency);
|
||||
void inputDelayRefPinArrival(Path *ref_path,
|
||||
ClockEdge *clk_edge,
|
||||
const ClockEdge *clk_edge,
|
||||
const MinMax *min_max,
|
||||
// Return values.
|
||||
float &ref_arrival,
|
||||
@@ -438,7 +434,7 @@ protected:
|
||||
float &ref_latency);
|
||||
Tag *inputDelayTag(const Pin *pin,
|
||||
const RiseFall *rf,
|
||||
ClockEdge *clk_edge,
|
||||
const ClockEdge *clk_edge,
|
||||
float clk_insertion,
|
||||
float clk_latency,
|
||||
InputDelay *input_delay,
|
||||
@@ -527,6 +523,9 @@ protected:
|
||||
bool matchesFilterTo(Path *path,
|
||||
const ClockEdge *to_clk_edge) const;
|
||||
PathRef pathClkPathArrival1(const Path *path) const;
|
||||
void clocks(const Vertex *vertex,
|
||||
// Return value.
|
||||
ClockSet &clks) const;
|
||||
|
||||
////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
+8
-8
@@ -71,11 +71,11 @@ public:
|
||||
}
|
||||
|
||||
static bool
|
||||
intersects(std::set<KEY, CMP> &set1,
|
||||
std::set<KEY, CMP> &set2);
|
||||
intersects(const std::set<KEY, CMP> &set1,
|
||||
const std::set<KEY, CMP> &set2);
|
||||
static bool
|
||||
intersects(std::set<KEY, CMP> *set1,
|
||||
std::set<KEY, CMP> *set2);
|
||||
intersects(const std::set<KEY, CMP> *set1,
|
||||
const std::set<KEY, CMP> *set2);
|
||||
|
||||
// Java style container itererator
|
||||
// Set::Iterator<Key*> iter(set);
|
||||
@@ -174,16 +174,16 @@ Set<KEY, CMP>::isSubset(const std::set<KEY, CMP> *set2)
|
||||
|
||||
template <class KEY, class CMP>
|
||||
bool
|
||||
Set<KEY, CMP>::intersects(std::set<KEY, CMP> &set1,
|
||||
std::set<KEY, CMP> &set2)
|
||||
Set<KEY, CMP>::intersects(const std::set<KEY, CMP> &set1,
|
||||
const std::set<KEY, CMP> &set2)
|
||||
{
|
||||
return intersects(&set1, &set2);
|
||||
}
|
||||
|
||||
template <class KEY, class CMP>
|
||||
bool
|
||||
Set<KEY, CMP>::intersects(std::set<KEY, CMP> *set1,
|
||||
std::set<KEY, CMP> *set2)
|
||||
Set<KEY, CMP>::intersects(const std::set<KEY, CMP> *set1,
|
||||
const std::set<KEY, CMP> *set2)
|
||||
{
|
||||
if (set1 && !set1->empty()
|
||||
&& set2 && !set2->empty()) {
|
||||
|
||||
+104
-109
@@ -59,7 +59,6 @@ class ClkSkews;
|
||||
class ReportField;
|
||||
class Power;
|
||||
class PowerResult;
|
||||
class ClockIterator;
|
||||
class EquivCells;
|
||||
|
||||
typedef InstanceSeq::Iterator SlowDrvrIterator;
|
||||
@@ -151,75 +150,77 @@ public:
|
||||
const EarlyLate *early_late,
|
||||
float derate);
|
||||
void unsetTimingDerate();
|
||||
void setInputSlew(Port *port,
|
||||
void setInputSlew(const Port *port,
|
||||
const RiseFallBoth *rf,
|
||||
const MinMaxAll *min_max,
|
||||
float slew);
|
||||
// Set port external pin load (set_load -pin port).
|
||||
void setPortExtPinCap(Port *port,
|
||||
void setPortExtPinCap(const Port *port,
|
||||
const RiseFallBoth *rf,
|
||||
const Corner *corner,
|
||||
const MinMaxAll *min_max,
|
||||
float cap);
|
||||
void portExtCaps(Port *port,
|
||||
void portExtCaps(const Port *port,
|
||||
const Corner *corner,
|
||||
const MinMax *min_max,
|
||||
float &pin_cap,
|
||||
float &wire_cap,
|
||||
int &fanout);
|
||||
// Set port external wire load (set_load -wire port).
|
||||
void setPortExtWireCap(Port *port,
|
||||
void setPortExtWireCap(const Port *port,
|
||||
bool subtract_pin_cap,
|
||||
const RiseFallBoth *rf,
|
||||
const Corner *corner,
|
||||
const MinMaxAll *min_max,
|
||||
float cap);
|
||||
// Set net wire capacitance (set_load -wire net).
|
||||
void setNetWireCap(Net *net,
|
||||
void setNetWireCap(const Net *net,
|
||||
bool subtract_pin_load,
|
||||
const Corner *corner,
|
||||
const MinMaxAll *min_max,
|
||||
float cap);
|
||||
// Set port external fanout (used by wireload models).
|
||||
void setPortExtFanout(Port *port,
|
||||
void setPortExtFanout(const Port *port,
|
||||
int fanout,
|
||||
const Corner *corner,
|
||||
const MinMaxAll *min_max);
|
||||
// Remove all "set_load net" annotations.
|
||||
void removeNetLoadCaps() const;
|
||||
// Liberty port capacitance.
|
||||
float capacitance(const LibertyPort *port,
|
||||
Corner *corner,
|
||||
const MinMax *min_max);
|
||||
// pin_cap = net pin capacitances + port external pin capacitance,
|
||||
// wire_cap = annotated net capacitance + port external wire capacitance.
|
||||
void connectedCap(Pin *drvr_pin,
|
||||
void connectedCap(const Pin *drvr_pin,
|
||||
const RiseFall *rf,
|
||||
const Corner *corner,
|
||||
const MinMax *min_max,
|
||||
float &pin_cap,
|
||||
float &wire_cap) const;
|
||||
void connectedCap(Net *net,
|
||||
void connectedCap(const Net *net,
|
||||
Corner *corner,
|
||||
const MinMax *min_max,
|
||||
float &pin_cap,
|
||||
float &wire_cap) const;
|
||||
void setResistance(Net *net,
|
||||
void setResistance(const Net *net,
|
||||
const MinMaxAll *min_max,
|
||||
float res);
|
||||
void setDriveCell(LibertyLibrary *library,
|
||||
LibertyCell *cell,
|
||||
Port *port,
|
||||
LibertyPort *from_port,
|
||||
void setDriveCell(const LibertyLibrary *library,
|
||||
const LibertyCell *cell,
|
||||
const Port *port,
|
||||
const LibertyPort *from_port,
|
||||
float *from_slews,
|
||||
LibertyPort *to_port,
|
||||
const LibertyPort *to_port,
|
||||
const RiseFallBoth *rf,
|
||||
const MinMaxAll *min_max);
|
||||
void setDriveResistance(Port *port,
|
||||
void setDriveResistance(const Port *port,
|
||||
const RiseFallBoth *rf,
|
||||
const MinMaxAll *min_max,
|
||||
float res);
|
||||
void setLatchBorrowLimit(Pin *pin,
|
||||
void setLatchBorrowLimit(const Pin *pin,
|
||||
float limit);
|
||||
void setLatchBorrowLimit(Instance *inst,
|
||||
void setLatchBorrowLimit(const Instance *inst,
|
||||
float limit);
|
||||
void setLatchBorrowLimit(Clock *clk,
|
||||
void setLatchBorrowLimit(const Clock *clk,
|
||||
float limit);
|
||||
void setMinPulseWidth(const RiseFallBoth *rf,
|
||||
float min_width);
|
||||
@@ -430,7 +431,7 @@ public:
|
||||
bool isDisabledClock(Edge *edge);
|
||||
// Return a set of constant pins that disabled edge.
|
||||
// Caller owns the returned set.
|
||||
PinSet *disabledConstantPins(Edge *edge);
|
||||
PinSet disabledConstantPins(Edge *edge);
|
||||
// Edge timing sense with propagated constants.
|
||||
TimingSense simTimingSense(Edge *edge);
|
||||
// Edge is disabled by set_disable_timing constraint.
|
||||
@@ -444,8 +445,8 @@ public:
|
||||
bool isDisabledPresetClr(Edge *edge) const;
|
||||
// Return a vector of graph edges that are disabled, sorted by
|
||||
// from/to vertex names. Caller owns the returned vector.
|
||||
EdgeSeq *disabledEdges();
|
||||
EdgeSeq *disabledEdgesSorted();
|
||||
EdgeSeq disabledEdges();
|
||||
EdgeSeq disabledEdgesSorted();
|
||||
void disableClockGatingCheck(Instance *inst);
|
||||
void disableClockGatingCheck(Pin *pin);
|
||||
void removeDisableClockGatingCheck(Instance *inst);
|
||||
@@ -540,35 +541,34 @@ public:
|
||||
void checkExceptionToPins(ExceptionTo *to,
|
||||
const char *file, int) const;
|
||||
void deleteExceptionTo(ExceptionTo *to);
|
||||
InstanceSet *findRegisterInstances(ClockSet *clks,
|
||||
const RiseFallBoth *clk_rf,
|
||||
bool edge_triggered,
|
||||
bool latches);
|
||||
PinSet *findRegisterDataPins(ClockSet *clks,
|
||||
const RiseFallBoth *clk_rf,
|
||||
bool registers,
|
||||
bool latches);
|
||||
PinSet *findRegisterClkPins(ClockSet *clks,
|
||||
const RiseFallBoth *clk_rf,
|
||||
bool registers,
|
||||
bool latches);
|
||||
PinSet *findRegisterAsyncPins(ClockSet *clks,
|
||||
const RiseFallBoth *clk_rf,
|
||||
bool registers,
|
||||
bool latches);
|
||||
PinSet *findRegisterOutputPins(ClockSet *clks,
|
||||
const RiseFallBoth *clk_rf,
|
||||
bool registers,
|
||||
bool latches);
|
||||
PinSet *
|
||||
findFaninPins(PinSeq *to,
|
||||
bool flat,
|
||||
bool startpoints_only,
|
||||
int inst_levels,
|
||||
int pin_levels,
|
||||
bool thru_disabled,
|
||||
bool thru_constants);
|
||||
InstanceSet *
|
||||
InstanceSet findRegisterInstances(ClockSet *clks,
|
||||
const RiseFallBoth *clk_rf,
|
||||
bool edge_triggered,
|
||||
bool latches);
|
||||
PinSet findRegisterDataPins(ClockSet *clks,
|
||||
const RiseFallBoth *clk_rf,
|
||||
bool registers,
|
||||
bool latches);
|
||||
PinSet findRegisterClkPins(ClockSet *clks,
|
||||
const RiseFallBoth *clk_rf,
|
||||
bool registers,
|
||||
bool latches);
|
||||
PinSet findRegisterAsyncPins(ClockSet *clks,
|
||||
const RiseFallBoth *clk_rf,
|
||||
bool registers,
|
||||
bool latches);
|
||||
PinSet findRegisterOutputPins(ClockSet *clks,
|
||||
const RiseFallBoth *clk_rf,
|
||||
bool registers,
|
||||
bool latches);
|
||||
PinSet findFaninPins(PinSeq *to,
|
||||
bool flat,
|
||||
bool startpoints_only,
|
||||
int inst_levels,
|
||||
int pin_levels,
|
||||
bool thru_disabled,
|
||||
bool thru_constants);
|
||||
InstanceSet
|
||||
findFaninInstances(PinSeq *to,
|
||||
bool flat,
|
||||
bool startpoints_only,
|
||||
@@ -576,7 +576,7 @@ public:
|
||||
int pin_levels,
|
||||
bool thru_disabled,
|
||||
bool thru_constants);
|
||||
PinSet *
|
||||
PinSet
|
||||
findFanoutPins(PinSeq *from,
|
||||
bool flat,
|
||||
bool endpoints_only,
|
||||
@@ -584,7 +584,7 @@ public:
|
||||
int pin_levels,
|
||||
bool thru_disabled,
|
||||
bool thru_constants);
|
||||
InstanceSet *
|
||||
InstanceSet
|
||||
findFanoutInstances(PinSeq *from,
|
||||
bool flat,
|
||||
bool endpoints_only,
|
||||
@@ -594,18 +594,16 @@ public:
|
||||
bool thru_constants);
|
||||
|
||||
// The set of clocks that reach pin.
|
||||
void clocks(const Pin *pin,
|
||||
// Return value.
|
||||
ClockSet &clks);
|
||||
ClockSet clocks(const Pin *pin);
|
||||
|
||||
void checkSlewLimitPreamble();
|
||||
// Return pins with the min/max slew limit slack.
|
||||
// net=null check all nets
|
||||
// corner=nullptr checks all corners.
|
||||
PinSeq *checkSlewLimits(Net *net,
|
||||
bool violators,
|
||||
const Corner *corner,
|
||||
const MinMax *min_max);
|
||||
PinSeq checkSlewLimits(Net *net,
|
||||
bool violators,
|
||||
const Corner *corner,
|
||||
const MinMax *min_max);
|
||||
void reportSlewLimitShortHeader();
|
||||
void reportSlewLimitShort(Pin *pin,
|
||||
const Corner *corner,
|
||||
@@ -625,7 +623,7 @@ public:
|
||||
float &limit,
|
||||
float &slack);
|
||||
void maxSlewCheck(// Return values.
|
||||
Pin *&pin,
|
||||
const Pin *&pin,
|
||||
Slew &slew,
|
||||
float &slack,
|
||||
float &limit);
|
||||
@@ -640,9 +638,9 @@ public:
|
||||
// Return pins with the min/max fanout limit slack.
|
||||
// net=null check all nets
|
||||
// corner=nullptr checks all corners.
|
||||
PinSeq *checkFanoutLimits(Net *net,
|
||||
bool violators,
|
||||
const MinMax *min_max);
|
||||
PinSeq checkFanoutLimits(Net *net,
|
||||
bool violators,
|
||||
const MinMax *min_max);
|
||||
void reportFanoutLimitShortHeader();
|
||||
void reportFanoutLimitShort(Pin *pin,
|
||||
const MinMax *min_max);
|
||||
@@ -656,7 +654,7 @@ public:
|
||||
float &limit,
|
||||
float &slack);
|
||||
void maxFanoutCheck(// Return values.
|
||||
Pin *&pin,
|
||||
const Pin *&pin,
|
||||
float &fanout,
|
||||
float &slack,
|
||||
float &limit);
|
||||
@@ -665,10 +663,10 @@ public:
|
||||
// Return pins with the min/max slew limit slack.
|
||||
// net=null check all nets
|
||||
// corner=nullptr checks all corners.
|
||||
PinSeq *checkCapacitanceLimits(Net *net,
|
||||
bool violators,
|
||||
const Corner *corner,
|
||||
const MinMax *min_max);
|
||||
PinSeq checkCapacitanceLimits(Net *net,
|
||||
bool violators,
|
||||
const Corner *corner,
|
||||
const MinMax *min_max);
|
||||
void reportCapacitanceLimitShortHeader();
|
||||
void reportCapacitanceLimitShort(Pin *pin,
|
||||
const Corner *corner,
|
||||
@@ -687,7 +685,7 @@ public:
|
||||
float &limit,
|
||||
float &slack);
|
||||
void maxCapacitanceCheck(// Return values.
|
||||
Pin *&pin,
|
||||
const Pin *&pin,
|
||||
float &capacitance,
|
||||
float &slack,
|
||||
float &limit);
|
||||
@@ -734,17 +732,17 @@ public:
|
||||
|
||||
// Instance specific process/voltage/temperature.
|
||||
// Defaults to operating condition if instance is not annotated.
|
||||
Pvt *pvt(Instance *inst,
|
||||
const MinMax *min_max);
|
||||
const Pvt *pvt(Instance *inst,
|
||||
const MinMax *min_max);
|
||||
void setPvt(Instance *inst,
|
||||
const MinMaxAll *min_max,
|
||||
float process,
|
||||
float voltage,
|
||||
float temperature);
|
||||
// Pvt may be shared among multiple instances.
|
||||
void setPvt(Instance *inst,
|
||||
void setPvt(const Instance *inst,
|
||||
const MinMaxAll *min_max,
|
||||
Pvt *pvt);
|
||||
const Pvt &pvt);
|
||||
// Clear all state except network.
|
||||
virtual void clear();
|
||||
// Remove all constraints.
|
||||
@@ -931,8 +929,7 @@ public:
|
||||
int endpointViolationCount(const MinMax *min_max);
|
||||
// Find the fanin vertices for a group path.
|
||||
// Vertices in the clock network are NOT included.
|
||||
// Return value is owned by the caller.
|
||||
PinSet *findGroupPathPins(const char *group_path_name);
|
||||
PinSet findGroupPathPins(const char *group_path_name);
|
||||
// Find all required times after updateTiming().
|
||||
void findRequireds();
|
||||
string *reportDelayCalc(Edge *edge,
|
||||
@@ -1176,26 +1173,26 @@ public:
|
||||
virtual void disconnectPin(Pin *pin);
|
||||
// Notify STA of network change.
|
||||
void networkChanged();
|
||||
void deleteLeafInstanceBefore(Instance *inst);
|
||||
void deleteInstancePinsBefore(Instance *inst);
|
||||
void deleteLeafInstanceBefore(const Instance *inst);
|
||||
void deleteInstancePinsBefore(const Instance *inst);
|
||||
|
||||
// Network edit before/after methods.
|
||||
void makeInstanceAfter(Instance *inst);
|
||||
void makeInstanceAfter(const Instance *inst);
|
||||
// Replace the instance cell with to_cell.
|
||||
// equivCells(from_cell, to_cell) must be true.
|
||||
virtual void replaceEquivCellBefore(Instance *inst,
|
||||
LibertyCell *to_cell);
|
||||
virtual void replaceEquivCellAfter(Instance *inst);
|
||||
virtual void replaceEquivCellBefore(const Instance *inst,
|
||||
const LibertyCell *to_cell);
|
||||
virtual void replaceEquivCellAfter(const Instance *inst);
|
||||
// Replace the instance cell with to_cell.
|
||||
// equivCellPorts(from_cell, to_cell) must be true.
|
||||
virtual void replaceCellBefore(Instance *inst,
|
||||
LibertyCell *to_cell);
|
||||
virtual void replaceCellAfter(Instance *inst);
|
||||
virtual void connectPinAfter(Pin *pin);
|
||||
virtual void disconnectPinBefore(Pin *pin);
|
||||
virtual void deleteNetBefore(Net *net);
|
||||
virtual void deleteInstanceBefore(Instance *inst);
|
||||
virtual void deletePinBefore(Pin *pin);
|
||||
virtual void replaceCellBefore(const Instance *inst,
|
||||
const LibertyCell *to_cell);
|
||||
virtual void replaceCellAfter(const Instance *inst);
|
||||
virtual void connectPinAfter(const Pin *pin);
|
||||
virtual void disconnectPinBefore(const Pin *pin);
|
||||
virtual void deleteNetBefore(const Net *net);
|
||||
virtual void deleteInstanceBefore(const Instance *inst);
|
||||
virtual void deletePinBefore(const Pin *pin);
|
||||
|
||||
////////////////////////////////////////////////////////////////
|
||||
|
||||
@@ -1241,18 +1238,18 @@ public:
|
||||
int level);
|
||||
|
||||
// Delays and arrivals downsteam from inst are invalid.
|
||||
void delaysInvalidFrom(Instance *inst);
|
||||
void delaysInvalidFrom(const Instance *inst);
|
||||
// Delays and arrivals downsteam from pin are invalid.
|
||||
void delaysInvalidFrom(Pin *pin);
|
||||
void delaysInvalidFrom(const Pin *pin);
|
||||
void delaysInvalidFrom(Vertex *vertex);
|
||||
// Delays to driving pins of net (fanin) are invalid.
|
||||
// Arrivals downsteam from net are invalid.
|
||||
void delaysInvalidFromFanin(Net *net);
|
||||
void delaysInvalidFromFanin(Pin *pin);
|
||||
void delaysInvalidFromFanin(const Net *net);
|
||||
void delaysInvalidFromFanin(const Pin *pin);
|
||||
void delaysInvalidFromFanin(Vertex *vertex);
|
||||
void replaceCellPinInvalidate(LibertyPort *from_port,
|
||||
void replaceCellPinInvalidate(const LibertyPort *from_port,
|
||||
Vertex *vertex,
|
||||
LibertyCell *to_cell);
|
||||
const LibertyCell *to_cell);
|
||||
|
||||
// Power API.
|
||||
Power *power() { return power_; }
|
||||
@@ -1264,10 +1261,8 @@ public:
|
||||
PowerResult &combinational,
|
||||
PowerResult ¯o,
|
||||
PowerResult &pad);
|
||||
void power(const Instance *inst,
|
||||
const Corner *corner,
|
||||
// Return values.
|
||||
PowerResult &result);
|
||||
PowerResult power(const Instance *inst,
|
||||
const Corner *corner);
|
||||
PwrActivity findClkedActivity(const Pin *pin);
|
||||
|
||||
void writeTimingModel(const char *lib_name,
|
||||
@@ -1321,18 +1316,18 @@ protected:
|
||||
virtual LibertyLibrary *readLibertyFile(const char *filename,
|
||||
bool infer_latches);
|
||||
void delayCalcPreamble();
|
||||
void delaysInvalidFrom(Port *port);
|
||||
void delaysInvalidFromFanin(Port *port);
|
||||
void delaysInvalidFrom(const Port *port);
|
||||
void delaysInvalidFromFanin(const Port *port);
|
||||
void deleteEdge(Edge *edge);
|
||||
void netParasiticCaps(Net *net,
|
||||
const RiseFall *rf,
|
||||
const MinMax *min_max,
|
||||
float &pin_cap,
|
||||
float &wire_cap) const;
|
||||
Pin *findNetParasiticDrvrPin(Net *net) const;
|
||||
const Pin *findNetParasiticDrvrPin(const Net *net) const;
|
||||
void exprConstantPins(FuncExpr *expr,
|
||||
Instance *inst,
|
||||
PinSet *pins);
|
||||
const Instance *inst,
|
||||
PinSet &pins);
|
||||
Slack vertexSlack1(Vertex *vertex,
|
||||
const RiseFall *rf,
|
||||
const ClockEdge *clk_edge,
|
||||
@@ -1359,7 +1354,7 @@ protected:
|
||||
bool startpoints_only,
|
||||
int inst_levels,
|
||||
int pin_levels,
|
||||
PinSet *fanin,
|
||||
PinSet &fanin,
|
||||
SearchPred &pred);
|
||||
void findFaninPins(Vertex *to,
|
||||
bool flat,
|
||||
@@ -1374,7 +1369,7 @@ protected:
|
||||
bool endpoints_only,
|
||||
int inst_levels,
|
||||
int pin_levels,
|
||||
PinSet *fanout,
|
||||
PinSet &fanout,
|
||||
SearchPred &pred);
|
||||
void findFanoutPins(Vertex *from,
|
||||
bool flat,
|
||||
|
||||
@@ -239,7 +239,7 @@ public:
|
||||
unsigned index() const { return index_; }
|
||||
TimingModel *model(const OperatingConditions *op_cond) const;
|
||||
TimingModel *model() const { return model_; }
|
||||
TimingArc *cornerArc(int ap_index);
|
||||
const TimingArc *cornerArc(int ap_index) const;
|
||||
void setCornerArc(TimingArc *corner_arc,
|
||||
int ap_index);
|
||||
float driveResistance() const;
|
||||
|
||||
@@ -31,6 +31,11 @@ public:
|
||||
{
|
||||
}
|
||||
|
||||
explicit UnorderedMap(const HASH &hash) :
|
||||
std::unordered_map<KEY, VALUE, HASH, EQUAL>(0, hash, std::equal_to<KEY>())
|
||||
{
|
||||
}
|
||||
|
||||
explicit UnorderedMap(size_t size,
|
||||
const HASH &hash,
|
||||
const EQUAL &equal) :
|
||||
@@ -101,6 +106,19 @@ public:
|
||||
delete iter.next();
|
||||
}
|
||||
|
||||
void
|
||||
deleteKeysContents()
|
||||
{
|
||||
Iterator iter(this);
|
||||
while (iter.hasNext()) {
|
||||
KEY key;
|
||||
VALUE value;
|
||||
iter.next(key, value);
|
||||
delete key;
|
||||
delete value;
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
deleteArrayContents()
|
||||
{
|
||||
|
||||
@@ -37,13 +37,13 @@ public:
|
||||
class VertexPinCollector : public VertexVisitor
|
||||
{
|
||||
public:
|
||||
VertexPinCollector(PinSet *pins);
|
||||
PinSet *pins() const { return pins_; }
|
||||
VertexPinCollector(PinSet &pins);
|
||||
const PinSet &pins() const { return pins_; }
|
||||
void visit(Vertex *vertex);
|
||||
virtual VertexVisitor *copy() const;
|
||||
|
||||
protected:
|
||||
PinSet *pins_;
|
||||
PinSet &pins_;
|
||||
};
|
||||
|
||||
} // namespace
|
||||
|
||||
Reference in New Issue
Block a user