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Network::id for maps/sets 

commit be70d30ae05665021254b0d7e69fb8d2f0a82890
Author: James Cherry <cherry@parallaxsw.com>
Date:   Tue Jan 17 17:04:49 2023 -0700

    cmp

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit 4d4ef96948afe3d6a00c4521aeb5bc74274f5737
Author: James Cherry <cherry@parallaxsw.com>
Date:   Tue Jan 17 16:08:50 2023 -0700

    rvo, const

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit bb584e4264af2bea867b17d07e8d38c0e9eb0025
Author: James Cherry <cherry@parallaxsw.com>
Date:   Tue Jan 17 15:05:00 2023 -0700

    const

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit a08fe558bca6b769b2728882258bd85aed990a27
Author: James Cherry <cherry@parallaxsw.com>
Date:   Tue Jan 17 14:57:33 2023 -0700

    LibertyPortPair no ptrs

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit 4d3bd60c109d1ce9d0589d746f4968fa7bebd90d
Author: James Cherry <cherry@parallaxsw.com>
Date:   Tue Jan 17 14:13:07 2023 -0700

    cleanup

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit dc25ff77771cfbe26f9318bad2b3c45879614783
Author: James Cherry <cherry@parallaxsw.com>
Date:   Tue Jan 17 14:06:13 2023 -0700

    const

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit 06e81586ce11a0cc06948ed78fef99353077d69e
Author: James Cherry <cherry@parallaxsw.com>
Date:   Tue Jan 17 14:01:10 2023 -0700

    sortByName

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit 9d8592aff5b246f83e47e1b94490e3cef8d8e119
Author: James Cherry <cherry@parallaxsw.com>
Date:   Tue Jan 17 11:57:17 2023 -0700

    sort pred

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit 462a8e14df8b561ddfc842addc62c4b8435b6347
Author: James Cherry <cherry@parallaxsw.com>
Date:   Tue Jan 17 11:09:57 2023 -0700

    const

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit 69f71505b684e88b22d395510429497e87bf1015
Author: James Cherry <cherry@parallaxsw.com>
Date:   Tue Jan 17 10:45:14 2023 -0700

    flush ConstPortSeq

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit 6429d578b78eac3fe7e99fcd67a120789932b2eb
Author: James Cherry <cherry@parallaxsw.com>
Date:   Tue Jan 17 09:19:15 2023 -0700

    rm ConstNetSet

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit f247930b16e40560b957a36af68947249ed1ef04
Author: James Cherry <cherry@parallaxsw.com>
Date:   Tue Jan 17 08:50:50 2023 -0700

    sortPathNames

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit 4ca2b0e0af7252c7bcbc65cf141d0ce40634d329
Author: James Cherry <cherry@parallaxsw.com>
Date:   Mon Jan 16 10:14:05 2023 -0700

    const

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit 3d18640d2ebc4aae3098c7e7242a554fcb64fd42
Author: James Cherry <cherry@parallaxsw.com>
Date:   Mon Jan 16 09:41:27 2023 -0700

    set_input/ouput_delay -reference_pin

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit d4a0854dd2102f46f96a94fb9eb8749f1593a85f
Author: James Cherry <cherry@parallaxsw.com>
Date:   Mon Jan 16 09:13:46 2023 -0700

    PinPairSet no malloc

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit a6f1583fc6a856c5ecc0dcb15a1d8b1f61e30718
Author: James Cherry <cherry@parallaxsw.com>
Date:   Mon Jan 16 08:53:33 2023 -0700

    no malloc for EdgePins

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit c8e4b92e8b619109d6aa3c141c720646067ccb4b
Author: James Cherry <cherry@parallaxsw.com>
Date:   Mon Jan 16 06:31:08 2023 +0000

    leak

commit abab99e0fc3e466d914f6c1705aa08cdc204df51
Author: James Cherry <cherry@parallaxsw.com>
Date:   Mon Jan 16 06:07:36 2023 +0000

    leaks

commit d1913b554bb6e98b89673d80d2295f552eb4ffca
Author: James Cherry <cherry@parallaxsw.com>
Date:   Sun Jan 15 19:48:39 2023 -0700

    LibertyCell::checkCornerCell

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit bcc172237d48deed647374f9592bac70bd2d5425
Author: James Cherry <cherry@parallaxsw.com>
Date:   Sun Jan 15 18:19:47 2023 -0700

    rvo

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit 8ef9800b87f5e5548055a13afc21397f28a6bcf7
Author: James Cherry <cherry@parallaxsw.com>
Date:   Sun Jan 15 18:07:46 2023 -0700

    sdc net id

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit d7235abed04ced4e2d84e91bf9968e621268567d
Author: James Cherry <cherry@parallaxsw.com>
Date:   Sun Jan 15 16:00:27 2023 -0700

    range iter

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit a22f91a3c54c644574339d1126821d9bc8045bd6
Author: James Cherry <cherry@parallaxsw.com>
Date:   Sun Jan 15 15:52:50 2023 -0700

    range iter

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit 762615ce3de91d950eeaaa4680549a45b13e0e0a
Author: James Cherry <cherry@parallaxsw.com>
Date:   Sun Jan 15 15:42:19 2023 -0700

    range iter

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit 7e0c531613d343d23f064c24873bf5a498f6f4ce
Author: James Cherry <cherry@parallaxsw.com>
Date:   Sun Jan 15 12:26:49 2023 -0700

    rm removeLoadCaps, removeNetLoadCaps

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit f2e88c6082e2d4605e9849348008bf4065401fc8
Author: James Cherry <cherry@parallaxsw.com>
Date:   Sun Jan 15 12:21:03 2023 -0700

    sdc rm map ptrs

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit b5939666188c0b94dfe957e22bbd8a92f4786125
Author: James Cherry <cherry@parallaxsw.com>
Date:   Sun Jan 15 11:36:16 2023 -0700

    sdc rm map ptrs

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit a435081bafe10260743319f53a59cbe2ed0388b7
Author: James Cherry <cherry@parallaxsw.com>
Date:   Sun Jan 15 08:43:37 2023 -0700

    sdc rm map ptrs

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit acfb247559db7b726d47f203613488df0f7add53
Author: James Cherry <cherry@parallaxsw.com>
Date:   Sun Jan 15 08:38:07 2023 -0700

    sdc rm map ptrs

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit 7541b71da92ea15085615988a1e6ea1d4d53d8d6
Author: James Cherry <cherry@parallaxsw.com>
Date:   Sun Jan 15 08:00:55 2023 -0700

    sdc rm map ptrs

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit d033210132656ea68fa834228575b9def1d02d90
Author: James Cherry <cherry@parallaxsw.com>
Date:   Sun Jan 15 07:52:03 2023 -0700

    sdc rm map ptrs

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit ca6e9ecb7821b83ab024c4fee6df8f7fc8fc2ce2
Author: James Cherry <cherry@parallaxsw.com>
Date:   Sun Jan 15 07:38:12 2023 -0700

    instance_pvt_maps_

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit 631e4209b596386f5818045d521784db5239f58d
Author: James Cherry <cherry@parallaxsw.com>
Date:   Sun Jan 15 07:26:42 2023 -0700

    rm GroupPathIterator

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit 059c32afa87617fff530c9afa1ef8005a136739d
Author: James Cherry <cherry@parallaxsw.com>
Date:   Sat Jan 14 20:07:44 2023 -0700

    rm ClockIterator

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit c65fe873a6a6696220bbb44c4ecac87d5ca978ac
Author: James Cherry <cherry@parallaxsw.com>
Date:   Sat Jan 14 19:45:58 2023 -0700

    rvo

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit ce15c9a0cc78915acddc2f03749573d989ae96d6
Author: James Cherry <cherry@parallaxsw.com>
Date:   Sun Jan 15 01:04:03 2023 +0000

    leaks

commit f97955a0c7e70b65ceb3f697ff47c0524a9b3cd4
Author: James Cherry <cherry@parallaxsw.com>
Date:   Sat Jan 14 01:17:58 2023 +0000

    leaks

commit 7cdd65684adeb14e02827f5d93e7fab3b19af5dd
Author: James Cherry <cherry@parallaxsw.com>
Date:   Fri Jan 13 16:07:47 2023 -0700

    leaks

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit ee97c7e50394a3927458e7ef09c5dbeb27719d15
Author: James Cherry <cherry@parallaxsw.com>
Date:   Fri Jan 13 11:52:48 2023 -0700

    swig rm Tmp collections

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit c49935da8704e41459280971b7645fccd97e3d13
Author: James Cherry <cherry@parallaxsw.com>
Date:   Fri Jan 13 11:18:36 2023 -0700

    swig rm Tmp types

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit 4320b00ce700914843006f592126cd8cc1c4657a
Author: James Cherry <cherry@parallaxsw.com>
Date:   Fri Jan 13 10:55:10 2023 -0700

    swig rm TmpPinSet, TmpPinSeq

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit ff6004910980c9b09b41f63a553a4481404cc539
Author: James Cherry <cherry@parallaxsw.com>
Date:   Fri Jan 13 10:45:06 2023 -0700

    swig rm Tmp collections

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit 9a5bf5c1a3e5a6d2996b3ab327fa2f3015f2ff20
Author: James Cherry <cherry@parallaxsw.com>
Date:   Fri Jan 13 10:15:29 2023 -0700

    swig rm one TmpPinSet

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit f441116b56e23849485b2393b30e7086c33165a8
Author: James Cherry <cherry@parallaxsw.com>
Date:   Fri Jan 13 09:16:56 2023 -0700

    leak

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit 050b08df8618340b568d9cd41fd3d5f052e2c680
Author: James Cherry <cherry@parallaxsw.com>
Date:   Fri Jan 13 09:10:53 2023 -0700

    leak

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit be8c17f3a715ab53140748dc1d94698209965cf9
Author: James Cherry <cherry@parallaxsw.com>
Date:   Fri Jan 13 08:59:06 2023 -0700

    leak

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit e43b82f8fb52eaeda90e3c7e76cf350ae6735ebd
Author: James Cherry <cherry@parallaxsw.com>
Date:   Thu Jan 12 18:57:49 2023 -0700

    range iter

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit 8db56209de7805ac2574fd2f76170bf68afd156d
Author: James Cherry <cherry@parallaxsw.com>
Date:   Thu Jan 12 18:08:54 2023 -0700

    GroupPathSet net id

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit cb7917f9827c2ea3afebd735cd4508405a0d77d4
Author: James Cherry <cherry@parallaxsw.com>
Date:   Thu Jan 12 12:00:15 2023 -0700

    DataCheckLess net id

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit d9da3c62d7a76699c6ad62cebb1f5c39f89722fa
Author: James Cherry <cherry@parallaxsw.com>
Date:   Thu Jan 12 11:42:27 2023 -0700

    rm hashPtr uses

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit 5bbea162bb1e023aba813598c7992c740ddf9d0b
Author: James Cherry <cherry@parallaxsw.com>
Date:   Thu Jan 12 11:30:12 2023 -0700

    EdgePins has use net id

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit df38405e2ebaabdd7bbf99f3b19d78b25bd95720
Author: James Cherry <cherry@parallaxsw.com>
Date:   Thu Jan 12 09:51:38 2023 -0700

    ExceptionPath hash use net id

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit 9a6dcfa54c54c9f50b14248a2449c70c20a0d977
Author: James Cherry <cherry@parallaxsw.com>
Date:   Thu Jan 12 08:56:49 2023 -0700

    ClockInsertion, ClockLatency net id

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit dbb6dc0b8c93812458df31e93f08e0dbd74e8105
Author: James Cherry <cherry@parallaxsw.com>
Date:   Thu Jan 12 08:34:03 2023 -0700

    ExceptionStateSet obj id

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit 70b8721c48ec0816289ee09b664c332ee095875f
Author: James Cherry <cherry@parallaxsw.com>
Date:   Thu Jan 12 08:14:37 2023 -0700

    ClockGroups cmp

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit 4c6c4ca191a99cd8541e106fec3202ee14968f39
Author: James Cherry <cherry@parallaxsw.com>
Date:   Thu Jan 12 07:38:17 2023 -0700

    ClockGroup typedef to ClockSet

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit 66f425315e16deee5f00b05c0a505766e7afbf01
Author: James Cherry <cherry@parallaxsw.com>
Date:   Wed Jan 11 20:32:38 2023 -0700

    set cmps

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit a94866c7828af5b6714e3e4fffc13bdaf5155c0e
Author: James Cherry <cherry@parallaxsw.com>
Date:   Wed Jan 11 19:08:09 2023 -0700

    net use id

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit 6348320908f42ebb5262117182e13d0024f65537
Author: James Cherry <cherry@parallaxsw.com>
Date:   Wed Jan 11 11:52:13 2023 -0700

    exception id cmp

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit 0edfca41b6d6408ac17f8dfe10e697c55146c1ef
Author: James Cherry <cherry@parallaxsw.com>
Date:   Wed Jan 11 10:47:02 2023 -0700

    range iter

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit 44ad77985da9f0b9e7f4780e3f233c8d94fa7db7
Author: James Cherry <cherry@parallaxsw.com>
Date:   Wed Jan 11 08:27:58 2023 -0700

    non-ptr set cmp

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit 36de7d88c3fa683465604a9e16b2fc1f6bc5fdd0
Author: James Cherry <cherry@parallaxsw.com>
Date:   Wed Jan 11 08:00:54 2023 -0700

    range iteration

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit 4a31a2c8d9bdae58b09af8c05a64702ea3ac6c15
Author: James Cherry <cherry@parallaxsw.com>
Date:   Tue Jan 10 16:43:54 2023 -0700

    tcl types

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit 056a7447b494a4c8ecc9764650d78a5bed3d87e8
Author: James Cherry <cherry@parallaxsw.com>
Date:   Tue Jan 10 16:10:36 2023 -0700

    tcl types

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit 97239554c7625ba50ee729260f08eda7dec02365
Author: James Cherry <cherry@parallaxsw.com>
Date:   Tue Jan 10 13:10:42 2023 -0700

    use RVO

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit c3247d8937d483102e3e1f2b69d7ac1d331ba9d4
Author: James Cherry <cherry@parallaxsw.com>
Date:   Mon Jan 9 22:41:20 2023 -0700

    swig template seq's

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit 5431c06feb256adb46858819fcf5d513cfa6b5ec
Author: James Cherry <cherry@parallaxsw.com>
Date:   Mon Jan 9 20:50:24 2023 -0700

    swig set in template

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit 592ad641bf01d3beb862314a0d8986f66e258642
Author: James Cherry <cherry@parallaxsw.com>
Date:   Mon Jan 9 17:27:25 2023 -0700

    network return containers

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit c95f8b77e0d6bd5ffa5ba8102413c70883c756e1
Author: James Cherry <cherry@parallaxsw.com>
Date:   Mon Jan 9 12:15:37 2023 -0700

    PinSeq const

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit 702e7f9ba2f901066a38f32e67b35602b6c7bbdf
Author: James Cherry <cherry@parallaxsw.com>
Date:   Mon Jan 9 12:02:29 2023 -0700

    InstanceSeq const

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit 44fc25ba4a15e4ae570d74af27c9435872a126e0
Author: James Cherry <cherry@parallaxsw.com>
Date:   Mon Jan 9 12:01:45 2023 -0700

    NetSeq const

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit 03b2725c81f5d52c33c875b55056c11d482144f1
Author: James Cherry <cherry@parallaxsw.com>
Date:   Mon Jan 9 11:33:18 2023 -0700

    rm PortPair

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit 3fb82a7344dc053171c9883a113764ba691ab827
Author: James Cherry <cherry@parallaxsw.com>
Date:   Mon Jan 9 11:20:53 2023 -0700

    PinSet id

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit 3dd31f027e15d40d62a11d0a88ef2a115f01fb73
Author: James Cherry <cherry@parallaxsw.com>
Date:   Sun Jan 8 15:03:33 2023 -0700

    InstanceSet id

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit a91dea5cc0af3bede36b3faed13adb05239ff907
Author: James Cherry <cherry@parallaxsw.com>
Date:   Sun Jan 8 11:40:15 2023 -0700

    NetSet id

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit b91e4b6410134eccae7969ddcfb0b27933b2e746
Author: James Cherry <cherry@parallaxsw.com>
Date:   Sun Jan 8 10:44:47 2023 -0700

    CellSet, PortSet id

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit 6f891f77fae5a6b19c1454a1a4b4e3dfae0b5c50
Author: James Cherry <cherry@parallaxsw.com>
Date:   Sun Jan 8 10:29:25 2023 -0700

    network object sets

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit eb8c627a57ecc6e7c5846a01d62b090ff91c08bf
Author: James Cherry <cherry@parallaxsw.com>
Date:   Sun Jan 8 10:09:00 2023 -0700

    PinSet1

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit 8e864ecbdf87000fbb3c3097c39f06173c941e35
Author: James Cherry <cherry@parallaxsw.com>
Date:   Sat Jan 7 17:13:03 2023 -0700

    concrete network object id

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

Signed-off-by: James Cherry <cherry@parallaxsw.com>
This commit is contained in:
James Cherry 2023-01-19 11:23:45 -07:00
parent 440247d0b5
commit 3f7df84fb8
144 changed files with 4509 additions and 4732 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
CMakeLists.txt
View File

@ -24,7 +24,7 @@ if(CMAKE_VERSION VERSION_GREATER_EQUAL 3.14)
cmake_policy(SET CMP0086 NEW)
endif()
project(STA VERSION 2.3.3
project(STA VERSION 2.4.0
LANGUAGES CXX
)

8
dcalc/ArcDelayCalc.cc
View File

@ -28,23 +28,23 @@ ArcDelayCalc::ArcDelayCalc(StaState *sta):
}
TimingModel *
ArcDelayCalc::model(TimingArc *arc,
ArcDelayCalc::model(const TimingArc *arc,
const DcalcAnalysisPt *dcalc_ap) const
{
const OperatingConditions *op_cond = dcalc_ap->operatingConditions();
TimingArc *corner_arc = arc->cornerArc(dcalc_ap->libertyIndex());
const TimingArc *corner_arc = arc->cornerArc(dcalc_ap->libertyIndex());
return corner_arc->model(op_cond);
}
GateTimingModel *
ArcDelayCalc::gateModel(TimingArc *arc,
ArcDelayCalc::gateModel(const TimingArc *arc,
const DcalcAnalysisPt *dcalc_ap) const
{
return dynamic_cast<GateTimingModel*>(model(arc, dcalc_ap));
}
CheckTimingModel *
ArcDelayCalc::checkModel(TimingArc *arc,
ArcDelayCalc::checkModel(const TimingArc *arc,
const DcalcAnalysisPt *dcalc_ap) const
{
return dynamic_cast<CheckTimingModel*>(model(arc, dcalc_ap));

3
dcalc/Arnoldi.hh
View File

@ -25,7 +25,6 @@
namespace sta {
struct delay_work;
class rcmodel;
class GateTableModel;
class Pin;
@ -71,7 +70,7 @@ public:
struct timing_table
{
GateTableModel *table;
const GateTableModel *table;
const LibertyCell *cell;
const Pvt *pvt;
float in_slew;

39
dcalc/ArnoldiDelayCalc.cc
View File

@ -119,11 +119,11 @@ public:
const DcalcAnalysisPt *dcalc_ap);
virtual ReducedParasiticType reducedParasiticType() const;
virtual void gateDelay(const LibertyCell *drvr_cell,
TimingArc *arc,
const TimingArc *arc,
const Slew &in_slew,
// Pass in load_cap or drvr_parasitic.
float load_cap,
Parasitic *drvr_parasitic,
const Parasitic *drvr_parasitic,
float related_out_cap,
const Pvt *pvt,
const DcalcAnalysisPt *dcalc_ap,
@ -137,13 +137,13 @@ public:
virtual void inputPortDelay(const Pin *port_pin,
float in_slew,
const RiseFall *rf,
Parasitic *parasitic,
const Parasitic *parasitic,
const DcalcAnalysisPt *dcalc_ap);
virtual void reportGateDelay(const LibertyCell *drvr_cell,
TimingArc *arc,
const TimingArc *arc,
const Slew &in_slew,
float load_cap,
Parasitic *,
const Parasitic *,
float related_out_cap,
const Pvt *pvt,
const DcalcAnalysisPt *dcalc_ap,
@ -157,15 +157,18 @@ public:
private:
void gateDelaySlew(const LibertyCell *drvr_cell,
GateTableModel *table_model,
const GateTableModel *table_model,
const Slew &in_slew,
float related_out_cap,
const Pvt *pvt,
// Return values.
ArcDelay &gate_delay,
Slew &drvr_slew);
void ar1_ceff_delay(delay_work *D,timing_table *tab, arnoldi1 *mod,
double *delays, double *slews);
void ar1_ceff_delay(delay_work *D,
timing_table *tab,
arnoldi1 *mod,
double *delays,
double *slews);
double ra_rdelay_1(timing_table *tab,
double ctot);
double ra_get_r(delay_work *D,
@ -265,8 +268,9 @@ ArnoldiDelayCalc::findParasitic(const Pin *drvr_pin,
const RiseFall *drvr_rf,
const DcalcAnalysisPt *dcalc_ap)
{
const Corner *corner = dcalc_ap->corner();
// set_load has precidence over parasitics.
if (!sdc_->drvrPinHasWireCap(drvr_pin)) {
if (!sdc_->drvrPinHasWireCap(drvr_pin, corner)) {
const ParasiticAnalysisPt *parasitic_ap = dcalc_ap->parasiticAnalysisPt();
Parasitic *parasitic_network =
parasitics_->findParasiticNetwork(drvr_pin, parasitic_ap);
@ -274,7 +278,6 @@ ArnoldiDelayCalc::findParasitic(const Pin *drvr_pin,
const MinMax *cnst_min_max = dcalc_ap->constraintMinMax();
const OperatingConditions *op_cond = dcalc_ap->operatingConditions();
const Corner *corner = dcalc_ap->corner();
if (parasitic_network == nullptr) {
Wireload *wireload = sdc_->wireload(cnst_min_max);
if (wireload) {
@ -317,7 +320,7 @@ void
ArnoldiDelayCalc::inputPortDelay(const Pin *drvr_pin,
float in_slew,
const RiseFall *rf,
Parasitic *parasitic,
const Parasitic *parasitic,
const DcalcAnalysisPt *dcalc_ap)
{
RCDelayCalc::inputPortDelay(drvr_pin, in_slew, rf, parasitic, dcalc_ap);
@ -327,7 +330,7 @@ ArnoldiDelayCalc::inputPortDelay(const Pin *drvr_pin,
int j;
if (parasitic) {
rcmodel_ = reinterpret_cast<rcmodel*>(parasitic);
rcmodel_ = reinterpret_cast<rcmodel*>(const_cast<Parasitic*>(parasitic));
pin_n_ = rcmodel_->n;
if (pin_n_ >= _pinNmax) {
_pinNmax *= 2;
@ -358,10 +361,10 @@ ArnoldiDelayCalc::inputPortDelay(const Pin *drvr_pin,
void
ArnoldiDelayCalc::gateDelay(const LibertyCell *drvr_cell,
TimingArc *arc,
const TimingArc *arc,
const Slew &in_slew,
float load_cap,
Parasitic *drvr_parasitic,
const Parasitic *drvr_parasitic,
float related_out_cap,
const Pvt *pvt,
const DcalcAnalysisPt *dcalc_ap,
@ -374,7 +377,7 @@ ArnoldiDelayCalc::gateDelay(const LibertyCell *drvr_cell,
drvr_library_ = drvr_cell->libertyLibrary();
drvr_parasitic_ = drvr_parasitic;
ConcreteParasitic *drvr_cparasitic =
reinterpret_cast<ConcreteParasitic*>(drvr_parasitic);
reinterpret_cast<ConcreteParasitic*>(const_cast<Parasitic*>(drvr_parasitic));
rcmodel_ = dynamic_cast<rcmodel*>(drvr_cparasitic);
GateTimingModel *model = gateModel(arc, dcalc_ap);
GateTableModel *table_model = dynamic_cast<GateTableModel*>(model);
@ -392,7 +395,7 @@ ArnoldiDelayCalc::gateDelay(const LibertyCell *drvr_cell,
void
ArnoldiDelayCalc::gateDelaySlew(const LibertyCell *drvr_cell,
GateTableModel *table_model,
const GateTableModel *table_model,
const Slew &in_slew,
float related_out_cap,
const Pvt *pvt,
@ -454,10 +457,10 @@ ArnoldiDelayCalc::loadDelay(const Pin *load_pin,
void
ArnoldiDelayCalc::reportGateDelay(const LibertyCell *,
TimingArc *,
const TimingArc *,
const Slew &,
float,
Parasitic *,
const Parasitic *,
float,
const Pvt *,
const DcalcAnalysisPt *,

2
dcalc/ArnoldiReduce.cc
View File

@ -451,7 +451,7 @@ ArnoldiReduce::pinCapacitance(ParasiticNode *node)
if (lib_port)
pin_cap = sdc_->pinCapacitance(pin,rf_, op_cond_, corner_, cnst_min_max_);
else if (network_->isTopLevelPort(pin))
pin_cap = sdc_->portExtCap(port, rf_, cnst_min_max_);
pin_cap = sdc_->portExtCap(port, rf_, corner_, cnst_min_max_);
}
return pin_cap;
}

13
dcalc/DelayCalc.cc
View File

@ -74,16 +74,13 @@ isDelayCalcName(const char *name)
return delay_calcs->hasKey(name);
}
StringSeq *
StringSeq
delayCalcNames()
{
StringSeq *names = new StringSeq;
DelayCalcMap::Iterator dcalc_iter(delay_calcs);
while (dcalc_iter.hasNext()) {
MakeArcDelayCalc maker;
const char *name;
dcalc_iter.next(name, maker);
names->push_back(name);
StringSeq names;
for (auto name_dcalc : *delay_calcs) {
const char *name = name_dcalc.first;
names.push_back(name);
}
return names;
}

2
dcalc/DelayCalc.i
View File

@ -24,7 +24,7 @@
%inline %{
TmpStringSeq *
StringSeq
delay_calc_names()
{
return sta::delayCalcNames();

20
dcalc/DmpCeff.cc
View File

@ -83,7 +83,7 @@ private:
static double
gateModelRd(const LibertyCell *cell,
GateTableModel *gate_model,
const GateTableModel *gate_model,
const RiseFall *rf,
double in_slew,
double c2,
@ -1546,7 +1546,7 @@ void
DmpCeffDelayCalc::inputPortDelay(const Pin *port_pin,
float in_slew,
const RiseFall *rf,
Parasitic *parasitic,
const Parasitic *parasitic,
const DcalcAnalysisPt *dcalc_ap)
{
dmp_alg_ = nullptr;
@ -1556,10 +1556,10 @@ DmpCeffDelayCalc::inputPortDelay(const Pin *port_pin,
void
DmpCeffDelayCalc::gateDelay(const LibertyCell *drvr_cell,
TimingArc *arc,
const TimingArc *arc,
const Slew &in_slew,
float load_cap,
Parasitic *drvr_parasitic,
const Parasitic *drvr_parasitic,
float related_out_cap,
const Pvt *pvt,
const DcalcAnalysisPt *dcalc_ap,
@ -1606,7 +1606,7 @@ void
DmpCeffDelayCalc::setCeffAlgorithm(const LibertyLibrary *drvr_library,
const LibertyCell *drvr_cell,
const Pvt *pvt,
GateTableModel *gate_model,
const GateTableModel *gate_model,
const RiseFall *rf,
double in_slew,
float related_out_cap,
@ -1647,10 +1647,10 @@ DmpCeffDelayCalc::setCeffAlgorithm(const LibertyLibrary *drvr_library,
float
DmpCeffDelayCalc::ceff(const LibertyCell *drvr_cell,
TimingArc *arc,
const TimingArc *arc,
const Slew &in_slew,
float load_cap,
Parasitic *drvr_parasitic,
const Parasitic *drvr_parasitic,
float related_out_cap,
const Pvt *pvt,
const DcalcAnalysisPt *dcalc_ap)
@ -1668,10 +1668,10 @@ DmpCeffDelayCalc::ceff(const LibertyCell *drvr_cell,
void
DmpCeffDelayCalc::reportGateDelay(const LibertyCell *drvr_cell,
TimingArc *arc,
const TimingArc *arc,
const Slew &in_slew,
float load_cap,
Parasitic *drvr_parasitic,
const Parasitic *drvr_parasitic,
float related_out_cap,
const Pvt *pvt,
const DcalcAnalysisPt *dcalc_ap,
@ -1715,7 +1715,7 @@ DmpCeffDelayCalc::reportGateDelay(const LibertyCell *drvr_cell,
static double
gateModelRd(const LibertyCell *cell,
GateTableModel *gate_model,
const GateTableModel *gate_model,
const RiseFall *rf,
double in_slew,
double c2,

16
dcalc/DmpCeff.hh
View File

@ -37,13 +37,13 @@ public:
virtual void inputPortDelay(const Pin *port_pin,
float in_slew,
const RiseFall *rf,
Parasitic *parasitic,
const Parasitic *parasitic,
const DcalcAnalysisPt *dcalc_ap);
virtual void gateDelay(const LibertyCell *drvr_cell,
TimingArc *arc,
const TimingArc *arc,
const Slew &in_slew,
float load_cap,
Parasitic *drvr_parasitic,
const Parasitic *drvr_parasitic,
float related_out_cap,
const Pvt *pvt,
const DcalcAnalysisPt *dcalc_ap,
@ -51,18 +51,18 @@ public:
ArcDelay &gate_delay,
Slew &drvr_slew);
virtual float ceff(const LibertyCell *drvr_cell,
TimingArc *arc,
const TimingArc *arc,
const Slew &in_slew,
float load_cap,
Parasitic *drvr_parasitic,
const Parasitic *drvr_parasitic,
float related_out_cap,
const Pvt *pvt,
const DcalcAnalysisPt *dcalc_ap);
virtual void reportGateDelay(const LibertyCell *drvr_cell,
TimingArc *arc,
const TimingArc *arc,
const Slew &in_slew,
float load_cap,
Parasitic *drvr_parasitic,
const Parasitic *drvr_parasitic,
float related_out_cap,
const Pvt *pvt,
const DcalcAnalysisPt *dcalc_ap,
@ -81,7 +81,7 @@ protected:
void setCeffAlgorithm(const LibertyLibrary *library,
const LibertyCell *cell,
const Pvt *pvt,
GateTableModel *gate_model,
const GateTableModel *gate_model,
const RiseFall *rf,
double in_slew,
float related_out_cap,

27
dcalc/DmpDelayCalc.cc
View File

@ -35,10 +35,10 @@ public:
DmpCeffElmoreDelayCalc(StaState *sta);
virtual ArcDelayCalc *copy();
virtual void gateDelay(const LibertyCell *drvr_cell,
TimingArc *arc,
const TimingArc *arc,
const Slew &in_slew,
float load_cap,
Parasitic *drvr_parasitic,
const Parasitic *drvr_parasitic,
float related_out_cap,
const Pvt *pvt,
const DcalcAnalysisPt *dcalc_ap,
@ -69,10 +69,10 @@ DmpCeffElmoreDelayCalc::copy()
void
DmpCeffElmoreDelayCalc::gateDelay(const LibertyCell *drvr_cell,
TimingArc *arc,
const TimingArc *arc,
const Slew &in_slew,
float load_cap,
Parasitic *drvr_parasitic,
const Parasitic *drvr_parasitic,
float related_out_cap,
const Pvt *pvt,
const DcalcAnalysisPt *dcalc_ap,
@ -133,13 +133,13 @@ public:
virtual void inputPortDelay(const Pin *port_pin,
float in_slew,
const RiseFall *rf,
Parasitic *parasitic,
const Parasitic *parasitic,
const DcalcAnalysisPt *dcalc_ap);
virtual void gateDelay(const LibertyCell *drvr_cell,
TimingArc *arc,
const TimingArc *arc,
const Slew &in_slew,
float load_cap,
Parasitic *drvr_parasitic,
const Parasitic *drvr_parasitic,
float related_out_cap,
const Pvt *pvt,
const DcalcAnalysisPt *dcalc_ap,
@ -201,8 +201,9 @@ DmpCeffTwoPoleDelayCalc::findParasitic(const Pin *drvr_pin,
const RiseFall *rf,
const DcalcAnalysisPt *dcalc_ap)
{
const Corner *corner = dcalc_ap->corner();
// set_load has precidence over parasitics.
if (!sdc_->drvrPinHasWireCap(drvr_pin)) {
if (!sdc_->drvrPinHasWireCap(drvr_pin, corner)) {
Parasitic *parasitic = nullptr;
const ParasiticAnalysisPt *parasitic_ap = dcalc_ap->parasiticAnalysisPt();
if (parasitics_->haveParasitics()) {
@ -221,7 +222,7 @@ DmpCeffTwoPoleDelayCalc::findParasitic(const Pin *drvr_pin,
if (parasitic_network) {
parasitics_->reduceToPiPoleResidue2(parasitic_network, drvr_pin,
dcalc_ap->operatingConditions(),
dcalc_ap->corner(),
corner,
dcalc_ap->constraintMinMax(),
parasitic_ap);
parasitic = parasitics_->findPiPoleResidue(drvr_pin, rf, parasitic_ap);
@ -240,7 +241,7 @@ DmpCeffTwoPoleDelayCalc::findParasitic(const Pin *drvr_pin,
parasitic = parasitics_->estimatePiElmore(drvr_pin, rf, wireload,
fanout, pin_cap,
dcalc_ap->operatingConditions(),
dcalc_ap->corner(),
corner,
cnst_min_max,
parasitic_ap);
// Estimated parasitics are not recorded in the "database", so
@ -263,7 +264,7 @@ void
DmpCeffTwoPoleDelayCalc::inputPortDelay(const Pin *port_pin,
float in_slew,
const RiseFall *rf,
Parasitic *parasitic,
const Parasitic *parasitic,
const DcalcAnalysisPt *dcalc_ap)
{
parasitic_is_pole_residue_ = parasitics_->isPiPoleResidue(parasitic);
@ -272,10 +273,10 @@ DmpCeffTwoPoleDelayCalc::inputPortDelay(const Pin *port_pin,
void
DmpCeffTwoPoleDelayCalc::gateDelay(const LibertyCell *drvr_cell,
TimingArc *arc,
const TimingArc *arc,
const Slew &in_slew,
float load_cap,
Parasitic *drvr_parasitic,
const Parasitic *drvr_parasitic,
float related_out_cap,
const Pvt *pvt,
const DcalcAnalysisPt *dcalc_ap,

4
dcalc/GraphDelayCalc.cc
View File

@ -127,7 +127,7 @@ GraphDelayCalc::minPulseWidth(const Pin *pin,
LibertyPort *port = network_->libertyPort(pin);
if (port) {
Instance *inst = network_->instance(pin);
Pvt *pvt = inst ? sdc_->pvt(inst, min_max) : nullptr;
const Pvt *pvt = inst ? sdc_->pvt(inst, min_max) : nullptr;
OperatingConditions *op_cond=sdc_->operatingConditions(min_max);
port->minPulseWidth(hi_low, op_cond, pvt, min_width, exists);
}
@ -160,7 +160,7 @@ GraphDelayCalc::minPeriod(const Pin *pin,
// Liberty library.
Instance *inst = network_->instance(pin);
OperatingConditions *op_cond = sdc_->operatingConditions(min_max);
Pvt *pvt = inst ? sdc_->pvt(inst, min_max) : nullptr;
const Pvt *pvt = inst ? sdc_->pvt(inst, min_max) : nullptr;
port->minPeriod(op_cond, pvt, min_period, exists);
}
}

34
dcalc/GraphDelayCalc1.cc
View File

@ -452,7 +452,7 @@ public:
FindNetDrvrs(PinSet &drvr_pins,
const Network *network,
const Graph *graph);
virtual void operator()(Pin *pin);
virtual void operator()(const Pin *pin);
protected:
PinSet &drvr_pins_;
@ -470,7 +470,7 @@ FindNetDrvrs::FindNetDrvrs(PinSet &drvr_pins,
}
void
FindNetDrvrs::operator()(Pin *pin)
FindNetDrvrs::operator()(const Pin *pin)
{
Vertex *vertex = graph_->pinDrvrVertex(pin);
if (isLeafDriver(pin, network_)
@ -491,7 +491,7 @@ GraphDelayCalc1::ensureMultiDrvrNetsFound()
Vertex *drvr_vertex = graph_->pinDrvrVertex(pin);
if (network_->isDriver(pin)
&& !multi_drvr_net_map_.hasKey(drvr_vertex)) {
PinSet drvr_pins;
PinSet drvr_pins(network_);
FindNetDrvrs visitor(drvr_pins, network_, graph_);
network_->visitConnectedPins(pin, visitor);
if (drvr_pins.size() > 1)
@ -515,7 +515,7 @@ GraphDelayCalc1::makeMultiDrvrNet(PinSet &drvr_pins)
Vertex *max_drvr = nullptr;
PinSet::Iterator pin_iter(drvr_pins);
while (pin_iter.hasNext()) {
Pin *pin = pin_iter.next();
const Pin *pin = pin_iter.next();
Vertex *drvr_vertex = graph_->pinDrvrVertex(pin);
debugPrint(debug_, "delay_calc", 3, " %s",
network_->pathName(pin));
@ -581,8 +581,8 @@ GraphDelayCalc1::seedDrvrSlew(Vertex *drvr_vertex,
for (auto dcalc_ap : corners_->dcalcAnalysisPts()) {
if (drive) {
const MinMax *cnst_min_max = dcalc_ap->constraintMinMax();
LibertyCell *drvr_cell;
LibertyPort *from_port, *to_port;
const LibertyCell *drvr_cell;
const LibertyPort *from_port, *to_port;
float *from_slews;
drive->driveCell(tr, cnst_min_max, drvr_cell, from_port,
from_slews, to_port);
@ -705,8 +705,8 @@ GraphDelayCalc1::seedLoadSlew(Vertex *vertex)
// defined in the cell that has a timing group to the output port
// is used. Not exactly reasonable, but it's compatible.
LibertyPort *
GraphDelayCalc1::driveCellDefaultFromPort(LibertyCell *cell,
LibertyPort *to_port)
GraphDelayCalc1::driveCellDefaultFromPort(const LibertyCell *cell,
const LibertyPort *to_port)
{
LibertyPort *from_port = 0;
int from_port_index = 0;
@ -724,8 +724,8 @@ GraphDelayCalc1::driveCellDefaultFromPort(LibertyCell *cell,
// Find the index that port is defined in cell.
int
GraphDelayCalc1::findPortIndex(LibertyCell *cell,
LibertyPort *port)
GraphDelayCalc1::findPortIndex(const LibertyCell *cell,
const LibertyPort *port)
{
int index = 0;
LibertyCellPortIterator port_iter(cell);
@ -740,14 +740,14 @@ GraphDelayCalc1::findPortIndex(LibertyCell *cell,
}
void
GraphDelayCalc1::findInputDriverDelay(LibertyCell *drvr_cell,
GraphDelayCalc1::findInputDriverDelay(const LibertyCell *drvr_cell,
const Pin *drvr_pin,
Vertex *drvr_vertex,
const RiseFall *rf,
LibertyPort *from_port,
const LibertyPort *from_port,
float *from_slews,
LibertyPort *to_port,
DcalcAnalysisPt *dcalc_ap)
const LibertyPort *to_port,
const DcalcAnalysisPt *dcalc_ap)
{
debugPrint(debug_, "delay_calc", 2, " driver cell %s %s",
drvr_cell->name(),
@ -767,12 +767,12 @@ GraphDelayCalc1::findInputDriverDelay(LibertyCell *drvr_cell,
// delay minus the intrinsic delay. Driving cell delays are annotated
// to the wire arcs from the input port pin to the load pins.
void
GraphDelayCalc1::findInputArcDelay(LibertyCell *drvr_cell,
GraphDelayCalc1::findInputArcDelay(const LibertyCell *drvr_cell,
const Pin *drvr_pin,
Vertex *drvr_vertex,
TimingArc *arc,
const TimingArc *arc,
float from_slew,
DcalcAnalysisPt *dcalc_ap)
const DcalcAnalysisPt *dcalc_ap)
{
debugPrint(debug_, "delay_calc", 3, " %s %s -> %s %s (%s)",
arc->from()->name(),

22
dcalc/GraphDelayCalc1.hh
View File

@ -104,24 +104,24 @@ protected:
ArcDelayCalc *arc_delay_calc);
void seedLoadSlew(Vertex *vertex);
void setInputPortWireDelays(Vertex *vertex);
void findInputDriverDelay(LibertyCell *drvr_cell,
void findInputDriverDelay(const LibertyCell *drvr_cell,
const Pin *drvr_pin,
Vertex *drvr_vertex,
const RiseFall *rf,
LibertyPort *from_port,
const LibertyPort *from_port,
float *from_slews,
LibertyPort *to_port,
DcalcAnalysisPt *dcalc_ap);
LibertyPort *driveCellDefaultFromPort(LibertyCell *cell,
LibertyPort *to_port);
int findPortIndex(LibertyCell *cell,
LibertyPort *port);
void findInputArcDelay(LibertyCell *drvr_cell,
const LibertyPort *to_port,
const DcalcAnalysisPt *dcalc_ap);
LibertyPort *driveCellDefaultFromPort(const LibertyCell *cell,
const LibertyPort *to_port);
int findPortIndex(const LibertyCell *cell,
const LibertyPort *port);
void findInputArcDelay(const LibertyCell *drvr_cell,
const Pin *drvr_pin,
Vertex *drvr_vertex,
TimingArc *arc,
const TimingArc *arc,
float from_slew,
DcalcAnalysisPt *dcalc_ap);
const DcalcAnalysisPt *dcalc_ap);
bool findDriverDelays(Vertex *drvr_vertex,
ArcDelayCalc *arc_delay_calc);
bool findDriverDelays1(Vertex *drvr_vertex,

25
dcalc/LumpedCapDelayCalc.cc
View File

@ -51,8 +51,9 @@ LumpedCapDelayCalc::findParasitic(const Pin *drvr_pin,
const RiseFall *rf,
const DcalcAnalysisPt *dcalc_ap)
{
const Corner *corner = dcalc_ap->corner();
// set_load has precidence over parasitics.
if (!sdc_->drvrPinHasWireCap(drvr_pin)) {
if (!sdc_->drvrPinHasWireCap(drvr_pin, corner)) {
Parasitic *parasitic = nullptr;
const ParasiticAnalysisPt *parasitic_ap = dcalc_ap->parasiticAnalysisPt();
if (parasitics_->haveParasitics()) {
@ -66,7 +67,7 @@ LumpedCapDelayCalc::findParasitic(const Pin *drvr_pin,
if (parasitic_network) {
parasitics_->reduceToPiElmore(parasitic_network, drvr_pin,
dcalc_ap->operatingConditions(),
dcalc_ap->corner(),
corner,
dcalc_ap->constraintMinMax(),
parasitic_ap);
parasitic = parasitics_->findPiElmore(drvr_pin, rf, parasitic_ap);
@ -85,7 +86,7 @@ LumpedCapDelayCalc::findParasitic(const Pin *drvr_pin,
parasitic = parasitics_->estimatePiElmore(drvr_pin, rf, wireload,
fanout, pin_cap,
dcalc_ap->operatingConditions(),
dcalc_ap->corner(),
corner,
cnst_min_max,
parasitic_ap);
// Estimated parasitics are not recorded in the "database", so
@ -118,7 +119,7 @@ LumpedCapDelayCalc::finishDrvrPin()
void
LumpedCapDelayCalc::inputPortDelay(const Pin *, float in_slew,
const RiseFall *rf,
Parasitic *,
const Parasitic *,
const DcalcAnalysisPt *)
{
drvr_slew_ = in_slew;
@ -129,10 +130,10 @@ LumpedCapDelayCalc::inputPortDelay(const Pin *, float in_slew,
float
LumpedCapDelayCalc::ceff(const LibertyCell *,
TimingArc *,
const TimingArc *,
const Slew &,
float load_cap,
Parasitic *,
const Parasitic *,
float,
const Pvt *,
const DcalcAnalysisPt *)
@ -142,10 +143,10 @@ LumpedCapDelayCalc::ceff(const LibertyCell *,
void
LumpedCapDelayCalc::gateDelay(const LibertyCell *drvr_cell,
TimingArc *arc,
const TimingArc *arc,
const Slew &in_slew,
float load_cap,
Parasitic *,
const Parasitic *,
float related_out_cap,
const Pvt *pvt,
const DcalcAnalysisPt *dcalc_ap,
@ -239,10 +240,10 @@ LumpedCapDelayCalc::thresholdLibrary(const Pin *load_pin)
void
LumpedCapDelayCalc::reportGateDelay(const LibertyCell *drvr_cell,
TimingArc *arc,
const TimingArc *arc,
const Slew &in_slew,
float load_cap,
Parasitic *,
const Parasitic *,
float related_out_cap,
const Pvt *pvt,
const DcalcAnalysisPt *dcalc_ap,
@ -259,7 +260,7 @@ LumpedCapDelayCalc::reportGateDelay(const LibertyCell *drvr_cell,
void
LumpedCapDelayCalc::checkDelay(const LibertyCell *cell,
TimingArc *arc,
const TimingArc *arc,
const Slew &from_slew,
const Slew &to_slew,
float related_out_cap,
@ -281,7 +282,7 @@ LumpedCapDelayCalc::checkDelay(const LibertyCell *cell,
void
LumpedCapDelayCalc::reportCheckDelay(const LibertyCell *cell,
TimingArc *arc,
const TimingArc *arc,
const Slew &from_slew,
const char *from_slew_annotation,
const Slew &to_slew,

18
dcalc/LumpedCapDelayCalc.hh
View File

@ -34,13 +34,13 @@ public:
virtual void inputPortDelay(const Pin *port_pin,
float in_slew,
const RiseFall *rf,
Parasitic *parasitic,
const Parasitic *parasitic,
const DcalcAnalysisPt *dcalc_ap);
virtual void gateDelay(const LibertyCell *drvr_cell,
TimingArc *arc,
const TimingArc *arc,
const Slew &in_slew,
float load_cap,
Parasitic *drvr_parasitic,
const Parasitic *drvr_parasitic,
float related_out_cap,
const Pvt *pvt,
const DcalcAnalysisPt *dcalc_ap,
@ -53,7 +53,7 @@ public:
ArcDelay &wire_delay,
Slew &load_slew);
virtual void checkDelay(const LibertyCell *cell,
TimingArc *arc,
const TimingArc *arc,
const Slew &from_slew,
const Slew &to_slew,
float related_out_cap,
@ -62,25 +62,25 @@ public:
// Return values.
ArcDelay &margin);
virtual float ceff(const LibertyCell *drvr_cell,
TimingArc *arc,
const TimingArc *arc,
const Slew &in_slew,
float load_cap,
Parasitic *drvr_parasitic,
const Parasitic *drvr_parasitic,
float related_out_cap,
const Pvt *pvt,
const DcalcAnalysisPt *dcalc_ap);
virtual void reportGateDelay(const LibertyCell *drvr_cell,
TimingArc *arc,
const TimingArc *arc,
const Slew &in_slew,
float load_cap,
Parasitic *drvr_parasitic,
const Parasitic *drvr_parasitic,
float related_out_cap,
const Pvt *pvt,
const DcalcAnalysisPt *dcalc_ap,
int digits,
string *result);
virtual void reportCheckDelay(const LibertyCell *cell,
TimingArc *arc,
const TimingArc *arc,
const Slew &from_slew,
const char *from_slew_annotation,
const Slew &to_slew,

2
dcalc/RCDelayCalc.cc
View File

@ -39,7 +39,7 @@ void
RCDelayCalc::inputPortDelay(const Pin *,
float in_slew,
const RiseFall *rf,
Parasitic *parasitic,
const Parasitic *parasitic,
const DcalcAnalysisPt *)
{
drvr_parasitic_ = parasitic;

4
dcalc/RCDelayCalc.hh
View File

@ -29,7 +29,7 @@ public:
virtual void inputPortDelay(const Pin *port_pin,
float in_slew,
const RiseFall *rf,
Parasitic *parasitic,
const Parasitic *parasitic,
const DcalcAnalysisPt *dcalc_ap);
protected:
@ -40,7 +40,7 @@ protected:
Slew &load_slew);
const LibertyCell *drvr_cell_;
Parasitic *drvr_parasitic_;
const Parasitic *drvr_parasitic_;
};
} // namespace

6
dcalc/SimpleRCDelayCalc.cc
View File

@ -46,7 +46,7 @@ void
SimpleRCDelayCalc::inputPortDelay(const Pin *port_pin,
float in_slew,
const RiseFall *rf,
Parasitic *parasitic,
const Parasitic *parasitic,
const DcalcAnalysisPt *dcalc_ap)
{
pvt_ = dcalc_ap->operatingConditions();
@ -55,10 +55,10 @@ SimpleRCDelayCalc::inputPortDelay(const Pin *port_pin,
void
SimpleRCDelayCalc::gateDelay(const LibertyCell *drvr_cell,
TimingArc *arc,
const TimingArc *arc,
const Slew &in_slew,
float load_cap,
Parasitic *drvr_parasitic,
const Parasitic *drvr_parasitic,
float related_out_cap,
const Pvt *pvt,
const DcalcAnalysisPt *dcalc_ap,

6
dcalc/SimpleRCDelayCalc.hh
View File

@ -33,13 +33,13 @@ public:
virtual void inputPortDelay(const Pin *port_pin,
float in_slew,
const RiseFall *rf,
Parasitic *parasitic,
const Parasitic *parasitic,
const DcalcAnalysisPt *dcalc_ap);
virtual void gateDelay(const LibertyCell *drvr_cell,
TimingArc *arc,
const TimingArc *arc,
const Slew &in_slew,
float load_cap,
Parasitic *drvr_parasitic,
const Parasitic *drvr_parasitic,
float related_out_cap,
const Pvt *pvt,
const DcalcAnalysisPt *dcalc_ap,

18
dcalc/UnitDelayCalc.cc
View File

@ -55,17 +55,17 @@ void
UnitDelayCalc::inputPortDelay(const Pin *,
float,
const RiseFall *,
Parasitic *,
const Parasitic *,
const DcalcAnalysisPt *)
{
}
void
UnitDelayCalc::gateDelay(const LibertyCell *,
TimingArc *,
const TimingArc *,
const Slew &,
float,
Parasitic *,
const Parasitic *,
float,
const Pvt *, const DcalcAnalysisPt *,
// Return values.
@ -86,10 +86,10 @@ UnitDelayCalc::loadDelay(const Pin *,
float
UnitDelayCalc::ceff(const LibertyCell *,
TimingArc *,
const TimingArc *,
const Slew &,
float,
Parasitic *,
const Parasitic *,
float,
const Pvt *,
const DcalcAnalysisPt *)
@ -99,10 +99,10 @@ UnitDelayCalc::ceff(const LibertyCell *,
void
UnitDelayCalc::reportGateDelay(const LibertyCell *,
TimingArc *,
const TimingArc *,
const Slew &,
float,
Parasitic *,
const Parasitic *,
float,
const Pvt *,
const DcalcAnalysisPt *,
@ -115,7 +115,7 @@ UnitDelayCalc::reportGateDelay(const LibertyCell *,
void
UnitDelayCalc::checkDelay(const LibertyCell *,
TimingArc *,
const TimingArc *,
const Slew &,
const Slew &,
float,
@ -129,7 +129,7 @@ UnitDelayCalc::checkDelay(const LibertyCell *,
void
UnitDelayCalc::reportCheckDelay(const LibertyCell *,
TimingArc *,
const TimingArc *,
const Slew &,
const char *,
const Slew &,

18
dcalc/UnitDelayCalc.hh
View File

@ -31,10 +31,10 @@ public:
const DcalcAnalysisPt *dcalc_ap);
virtual ReducedParasiticType reducedParasiticType() const;
virtual void gateDelay(const LibertyCell *drvr_cell,
TimingArc *arc,
const TimingArc *arc,
const Slew &in_slew,
float load_cap,
Parasitic *drvr_parasitic,
const Parasitic *drvr_parasitic,
float related_out_cap,
const Pvt *pvt,
const DcalcAnalysisPt *dcalc_ap,
@ -47,20 +47,20 @@ public:
Slew &load_slew);
virtual void setMultiDrvrSlewFactor(float) {}
virtual float ceff(const LibertyCell *drvr_cell,
TimingArc *arc,
const TimingArc *arc,
const Slew &in_slew,
float load_cap,
Parasitic *drvr_parasitic,
const Parasitic *drvr_parasitic,
float related_out_cap,
const Pvt *pvt,
const DcalcAnalysisPt *dcalc_ap);
virtual void inputPortDelay(const Pin *port_pin,
float in_slew,
const RiseFall *rf,
Parasitic *parasitic,
const Parasitic *parasitic,
const DcalcAnalysisPt *dcalc_ap);
virtual void checkDelay(const LibertyCell *cell,
TimingArc *arc,
const TimingArc *arc,
const Slew &from_slew,
const Slew &to_slew,
float related_out_cap,
@ -69,17 +69,17 @@ public:
// Return values.
ArcDelay &margin);
virtual void reportGateDelay(const LibertyCell *drvr_cell,
TimingArc *arc,
const TimingArc *arc,
const Slew &in_slew,
float load_cap,
Parasitic *drvr_parasitic,
const Parasitic *drvr_parasitic,
float related_out_cap,
const Pvt *pvt,
const DcalcAnalysisPt *dcalc_ap,
int digits,
string *result);
virtual void reportCheckDelay(const LibertyCell *cell,
TimingArc *arc,
const TimingArc *arc,
const Slew &from_slew,
const char *from_slew_annotation,
const Slew &to_slew,

18
doc/ApiChanges.txt
View File

@ -16,6 +16,24 @@
This file summarizes STA API changes for each release.
Release 2.4.0 2023/01/??
-------------------------
The Network API and associated containers now 'const' the network class objects.
The Network API now requires network objects to have and "id" function that
returns an ObjectId (unsigned int) that is unique to the object among objects
of the same type.
virtual ObjectId id(const Instance *instance) const = 0;
Object IDs are used for comparing and hashing network objects.
If network Ids are not available in the host application database object pointers
can be cast to intptr_t. Using pointers as object Ids can result in memory layout
dependent results that are inconsistent from run to run or across host systems.
Many Network and Sta class functions now return collections rather than pointers
to temporary collections that the caller would have to delete.
Release 2.3.1 2022/06/12
-------------------------
LibertyCellTimingArcSetIterator has been removed.

36
graph/Graph.cc
View File

@ -168,7 +168,7 @@ Graph::makeInstanceEdges(const Instance *inst)
}
void
Graph::makePinInstanceEdges(Pin *pin)
Graph::makePinInstanceEdges(const Pin *pin)
{
const Instance *inst = network_->instance(pin);
if (inst) {
@ -232,7 +232,7 @@ Graph::makePortInstanceEdges(const Instance *inst,
void
Graph::makeWireEdges()
{
PinSet visited_drvrs;
PinSet visited_drvrs(network_);
LeafInstanceIterator *inst_iter = network_->leafInstanceIterator();
while (inst_iter->hasNext()) {
Instance *inst = inst_iter->next();
@ -243,7 +243,7 @@ Graph::makeWireEdges()
}
void
Graph::makeInstDrvrWireEdges(Instance *inst,
Graph::makeInstDrvrWireEdges(const Instance *inst,
PinSet &visited_drvrs)
{
InstancePinIterator *pin_iter = network_->pinIterator(inst);
@ -257,10 +257,10 @@ Graph::makeInstDrvrWireEdges(Instance *inst,
}
void
Graph::makeWireEdgesFromPin(Pin *drvr_pin)
Graph::makeWireEdgesFromPin(const Pin *drvr_pin)
{
PinSeq loads, drvrs;
PinSet visited_drvrs;
PinSet visited_drvrs(network_);
FindNetDrvrLoads visitor(drvr_pin, visited_drvrs, loads, drvrs, network_);
network_->visitConnectedPins(drvr_pin, visitor);
@ -271,7 +271,7 @@ Graph::makeWireEdgesFromPin(Pin *drvr_pin)
}
void
Graph::makeWireEdgesFromPin(Pin *drvr_pin,
Graph::makeWireEdgesFromPin(const Pin *drvr_pin,
PinSet &visited_drvrs)
{
// Find all drivers and loads on the net to avoid N*M run time
@ -289,7 +289,7 @@ Graph::makeWireEdgesFromPin(Pin *drvr_pin,
}
void
Graph::makeWireEdgesToPin(Pin *to_pin)
Graph::makeWireEdgesToPin(const Pin *to_pin)
{
PinSet *drvrs = network_->drivers(to_pin);
if (drvrs) {
@ -306,8 +306,8 @@ public:
MakeEdgesThruHierPin(Graph *graph);
private:
virtual void visit(Pin *drvr,
Pin *load);
virtual void visit(const Pin *drvr,
const Pin *load);
Graph *graph_;
};
@ -319,22 +319,22 @@ MakeEdgesThruHierPin::MakeEdgesThruHierPin(Graph *graph) :
}
void
MakeEdgesThruHierPin::visit(Pin *drvr,
Pin *load)
MakeEdgesThruHierPin::visit(const Pin *drvr,
const Pin *load)
{
graph_->makeWireEdge(drvr, load);
}
void
Graph::makeWireEdgesThruPin(Pin *hpin)
Graph::makeWireEdgesThruPin(const Pin *hpin)
{
MakeEdgesThruHierPin visitor(this);
visitDrvrLoadsThruHierPin(hpin, network_, &visitor);
}
void
Graph::makeWireEdge(Pin *from_pin,
Pin *to_pin)
Graph::makeWireEdge(const Pin *from_pin,
const Pin *to_pin)
{
TimingArcSet *arc_set = TimingArcSet::wireTimingArcSet();
Vertex *from_vertex, *from_bidirect_drvr_vertex;
@ -1557,8 +1557,8 @@ class FindEdgesThruHierPinVisitor : public HierPinThruVisitor
public:
FindEdgesThruHierPinVisitor(EdgeSet &edges,
Graph *graph);
virtual void visit(Pin *drvr,
Pin *load);
virtual void visit(const Pin *drvr,
const Pin *load);
protected:
EdgeSet &edges_;
@ -1574,8 +1574,8 @@ FindEdgesThruHierPinVisitor::FindEdgesThruHierPinVisitor(EdgeSet &edges,
}
void
FindEdgesThruHierPinVisitor::visit(Pin *drvr,
Pin *load)
FindEdgesThruHierPinVisitor::visit(const Pin *drvr,
const Pin *load)
{
Vertex *drvr_vertex = graph_->pinDrvrVertex(drvr);
Vertex *load_vertex = graph_->pinLoadVertex(load);

24
include/sta/ArcDelayCalc.hh
View File

@ -60,16 +60,16 @@ public:
virtual void inputPortDelay(const Pin *port_pin,
float in_slew,
const RiseFall *rf,
Parasitic *parasitic,
const Parasitic *parasitic,
const DcalcAnalysisPt *dcalc_ap) = 0;
// Find the delay and slew for arc driving drvr_pin.
virtual void gateDelay(const LibertyCell *drvr_cell,
TimingArc *arc,
const TimingArc *arc,
const Slew &in_slew,
// Pass in load_cap or drvr_parasitic.
float load_cap,
Parasitic *drvr_parasitic,
const Parasitic *drvr_parasitic,
float related_out_cap,
const Pvt *pvt,
const DcalcAnalysisPt *dcalc_ap,
@ -85,10 +85,10 @@ public:
virtual void setMultiDrvrSlewFactor(float factor) = 0;
// Ceff for parasitics with pi models.
virtual float ceff(const LibertyCell *drvr_cell,
TimingArc *arc,
const TimingArc *arc,
const Slew &in_slew,
float load_cap,
Parasitic *drvr_parasitic,
const Parasitic *drvr_parasitic,
float related_out_cap,
const Pvt *pvt,
const DcalcAnalysisPt *dcalc_ap) = 0;
@ -96,7 +96,7 @@ public:
// Find the delay for a timing check arc given the arc's
// from/clock, to/data slews and related output pin parasitic.
virtual void checkDelay(const LibertyCell *drvr_cell,
TimingArc *arc,
const TimingArc *arc,
const Slew &from_slew,
const Slew &to_slew,
float related_out_cap,
@ -106,11 +106,11 @@ public:
ArcDelay &margin) = 0;
// Report delay and slew calculation.
virtual void reportGateDelay(const LibertyCell *drvr_cell,
TimingArc *arc,
const TimingArc *arc,
const Slew &in_slew,
// Pass in load_cap or drvr_parasitic.
float load_cap,
Parasitic *drvr_parasitic,
const Parasitic *drvr_parasitic,
float related_out_cap,
const Pvt *pvt,
const DcalcAnalysisPt *dcalc_ap,
@ -118,7 +118,7 @@ public:
string *result) = 0;
// Report timing check delay calculation.
virtual void reportCheckDelay(const LibertyCell *cell,
TimingArc *arc,
const TimingArc *arc,
const Slew &from_slew,
const char *from_slew_annotation,
const Slew &to_slew,
@ -130,11 +130,11 @@ public:
virtual void finishDrvrPin() = 0;
protected:
GateTimingModel *gateModel(TimingArc *arc,
GateTimingModel *gateModel(const TimingArc *arc,
const DcalcAnalysisPt *dcalc_ap) const;
CheckTimingModel *checkModel(TimingArc *arc,
CheckTimingModel *checkModel(const TimingArc *arc,
const DcalcAnalysisPt *dcalc_ap) const;
TimingModel *model(TimingArc *arc,
TimingModel *model(const TimingArc *arc,
const DcalcAnalysisPt *dcalc_ap) const;
};

3
include/sta/ClkNetwork.hh
View File

@ -26,7 +26,7 @@
namespace sta {
typedef Map<const Pin*, ClockSet> PinClksMap;
typedef Map<const Clock *, PinSet> ClkPinsMap;
typedef Map<const Clock *, PinSet*> ClkPinsMap;
class Sta;
@ -36,6 +36,7 @@ class ClkNetwork : public StaState
{
public:
ClkNetwork(StaState *sta);
~ClkNetwork();
void ensureClkNetwork();
void clear();
bool isClock(const Pin *pin) const;

33
include/sta/Clock.hh
View File

@ -34,7 +34,6 @@ public:
float period() const { return period_; }
// Virtual clocks have no pins.
bool isVirtual() const;
PinSet &pins() { return pins_; }
const PinSet &pins() const { return pins_; }
// The clock source pin's leaf pins.
// If the source pin is hierarchical, the leaf pins are:
@ -44,7 +43,7 @@ public:
const PinSet &leafPins() const { return leaf_pins_; }
// Clock pin used by input/output delay for propagated generated
// clock insertion delay.
Pin *defaultPin() const;
const Pin *defaultPin() const;
bool addToPins() const { return add_to_pins_; }
void setAddToPins(bool add_to_pins);
FloatSeq *waveform() { return waveform_; }
@ -69,7 +68,7 @@ public:
const MinMaxAll *min_max,
float slew);
void removeSlew();
RiseFallMinMax *slews() { return &slews_; }
const RiseFallMinMax &slews() const { return slews_; }
void setSlewLimit(const RiseFallBoth *rf,
const PathClkOrData clk_data,
const MinMax *min_max,
@ -94,8 +93,8 @@ public:
void setPeriod(float period);
void setWaveform(FloatSeq *waveform);
void addPin(Pin *pin);
void deletePin(Pin *pin);
void addPin(const Pin *pin);
void deletePin(const Pin *pin);
void makeLeafPins(const Network *network);
bool isGenerated() const;
@ -123,9 +122,10 @@ public:
void waveformInvalid();
protected:
// Private to Constraints::makeClock.
// Private to Sdc::makeClock.
Clock(const char *name,
int index);
int index,
const Network *network);
void initClk(PinSet *pins,
bool add_to_pins,
float period,
@ -218,16 +218,17 @@ int
clkCmp(const Clock *clk1,
const Clock *clk2);
int
clkEdgeCmp(ClockEdge *clk_edge1,
ClockEdge *clk_edge2);
clkEdgeCmp(const ClockEdge *clk_edge1,
const ClockEdge *clk_edge2);
bool
clkEdgeLess(ClockEdge *clk_edge1,
ClockEdge *clk_edge2);
clkEdgeLess(const ClockEdge *clk_edge1,
const ClockEdge *clk_edge2);
class ClockNameLess
{
public:
bool operator()(const Clock *clk1, const Clock *clk2);
bool operator()(const Clock *clk1,
const Clock *clk2);
};
////////////////////////////////////////////////////////////////
@ -278,8 +279,10 @@ public:
}
};
void
sortClockSet(ClockSet * set,
ClockSeq &clks);
ClockSeq
sortByName(ClockSet *set);
int
compare(const ClockSet *set1,
const ClockSet *set2);
} // namespace

14
include/sta/ClockGroups.hh
View File

@ -21,18 +21,6 @@
namespace sta {
class ClockGroup
{
public:
ClockGroup(ClockSet *clks);
~ClockGroup();
bool isMember(const Clock *clk);
ClockSet *clks() const { return clks_; }
private:
ClockSet *clks_;
};
class ClockGroups : public SdcCmdComment
{
public:
@ -43,7 +31,7 @@ public:
bool allow_paths,
const char *comment);
~ClockGroups();
ClockGroup *makeClockGroup(ClockSet *clks);
void makeClockGroup(ClockSet *clks);
const char *name() const { return name_; }
ClockGroupSet *groups() { return &groups_; }
bool logicallyExclusive() const { return logically_exclusive_; }

32
include/sta/ConcreteLibrary.hh
View File

@ -53,6 +53,7 @@ public:
virtual ~ConcreteLibrary();
const char *name() const { return name_; }
void setName(const char *name);
ObjectId id() const { return id_; }
bool isLiberty() const { return is_liberty_; }
const char *filename() const { return filename_; }
void addCell(ConcreteCell *cell);
@ -62,8 +63,7 @@ public:
void deleteCell(ConcreteCell *cell);
ConcreteLibraryCellIterator *cellIterator() const;
ConcreteCell *findCell(const char *name) const;
void findCellsMatching(const PatternMatch *pattern,
CellSeq *cells) const;
CellSeq findCellsMatching(const PatternMatch *pattern) const;
char busBrktLeft() const { return bus_brkt_left_; }
char busBrktRight() const { return bus_brkt_right_; }
void setBusBrkts(char left,
@ -74,6 +74,7 @@ protected:
const char *cell_name);
const char *name_;
ObjectId id_;
const char *filename_;
bool is_liberty_;
char bus_brkt_left_;
@ -89,17 +90,17 @@ class ConcreteCell
public:
// Use ConcreteLibrary::deleteCell.
virtual ~ConcreteCell();
ConcreteLibrary *library() const { return library_; }
const char *name() const { return name_; }
ObjectId id() const { return id_; }
const char *filename() const { return filename_; }
ConcreteLibrary *library() const { return library_; }
LibertyCell *libertyCell() const { return liberty_cell_; }
void setLibertyCell(LibertyCell *cell);
void *extCell() const { return ext_cell_; }
void setExtCell(void *ext_cell);
int portBitCount() const { return port_bit_count_; }
ConcretePort *findPort(const char *name) const;
void findPortsMatching(const PatternMatch *pattern,
PortSeq *ports) const;
PortSeq findPortsMatching(const PatternMatch *pattern) const;
ConcreteCellPortIterator *portIterator() const;
ConcreteCellPortBitIterator *portBitIterator() const;
bool isLeaf() const { return is_leaf_; }
@ -124,10 +125,10 @@ public:
void addPortBit(ConcretePort *port);
protected:
ConcreteCell(ConcreteLibrary *library,
const char *name,
bool is_leaf,
const char *filename);
ConcreteCell(const char *name,
const char *filename,
bool is_leaf,
ConcreteLibrary *library);
ConcretePort *makeBusPort(const char *name,
int from_index,
int to_index,
@ -143,10 +144,11 @@ protected:
const char *name,
int index);
ConcreteLibrary *library_;
const char *name_;
ObjectId id_;
// Filename is optional.
const char *filename_;
ConcreteLibrary *library_;
LibertyCell *liberty_cell_;
// External application cell.
void *ext_cell_;
@ -167,6 +169,7 @@ class ConcretePort
public:
virtual ~ConcretePort();
const char *name() const { return name_; }
ObjectId id() const { return id_; }
const char *busName() const;
Cell *cell() const;
ConcreteLibrary *library() const { return cell_->library(); }
@ -212,15 +215,16 @@ public:
protected:
// Constructors for factory in cell class.
ConcretePort(ConcreteCell *cell,
const char *name,
bool is_bus,
ConcretePort(const char *name,
bool is_bus,
int from_index,
int to_index,
bool is_bundle,
ConcretePortSeq *member_ports);
ConcretePortSeq *member_ports,
ConcreteCell *cell);
const char *name_;
ObjectId id_;
ConcreteCell *cell_;
PortDirection *direction_;
LibertyPort *liberty_port_;

48
include/sta/ConcreteNetwork.hh
View File

@ -60,20 +60,21 @@ public:
Report *report);
virtual Instance *topInstance() const;
virtual const char *name(const Library *library) const;
virtual ObjectId id(const Library *library) const;
virtual LibraryIterator *libraryIterator() const;
virtual LibertyLibraryIterator *libertyLibraryIterator() const ;
virtual Library *findLibrary(const char *name);
virtual const char *name(const Library *library) const;
virtual LibertyLibrary *findLiberty(const char *name);
virtual LibertyLibrary *libertyLibrary(Library *library) const;
virtual Cell *findCell(const Library *library,
const char *name) const;
virtual Cell *findAnyCell(const char *name);
virtual void findCellsMatching(const Library *library,
const PatternMatch *pattern,
CellSeq *cells) const;
virtual CellSeq findCellsMatching(const Library *library,
const PatternMatch *pattern) const;
virtual const char *name(const Cell *cell) const;
virtual ObjectId id(const Cell *cell) const;
virtual Library *library(const Cell *cell) const;
virtual LibertyCell *libertyCell(Cell *cell) const;
virtual const LibertyCell *libertyCell(const Cell *cell) const;
@ -82,15 +83,15 @@ public:
virtual const char *filename(const Cell *cell);
virtual Port *findPort(const Cell *cell,
const char *name) const;
virtual void findPortsMatching(const Cell *cell,
const PatternMatch *pattern,
PortSeq *ports) const;
virtual PortSeq findPortsMatching(const Cell *cell,
const PatternMatch *pattern) const;
virtual bool isLeaf(const Cell *cell) const;
virtual CellPortIterator *portIterator(const Cell *cell) const;
virtual CellPortBitIterator *portBitIterator(const Cell *cell) const;
virtual int portBitCount(const Cell *cell) const;
virtual const char *name(const Port *port) const;
virtual ObjectId id(const Port *port) const;
virtual Cell *cell(const Port *port) const;
virtual LibertyPort *libertyPort(const Port *port) const;
virtual PortDirection *direction(const Port *port) const;
@ -109,6 +110,7 @@ public:
virtual PortMemberIterator *memberIterator(const Port *port) const;
virtual const char *name(const Instance *instance) const;
virtual ObjectId id(const Instance *instance) const;
virtual Cell *cell(const Instance *instance) const;
virtual Instance *parent(const Instance *instance) const;
virtual bool isLeaf(const Instance *instance) const;
@ -126,6 +128,7 @@ public:
virtual InstanceNetIterator *
netIterator(const Instance *instance) const;
virtual ObjectId id(const Pin *pin) const;
virtual Instance *instance(const Pin *pin) const;
virtual Net *net(const Pin *pin) const;
virtual Term *term(const Pin *pin) const;
@ -135,15 +138,17 @@ public:
virtual void setVertexId(Pin *pin,
VertexId id);
virtual ObjectId id(const Term *term) const;
virtual Net *net(const Term *term) const;
virtual Pin *pin(const Term *term) const;
virtual const char *name(const Net *net) const;
virtual ObjectId id(const Net *net) const;
virtual Net *findNet(const Instance *instance,
const char *net_name) const;
virtual void findInstNetsMatching(const Instance *instance,
const PatternMatch *pattern,
NetSeq *nets) const;
virtual const char *name(const Net *net) const;
const PatternMatch *pattern,
NetSeq &matches) const;
virtual Instance *instance(const Net *net) const;
virtual bool isPower(const Net *net) const;
virtual bool isGround(const Net *net) const;
@ -227,6 +232,8 @@ public:
virtual void setLinkFunc(LinkNetworkFunc *link);
void setTopInstance(Instance *top_inst);
static ObjectId nextObjectId();
using Network::netIterator;
using Network::findPin;
using Network::findNet;
@ -242,7 +249,7 @@ protected:
void clearConstantNets();
virtual void visitConnectedPins(const Net *net,
PinVisitor &visitor,
ConstNetSet &visited_nets) const;
NetSet &visited_nets) const;
Instance *makeConcreteInstance(ConcreteCell *cell,
const char *name,
Instance *parent);
@ -258,6 +265,7 @@ protected:
NetSet constant_nets_[2]; // LogicValue::zero/one
LinkNetworkFunc *link_func_;
CellNetworkViewMap cell_network_view_map_;
static ObjectId object_id_;
private:
friend class ConcreteLibertyLibraryIterator;
@ -267,13 +275,14 @@ class ConcreteInstance
{
public:
const char *name() const { return name_; }
ObjectId id() const { return id_; }
Cell *cell() const;
ConcreteInstance *parent() const { return parent_; }
ConcretePin *findPin(const char *port_name) const;
ConcretePin *findPin(const Port *port) const;
ConcreteNet *findNet(const char *net_name) const;
void findNetsMatching(const PatternMatch *pattern,
NetSeq *nets) const;
NetSeq &matches) const;
InstanceNetIterator *netIterator() const;
Instance *findChild(const char *name) const;
InstanceChildIterator *childIterator() const;
@ -289,13 +298,14 @@ public:
void initPins();
protected:
ConcreteInstance(ConcreteCell *cell,
const char *name,
ConcreteInstance *parent);
ConcreteInstance(const char *name,
ConcreteCell *cell,
ConcreteInstance *parent);
~ConcreteInstance();
ConcreteCell *cell_;
const char *name_;
ObjectId id_;
ConcreteCell *cell_;
ConcreteInstance *parent_;
// Array of pins indexed by pin->port->index().
ConcretePin **pins_;
@ -315,6 +325,7 @@ public:
ConcreteNet *net() const { return net_; }
ConcretePort *port() const { return port_; }
ConcreteTerm *term() const { return term_; }
ObjectId id() const { return id_; }
VertexId vertexId() const { return vertex_id_; }
void setVertexId(VertexId id);
@ -328,6 +339,7 @@ protected:
ConcretePort *port_;
ConcreteNet *net_;
ConcreteTerm *term_;
ObjectId id_;
// Doubly linked list of net pins.
ConcretePin *net_next_;
ConcretePin *net_prev_;
@ -343,6 +355,7 @@ class ConcreteTerm
{
public:
const char *name() const;
ObjectId id() const { return id_; }
ConcreteNet *net() const { return net_; }
ConcretePin *pin() const { return pin_; }
@ -353,6 +366,7 @@ protected:
ConcretePin *pin_;
ConcreteNet *net_;
ObjectId id_;
// Linked list of net terms.
ConcreteTerm *net_next_;
@ -366,6 +380,7 @@ class ConcreteNet
{
public:
const char *name() const { return name_; }
ObjectId id() const { return id_; }
ConcreteInstance *instance() const { return instance_; }
void addPin(ConcretePin *pin);
void deletePin(ConcretePin *pin);
@ -379,6 +394,7 @@ protected:
ConcreteInstance *instance);
~ConcreteNet();
const char *name_;
ObjectId id_;
ConcreteInstance *instance_;
// Pointer to head of linked list of pins.
ConcretePin *pins_;

6
include/sta/DataCheck.hh
View File

@ -25,8 +25,6 @@
namespace sta {
class PinPathNameLess;
class DataCheck
{
public:
@ -65,12 +63,12 @@ private:
class DataCheckLess
{
public:
explicit DataCheckLess(const Network *network);
DataCheckLess(const Network *network);
bool operator()(const DataCheck *check1,
const DataCheck *check2) const;
private:
PinPathNameLess pin_less_;
const Network *network_;
};
} // namespace

3
include/sta/DelayCalc.hh
View File

@ -34,8 +34,7 @@ registerDelayCalc(const char *name,
MakeArcDelayCalc maker);
bool
isDelayCalcName(const char *name);
// Caller owns return value.
StringSeq *
StringSeq
delayCalcNames();
void
deleteDelayCalcs();

19
include/sta/DisabledPorts.hh
View File

@ -29,7 +29,7 @@ class DisabledInstancePorts;
typedef Vector<DisabledInstancePorts*> DisabledInstancePortsSeq;
typedef Vector<DisabledCellPorts*> DisabledCellPortsSeq;
typedef Vector<LibertyPortPair*> LibertyPortPairSeq;
typedef Vector<LibertyPortPair> LibertyPortPairSeq;
typedef Set<TimingArcSet*> TimingArcSetSet;
// Base class for disabled cell and instance ports.
@ -93,15 +93,12 @@ private:
Instance *inst_;
};
void
sortDisabledCellPortsMap(DisabledCellPortsMap *cell_map,
DisabledCellPortsSeq &disables);
void
sortDisabledInstancePortsMap(DisabledInstancePortsMap *inst_map,
Network *network,
DisabledInstancePortsSeq &disables);
void
sortLibertyPortPairSet(LibertyPortPairSet *sets,
LibertyPortPairSeq &pairs);
DisabledCellPortsSeq
sortByName(DisabledCellPortsMap *cell_map);
DisabledInstancePortsSeq
sortByPathName(const DisabledInstancePortsMap *inst_map,
const Network *network);
LibertyPortPairSeq
sortByName(const LibertyPortPairSet *set);
} // namespace

137
include/sta/ExceptionPath.hh
View File

@ -314,22 +314,28 @@ public:
virtual NetSet *nets() = 0;
virtual EdgePinsSet *edges() = 0;
size_t hash() const;
virtual int nameCmp(ExceptionPt *pt, const Network *network) const = 0;
virtual void mergeInto(ExceptionPt *pt) = 0;
virtual int compare(ExceptionPt *pt,
const Network *network) const = 0;
virtual void mergeInto(ExceptionPt *pt,
const Network *network) = 0;
// All pins and instance/net pins.
virtual void allPins(const Network *network,
PinSet *pins) = 0;
virtual int typePriority() const = 0;
virtual const char *asString(const Network *network) const = 0;
virtual size_t objectCount() const = 0;
virtual void addPin(Pin *pin) = 0;
virtual void addPin(const Pin *pin,
const Network *network) = 0;
virtual void addClock(Clock *clk) = 0;
virtual void addInstance(Instance *inst) = 0;
virtual void addNet(Net *net) = 0;
virtual void addEdge(EdgePins *edge) = 0;
virtual void addInstance(const Instance *inst,
const Network *network) = 0;
virtual void addNet(const Net *net,
const Network *network) = 0;
virtual void addEdge(const EdgePins &edge,
const Network *network) = 0;
virtual void connectPinAfter(PinSet *,
Network *network) = 0;
virtual void disconnectPinBefore(Pin *pin,
virtual void disconnectPinBefore(const Pin *pin,
Network *network) = 0;
protected:
@ -351,10 +357,12 @@ protected:
class ExceptionFromTo : public ExceptionPt
{
public:
ExceptionFromTo(PinSet *pins, ClockSet *clks,
ExceptionFromTo(PinSet *pins,
ClockSet *clks,
InstanceSet *insts,
const RiseFallBoth *rf,
bool own_pts);
bool own_pts,
const Network *network);
~ExceptionFromTo();
virtual PinSet *pins() { return pins_; }
bool hasPins() const;
@ -365,31 +373,39 @@ public:
virtual NetSet *nets() { return nullptr; }
virtual EdgePinsSet *edges() { return nullptr; }
bool hasObjects() const;
void deleteObjects(ExceptionFromTo *pt);
void deleteObjects(ExceptionFromTo *pt,
const Network *network);
virtual void allPins(const Network *network,
PinSet *pins);
bool equal(ExceptionFromTo *from_to) const;
virtual int nameCmp(ExceptionPt *pt,
virtual int compare(ExceptionPt *pt,
const Network *network) const;
virtual void mergeInto(ExceptionPt *pt);
virtual void mergeInto(ExceptionPt *pt,
const Network *network);
virtual const char *asString(const Network *network) const;
virtual size_t objectCount() const;
void deleteClock(Clock *clk);
virtual void addPin(Pin *pin);
virtual void addPin(const Pin *pin,
const Network *network);
virtual void addClock(Clock *clk);
virtual void addInstance(Instance *inst);
virtual void addNet(Net *) {}
virtual void addEdge(EdgePins *) {}
virtual void addInstance(const Instance *inst,
const Network *network);
virtual void addNet(const Net *,
const Network *) {}
virtual void addEdge(const EdgePins &,
const Network *) {}
virtual void connectPinAfter(PinSet *,
Network *) {}
virtual void disconnectPinBefore(Pin *,
virtual void disconnectPinBefore(const Pin *,
Network *) {}
protected:
virtual void findHash();
virtual void findHash(const Network *network);
void deletePin(Pin *pin);
void deleteInstance(Instance *inst);
void deletePin(const Pin *pin,
const Network *network);
void deleteInstance(const Instance *inst,
const Network *network);
virtual const char *cmdKeyword() const = 0;
PinSet *pins_;
@ -404,15 +420,16 @@ public:
ClockSet *clks,
InstanceSet *insts,
const RiseFallBoth *rf,
bool own_pts);
ExceptionFrom *clone();
bool own_pts,
const Network *network);
ExceptionFrom *clone(const Network *network);
virtual bool isFrom() const { return true; }
bool intersectsPts(ExceptionFrom *from) const;
virtual int typePriority() const { return 0; }
protected:
virtual const char *cmdKeyword() const;
virtual void findHash();
virtual void findHash(const Network *network);
};
class ExceptionTo : public ExceptionFromTo
@ -425,8 +442,9 @@ public:
const RiseFallBoth *rf,
// -rise|-fall endpoint transition.
const RiseFallBoth *end_rf,
bool own_pts);
ExceptionTo *clone();
bool own_pts,
const Network *network);
ExceptionTo *clone(const Network *network);
virtual bool isTo() const { return true; }
const char *asString(const Network *network) const;
const RiseFallBoth *endTransition() { return end_rf_; }
@ -446,7 +464,8 @@ public:
const ClockEdge *clk_edge,
const RiseFall *end_rf,
const Network *network) const;
virtual int nameCmp(ExceptionPt *pt, const Network *network) const;
virtual int compare(ExceptionPt *pt,
const Network *network) const;
protected:
bool matches(const Pin *pin,
@ -479,7 +498,8 @@ public:
InstanceSet *instances() { return insts_; }
virtual ClockSet *clks() { return nullptr; }
bool hasObjects() const;
void deleteObjects(ExceptionThru *pt);
void deleteObjects(ExceptionThru *pt,
const Network *network);
virtual void allPins(const Network *network,
PinSet *pins);
bool matches(const Pin *from_pin,
@ -487,41 +507,49 @@ public:
const RiseFall *to_rf,
const Network *network);
bool equal(ExceptionThru *thru) const;
virtual int nameCmp(ExceptionPt *pt,
virtual int compare(ExceptionPt *pt,
const Network *network) const;
virtual void mergeInto(ExceptionPt *pt);
virtual void mergeInto(ExceptionPt *pt,
const Network *network);
bool intersectsPts(ExceptionThru *thru) const;
virtual int typePriority() const { return 2; }
virtual size_t objectCount() const;
virtual void connectPinAfter(PinSet *drvrs,
Network *network);
virtual void disconnectPinBefore(Pin *pin,
virtual void disconnectPinBefore(const Pin *pin,
Network *network);
protected:
void findHash();
virtual void addPin(Pin *pin);
virtual void addEdge(EdgePins *edge);
virtual void addNet(Net *net);
virtual void addInstance(Instance *inst);
void findHash(const Network *network);
virtual void addPin(const Pin *pin,
const Network *network);
virtual void addEdge(const EdgePins &edge,
const Network *network);
virtual void addNet(const Net *net,
const Network *network);
virtual void addInstance(const Instance *inst,
const Network *network);
virtual void addClock(Clock *) {}
void deletePin(Pin *pin);
void deleteEdge(EdgePins *edge);
void deleteNet(Net *net);
void deleteInstance(Instance *inst);
void deletePin(const Pin *pin,
const Network *network);
void deleteEdge(const EdgePins &edge);
void deleteNet(const Net *net,
const Network *network);
void deleteInstance(const Instance *inst,
const Network *network);
void makeAllEdges(const Network *network);
void makePinEdges(const Network *network);
void makeNetEdges(const Network *network);
void makeInstEdges(const Network *network);
void makeHpinEdges(const Pin *pin,
const Network *network);
void makePinEdges(Pin *pin,
void makePinEdges(const Pin *pin,
const Network *network);
void makeNetEdges(Net *net,
void makeNetEdges(const Net *net,
const Network *network);
void makeInstEdges(Instance *inst,
Network *network);
void deletePinEdges(Pin *pin,
void deletePinEdges(const Pin *pin,
Network *network);
void deleteNetEdges(Net *net,
const Network *network);
@ -598,6 +626,7 @@ public:
ExceptionThru *next_thru,
int index);
ExceptionPath *exception() { return exception_; }
const ExceptionPath *exception() const { return exception_; }
bool matchesNextThru(const Pin *from_pin,
const Pin *to_pin,
const RiseFall *to_rf,
@ -607,6 +636,7 @@ public:
ExceptionThru *nextThru() const { return next_thru_; }
ExceptionState *nextState() const { return next_state_; }
void setNextState(ExceptionState *next_state);
int index() const { return index_; }
size_t hash() const;
private:
@ -623,22 +653,21 @@ public:
virtual const char *what() const noexcept;
};
class ExceptionPathLess
{
public:
ExceptionPathLess(const Network *network);
bool operator()(const ExceptionPath *except1,
const ExceptionPath *except2) const;
private:
const Network *network_;
};
// Throws EmptyExpceptionPt it finds an empty exception point.
void
checkFromThrusTo(ExceptionFrom *from,
ExceptionThruSeq *thrus,
ExceptionTo *to);
void
sortExceptions(ExceptionPathSet *set,
ExceptionPathSeq &exceptions,
Network *network);
bool
intersects(PinSet *set1,
PinSet *set2);
bool
intersects(ClockSet *set1,
ClockSet *set2);
} // namespace

16
include/sta/Graph.hh
View File

@ -133,13 +133,13 @@ public:
virtual Edge *makeEdge(Vertex *from,
Vertex *to,
TimingArcSet *arc_set);
virtual void makeWireEdge(Pin *from_pin,
Pin *to_pin);
void makePinInstanceEdges(Pin *pin);
virtual void makeWireEdge(const Pin *from_pin,
const Pin *to_pin);
void makePinInstanceEdges(const Pin *pin);
void makeInstanceEdges(const Instance *inst);
void makeWireEdgesToPin(Pin *to_pin);
void makeWireEdgesThruPin(Pin *hpin);
virtual void makeWireEdgesFromPin(Pin *drvr_pin);
void makeWireEdgesToPin(const Pin *to_pin);
void makeWireEdgesThruPin(const Pin *hpin);
virtual void makeWireEdgesFromPin(const Pin *drvr_pin);
virtual void deleteEdge(Edge *edge);
virtual ArcDelay arcDelay(const Edge *edge,
const TimingArc *arc,
@ -211,10 +211,10 @@ protected:
bool is_reg_clk);
virtual void makeEdgeArcDelays(Edge *edge);
void makePinVertices(const Instance *inst);
void makeWireEdgesFromPin(Pin *drvr_pin,
void makeWireEdgesFromPin(const Pin *drvr_pin,
PinSet &visited_drvrs);
void makeWireEdges();
virtual void makeInstDrvrWireEdges(Instance *inst,
virtual void makeInstDrvrWireEdges(const Instance *inst,
PinSet &visited_drvrs);
virtual void makePortInstanceEdges(const Instance *inst,
LibertyCell *cell,

2
include/sta/Hash.hh
View File

@ -52,6 +52,8 @@ nextMersenne(size_t n)
size_t
hashString(const char *str);
// Pointer hashing is strongly discouraged because it causes results to change
// from run to run. Use Network::id functions instead.
#if __WORDSIZE == 64
#define hashPtr(ptr) (reinterpret_cast<intptr_t>(ptr) >> 3)
#else

18
include/sta/HpinDrvrLoad.hh
View File

@ -48,23 +48,23 @@ public:
class HpinDrvrLoad
{
public:
HpinDrvrLoad(Pin *drvr,
Pin *load,
HpinDrvrLoad(const Pin *drvr,
const Pin *load,
PinSet *hpins_from_drvr,
PinSet *hpins_to_load);
~HpinDrvrLoad();
void report(const Network *network);
HpinDrvrLoad(Pin *drvr,
Pin *load);
Pin *drvr() const { return drvr_; }
Pin *load() const { return load_; }
HpinDrvrLoad(const Pin *drvr,
const Pin *load);
const Pin *drvr() const { return drvr_; }
const Pin *load() const { return load_; }
PinSet *hpinsFromDrvr() { return hpins_from_drvr_; }
PinSet *hpinsToLoad() { return hpins_to_load_; }
void setDrvr(Pin *drvr);
void setDrvr(const Pin *drvr);
private:
Pin *drvr_;
Pin *load_;
const Pin *drvr_;
const Pin *load_;
PinSet *hpins_from_drvr_;
PinSet *hpins_to_load_;
};

48
include/sta/InputDrive.hh
View File

@ -47,20 +47,20 @@ public:
bool hasDriveResistance(const RiseFall *rf,
const MinMax *min_max);
bool driveResistanceMinMaxEqual(const RiseFall *rf);
void setDriveCell(LibertyLibrary *library,
LibertyCell *cell,
LibertyPort *from_port,
void setDriveCell(const LibertyLibrary *library,
const LibertyCell *cell,
const LibertyPort *from_port,
float *from_slews,
LibertyPort *to_port,
const LibertyPort *to_port,
const RiseFallBoth *rf,
const MinMaxAll *min_max);
void driveCell(const RiseFall *rf,
const MinMax *min_max,
// Return values.
LibertyCell *&cell,
LibertyPort *&from_port,
const LibertyCell *&cell,
const LibertyPort *&from_port,
float *&from_slews,
LibertyPort *&to_port);
const LibertyPort *&to_port);
InputDriveCell *driveCell(const RiseFall *rf,
const MinMax *min_max);
bool hasDriveCell(const RiseFall *rf,
@ -83,29 +83,29 @@ private:
class InputDriveCell
{
public:
InputDriveCell(LibertyLibrary *library,
LibertyCell *cell,
LibertyPort *from_port,
InputDriveCell(const LibertyLibrary *library,
const LibertyCell *cell,
const LibertyPort *from_port,
float *from_slews,
LibertyPort *to_port);
LibertyLibrary *library() const { return library_; }
void setLibrary(LibertyLibrary *library);
LibertyCell *cell() const { return cell_; }
void setCell(LibertyCell *cell);
LibertyPort *fromPort() const { return from_port_; }
void setFromPort(LibertyPort *from_port);
const LibertyPort *to_port);
const LibertyLibrary *library() const { return library_; }
void setLibrary(const LibertyLibrary *library);
const LibertyCell *cell() const { return cell_; }
void setCell(const LibertyCell *cell);
const LibertyPort *fromPort() const { return from_port_; }
void setFromPort(const LibertyPort *from_port);
float *fromSlews() { return from_slews_; }
void setFromSlews(float *from_slews);
LibertyPort *toPort() const { return to_port_; }
void setToPort(LibertyPort *to_port);
bool equal(InputDriveCell *drive) const;
const LibertyPort *toPort() const { return to_port_; }
void setToPort(const LibertyPort *to_port);
bool equal(const InputDriveCell *drive) const;
private:
LibertyLibrary *library_;
LibertyCell *cell_;
LibertyPort *from_port_;
const LibertyLibrary *library_;
const LibertyCell *cell_;
const LibertyPort *from_port_;
float from_slews_[RiseFall::index_count];
LibertyPort *to_port_;
const LibertyPort *to_port_;
};
} // namespace

11
include/sta/Liberty.hh
View File

@ -132,8 +132,7 @@ public:
const char *filename);
virtual ~LibertyLibrary();
LibertyCell *findLibertyCell(const char *name) const;
void findLibertyCellsMatching(PatternMatch *pattern,
LibertyCellSeq *cells);
LibertyCellSeq findLibertyCellsMatching(PatternMatch *pattern);
// Liberty cells that are buffers.
LibertyCellSeq *buffers();
@ -398,8 +397,7 @@ public:
LibertyLibrary *libertyLibrary() const { return liberty_library_; }
LibertyLibrary *libertyLibrary() { return liberty_library_; }
LibertyPort *findLibertyPort(const char *name) const;
void findLibertyPortsMatching(PatternMatch *pattern,
LibertyPortSeq *ports) const;
LibertyPortSeq findLibertyPortsMatching(PatternMatch *pattern) const;
bool hasInternalPorts() const { return has_internal_ports_; }
LibertyPgPort *findPgPort(const char *name) const;
size_t pgPortCount() const { return pg_port_map_.size(); }
@ -842,9 +840,8 @@ private:
friend class LibertyReader;
};
void
sortLibertyPortSet(LibertyPortSet *set,
LibertyPortSeq &ports);
LibertyPortSeq
sortByName(const LibertyPortSet *set);
class LibertyPortMemberIterator : public Iterator<LibertyPort*>
{

2
include/sta/LibertyClass.hh
View File

@ -151,8 +151,6 @@ public:
class LibertyPortPairLess
{
public:
bool operator()(const LibertyPortPair *pair1,
const LibertyPortPair *pair2) const;
bool operator()(const LibertyPortPair &pair1,
const LibertyPortPair &pair2) const;
};

11
include/sta/Map.hh
View File

@ -98,6 +98,17 @@ public:
delete iter.next();
}
void
deleteKeysContents()
{
for (auto key_value : this) {
KEY key = key_value.first;
VALUE value = key_value.second;
delete key;
delete value;
}
}
void
deleteArrayContents()
{

142
include/sta/Network.hh
View File

@ -31,7 +31,6 @@ class Report;
class PatternMatch;
class PinVisitor;
typedef Set<const Net*> ConstNetSet;
typedef Map<const char*, LibertyLibrary*, CharPtrLess> LibertyLibraryMap;
// Link network function returns top level instance.
// Return nullptr if link fails.
@ -103,20 +102,19 @@ public:
////////////////////////////////////////////////////////////////
// Library functions.
virtual const char *name(const Library *library) const = 0;
virtual ObjectId id(const Library *library) const = 0;
virtual LibraryIterator *libraryIterator() const = 0;
virtual LibertyLibraryIterator *libertyLibraryIterator() const = 0;
virtual Library *findLibrary(const char *name) = 0;
virtual LibertyLibrary *findLiberty(const char *name) = 0;
// Find liberty library by filename.
virtual LibertyLibrary *findLibertyFilename(const char *filename);
virtual const char *name(const Library *library) const = 0;
virtual Cell *findCell(const Library *library,
const char *name) const = 0;
// Search the design (non-liberty) libraries for cells matching pattern.
virtual void findCellsMatching(const Library *library,
const PatternMatch *pattern,
// Return value.
CellSeq *cells) const = 0;
virtual CellSeq findCellsMatching(const Library *library,
const PatternMatch *pattern) const = 0;
// Search liberty libraries for cell name.
virtual LibertyCell *findLibertyCell(const char *name) const;
virtual LibertyLibrary *makeLibertyLibrary(const char *name,
@ -136,6 +134,7 @@ public:
////////////////////////////////////////////////////////////////
// Cell functions.
virtual const char *name(const Cell *cell) const = 0;
virtual ObjectId id(const Cell *cell) const = 0;
virtual Library *library(const Cell *cell) const = 0;
virtual LibertyLibrary *libertyLibrary(const Cell *cell) const;
// Find the corresponding liberty cell.
@ -148,10 +147,8 @@ public:
// Name can be a simple, bundle, bus, or bus bit name.
virtual Port *findPort(const Cell *cell,
const char *name) const = 0;
virtual void findPortsMatching(const Cell *cell,
const PatternMatch *pattern,
// Return value.
PortSeq *ports) const = 0;
virtual PortSeq findPortsMatching(const Cell *cell,
const PatternMatch *pattern) const = 0;
virtual bool isLeaf(const Cell *cell) const = 0;
virtual CellPortIterator *portIterator(const Cell *cell) const = 0;
// Iterate over port bits (expanded buses).
@ -162,6 +159,7 @@ public:
////////////////////////////////////////////////////////////////
// Port functions
virtual const char *name(const Port *port) const = 0;
virtual ObjectId id(const Port *port) const = 0;
virtual Cell *cell(const Port *port) const = 0;
virtual LibertyPort *libertyPort(const Port *port) const = 0;
virtual PortDirection *direction(const Port *port) const = 0;
@ -193,6 +191,9 @@ public:
////////////////////////////////////////////////////////////////
// Instance functions
// Name local to containing cell/instance.
virtual const char *name(const Instance *instance) const = 0;
virtual ObjectId id(const Instance *instance) const = 0;
// Top level instance of the design (defined after link).
virtual Instance *topInstance() const = 0;
virtual bool isTopInstance(const Instance *inst) const;
@ -201,16 +202,10 @@ public:
Instance *findInstanceRelative(const Instance *inst,
const char *path_name) const;
// Default implementation uses linear search.
virtual void findInstancesMatching(const Instance *context,
const PatternMatch *pattern,
// Return value.
InstanceSeq *insts) const;
virtual void findInstancesHierMatching(const Instance *instance,
const PatternMatch *pattern,
// Return value.
InstanceSeq *insts) const;
// Name local to containing cell/instance.
virtual const char *name(const Instance *instance) const = 0;
virtual InstanceSeq findInstancesMatching(const Instance *context,
const PatternMatch *pattern) const;
virtual InstanceSeq findInstancesHierMatching(const Instance *instance,
const PatternMatch *pattern) const;
// Hierarchical path name.
virtual const char *pathName(const Instance *instance) const;
bool pathNameLess(const Instance *inst1,
@ -220,7 +215,7 @@ public:
// Path from instance up to top level (last in the sequence).
void path(const Instance *inst,
// Return value.
ConstInstanceSeq &path) const;
InstanceSeq &path) const;
virtual Cell *cell(const Instance *instance) const = 0;
virtual const char *cellName(const Instance *instance) const;
virtual LibertyLibrary *libertyLibrary(const Instance *instance) const;
@ -232,8 +227,8 @@ public:
const char *name) const = 0;
virtual void findChildrenMatching(const Instance *parent,
const PatternMatch *pattern,
// Return value.
InstanceSeq *insts) const;
// Return value.
InstanceSeq &matches) const;
// Is inst inside of hier_inst?
bool isInside(const Instance *inst,
const Instance *hier_inst) const;
@ -260,6 +255,9 @@ public:
////////////////////////////////////////////////////////////////
// Pin functions
// Name is instance_name/port_name (the same as path name).
virtual const char *name(const Pin *pin) const;
virtual ObjectId id(const Pin *pin) const = 0;
virtual Pin *findPin(const char *path_name) const;
virtual Pin *findPin(const Instance *instance,
const char *port_name) const = 0;
@ -271,18 +269,12 @@ public:
Pin *findPinRelative(const Instance *inst,
const char *path_name) const;
// Default implementation uses linear search.
virtual void findPinsMatching(const Instance *instance,
const PatternMatch *pattern,
// Return value.
PinSeq *pins) const;
virtual PinSeq findPinsMatching(const Instance *instance,
const PatternMatch *pattern) const;
// Traverse the hierarchy from instance down and find pins matching
// pattern of the form instance_name/port_name.
virtual void findPinsHierMatching(const Instance *instance,
const PatternMatch *pattern,
// Return value.
PinSeq *pins) const;
// Name is instance_name/port_name (the same as path name).
virtual const char *name(const Pin *pin) const;
virtual PinSeq findPinsHierMatching(const Instance *instance,
const PatternMatch *pattern) const;
virtual const char *portName(const Pin *pin) const;
// Path name is instance_name/port_name.
virtual const char *pathName(const Pin *pin) const;
@ -317,7 +309,7 @@ public:
// and child nets it is hierarchically connected to (port, leaf and
// hierarchical pins).
virtual PinConnectedPinIterator *connectedPinIterator(const Pin *pin) const;
virtual void visitConnectedPins(Pin *pin,
virtual void visitConnectedPins(const Pin *pin,
PinVisitor &visitor) const;
// Find driver pins for the net connected to pin.
@ -344,6 +336,7 @@ public:
// Terminal functions
// Name is instance_name/port_name (the same as path name).
virtual const char *name(const Term *term) const;
virtual ObjectId id(const Term *term) const = 0;
virtual const char *portName(const Term *term) const;
// Path name is instance_name/port_name (pin name).
virtual const char *pathName(const Term *term) const;
@ -352,28 +345,25 @@ public:
////////////////////////////////////////////////////////////////
// Net functions
virtual const char *name(const Net *net) const = 0; // no hierarchy prefix
virtual ObjectId id(const Net *net) const = 0;
virtual Net *findNet(const char *path_name) const;
// Find net relative to hierarchical instance.
Net *findNetRelative(const Instance *inst,
const char *path_name) const;
// Default implementation uses linear search.
virtual void findNetsMatching(const Instance *context,
const PatternMatch *pattern,
// Return value.
NetSeq *nets) const;
virtual NetSeq findNetsMatching(const Instance *context,
const PatternMatch *pattern) const;
virtual Net *findNet(const Instance *instance,
const char *net_name) const = 0;
// Traverse the hierarchy from instance down and find nets matching
// pattern of the form instance_name/net_name.
virtual void findNetsHierMatching(const Instance *instance,
const PatternMatch *pattern,
// Return value.
NetSeq *nets) const;
virtual NetSeq findNetsHierMatching(const Instance *instance,
const PatternMatch *pattern) const;
// Primitive used by findNetsMatching.
virtual void findInstNetsMatching(const Instance *instance,
const PatternMatch *pattern,
// Return value.
NetSeq *nets) const = 0;
virtual const char *name(const Net *net) const = 0; // no hierarchy prefix
const PatternMatch *pattern,
NetSeq &matches) const = 0;
virtual const char *pathName(const Net *net) const;
bool pathNameLess(const Net *net1,
const Net *net2) const;
@ -390,7 +380,7 @@ public:
virtual bool isConnected(const Net *net1,
const Net *net2) const;
virtual Net *highestNetAbove(Net *net) const;
virtual Net *highestConnectedNet(Net *net) const;
virtual const Net *highestConnectedNet(Net *net) const;
virtual void connectedNets(Net *net,
NetSet *nets) const;
virtual void connectedNets(const Pin *pin,
@ -445,35 +435,45 @@ protected:
void findInstancesMatching1(const Instance *context,
size_t context_name_length,
const PatternMatch *pattern,
// Return value.
InstanceSeq *insts) const;
InstanceSeq &insts) const;
void findInstancesHierMatching1(const Instance *instance,
const PatternMatch *pattern,
InstanceSeq &matches) const;
void findNetsMatching(const Instance *context,
const PatternMatch *pattern,
NetSeq &matches) const;
void findNetsHierMatching(const Instance *instance,
const PatternMatch *pattern,
NetSeq &matches) const;
void findPinsHierMatching(const Instance *instance,
const PatternMatch *pattern,
// Return value.
PinSeq &matches) const;
bool isConnected(const Net *net,
const Pin *pin,
ConstNetSet &nets) const;
NetSet &nets) const;
bool isConnected(const Net *net1,
const Net *net2,
ConstNetSet &nets) const;
NetSet &nets) const;
int hierarchyLevel(const Net *net) const;
virtual void visitConnectedPins(const Net *net,
PinVisitor &visitor,
ConstNetSet &visited_nets) const;
NetSet &visited_nets) const;
// Default implementation uses linear search.
virtual void findInstPinsMatching(const Instance *instance,
const PatternMatch *pattern,
// Return value.
PinSeq *pins) const;
const PatternMatch *pattern,
// Return value.
PinSeq &matches) const;
void findInstPinsHierMatching(const Instance *parent,
const PatternMatch *pattern,
// Return value.
PinSeq *pins) const;
const PatternMatch *pattern,
// Return value.
PinSeq &matches) const;
// findNet using linear search.
Net *findNetLinear(const Instance *instance,
const char *net_name) const;
// findNetsMatching using linear search.
void findNetsMatchingLinear(const Instance *instance,
const PatternMatch *pattern,
// Return value.
NetSeq *nets) const;
NetSeq findNetsMatchingLinear(const Instance *instance,
const PatternMatch *pattern) const;
// Connect/disconnect net/pins should clear the net->drvrs map.
// Incrementally maintaining the map is expensive because
// nets may be connected across hierarchy levels.
@ -588,7 +588,7 @@ public:
ConstantPinIterator() {}
virtual ~ConstantPinIterator() {}
virtual bool hasNext() = 0;
virtual void next(Pin *&pin,
virtual void next(const Pin *&pin,
LogicValue &value) = 0;
};
@ -601,7 +601,7 @@ public:
NetSet &one_nets);
~NetworkConstantPinIterator();
virtual bool hasNext();
virtual void next(Pin *&pin, LogicValue &value);
virtual void next(const Pin *&pin, LogicValue &value);
private:
void findConstantPins(NetSet &nets,
@ -619,29 +619,29 @@ class HierPinThruVisitor
public:
HierPinThruVisitor() {}
virtual ~HierPinThruVisitor() {}
virtual void visit(Pin *drvr,
Pin *load) = 0;
virtual void visit(const Pin *drvr,
const Pin *load) = 0;
};
class PinVisitor
{
public:
virtual ~PinVisitor() {}
virtual void operator()(Pin *pin) = 0;
virtual void operator()(const Pin *pin) = 0;
};
class FindNetDrvrLoads : public PinVisitor
{
public:
FindNetDrvrLoads(Pin *drvr_pin,
FindNetDrvrLoads(const Pin *drvr_pin,
PinSet &visited_drvrs,
PinSeq &loads,
PinSeq &drvrs,
const Network *network);
virtual void operator()(Pin *pin);
virtual void operator()(const Pin *pin);
protected:
Pin *drvr_pin_;
const Pin *drvr_pin_;
PinSet &visited_drvrs_;
PinSeq &loads_;
PinSeq &drvrs_;
@ -654,7 +654,7 @@ visitDrvrLoadsThruHierPin(const Pin *hpin,
const Network *network,
HierPinThruVisitor *visitor);
void
visitDrvrLoadsThruNet(Net *net,
visitDrvrLoadsThruNet(const Net *net,
const Network *network,
HierPinThruVisitor *visitor);

133
include/sta/NetworkClass.hh
View File

@ -16,6 +16,7 @@
#pragma once
#include <cstdint>
#include "Set.hh"
#include "Vector.hh"
#include "Iterator.hh"
@ -40,40 +41,130 @@ class LibertyLibrary;
typedef Iterator<Library*> LibraryIterator;
typedef Iterator<LibertyLibrary*> LibertyLibraryIterator;
typedef Vector<Cell*> CellSeq;
typedef Set<Cell*> CellSet;
typedef Vector<Port*> PortSeq;
typedef Set<Port*> PortSet;
typedef Vector<const Port*> PortSeq;
typedef Iterator<Port*> CellPortIterator;
typedef Iterator<Port*> CellPortBitIterator;
typedef Iterator<Port*> PortMemberIterator;
typedef std::pair<Port*, Port*> PortPair;
typedef Vector<Pin*> PinSeq;
typedef Vector<const Pin*> ConstPinSeq;
typedef Vector<Instance*> InstanceSeq;
typedef Vector<const Instance*> ConstInstanceSeq;
typedef Vector<Net*> NetSeq;
typedef Set<Pin*> PinSet;
typedef Set<Instance*> InstanceSet;
typedef Set<Net*> NetSet;
typedef Vector<const Pin*> PinSeq;
typedef Vector<const Instance*> InstanceSeq;
typedef Vector<const Net*> NetSeq;
typedef Iterator<Instance*> InstanceChildIterator;
typedef Iterator<Pin*> InstancePinIterator;
typedef Iterator<Net*> InstanceNetIterator;
typedef Iterator<Instance*> LeafInstanceIterator;
typedef Iterator<Net*> NetIterator;
typedef Iterator<Pin*> NetPinIterator;
typedef Iterator<const Pin*> NetPinIterator;
typedef Iterator<Term*> NetTermIterator;
typedef Iterator<Pin*> ConnectedPinIterator;
typedef Iterator<const Pin*> ConnectedPinIterator;
typedef ConnectedPinIterator NetConnectedPinIterator;
typedef ConnectedPinIterator PinConnectedPinIterator;
class PortPairLess
{
public:
bool operator()(const PortPair *pair1,
const PortPair *pair2) const;
};
typedef uint32_t ObjectId;
enum class LogicValue : unsigned { zero, one, unknown, rise, fall };
class CellIdLess
{
public:
CellIdLess(const Network *network);
bool operator()(const Cell *cell1,
const Cell *cell2) const;
private:
const Network *network_;
};
class PortIdLess
{
public:
PortIdLess(const Network *network);
bool operator()(const Port *port1,
const Port *port2) const;
private:
const Network *network_;
};
class InstanceIdLess
{
public:
InstanceIdLess(const Network *network);
bool operator()(const Instance *inst1,
const Instance *inst2) const;
private:
const Network *network_;
};
class PinIdLess
{
public:
PinIdLess(const Network *network);
bool operator()(const Pin *pin1,
const Pin *pin2) const;
private:
const Network *network_;
};
class PinIdHash
{
public:
PinIdHash(const Network *network);
size_t operator()(const Pin *pin) const;
private:
const Network *network_;
};
class NetIdLess
{
public:
NetIdLess(const Network *network);
bool operator()(const Net *net1,
const Net *net2) const;
private:
const Network *network_;
};
////////////////////////////////////////////////////////////////
class CellSet : public Set<const Cell*, CellIdLess>
{
public:
CellSet(const Network *network);
};
class PortSet : public Set<const Port*, PortIdLess>
{
public:
PortSet(const Network *network);
};
class InstanceSet : public Set<const Instance*, InstanceIdLess>
{
public:
InstanceSet();
InstanceSet(const Network *network);
static int compare(const InstanceSet *set1,
const InstanceSet *set2,
const Network *network);
};
class PinSet : public Set<const Pin*, PinIdLess>
{
public:
PinSet();
PinSet(const Network *network);
static int compare(const PinSet *set1,
const PinSet *set2,
const Network *network);
};
class NetSet : public Set<const Net*, NetIdLess>
{
public:
NetSet();
NetSet(const Network *network);
static int compare(const NetSet *set1,
const NetSet *set2,
const Network *network);
};
} // namespace

30
include/sta/NetworkCmp.hh
View File

@ -21,7 +21,7 @@
namespace sta {
// Comparison operators for sorting network objects.
// Comparison operators for network objects.
class PortNameLess
{
@ -67,21 +67,17 @@ private:
const Network *network_;
};
void
sortPinSet(PinSet *set,
const Network *network,
PinSeq &pins);
void
sortPortSet(PortSet *set,
const Network *network,
PortSeq &ports);
void
sortInstanceSet(InstanceSet *set,
const Network *network,
InstanceSeq &insts);
void
sortNetSet(NetSet *set,
const Network *network,
NetSeq &nets);
PinSeq
sortByPathName(const PinSet *set,
const Network *network);
PortSeq
sortByName(const PortSet *set,
const Network *network);
InstanceSeq
sortByPathName(InstanceSet *set,
const Network *network);
NetSeq
sortByPathName(NetSet *set,
const Network *network);
} // namespace

26
include/sta/NullParasitics.hh
View File

@ -47,23 +47,31 @@ public:
virtual Parasitic *makePiElmore(const Pin *drvr_pin,
const RiseFall *rf,
const ParasiticAnalysisPt *ap,
float c2, float rpi, float c1);
virtual bool isPiElmore(Parasitic *parasitic) const;
float c2,
float rpi,
float c1);
virtual bool isPiElmore(const Parasitic *parasitic) const;
virtual bool
isReducedParasiticNetwork(Parasitic *parasitic) const;
isReducedParasiticNetwork(const Parasitic *parasitic) const;
virtual void setIsReducedParasiticNetwork(Parasitic *parasitic,
bool is_reduced);
virtual void piModel(Parasitic *parasitic, float &c2, float &rpi,
virtual void piModel(const Parasitic *parasitic,
float &c2,
float &rpi,
float &c1) const;
virtual void setPiModel(Parasitic *parasitic, float c2, float rpi,
virtual void setPiModel(Parasitic *parasitic,
float c2,
float rpi,
float c1);
virtual void findElmore(Parasitic *parasitic, const Pin *load_pin,
float &elmore, bool &exists) const;
virtual void findElmore(const Parasitic *parasitic,
const Pin *load_pin,
float &elmore,
bool &exists) const;
virtual void setElmore(Parasitic *parasitic, const Pin *load_pin,
float elmore);
virtual bool isPiModel(Parasitic* parasitic) const;
virtual bool isPiPoleResidue(Parasitic* parasitic) const;
virtual bool isPiModel(const Parasitic* parasitic) const;
virtual bool isPiPoleResidue(const Parasitic* parasitic) const;
virtual Parasitic *
findPiPoleResidue(const Pin *drvr_pin,
const RiseFall *rf,

14
include/sta/Parasitics.hh
View File

@ -64,7 +64,7 @@ public:
const ParasiticAnalysisPt *ap) = 0;
virtual void deleteDrvrReducedParasitics(const Pin *drvr_pin) = 0;
virtual bool isReducedParasiticNetwork(Parasitic *parasitic) const = 0;
virtual bool isReducedParasiticNetwork(const Parasitic *parasitic) const = 0;
// Flag this parasitic as reduced from a parasitic network.
virtual void setIsReducedParasiticNetwork(Parasitic *parasitic,
bool is_reduced) = 0;
@ -76,7 +76,7 @@ public:
// Pi model driver load with elmore delays to load pins (RSPF).
// This follows the SPEF documentation of c2/c1, with c2 being the
// capacitor on the driver pin.
virtual bool isPiElmore(Parasitic *parasitic) const = 0;
virtual bool isPiElmore(const Parasitic *parasitic) const = 0;
virtual Parasitic *findPiElmore(const Pin *drvr_pin,
const RiseFall *rf,
const ParasiticAnalysisPt *ap) const = 0;
@ -89,8 +89,8 @@ public:
////////////////////////////////////////////////////////////////
// Pi models are common to PiElmore and PiPoleResidue.
virtual bool isPiModel(Parasitic *parasitic) const = 0;
virtual void piModel(Parasitic *parasitic,
virtual bool isPiModel(const Parasitic *parasitic) const = 0;
virtual void piModel(const Parasitic *parasitic,
float &c2,
float &rpi,
float &c1) const = 0;
@ -103,7 +103,7 @@ public:
////////////////////////////////////////////////////////////////
// Elmore driver to load delay.
// Common to LumpedElmore and PiElmore parasitics.
virtual void findElmore(Parasitic *parasitic,
virtual void findElmore(const Parasitic *parasitic,
const Pin *load_pin,
float &elmore,
bool &exists) const = 0;
@ -114,7 +114,7 @@ public:
////////////////////////////////////////////////////////////////
// Pi model driver load with pole/residue interconnect model to load pins.
virtual bool isPiPoleResidue(Parasitic* parasitic) const = 0;
virtual bool isPiPoleResidue(const Parasitic* parasitic) const = 0;
virtual Parasitic *findPiPoleResidue(const Pin *drvr_pin,
const RiseFall *rf,
const ParasiticAnalysisPt *ap) const=0;
@ -310,7 +310,7 @@ protected:
float fanout,
const ParasiticAnalysisPt *ap);
Net *findParasiticNet(const Pin *pin) const;
const Net *findParasiticNet(const Pin *pin) const;
};
// Managed by the Corner class.

4
include/sta/Path.hh
View File

@ -47,8 +47,8 @@ public:
virtual Tag *tag(const StaState *sta) const = 0;
virtual TagIndex tagIndex(const StaState *sta) const;
virtual ClkInfo *clkInfo(const StaState *sta) const;
virtual ClockEdge *clkEdge(const StaState *sta) const;
virtual Clock *clock(const StaState *sta) const;
virtual const ClockEdge *clkEdge(const StaState *sta) const;
virtual const Clock *clock(const StaState *sta) const;
virtual bool isClock(const StaState *sta) const;
virtual const RiseFall *transition(const StaState *sta) const = 0;
virtual int rfIndex(const StaState *sta) const;

16
include/sta/PathEnd.hh
View File

@ -104,7 +104,7 @@ public:
virtual Slack slack(const StaState *sta) const = 0;
virtual Slack slackNoCrpr(const StaState *sta) const = 0;
virtual Arrival borrow(const StaState *sta) const;
ClockEdge *sourceClkEdge(const StaState *sta) const;
const ClockEdge *sourceClkEdge(const StaState *sta) const;
// Time offset for the path start so the path begins in the correct
// source cycle.
virtual float sourceClkOffset(const StaState *sta) const = 0;
@ -112,8 +112,8 @@ public:
virtual Delay sourceClkInsertionDelay(const StaState *sta) const;
virtual PathVertex *targetClkPath();
virtual const PathVertex *targetClkPath() const;
virtual Clock *targetClk(const StaState *sta) const;
virtual ClockEdge *targetClkEdge(const StaState *sta) const;
virtual const Clock *targetClk(const StaState *sta) const;
virtual const ClockEdge *targetClkEdge(const StaState *sta) const;
const RiseFall *targetClkEndTrans(const StaState *sta) const;
// Target clock with cycle accounting and source clock offsets.
virtual float targetClkTime(const StaState *sta) const;
@ -232,8 +232,8 @@ public:
virtual float sourceClkOffset(const StaState *sta) const;
virtual Delay sourceClkLatency(const StaState *sta) const;
virtual Delay sourceClkInsertionDelay(const StaState *sta) const;
virtual Clock *targetClk(const StaState *sta) const;
virtual ClockEdge *targetClkEdge(const StaState *sta) const;
virtual const Clock *targetClk(const StaState *sta) const;
virtual const ClockEdge *targetClkEdge(const StaState *sta) const;
virtual PathVertex *targetClkPath();
virtual const PathVertex *targetClkPath() const;
virtual float targetClkTime(const StaState *sta) const;
@ -420,7 +420,7 @@ public:
virtual bool isOutputDelay() const { return true; }
virtual ArcDelay margin(const StaState *sta) const;
virtual TimingRole *checkRole(const StaState *sta) const;
virtual ClockEdge *targetClkEdge(const StaState *sta) const;
virtual const ClockEdge *targetClkEdge(const StaState *sta) const;
virtual Arrival targetClkArrivalNoCrpr(const StaState *sta) const;
virtual Delay targetClkDelay(const StaState *sta) const;
virtual Delay targetClkInsertionDelay(const StaState *sta) const;
@ -496,7 +496,7 @@ public:
virtual void reportShort(ReportPath *report) const;
virtual void reportFull(ReportPath *report) const;
virtual bool isDataCheck() const { return true; }
virtual ClockEdge *targetClkEdge(const StaState *sta) const;
virtual const ClockEdge *targetClkEdge(const StaState *sta) const;
virtual TimingRole *checkRole(const StaState *sta) const;
virtual ArcDelay margin(const StaState *sta) const;
virtual int exceptPathCmp(const PathEnd *path_end,
@ -553,7 +553,7 @@ public:
virtual PathDelay *pathDelay() const { return path_delay_; }
virtual ArcDelay margin(const StaState *sta) const;
virtual float sourceClkOffset(const StaState *sta) const;
virtual ClockEdge *targetClkEdge(const StaState *sta) const;
virtual const ClockEdge *targetClkEdge(const StaState *sta) const;
virtual float targetClkTime(const StaState *sta) const;
virtual Arrival targetClkArrivalNoCrpr(const StaState *sta) const;
virtual float targetClkOffset(const StaState *sta) const;

27
include/sta/PinPair.hh
View File

@ -22,28 +22,41 @@
namespace sta {
typedef std::pair<Pin*, Pin*> PinPair;
typedef std::pair<const Pin*, const Pin*> PinPair;
class PinPairLess
{
public:
bool operator()(const PinPair *pair1,
const PinPair *pair2) const;
PinPairLess(const Network *network);
bool operator()(const PinPair &pair1,
const PinPair &pair2) const;
private:
const Network *network_;
};
typedef Set<PinPair*, PinPairLess> PinPairSet;
class PinPairSet : public Set<PinPair, PinPairLess>
{
public:
PinPairSet(const Network *network);
};
class PinPairHash
{
public:
size_t operator()(const PinPair *pair) const;
PinPairHash(const Network *network);
size_t operator()(const PinPair &pair) const;
private:
const Network *network_;
};
class PinPairEqual
{
public:
bool operator()(const PinPair *pair1,
const PinPair *pair2) const;
bool operator()(const PinPair &pair1,
const PinPair &pair2) const;
};
} // namespace

33
include/sta/PortDelay.hh
View File

@ -30,27 +30,28 @@ class PortDelay
{
public:
RiseFallMinMax *delays() { return &delays_; }
Pin *pin() const { return pin_; }
const Pin *pin() const { return pin_; }
PinSet &leafPins() { return leaf_pins_; }
Clock *clock() const;
ClockEdge *clkEdge() const { return clk_edge_; }
const ClockEdge *clkEdge() const { return clk_edge_; }
bool sourceLatencyIncluded() const;
void setSourceLatencyIncluded(bool included);
bool networkLatencyIncluded() const;
void setNetworkLatencyIncluded(bool included);
Pin *refPin() const { return ref_pin_; }
const Pin *refPin() const { return ref_pin_; }
void setRefPin(const Pin *ref_pin);
RiseFall *refTransition() const;
protected:
PortDelay(Pin *pin,
ClockEdge *clk_edge,
Pin *ref_pin);
PortDelay(const Pin *pin,
const ClockEdge *clk_edge,
const Network *network);
Pin *pin_;
ClockEdge *clk_edge_;
const Pin *pin_;
const ClockEdge *clk_edge_;
bool source_latency_included_;
bool network_latency_included_;
Pin *ref_pin_;
const Pin *ref_pin_;
RiseFallMinMax delays_;
PinSet leaf_pins_;
};
@ -61,11 +62,10 @@ public:
int index() const { return index_; }
protected:
InputDelay(Pin *pin,
ClockEdge *clk_edge,
Pin *ref_pin,
InputDelay(const Pin *pin,
const ClockEdge *clk_edge,
int index,
Network *network);
const Network *network);
private:
int index_;
@ -78,10 +78,9 @@ class OutputDelay : public PortDelay
public:
protected:
OutputDelay(Pin *pin,
ClockEdge *clk_edge,
Pin *ref_pin,
Network *network);
OutputDelay(const Pin *pin,
const ClockEdge *clk_edge,
const Network *network);
private:
friend class Sdc;

12
include/sta/PortExtCap.hh
View File

@ -30,12 +30,13 @@ typedef MinMaxIntValues FanoutValues;
class PortExtCap
{
public:
explicit PortExtCap(Port *port);
Port *port() { return port_; }
PortExtCap(const Port *port);
const Port *port() { return port_; }
void pinCap(const RiseFall *rf,
const MinMax *min_max,
// Return values.
float &cap, bool &exists);
float &cap,
bool &exists);
RiseFallMinMax *pinCap() { return &pin_cap_; }
void setPinCap(float cap,
const RiseFall *rf,
@ -43,7 +44,8 @@ public:
void wireCap(const RiseFall *rf,
const MinMax *min_max,
// Return values.
float &cap, bool &exists);
float &cap,
bool &exists);
RiseFallMinMax *wireCap() { return &wire_cap_; }
void setWireCap(float cap,
const RiseFall *rf,
@ -57,7 +59,7 @@ public:
FanoutValues *fanout() { return &fanout_; }
private:
Port *port_;
const Port *port_;
RiseFallMinMax pin_cap_;
RiseFallMinMax wire_cap_;
FanoutValues fanout_;

61
include/sta/Property.hh
View File

@ -54,18 +54,19 @@ public:
PropertyValue(float value,
const Unit *unit);
explicit PropertyValue(bool value);
PropertyValue(Library *value);
PropertyValue(Cell *value);
PropertyValue(Port *value);
PropertyValue(LibertyLibrary *value);
PropertyValue(LibertyCell *value);
PropertyValue(LibertyPort *value);
PropertyValue(Instance *value);
PropertyValue(Pin *value);
PropertyValue(const Library *value);
PropertyValue(const Cell *value);
PropertyValue(const Port *value);
PropertyValue(const LibertyLibrary *value);
PropertyValue(const LibertyCell *value);
PropertyValue(const LibertyPort *value);
PropertyValue(const Instance *value);
PropertyValue(const Pin *value);
PropertyValue(PinSeq *value);
PropertyValue(PinSet *value);
PropertyValue(Net *value);
PropertyValue(Clock *value);
PropertyValue(const PinSet &value);
PropertyValue(const Net *value);
PropertyValue(const Clock *value);
PropertyValue(ClockSeq *value);
PropertyValue(ClockSet *value);
PropertyValue(PathRefSeq *value);
@ -81,17 +82,17 @@ public:
const char *stringValue() const { return string_; }
float floatValue() const { return float_; }
bool boolValue() const { return bool_; }
LibertyLibrary *libertyLibrary() const { return liberty_library_; }
LibertyCell *libertyCell() const { return liberty_cell_; }
LibertyPort *libertyPort() const { return liberty_port_; }
Library *library() const { return library_; }
Cell *cell() const { return cell_; }
Port *port() const { return port_; }
Instance *instance() const { return inst_; }
Pin *pin() const { return pin_; }
const LibertyLibrary *libertyLibrary() const { return liberty_library_; }
const LibertyCell *libertyCell() const { return liberty_cell_; }
const LibertyPort *libertyPort() const { return liberty_port_; }
const Library *library() const { return library_; }
const Cell *cell() const { return cell_; }
const Port *port() const { return port_; }
const Instance *instance() const { return inst_; }
const Pin *pin() const { return pin_; }
PinSeq *pins() const { return pins_; }
Net *net() const { return net_; }
Clock *clock() const { return clk_; }
const Net *net() const { return net_; }
const Clock *clock() const { return clk_; }
ClockSeq *clocks() const { return clks_; }
PathRefSeq *pathRefs() const { return path_refs_; }
PwrActivity pwrActivity() const { return pwr_activity_; }
@ -107,17 +108,17 @@ private:
const char *string_;
float float_;
bool bool_;
Library *library_;
Cell *cell_;
Port *port_;
LibertyLibrary *liberty_library_;
LibertyCell *liberty_cell_;
LibertyPort *liberty_port_;
Instance *inst_;
Pin *pin_;
const Library *library_;
const Cell *cell_;
const Port *port_;
const LibertyLibrary *liberty_library_;
const LibertyCell *liberty_cell_;
const LibertyPort *liberty_port_;
const Instance *inst_;
const Pin *pin_;
PinSeq *pins_;
Net *net_;
Clock *clk_;
const Net *net_;
const Clock *clk_;
ClockSeq *clks_;
PathRefSeq *path_refs_;
PwrActivity pwr_activity_;

380
include/sta/Sdc.hh
View File

@ -32,6 +32,7 @@
#include "Clock.hh"
#include "DataCheck.hh"
#include "CycleAccting.hh"
#include "ExceptionPath.hh"
namespace sta {
@ -50,24 +51,33 @@ class FindNetCaps;
class ClkHpinDisable;
class FindClkHpinDisables;
class Corner;
class GroupPathIterator;
class ClockPinIterator;
class ClockIterator;
using std::vector;
typedef std::pair<const Pin*, const Clock*> PinClockPair;
class ClockInsertionPinClkLess
class ClockInsertionkLess
{
public:
ClockInsertionkLess(const Network *network);
bool operator()(const ClockInsertion *insert1,
const ClockInsertion *insert2) const;
private:
const Network *network_;
};
class ClockLatencyPinClkLess
class ClockLatencyLess
{
public:
ClockLatencyLess(const Network *network);
bool operator()(const ClockLatency *latency1,
const ClockLatency *latency2) const;
private:
const Network *network_;
};
// This is symmetric with respect to the clocks
@ -94,53 +104,55 @@ protected:
class ClkHpinDisableLess
{
public:
ClkHpinDisableLess(const Network *network);
bool operator()(const ClkHpinDisable *disable1,
const ClkHpinDisable *disable2) const;
private:
const Network *network_;
};
typedef Map<const char*,Clock*, CharPtrLess> ClockNameMap;
typedef UnorderedMap<const Pin*, ClockSet*> ClockPinMap;
typedef UnorderedMap<const Pin*, ClockSet*, PinIdHash> ClockPinMap;
typedef Set<InputDelay*> InputDelaySet;
typedef Map<const Pin*,InputDelaySet*> InputDelaysPinMap;
typedef Map<const Pin*, InputDelaySet*, PinIdLess> InputDelaysPinMap;
typedef Set<OutputDelay*> OutputDelaySet;
typedef Map<const Pin*,OutputDelaySet*> OutputDelaysPinMap;
typedef Set<Instance*> InstanceSet;
typedef Map<const Pin*,OutputDelaySet*, PinIdLess> OutputDelaysPinMap;
typedef UnorderedMap<const Pin*,ExceptionPathSet*> PinExceptionsMap;
typedef Map<const Clock*,ExceptionPathSet*> ClockExceptionsMap;
typedef Map<const Instance*,ExceptionPathSet*> InstanceExceptionsMap;
typedef Map<const Net*,ExceptionPathSet*> NetExceptionsMap;
typedef UnorderedMap<const EdgePins*,ExceptionPathSet*,
typedef UnorderedMap<EdgePins, ExceptionPathSet*,
PinPairHash, PinPairEqual> EdgeExceptionsMap;
typedef Vector<ExceptionThru*> ExceptionThruSeq;
typedef Map<const Port*,InputDrive*> InputDriveMap;
typedef Map<int, ExceptionPathSet*, std::less<int> > ExceptionPathPtHash;
typedef Set<ClockLatency*, ClockLatencyPinClkLess> ClockLatencies;
typedef Set<ClockLatency*, ClockLatencyLess> ClockLatencies;
typedef Map<const Pin*, ClockUncertainties*> PinClockUncertaintyMap;
typedef Set<InterClockUncertainty*,
InterClockUncertaintyLess> InterClockUncertaintySet;
typedef Set<InterClockUncertainty*, InterClockUncertaintyLess> InterClockUncertaintySet;
typedef Map<const Clock*, ClockGatingCheck*> ClockGatingCheckMap;
typedef Map<const Instance*, ClockGatingCheck*> InstanceClockGatingCheckMap;
typedef Map<const Pin*, ClockGatingCheck*> PinClockGatingCheckMap;
typedef Set<ClockInsertion*, ClockInsertionPinClkLess> ClockInsertions;
typedef Set<ClockInsertion*, ClockInsertionkLess> ClockInsertions;
typedef Map<const Pin*, float> PinLatchBorrowLimitMap;
typedef Map<const Instance*, float> InstLatchBorrowLimitMap;
typedef Map<const Clock*, float> ClockLatchBorrowLimitMap;
typedef Set<DataCheck*, DataCheckLess> DataCheckSet;
typedef Map<const Pin*, DataCheckSet*> DataChecksMap;
typedef Map<Port*, PortExtCap*> PortExtCapMap;
typedef Map<Net*, MinMaxFloatValues> NetResistanceMap;
typedef Map<Port*, MinMaxFloatValues> PortSlewLimitMap;
typedef Map<const Net*, MinMaxFloatValues> NetResistanceMap;
typedef Map<const Port*, MinMaxFloatValues> PortSlewLimitMap;
typedef Map<const Pin*, MinMaxFloatValues> PinSlewLimitMap;
typedef Map<Cell*, MinMaxFloatValues> CellSlewLimitMap;
typedef Map<Cell*, MinMaxFloatValues> CellCapLimitMap;
typedef Map<Port*, MinMaxFloatValues> PortCapLimitMap;
typedef Map<Pin*, MinMaxFloatValues> PinCapLimitMap;
typedef Map<Port*, MinMaxFloatValues> PortFanoutLimitMap;
typedef Map<Cell*, MinMaxFloatValues> CellFanoutLimitMap;
typedef Map<Net*, MinMaxFloatValues> NetWireCapMap;
typedef Map<Pin*, MinMaxFloatValues*> PinWireCapMap;
typedef Map<Instance*, Pvt*> InstancePvtMap;
typedef Map<Edge*, ClockLatency*> EdgeClockLatencyMap;
typedef Map<const Cell*, MinMaxFloatValues> CellSlewLimitMap;
typedef Map<const Cell*, MinMaxFloatValues> CellCapLimitMap;
typedef Map<const Port*, MinMaxFloatValues> PortCapLimitMap;
typedef Map<const Pin*, MinMaxFloatValues> PinCapLimitMap;
typedef Map<const Port*, MinMaxFloatValues> PortFanoutLimitMap;
typedef Map<const Cell*, MinMaxFloatValues> CellFanoutLimitMap;
typedef Map<const Port*, PortExtCap*, PortIdLess> PortExtCapMap;
typedef Map<const Net*, MinMaxFloatValues, NetIdLess> NetWireCapMap;
typedef Map<const Pin*, MinMaxFloatValues*, PinIdLess> PinWireCapMap;
typedef Map<const Instance*, Pvt*> InstancePvtMap;
typedef Map<const Edge*, ClockLatency*> EdgeClockLatencyMap;
typedef Map<const Pin*, RiseFallValues*> PinMinPulseWidthMap;
typedef Map<const Clock*, RiseFallValues*> ClockMinPulseWidthMap;
typedef Map<const Instance*, RiseFallValues*> InstMinPulseWidthMap;
@ -152,16 +164,16 @@ typedef Map<const Clock*, ClockGroupsSet*> ClockGroupsClkMap;
typedef Map<const char*, ClockGroups*, CharPtrLess> ClockGroupsNameMap;
typedef Map<PinClockPair, ClockSense, PinClockPairLess> ClockSenseMap;
typedef Set<ClkHpinDisable*, ClkHpinDisableLess> ClkHpinDisables;
typedef Set<GroupPath*> GroupPathSet;
typedef Set<GroupPath*, ExceptionPathLess> GroupPathSet;
typedef Map<const char*, GroupPathSet*, CharPtrLess> GroupPathMap;
typedef Set<ClockPair, ClockPairLess> ClockPairSet;
void
findLeafLoadPins(Pin *pin,
findLeafLoadPins(const Pin *pin,
const Network *network,
PinSet *leaf_pins);
void
findLeafDriverPins(Pin *pin,
findLeafDriverPins(const Pin *pin,
const Network *network,
PinSet *leaf_pins);
@ -172,6 +184,7 @@ public:
~Sdc();
// Note that Search may reference a Filter exception removed by clear().
void clear();
void makeCornersAfter(Corners *corners);
// Return true if pin is referenced by any constraint.
bool isConstrained(const Pin *pin) const;
// Return true if inst is referenced by any constraint.
@ -182,7 +195,7 @@ public:
bool isConstrained(const Net *net) const;
// Build data structures for search.
void searchPreamble();
void deleteNetBefore(Net *net);
void deleteNetBefore(const Net *net);
// SWIG sdc interface.
AnalysisType analysisType() { return analysis_type_; }
@ -227,34 +240,36 @@ public:
static void moveDeratingFactors(Sdc *from,
Sdc *to);
void setInputSlew(Port *port, const RiseFallBoth *rf,
const MinMaxAll *min_max, float slew);
void setInputSlew(const Port *port,
const RiseFallBoth *rf,
const MinMaxAll *min_max,
float slew);
// Set the rise/fall drive resistance on design port.
void setDriveResistance(Port *port,
void setDriveResistance(const Port *port,
const RiseFallBoth *rf,
const MinMaxAll *min_max,
float res);
// Set the drive on design port using external cell timing arcs of
// cell driven by from_slews between from_port and to_port.
void setDriveCell(LibertyLibrary *library,
LibertyCell *cell,
Port *port,
LibertyPort *from_port,
void setDriveCell(const LibertyLibrary *library,
const LibertyCell *cell,
const Port *port,
const LibertyPort *from_port,
float *from_slews,
LibertyPort *to_port,
const LibertyPort *to_port,
const RiseFallBoth *rf,
const MinMaxAll *min_max);
void setLatchBorrowLimit(Pin *pin,
void setLatchBorrowLimit(const Pin *pin,
float limit);
void setLatchBorrowLimit(Instance *inst,
void setLatchBorrowLimit(const Instance *inst,
float limit);
void setLatchBorrowLimit(Clock *clk,
void setLatchBorrowLimit(const Clock *clk,
float limit);
// Return the latch borrow limit respecting precidence if multiple
// limits apply.
void latchBorrowLimit(Pin *data_pin,
Pin *enable_pin,
Clock *clk,
void latchBorrowLimit(const Pin *data_pin,
const Pin *enable_pin,
const Clock *clk,
// Return values.
float &limit,
bool &exists);
@ -442,7 +457,7 @@ public:
// Return values.
float &insertion,
bool &exists) const;
ClockInsertions *clockInsertions() { return clk_insertions_; }
const ClockInsertions &clockInsertions() const { return clk_insertions_; }
// Clock uncertainty.
virtual void setClockUncertainty(Pin *pin,
const SetupHoldAll *setup_hold,
@ -520,44 +535,47 @@ public:
const SetupHoldAll *setup_hold);
DataCheckSet *dataChecksFrom(const Pin *from) const;
DataCheckSet *dataChecksTo(const Pin *to) const;
void setInputDelay(Pin *pin,
void setInputDelay(const Pin *pin,
const RiseFallBoth *rf,
Clock *clk,
const Clock *clk,
const RiseFall *clk_rf,
Pin *ref_pin,
const Pin *ref_pin,
bool source_latency_included,
bool network_latency_included,
const MinMaxAll *min_max,
bool add, float delay);
void removeInputDelay(Pin *pin,
bool add,
float delay);
void removeInputDelay(const Pin *pin,
const RiseFallBoth *rf,
Clock *clk,
RiseFall *clk_rf,
MinMaxAll *min_max);
void setOutputDelay(Pin *pin,
const Clock *clk,
const RiseFall *clk_rf,
const MinMaxAll *min_max);
void setOutputDelay(const Pin *pin,
const RiseFallBoth *rf,
Clock *clk,
const Clock *clk,
const RiseFall *clk_tr,
Pin *ref_pin,
const Pin *ref_pin,
bool source_latency_included,
bool network_latency_included,
const MinMaxAll *min_max,
bool add, float delay);
void removeOutputDelay(Pin *pin,
RiseFallBoth *rf,
Clock *clk,
RiseFall *clk_rf,
MinMaxAll *min_max);
bool add,
float delay);
void removeOutputDelay(const Pin *pin,
const RiseFallBoth *rf,
const Clock *clk,
const RiseFall *clk_rf,
const MinMaxAll *min_max);
static void movePortDelays(Sdc *from,
Sdc *to);
// Set port external pin load (set_load -pin_load port).
void setPortExtPinCap(Port *port,
void setPortExtPinCap(const Port *port,
const RiseFall *rf,
const Corner *corner,
const MinMax *min_max,
float cap);
// Set port external wire load (set_load -wire port).
void setPortExtWireCap(Port *port,
void setPortExtWireCap(const Port *port,
bool subtract_pin_cap,
const RiseFall *rf,
const Corner *corner,
@ -565,18 +583,15 @@ public:
float cap);
static void movePortExtCaps(Sdc *from,
Sdc *to);
// Remove all "set_load" and "set_fanout_load" annotations.
void removeLoadCaps();
// Remove all "set_load net" annotations.
void removeNetLoadCaps();
void setNetWireCap(Net *net,
void setNetWireCap(const Net *net,
bool subtract_pin_cap,
const Corner *corner,
const MinMax *min_max,
float cap);
bool hasNetWireCap(Net *net) const;
bool hasNetWireCap(const Net *net) const;
// True if driver pin net has wire capacitance.
bool drvrPinHasWireCap(const Pin *pin);
bool drvrPinHasWireCap(const Pin *pin,
const Corner *corner);
// Net wire capacitance (set_load -wire net).
void drvrPinWireCap(const Pin *drvr_pin,
const Corner *corner,
@ -590,15 +605,16 @@ public:
const OperatingConditions *op_cond,
const Corner *corner,
const MinMax *min_max);
void setResistance(Net *net,
void setResistance(const Net *net,
const MinMaxAll *min_max,
float res);
void resistance(Net *net,
void resistance(const Net *net,
const MinMax *min_max,
float &res,
bool &exists);
NetResistanceMap *netResistances() { return &net_res_map_; }
void setPortExtFanout(Port *port,
NetResistanceMap &netResistances() { return net_res_map_; }
void setPortExtFanout(const Port *port,
const Corner *corner,
const MinMax *min_max,
int fanout);
// set_disable_timing cell [-from] [-to]
@ -628,7 +644,7 @@ public:
LibertyPort *from,
LibertyPort *to);
// set_disable_timing pin
void disable(Pin *pin);
void disable(const Pin *pin);
void removeDisable(Pin *pin);
// set_disable_timing [get_timing_arc -of_objects instance]]
void disable(Edge *edge);
@ -652,11 +668,11 @@ public:
bool isDisabled(Edge *edge);
bool isDisabled(TimingArcSet *arc_set) const;
DisabledCellPortsMap *disabledCellPorts();
DisabledInstancePortsMap *disabledInstancePorts();
PinSet *disabledPins() { return &disabled_pins_; }
PortSet *disabledPorts() { return &disabled_ports_; }
LibertyPortSet *disabledLibPorts() { return &disabled_lib_ports_; }
EdgeSet *disabledEdges() { return &disabled_edges_; }
const DisabledInstancePortsMap *disabledInstancePorts() const;
const PinSet *disabledPins() const { return &disabled_pins_; }
const PortSet *disabledPorts() const { return &disabled_ports_; }
const LibertyPortSet *disabledLibPorts() const { return &disabled_lib_ports_; }
const EdgeSet *disabledEdges() const { return &disabled_edges_; }
void disableClockGatingCheck(Instance *inst);
void disableClockGatingCheck(Pin *pin);
void removeDisableClockGatingCheck(Instance *inst);
@ -664,16 +680,18 @@ public:
bool isDisableClockGatingCheck(const Pin *pin);
bool isDisableClockGatingCheck(const Instance *inst);
// set_LogicValue::zero, set_LogicValue::one, set_logic_dc
void setLogicValue(Pin *pin,
void setLogicValue(const Pin *pin,
LogicValue value);
// set_case_analysis
void setCaseAnalysis(Pin *pin,
void setCaseAnalysis(const Pin *pin,
LogicValue value);
void removeCaseAnalysis(Pin *pin);
void removeCaseAnalysis(const Pin *pin);
void logicValue(const Pin *pin,
LogicValue &value,
bool &exists);
void caseLogicValue(const Pin *pin, LogicValue &value, bool &exists);
void caseLogicValue(const Pin *pin,
LogicValue &value,
bool &exists);
// Pin has set_case_analysis or set_logic constant value.
bool hasLogicValue(const Pin *pin);
// The from/thrus/to arguments passed into the following functions
@ -716,8 +734,8 @@ public:
ExceptionThruSeq *thrus,
ExceptionTo *to,
const char *comment);
GroupPathIterator *groupPathIterator();
bool isGroupPathName(const char *group_name);
GroupPathMap &groupPaths() { return group_path_map_; }
void addException(ExceptionPath *exception);
// The pin/clk/instance/net set arguments passed into the following
// functions that make exception from/thru/to's are owned by the
@ -741,9 +759,6 @@ public:
FilterPath *makeFilterPath(ExceptionFrom *from,
ExceptionThruSeq *thrus,
ExceptionTo *to);
Clock *findClock(const char *name) const;
virtual void findClocksMatching(PatternMatch *pattern,
ClockSeq *clks) const;
Wireload *wireload(const MinMax *min_max);
void setWireload(Wireload *wireload,
const MinMaxAll *min_max);
@ -803,17 +818,19 @@ public:
// STA interface.
InputDelaySet *refPinInputDelays(const Pin *ref_pin) const;
LogicValueMap *logicValues() { return &logic_value_map_; }
LogicValueMap *caseLogicValues() { return &case_value_map_; }
LogicValueMap &logicValues() { return logic_value_map_; }
LogicValueMap &caseLogicValues() { return case_value_map_; }
// Returns nullptr if set_operating_conditions has not been called.
OperatingConditions *operatingConditions(const MinMax *min_max);
// Instance specific process/voltage/temperature.
Pvt *pvt(Instance *inst, const MinMax *min_max) const;
const Pvt *pvt(Instance *inst, const MinMax *min_max) const;
// Pvt may be shared among multiple instances.
void setPvt(Instance *inst,
void setPvt(const Instance *inst,
const MinMaxAll *min_max,
Pvt *pvt);
const Pvt &pvt);
InputDrive *findInputDrive(Port *port);
Clock *findClock(const char *name) const;
virtual ClockSeq findClocksMatching(PatternMatch *pattern) const;
// True if pin is defined as a clock source (pin may be hierarchical).
bool isClock(const Pin *pin) const;
// True if pin is a clock source vertex.
@ -882,15 +899,17 @@ public:
const OutputDelaySet &outputDelays() const { return output_delays_; }
// Pin -> output delays.
const OutputDelaysPinMap &outputDelayPinMap() const { return output_delay_pin_map_; }
const OutputDelaysPinMap &outputDelaysPinMap() const { return output_delay_pin_map_; }
// Output delays on leaf_pin.
OutputDelaySet *outputDelaysLeafPin(const Pin *leaf_pin);
bool hasOutputDelay(const Pin *leaf_pin) const;
PortExtCap *portExtCap(Port *port) const;
bool hasPortExtCap(Port *port) const;
void portExtCap(Port *port,
PortExtCap *portExtCap(const Port *port,
const Corner *corner) const;
bool hasPortExtCap(const Port *port) const;
void portExtCap(const Port *port,
const RiseFall *rf,
const Corner *corner,
const MinMax *min_max,
// Return values.
float &pin_cap,
@ -899,8 +918,9 @@ public:
bool &has_wire_cap,
int &fanout,
bool &has_fanout) const;
float portExtCap(Port *port,
float portExtCap(const Port *port,
const RiseFall *rf,
const Corner *corner,
const MinMax *min_max) const;
// Connected total capacitance.
// pin_cap = pin capacitance + port external pin
@ -914,12 +934,14 @@ public:
float &wire_cap,
float &fanout,
bool &has_set_load) const;
void portExtFanout(Port *port,
void portExtFanout(const Port *port,
const Corner *corner,
const MinMax *min_max,
// Return values.
int &fanout,
bool &exists);
int portExtFanout(Port *port,
const Corner *corner,
const MinMax *min_max);
// Return true if search should proceed from pin/clk (no false paths
// start at pin/clk). When thru is true, consider -thru exceptions
@ -984,7 +1006,7 @@ public:
const RiseFall *rf,
const MinMax *min_max) const;
bool isPathDelayInternalStartpoint(const Pin *pin) const;
PinSet *pathDelayInternalStartpoints() const;
const PinSet &pathDelayInternalStartpoints() const;
bool isPathDelayInternalEndpoint(const Pin *pin) const;
ExceptionPathSet *exceptions() { return &exceptions_; }
void deleteExceptions();
@ -995,12 +1017,12 @@ public:
void removeGraphAnnotations();
// Network edit before/after methods.
void disconnectPinBefore(Pin *pin);
void connectPinAfter(Pin *pin);
void clkHpinDisablesChanged(Pin *pin);
void makeClkHpinDisable(Clock *clk,
Pin *drvr,
Pin *load);
void disconnectPinBefore(const Pin *pin);
void connectPinAfter(const Pin *pin);
void clkHpinDisablesChanged(const Pin *pin);
void makeClkHpinDisable(const Clock *clk,
const Pin *drvr,
const Pin *load);
void ensureClkHpinDisables();
bool bidirectDrvrSlewFromLoad(const Pin *pin) const;
@ -1008,11 +1030,6 @@ protected:
void initVariables();
void clearCycleAcctings();
void removeLibertyAnnotations();
void deleteExceptionMap(PinExceptionsMap *&exception_map);
void deleteExceptionMap(InstanceExceptionsMap *&exception_map);
void deleteExceptionMap(NetExceptionsMap *&exception_map);
void deleteExceptionMap(ClockExceptionsMap *&exception_map);
void deleteExceptionMap(EdgeExceptionsMap *&exception_map);
void deleteExceptionsReferencing(Clock *clk);
void deleteClkPinMappings(Clock *clk);
void deleteExceptionPtHashMapSets(ExceptionPathPtHash &map);
@ -1020,8 +1037,9 @@ protected:
virtual void deletePinClocks(Clock *defining_clk,
PinSet *pins);
void makeDefaultArrivalClock();
InputDrive *ensureInputDrive(Port *port);
PortExtCap *ensurePortExtPinCap(Port *port);
InputDrive *ensureInputDrive(const Port *port);
PortExtCap *ensurePortExtPinCap(const Port *port,
const Corner *corner);
ExceptionPath *findMergeMatch(ExceptionPath *exception);
void addException1(ExceptionPath *exception);
void addException2(ExceptionPath *exception);
@ -1044,15 +1062,15 @@ protected:
ExceptionPathSet &matches);
void findMatchingExceptionsClks(ExceptionPath *exception,
ClockSet *clks,
ClockExceptionsMap *exception_map,
ClockExceptionsMap &exception_map,
ExceptionPathSet &matches);
void findMatchingExceptionsPins(ExceptionPath *exception,
PinSet *pins,
PinExceptionsMap *exception_map,
PinExceptionsMap &exception_map,
ExceptionPathSet &matches);
void findMatchingExceptionsInsts(ExceptionPath *exception,
InstanceSet *insts,
InstanceExceptionsMap *exception_map,
InstanceExceptionsMap &exception_map,
ExceptionPathSet &matches);
void findMatchingExceptions(ExceptionPath *exception,
ExceptionPathSet *potential_matches,
@ -1067,43 +1085,43 @@ protected:
void recordExceptionFirstTo(ExceptionPath *exception);
void recordExceptionClks(ExceptionPath *exception,
ClockSet *clks,
ClockExceptionsMap *&exception_map);
ClockExceptionsMap &exception_map);
void recordExceptionInsts(ExceptionPath *exception,
InstanceSet *insts,
InstanceExceptionsMap *&exception_map);
InstanceExceptionsMap &exception_map);
void recordExceptionPins(ExceptionPath *exception,
PinSet *pins,
PinExceptionsMap *&exception_map);
PinExceptionsMap &exception_map);
void recordExceptionNets(ExceptionPath *exception,
NetSet *nets,
NetExceptionsMap *&exception_map);
NetExceptionsMap &exception_map);
void recordExceptionHpin(ExceptionPath *exception,
Pin *pin,
PinExceptionsMap *&exception_map);
PinExceptionsMap &exception_map);
void recordExceptionEdges(ExceptionPath *exception,
EdgePinsSet *edges,
EdgeExceptionsMap *&exception_map);
EdgeExceptionsMap &exception_map);
void recordMergeHash(ExceptionPath *exception, ExceptionPt *missing_pt);
void recordMergeHashes(ExceptionPath *exception);
void unrecordExceptionFirstPts(ExceptionPath *exception);
void unrecordExceptionClks(ExceptionPath *exception,
ClockSet *clks,
ClockExceptionsMap *exception_map);
ClockExceptionsMap &exception_map);
void unrecordExceptionPins(ExceptionPath *exception,
PinSet *pins,
PinExceptionsMap *exception_map);
PinExceptionsMap &exception_map);
void unrecordExceptionInsts(ExceptionPath *exception,
InstanceSet *insts,
InstanceExceptionsMap *exception_map);
InstanceExceptionsMap &exception_map);
void unrecordExceptionEdges(ExceptionPath *exception,
EdgePinsSet *edges,
EdgeExceptionsMap *exception_map);
EdgeExceptionsMap &exception_map);
void unrecordExceptionNets(ExceptionPath *exception,
NetSet *nets,
NetExceptionsMap *exception_map);
NetExceptionsMap &exception_map);
void unrecordExceptionHpin(ExceptionPath *exception,
Pin *pin,
PinExceptionsMap *&exception_map);
PinExceptionsMap &exception_map);
void unrecordMergeHashes(ExceptionPath *exception);
void unrecordMergeHash(ExceptionPath *exception,
ExceptionPt *missing_pt);
@ -1142,33 +1160,29 @@ protected:
ExceptionPath *&hi_priority_exception,
int &hi_priority) const;
void makeLoopPath(ExceptionThruSeq *thrus);
void makeLoopException(Pin *loop_input_pin,
Pin *loop_pin,
Pin *loop_prev_pin);
void makeLoopExceptionThru(Pin *pin,
void makeLoopException(const Pin *loop_input_pin,
const Pin *loop_pin,
const Pin *loop_prev_pin);
void makeLoopExceptionThru(const Pin *pin,
ExceptionThruSeq *thrus);
void deleteLoopExceptions();
void deleteConstraints();
InputDelay *findInputDelay(const Pin *pin,
ClockEdge *clk_edge,
Pin *ref_pin);
InputDelay *makeInputDelay(Pin *pin,
ClockEdge *clk_edge,
Pin *ref_pin);
void deleteInputDelays(Pin *pin,
const ClockEdge *clk_edge);
InputDelay *makeInputDelay(const Pin *pin,
const ClockEdge *clk_edge);
void deleteInputDelays(const Pin *pin,
InputDelay *except);
void deleteInputDelaysReferencing(Clock *clk);
void deleteInputDelaysReferencing(const Clock *clk);
void deleteInputDelay(InputDelay *input_delay);
OutputDelay *findOutputDelay(const Pin *pin,
ClockEdge *clk_edge,
Pin *ref_pin);
OutputDelay *makeOutputDelay(Pin *pin,
ClockEdge *clk_edge,
Pin *ref_pin);
void deleteOutputDelays(Pin *pin, OutputDelay *except);
void deleteOutputDelaysReferencing(Clock *clk);
const ClockEdge *clk_edge);
OutputDelay *makeOutputDelay(const Pin *pin,
const ClockEdge *clk_edge);
void deleteOutputDelays(const Pin *pin,
OutputDelay *except);
void deleteOutputDelaysReferencing(const Clock *clk);
void deleteOutputDelay(OutputDelay *output_delay);
void deleteInstancePvts();
void deleteClockInsertion(ClockInsertion *insertion);
void deleteClockInsertionsReferencing(Clock *clk);
void deleteInterClockUncertainty(InterClockUncertainty *uncertainties);
@ -1198,7 +1212,6 @@ protected:
void annotateHierClkLatency();
void annotateHierClkLatency(const Pin *hpin,
ClockLatency *latency);
void initInstancePvtMaps();
void pinCaps(const Pin *pin,
const RiseFall *rf,
const OperatingConditions *op_cond,
@ -1244,18 +1257,18 @@ protected:
const Clock *clk,
const RiseFall *from_rf,
const RiseFall *to_rf) const;
void disconnectPinBefore(Pin *pin,
void disconnectPinBefore(const Pin *pin,
ExceptionPathSet *exceptions);
void clockGroupsDeleteClkRefs(Clock *clk);
void clearGroupPathMap();
AnalysisType analysis_type_;
OperatingConditions *operating_conditions_[MinMax::index_count];
InstancePvtMap *instance_pvt_maps_[MinMax::index_count];
InstancePvtMap instance_pvt_maps_[MinMax::index_count];
DeratingFactorsGlobal *derating_factors_;
NetDeratingFactorsMap *net_derating_factors_;
InstDeratingFactorsMap *inst_derating_factors_;
CellDeratingFactorsMap *cell_derating_factors_;
NetDeratingFactorsMap net_derating_factors_;
InstDeratingFactorsMap inst_derating_factors_;
CellDeratingFactorsMap cell_derating_factors_;
// Clock sequence retains clock definition order.
// This is important for getting consistent regression results,
// which iterating over the name map can't provide.
@ -1273,15 +1286,15 @@ protected:
bool clk_hpin_disables_valid_;
PinSet propagated_clk_pins_;
ClockLatencies clk_latencies_;
ClockInsertions *clk_insertions_;
ClockInsertions clk_insertions_;
PinClockUncertaintyMap pin_clk_uncertainty_map_;
InterClockUncertaintySet inter_clk_uncertainties_;
// clk_groups name -> clk_groups
ClockGroupsNameMap clk_groups_name_map_;
// clk to clk paths excluded by clock groups.
ClockPairSet *clk_group_exclusions_;
ClockPairSet clk_group_exclusions_;
// clks in the same set_clock_group set.
ClockPairSet *clk_group_same_;
ClockPairSet clk_group_same_;
ClockSenseMap clk_sense_map_;
ClockGatingCheck *clk_gating_check_;
ClockGatingCheckMap clk_gating_check_map_;
@ -1294,11 +1307,11 @@ protected:
InputDelaySet input_delays_;
InputDelaysPinMap input_delay_pin_map_;
int input_delay_index_;
InputDelaysPinMap input_delay_ref_pin_map_;
// Input delays on hierarchical pins are indexed by the load pins.
InputDelaysPinMap input_delay_leaf_pin_map_;
InputDelaysPinMap input_delay_internal_pin_map_;
int input_delay_index_;
OutputDelaySet output_delays_;
OutputDelaysPinMap output_delay_pin_map_;
@ -1318,12 +1331,12 @@ protected:
// set_load port
// set_fanout_load port
// Indexed by corner_index.
PortExtCapMap *port_cap_map_;
vector<PortExtCapMap> port_ext_cap_maps_;
// set_load net
// Indexed by corner_index.
NetWireCapMap *net_wire_cap_map_;
vector<NetWireCapMap> net_wire_cap_maps_;
// Indexed by corner_index.
PinWireCapMap *drvr_pin_wire_cap_map_;
vector<PinWireCapMap> drvr_pin_wire_cap_maps_;
NetResistanceMap net_res_map_;
PinSet disabled_pins_;
PortSet disabled_ports_;
@ -1338,25 +1351,24 @@ protected:
bool have_thru_hpin_exceptions_;
// First pin/clock/instance/net/edge exception point to exception set map.
PinExceptionsMap *first_from_pin_exceptions_;
ClockExceptionsMap *first_from_clk_exceptions_;
InstanceExceptionsMap *first_from_inst_exceptions_;
PinExceptionsMap *first_thru_pin_exceptions_;
InstanceExceptionsMap *first_thru_inst_exceptions_;
PinExceptionsMap first_from_pin_exceptions_;
ClockExceptionsMap first_from_clk_exceptions_;
InstanceExceptionsMap first_from_inst_exceptions_;
PinExceptionsMap first_thru_pin_exceptions_;
InstanceExceptionsMap first_thru_inst_exceptions_;
// Nets that have exception -thru nets.
NetExceptionsMap *first_thru_net_exceptions_;
PinExceptionsMap *first_to_pin_exceptions_;
ClockExceptionsMap *first_to_clk_exceptions_;
InstanceExceptionsMap *first_to_inst_exceptions_;
NetExceptionsMap first_thru_net_exceptions_;
PinExceptionsMap first_to_pin_exceptions_;
ClockExceptionsMap first_to_clk_exceptions_;
InstanceExceptionsMap first_to_inst_exceptions_;
// Edges that traverse hierarchical exception pins.
EdgeExceptionsMap *first_thru_edge_exceptions_;
EdgeExceptionsMap first_thru_edge_exceptions_;
// Exception hash with one missing from/thru/to point, used for merging.
ExceptionPathPtHash exception_merge_hash_;
// Path delay -from pin internal startpoints.
PinSet *path_delay_internal_startpoints_;
PinSet path_delay_internal_startpoints_;
// Path delay -to pin internal endpoints.
PinSet *path_delay_internal_endpoints_;
PinSet path_delay_internal_endpoints_;
// There is a path delay exception without a -to.
bool path_delays_without_to_;
// Group path exception names.
@ -1401,26 +1413,4 @@ private:
friend class GroupPathIterator;
};
class ClockIterator : public ClockSeq::Iterator
{
public:
ClockIterator(Sdc *sdc);
private:
ClockIterator(ClockSeq &clocks);
friend class Sdc;
};
class GroupPathIterator : public GroupPathMap::Iterator
{
public:
GroupPathIterator(Sdc *sdc);
private:
GroupPathIterator(GroupPathMap &group_path_map);
friend class Sdc;
};
} // namespace

41
include/sta/SdcClass.hh
View File

@ -53,7 +53,6 @@ class DataCheck;
class Wireload;
class ClockLatency;
class ClockInsertion;
class ClockGroup;
class ClockGroups;
class PortDelay;
@ -66,28 +65,56 @@ enum class ClockSense { positive, negative, stop };
typedef std::pair<const Clock*, const Clock*> ClockPair;
class ClockIndexLess
{
public:
bool operator()(const Clock *clk1,
const Clock *clk2) const;
};
typedef Vector<float> FloatSeq;
typedef Vector<int> IntSeq;
typedef Vector<Clock*> ClockSeq;
typedef Set<Clock*> ClockSet;
typedef Set<Clock*, ClockIndexLess> ClockSet;
typedef ClockSet ClockGroup;
typedef Vector<PinSet*> PinSetSeq;
typedef MinMax SetupHold;
typedef MinMaxAll SetupHoldAll;
typedef Vector<ExceptionThru*> ExceptionThruSeq;
typedef Set<LibertyPortPair*, LibertyPortPairLess> LibertyPortPairSet;
typedef Map<Instance*, DisabledInstancePorts*> DisabledInstancePortsMap;
typedef Map<LibertyCell*, DisabledCellPorts*> DisabledCellPortsMap;
typedef Set<LibertyPortPair, LibertyPortPairLess> LibertyPortPairSet;
typedef Map<const Instance*, DisabledInstancePorts*> DisabledInstancePortsMap;
typedef Map<const LibertyCell*, DisabledCellPorts*> DisabledCellPortsMap;
typedef MinMaxValues<float> ClockUncertainties;
typedef Set<ExceptionPath*> ExceptionPathSet;
typedef PinPair EdgePins;
typedef PinPairSet EdgePinsSet;
typedef Map<const Pin*, LogicValue> LogicValueMap;
typedef Set<ClockGroup*> ClockGroupSet;
class ClockSetLess
{
public:
bool operator()(const ClockSet *set1,
const ClockSet *set2) const;
};
typedef Set<ClockGroup*, ClockSetLess> ClockGroupSet;
// For Search.
class ExceptionState;
class ExceptionStateLess
{
public:
ExceptionStateLess(const Network *network);
bool operator()(const ExceptionState *state1,
const ExceptionState *state2) const;
private:
const Network *network_;
};
class ExceptionPath;
typedef Set<ExceptionState*> ExceptionStateSet;
typedef Set<ExceptionState*, ExceptionStateLess> ExceptionStateSet;
enum class CrprMode { same_pin, same_transition };

49
include/sta/SdcNetwork.hh
View File

@ -32,19 +32,20 @@ public:
bool make_black_boxes,
Report *report);
virtual const char *name(const Library *library) const;
virtual ObjectId id(const Library *library) const;
virtual LibraryIterator *libraryIterator() const;
virtual LibertyLibraryIterator *libertyLibraryIterator() const;
virtual Library *findLibrary(const char *name);
virtual LibertyLibrary *findLibertyFilename(const char *filename);
virtual LibertyLibrary *findLiberty(const char *name);
virtual const char *name(const Library *library) const;
virtual Cell *findCell(const Library *library,
const char *name) const;
virtual void findCellsMatching(const Library *library,
const PatternMatch *pattern,
CellSeq *cells) const;
virtual CellSeq findCellsMatching(const Library *library,
const PatternMatch *pattern) const;
virtual const char *name(const Cell *cell) const;
virtual ObjectId id(const Cell *cell) const;
virtual Library *library(const Cell *cell) const;
virtual LibertyCell *libertyCell(Cell *cell) const;
virtual const LibertyCell *libertyCell(const Cell *cell) const;
@ -53,15 +54,15 @@ public:
virtual const char *filename(const Cell *cell);
virtual Port *findPort(const Cell *cell,
const char *name) const;
virtual void findPortsMatching(const Cell *cell,
const PatternMatch *pattern,
PortSeq *ports) const;
virtual PortSeq findPortsMatching(const Cell *cell,
const PatternMatch *pattern) const;
virtual bool isLeaf(const Cell *cell) const;
virtual CellPortIterator *portIterator(const Cell *cell) const;
virtual CellPortBitIterator *portBitIterator(const Cell *cell) const;
virtual int portBitCount(const Cell *cell) const;
virtual const char *name(const Port *port) const;
virtual ObjectId id(const Port *port) const;
virtual Cell *cell(const Port *port) const;
virtual LibertyPort *libertyPort(const Port *port) const;
virtual PortDirection *direction(const Port *port) const;
@ -78,6 +79,7 @@ public:
virtual PortMemberIterator *memberIterator(const Port *port) const;
virtual bool hasMembers(const Port *port) const;
virtual ObjectId id(const Instance *instance) const;
virtual Instance *topInstance() const;
virtual Cell *cell(const Instance *instance) const;
virtual Instance *parent(const Instance *instance) const;
@ -94,6 +96,7 @@ public:
virtual InstanceNetIterator *
netIterator(const Instance *instance) const;
virtual ObjectId id(const Pin *pin) const;
virtual Port *port(const Pin *pin) const;
virtual Instance *instance(const Pin *pin) const;
virtual Net *net(const Pin *pin) const;
@ -108,9 +111,11 @@ public:
double &y,
bool &exists) const;
virtual ObjectId id(const Term *term) const;
virtual Net *net(const Term *term) const;
virtual Pin *pin(const Term *term) const;
virtual ObjectId id(const Net *net) const;
virtual Instance *instance(const Net *net) const;
virtual bool isPower(const Net *net) const;
virtual bool isGround(const Net *net) const;
@ -151,6 +156,7 @@ public:
// Any overloaded functions from the base class must be listed here.
using Network::name;
using Network::id;
using Network::isLeaf;
using Network::netIterator;
using Network::findPin;
@ -175,9 +181,8 @@ public:
virtual Port *findPort(const Cell *cell,
const char *name) const;
virtual void findPortsMatching(const Cell *cell,
const PatternMatch *pattern,
PortSeq *ports) const;
virtual PortSeq findPortsMatching(const Cell *cell,
const PatternMatch *pattern) const;
virtual const char *name(const Port *port) const;
virtual const char *busName(const Port *port) const;
@ -185,30 +190,28 @@ public:
virtual const char *pathName(const Instance *instance) const;
virtual const char *pathName(const Pin *pin) const;
virtual const char *portName(const Pin *pin) const;
virtual const char *name(const Net *net) const;
virtual const char *pathName(const Net *net) const;
virtual Instance *findInstance(const char *path_name) const;
virtual void findInstancesMatching(const Instance *context,
const PatternMatch *pattern,
InstanceSeq *insts) const;
virtual InstanceSeq findInstancesMatching(const Instance *context,
const PatternMatch *pattern) const;
virtual Net *findNet(const char *path_name) const;
virtual Net *findNet(const Instance *instance,
const char *net_name) const;
virtual void findNetsMatching(const Instance *parent,
const PatternMatch *pattern,
NetSeq *nets) const;
virtual NetSeq findNetsMatching(const Instance *parent,
const PatternMatch *pattern) const;
virtual void findInstNetsMatching(const Instance *instance,
const PatternMatch *pattern,
NetSeq *nets) const;
NetSeq &nets) const;
virtual Instance *findChild(const Instance *parent,
const char *name) const;
virtual Pin *findPin(const char *path_name) const;
virtual Pin *findPin(const Instance *instance,
const char *port_name) const;
virtual void findPinsMatching(const Instance *instance,
const PatternMatch *pattern,
PinSeq *pins) const;
virtual PinSeq findPinsMatching(const Instance *instance,
const PatternMatch *pattern) const;
virtual Instance *makeInstance(LibertyCell *cell,
const char *name,
@ -221,6 +224,7 @@ public:
// findInstPinsMatching(instance, pattern)
using Network::name;
using Network::id;
using Network::findPin;
protected:
@ -246,7 +250,10 @@ protected:
visit_tail) const;
bool visitPinTail(const Instance *instance,
const PatternMatch *tail,
PinSeq *pins) const;
PinSeq &matches) const;
void findInstancesMatching1(const Instance *context,
const PatternMatch *pattern,
InstanceSeq &matches) const;
const char *staToSdc(const char *sta_name) const;
};

43
include/sta/Search.hh
View File

@ -114,7 +114,7 @@ public:
void requiredsInvalid();
// Invalidate vertex required time.
void requiredInvalid(Vertex *vertex);
void requiredInvalid(Instance *inst);
void requiredInvalid(const Instance *inst);
void requiredInvalid(const Pin *pin);
// Vertex will be deleted.
void deleteVertexBefore(Vertex *vertex);
@ -150,7 +150,7 @@ public:
Arrival clkPathArrival(const Path *clk_path) const;
Arrival clkPathArrival(const Path *clk_path,
ClkInfo *clk_info,
ClockEdge *clk_edge,
const ClockEdge *clk_edge,
const MinMax *min_max,
const PathAnalysisPt *path_ap) const;
// Clock arrival at the path source/launch point.
@ -179,12 +179,8 @@ public:
// Vertices on propagated generated clock source paths.
bool isGenClkSrc(const Vertex *vertex) const;
// The set of clocks that arrive at vertex.
void clocks(const Vertex *vertex,
// Return value.
ClockSet &clks) const;
void clocks(const Pin *pin,
// Return value.
ClockSet &clks) const;
ClockSet clocks(const Vertex *vertex) const;
ClockSet clocks(const Pin *pin) const;
void visitStartpoints(VertexVisitor *visitor);
void visitEndpoints(VertexVisitor *visitor);
bool havePathGroups() const;
@ -222,7 +218,7 @@ public:
bool require_exception);
Tag *fromRegClkTag(const Pin *from_pin,
const RiseFall *from_rf,
Clock *clk,
const Clock *clk,
const RiseFall *clk_rf,
ClkInfo *clk_info,
const Pin *to_pin,
@ -305,7 +301,7 @@ public:
bool own_states);
void reportTags() const;
void reportClkInfos() const;
virtual ClkInfo *findClkInfo(ClockEdge *clk_edge,
virtual ClkInfo *findClkInfo(const ClockEdge *clk_edge,
const Pin *clk_src,
bool is_propagated,
const Pin *gen_clk_src,
@ -316,7 +312,7 @@ public:
ClockUncertainties *uncertainties,
const PathAnalysisPt *path_ap,
PathVertex *crpr_clk_path);
ClkInfo *findClkInfo(ClockEdge *clk_edge,
ClkInfo *findClkInfo(const ClockEdge *clk_edge,
const Pin *clk_src,
bool is_propagated,
Arrival insertion,
@ -368,24 +364,24 @@ protected:
void findClockVertices(VertexSet &vertices);
void seedClkDataArrival(const Pin *pin,
const RiseFall *rf,
Clock *clk,
ClockEdge *clk_edge,
const Clock *clk,
const ClockEdge *clk_edge,
const MinMax *min_max,
const PathAnalysisPt *path_ap,
Arrival insertion,
TagGroupBldr *tag_bldr);
void seedClkArrival(const Pin *pin,
const RiseFall *rf,
Clock *clk,
ClockEdge *clk_edge,
const Clock *clk,
const ClockEdge *clk_edge,
const MinMax *min_max,
const PathAnalysisPt *path_ap,
Arrival insertion,
TagGroupBldr *tag_bldr);
Tag *clkDataTag(const Pin *pin,
Clock *clk,
const Clock *clk,
const RiseFall *rf,
ClockEdge *clk_edge,
const ClockEdge *clk_edge,
Arrival insertion,
const MinMax *min_max,
const PathAnalysisPt *path_ap);
@ -402,7 +398,7 @@ protected:
ClockSet *wrt_clks);
void seedInputDelayArrival(const Pin *pin,
InputDelay *input_delay,
ClockEdge *clk_edge,
const ClockEdge *clk_edge,
float clk_arrival,
float clk_insertion,
float clk_latency,
@ -414,7 +410,7 @@ protected:
const RiseFall *rf,
float arrival,
InputDelay *input_delay,
ClockEdge *clk_edge,
const ClockEdge *clk_edge,
float clk_insertion,
float clk_latency,
bool is_segment_start,
@ -422,7 +418,7 @@ protected:
PathAnalysisPt *path_ap,
TagGroupBldr *tag_bldr);
void inputDelayClkArrival(InputDelay *input_delay,
ClockEdge *clk_edge,
const ClockEdge *clk_edge,
const MinMax *min_max,
const PathAnalysisPt *path_ap,
// Return values.
@ -430,7 +426,7 @@ protected:
float &clk_insertion,
float &clk_latency);
void inputDelayRefPinArrival(Path *ref_path,
ClockEdge *clk_edge,
const ClockEdge *clk_edge,
const MinMax *min_max,
// Return values.
float &ref_arrival,
@ -438,7 +434,7 @@ protected:
float &ref_latency);
Tag *inputDelayTag(const Pin *pin,
const RiseFall *rf,
ClockEdge *clk_edge,
const ClockEdge *clk_edge,
float clk_insertion,
float clk_latency,
InputDelay *input_delay,
@ -527,6 +523,9 @@ protected:
bool matchesFilterTo(Path *path,
const ClockEdge *to_clk_edge) const;
PathRef pathClkPathArrival1(const Path *path) const;
void clocks(const Vertex *vertex,
// Return value.
ClockSet &clks) const;
////////////////////////////////////////////////////////////////

16
include/sta/Set.hh
View File

@ -71,11 +71,11 @@ public:
}
static bool
intersects(std::set<KEY, CMP> &set1,
std::set<KEY, CMP> &set2);
intersects(const std::set<KEY, CMP> &set1,
const std::set<KEY, CMP> &set2);
static bool
intersects(std::set<KEY, CMP> *set1,
std::set<KEY, CMP> *set2);
intersects(const std::set<KEY, CMP> *set1,
const std::set<KEY, CMP> *set2);
// Java style container itererator
// Set::Iterator<Key*> iter(set);
@ -174,16 +174,16 @@ Set<KEY, CMP>::isSubset(const std::set<KEY, CMP> *set2)
template <class KEY, class CMP>
bool
Set<KEY, CMP>::intersects(std::set<KEY, CMP> &set1,
std::set<KEY, CMP> &set2)
Set<KEY, CMP>::intersects(const std::set<KEY, CMP> &set1,
const std::set<KEY, CMP> &set2)
{
return intersects(&set1, &set2);
}
template <class KEY, class CMP>
bool
Set<KEY, CMP>::intersects(std::set<KEY, CMP> *set1,
std::set<KEY, CMP> *set2)
Set<KEY, CMP>::intersects(const std::set<KEY, CMP> *set1,
const std::set<KEY, CMP> *set2)
{
if (set1 && !set1->empty()
&& set2 && !set2->empty()) {

213
include/sta/Sta.hh
View File

@ -59,7 +59,6 @@ class ClkSkews;
class ReportField;
class Power;
class PowerResult;
class ClockIterator;
class EquivCells;
typedef InstanceSeq::Iterator SlowDrvrIterator;
@ -151,75 +150,77 @@ public:
const EarlyLate *early_late,
float derate);
void unsetTimingDerate();
void setInputSlew(Port *port,
void setInputSlew(const Port *port,
const RiseFallBoth *rf,
const MinMaxAll *min_max,
float slew);
// Set port external pin load (set_load -pin port).
void setPortExtPinCap(Port *port,
void setPortExtPinCap(const Port *port,
const RiseFallBoth *rf,
const Corner *corner,
const MinMaxAll *min_max,
float cap);
void portExtCaps(Port *port,
void portExtCaps(const Port *port,
const Corner *corner,
const MinMax *min_max,
float &pin_cap,
float &wire_cap,
int &fanout);
// Set port external wire load (set_load -wire port).
void setPortExtWireCap(Port *port,
void setPortExtWireCap(const Port *port,
bool subtract_pin_cap,
const RiseFallBoth *rf,
const Corner *corner,
const MinMaxAll *min_max,
float cap);
// Set net wire capacitance (set_load -wire net).
void setNetWireCap(Net *net,
void setNetWireCap(const Net *net,
bool subtract_pin_load,
const Corner *corner,
const MinMaxAll *min_max,
float cap);
// Set port external fanout (used by wireload models).
void setPortExtFanout(Port *port,
void setPortExtFanout(const Port *port,
int fanout,
const Corner *corner,
const MinMaxAll *min_max);
// Remove all "set_load net" annotations.
void removeNetLoadCaps() const;
// Liberty port capacitance.
float capacitance(const LibertyPort *port,
Corner *corner,
const MinMax *min_max);
// pin_cap = net pin capacitances + port external pin capacitance,
// wire_cap = annotated net capacitance + port external wire capacitance.
void connectedCap(Pin *drvr_pin,
void connectedCap(const Pin *drvr_pin,
const RiseFall *rf,
const Corner *corner,
const MinMax *min_max,
float &pin_cap,
float &wire_cap) const;
void connectedCap(Net *net,
void connectedCap(const Net *net,
Corner *corner,
const MinMax *min_max,
float &pin_cap,
float &wire_cap) const;
void setResistance(Net *net,
void setResistance(const Net *net,
const MinMaxAll *min_max,
float res);
void setDriveCell(LibertyLibrary *library,
LibertyCell *cell,
Port *port,
LibertyPort *from_port,
void setDriveCell(const LibertyLibrary *library,
const LibertyCell *cell,
const Port *port,
const LibertyPort *from_port,
float *from_slews,
LibertyPort *to_port,
const LibertyPort *to_port,
const RiseFallBoth *rf,
const MinMaxAll *min_max);
void setDriveResistance(Port *port,
void setDriveResistance(const Port *port,
const RiseFallBoth *rf,
const MinMaxAll *min_max,
float res);
void setLatchBorrowLimit(Pin *pin,
void setLatchBorrowLimit(const Pin *pin,
float limit);
void setLatchBorrowLimit(Instance *inst,
void setLatchBorrowLimit(const Instance *inst,
float limit);
void setLatchBorrowLimit(Clock *clk,
void setLatchBorrowLimit(const Clock *clk,
float limit);
void setMinPulseWidth(const RiseFallBoth *rf,
float min_width);
@ -430,7 +431,7 @@ public:
bool isDisabledClock(Edge *edge);
// Return a set of constant pins that disabled edge.
// Caller owns the returned set.
PinSet *disabledConstantPins(Edge *edge);
PinSet disabledConstantPins(Edge *edge);
// Edge timing sense with propagated constants.
TimingSense simTimingSense(Edge *edge);
// Edge is disabled by set_disable_timing constraint.
@ -444,8 +445,8 @@ public:
bool isDisabledPresetClr(Edge *edge) const;
// Return a vector of graph edges that are disabled, sorted by
// from/to vertex names. Caller owns the returned vector.
EdgeSeq *disabledEdges();
EdgeSeq *disabledEdgesSorted();
EdgeSeq disabledEdges();
EdgeSeq disabledEdgesSorted();
void disableClockGatingCheck(Instance *inst);
void disableClockGatingCheck(Pin *pin);
void removeDisableClockGatingCheck(Instance *inst);
@ -540,35 +541,34 @@ public:
void checkExceptionToPins(ExceptionTo *to,
const char *file, int) const;
void deleteExceptionTo(ExceptionTo *to);
InstanceSet *findRegisterInstances(ClockSet *clks,
const RiseFallBoth *clk_rf,
bool edge_triggered,
bool latches);
PinSet *findRegisterDataPins(ClockSet *clks,
const RiseFallBoth *clk_rf,
bool registers,
bool latches);
PinSet *findRegisterClkPins(ClockSet *clks,
const RiseFallBoth *clk_rf,
bool registers,
bool latches);
PinSet *findRegisterAsyncPins(ClockSet *clks,
const RiseFallBoth *clk_rf,
bool registers,
bool latches);
PinSet *findRegisterOutputPins(ClockSet *clks,
const RiseFallBoth *clk_rf,
bool registers,
bool latches);
PinSet *
findFaninPins(PinSeq *to,
bool flat,
bool startpoints_only,
int inst_levels,
int pin_levels,
bool thru_disabled,
bool thru_constants);
InstanceSet *
InstanceSet findRegisterInstances(ClockSet *clks,
const RiseFallBoth *clk_rf,
bool edge_triggered,
bool latches);
PinSet findRegisterDataPins(ClockSet *clks,
const RiseFallBoth *clk_rf,
bool registers,
bool latches);
PinSet findRegisterClkPins(ClockSet *clks,
const RiseFallBoth *clk_rf,
bool registers,
bool latches);
PinSet findRegisterAsyncPins(ClockSet *clks,
const RiseFallBoth *clk_rf,
bool registers,
bool latches);
PinSet findRegisterOutputPins(ClockSet *clks,
const RiseFallBoth *clk_rf,
bool registers,
bool latches);
PinSet findFaninPins(PinSeq *to,
bool flat,
bool startpoints_only,
int inst_levels,
int pin_levels,
bool thru_disabled,
bool thru_constants);
InstanceSet
findFaninInstances(PinSeq *to,
bool flat,
bool startpoints_only,
@ -576,7 +576,7 @@ public:
int pin_levels,
bool thru_disabled,
bool thru_constants);
PinSet *
PinSet
findFanoutPins(PinSeq *from,
bool flat,
bool endpoints_only,
@ -584,7 +584,7 @@ public:
int pin_levels,
bool thru_disabled,
bool thru_constants);
InstanceSet *
InstanceSet
findFanoutInstances(PinSeq *from,
bool flat,
bool endpoints_only,
@ -594,18 +594,16 @@ public:
bool thru_constants);
// The set of clocks that reach pin.
void clocks(const Pin *pin,
// Return value.
ClockSet &clks);
ClockSet clocks(const Pin *pin);
void checkSlewLimitPreamble();
// Return pins with the min/max slew limit slack.
// net=null check all nets
// corner=nullptr checks all corners.
PinSeq *checkSlewLimits(Net *net,
bool violators,
const Corner *corner,
const MinMax *min_max);
PinSeq checkSlewLimits(Net *net,
bool violators,
const Corner *corner,
const MinMax *min_max);
void reportSlewLimitShortHeader();
void reportSlewLimitShort(Pin *pin,
const Corner *corner,
@ -625,7 +623,7 @@ public:
float &limit,
float &slack);
void maxSlewCheck(// Return values.
Pin *&pin,
const Pin *&pin,
Slew &slew,
float &slack,
float &limit);
@ -640,9 +638,9 @@ public:
// Return pins with the min/max fanout limit slack.
// net=null check all nets
// corner=nullptr checks all corners.
PinSeq *checkFanoutLimits(Net *net,
bool violators,
const MinMax *min_max);
PinSeq checkFanoutLimits(Net *net,
bool violators,
const MinMax *min_max);
void reportFanoutLimitShortHeader();
void reportFanoutLimitShort(Pin *pin,
const MinMax *min_max);
@ -656,7 +654,7 @@ public:
float &limit,
float &slack);
void maxFanoutCheck(// Return values.
Pin *&pin,
const Pin *&pin,
float &fanout,
float &slack,
float &limit);
@ -665,10 +663,10 @@ public:
// Return pins with the min/max slew limit slack.
// net=null check all nets
// corner=nullptr checks all corners.
PinSeq *checkCapacitanceLimits(Net *net,
bool violators,
const Corner *corner,
const MinMax *min_max);
PinSeq checkCapacitanceLimits(Net *net,
bool violators,
const Corner *corner,
const MinMax *min_max);
void reportCapacitanceLimitShortHeader();
void reportCapacitanceLimitShort(Pin *pin,
const Corner *corner,
@ -687,7 +685,7 @@ public:
float &limit,
float &slack);
void maxCapacitanceCheck(// Return values.
Pin *&pin,
const Pin *&pin,
float &capacitance,
float &slack,
float &limit);
@ -734,17 +732,17 @@ public:
// Instance specific process/voltage/temperature.
// Defaults to operating condition if instance is not annotated.
Pvt *pvt(Instance *inst,
const MinMax *min_max);
const Pvt *pvt(Instance *inst,
const MinMax *min_max);
void setPvt(Instance *inst,
const MinMaxAll *min_max,
float process,
float voltage,
float temperature);
// Pvt may be shared among multiple instances.
void setPvt(Instance *inst,
void setPvt(const Instance *inst,
const MinMaxAll *min_max,
Pvt *pvt);
const Pvt &pvt);
// Clear all state except network.
virtual void clear();
// Remove all constraints.
@ -931,8 +929,7 @@ public:
int endpointViolationCount(const MinMax *min_max);
// Find the fanin vertices for a group path.
// Vertices in the clock network are NOT included.
// Return value is owned by the caller.
PinSet *findGroupPathPins(const char *group_path_name);
PinSet findGroupPathPins(const char *group_path_name);
// Find all required times after updateTiming().
void findRequireds();
string *reportDelayCalc(Edge *edge,
@ -1176,26 +1173,26 @@ public:
virtual void disconnectPin(Pin *pin);
// Notify STA of network change.
void networkChanged();
void deleteLeafInstanceBefore(Instance *inst);
void deleteInstancePinsBefore(Instance *inst);
void deleteLeafInstanceBefore(const Instance *inst);
void deleteInstancePinsBefore(const Instance *inst);
// Network edit before/after methods.
void makeInstanceAfter(Instance *inst);
void makeInstanceAfter(const Instance *inst);
// Replace the instance cell with to_cell.
// equivCells(from_cell, to_cell) must be true.
virtual void replaceEquivCellBefore(Instance *inst,
LibertyCell *to_cell);
virtual void replaceEquivCellAfter(Instance *inst);
virtual void replaceEquivCellBefore(const Instance *inst,
const LibertyCell *to_cell);
virtual void replaceEquivCellAfter(const Instance *inst);
// Replace the instance cell with to_cell.
// equivCellPorts(from_cell, to_cell) must be true.
virtual void replaceCellBefore(Instance *inst,
LibertyCell *to_cell);
virtual void replaceCellAfter(Instance *inst);
virtual void connectPinAfter(Pin *pin);
virtual void disconnectPinBefore(Pin *pin);
virtual void deleteNetBefore(Net *net);
virtual void deleteInstanceBefore(Instance *inst);
virtual void deletePinBefore(Pin *pin);
virtual void replaceCellBefore(const Instance *inst,
const LibertyCell *to_cell);
virtual void replaceCellAfter(const Instance *inst);
virtual void connectPinAfter(const Pin *pin);
virtual void disconnectPinBefore(const Pin *pin);
virtual void deleteNetBefore(const Net *net);
virtual void deleteInstanceBefore(const Instance *inst);
virtual void deletePinBefore(const Pin *pin);
////////////////////////////////////////////////////////////////
@ -1241,18 +1238,18 @@ public:
int level);
// Delays and arrivals downsteam from inst are invalid.
void delaysInvalidFrom(Instance *inst);
void delaysInvalidFrom(const Instance *inst);
// Delays and arrivals downsteam from pin are invalid.
void delaysInvalidFrom(Pin *pin);
void delaysInvalidFrom(const Pin *pin);
void delaysInvalidFrom(Vertex *vertex);
// Delays to driving pins of net (fanin) are invalid.
// Arrivals downsteam from net are invalid.
void delaysInvalidFromFanin(Net *net);
void delaysInvalidFromFanin(Pin *pin);
void delaysInvalidFromFanin(const Net *net);
void delaysInvalidFromFanin(const Pin *pin);
void delaysInvalidFromFanin(Vertex *vertex);
void replaceCellPinInvalidate(LibertyPort *from_port,
void replaceCellPinInvalidate(const LibertyPort *from_port,
Vertex *vertex,
LibertyCell *to_cell);
const LibertyCell *to_cell);
// Power API.
Power *power() { return power_; }
@ -1264,10 +1261,8 @@ public:
PowerResult &combinational,
PowerResult &macro,
PowerResult &pad);
void power(const Instance *inst,
const Corner *corner,
// Return values.
PowerResult &result);
PowerResult power(const Instance *inst,
const Corner *corner);
PwrActivity findClkedActivity(const Pin *pin);
void writeTimingModel(const char *lib_name,
@ -1321,18 +1316,18 @@ protected:
virtual LibertyLibrary *readLibertyFile(const char *filename,
bool infer_latches);
void delayCalcPreamble();
void delaysInvalidFrom(Port *port);
void delaysInvalidFromFanin(Port *port);
void delaysInvalidFrom(const Port *port);
void delaysInvalidFromFanin(const Port *port);
void deleteEdge(Edge *edge);
void netParasiticCaps(Net *net,
const RiseFall *rf,
const MinMax *min_max,
float &pin_cap,
float &wire_cap) const;
Pin *findNetParasiticDrvrPin(Net *net) const;
const Pin *findNetParasiticDrvrPin(const Net *net) const;
void exprConstantPins(FuncExpr *expr,
Instance *inst,
PinSet *pins);
const Instance *inst,
PinSet &pins);
Slack vertexSlack1(Vertex *vertex,
const RiseFall *rf,
const ClockEdge *clk_edge,
@ -1359,7 +1354,7 @@ protected:
bool startpoints_only,
int inst_levels,
int pin_levels,
PinSet *fanin,
PinSet &fanin,
SearchPred &pred);
void findFaninPins(Vertex *to,
bool flat,
@ -1374,7 +1369,7 @@ protected:
bool endpoints_only,
int inst_levels,
int pin_levels,
PinSet *fanout,
PinSet &fanout,
SearchPred &pred);
void findFanoutPins(Vertex *from,
bool flat,

2
include/sta/TimingArc.hh
View File

@ -239,7 +239,7 @@ public:
unsigned index() const { return index_; }
TimingModel *model(const OperatingConditions *op_cond) const;
TimingModel *model() const { return model_; }
TimingArc *cornerArc(int ap_index);
const TimingArc *cornerArc(int ap_index) const;
void setCornerArc(TimingArc *corner_arc,
int ap_index);
float driveResistance() const;

18
include/sta/UnorderedMap.hh
View File

@ -31,6 +31,11 @@ public:
{
}
explicit UnorderedMap(const HASH &hash) :
std::unordered_map<KEY, VALUE, HASH, EQUAL>(0, hash, std::equal_to<KEY>())
{
}
explicit UnorderedMap(size_t size,
const HASH &hash,
const EQUAL &equal) :
@ -101,6 +106,19 @@ public:
delete iter.next();
}
void
deleteKeysContents()
{
Iterator iter(this);
while (iter.hasNext()) {
KEY key;
VALUE value;
iter.next(key, value);
delete key;
delete value;
}
}
void
deleteArrayContents()
{

6
include/sta/VertexVisitor.hh
View File

@ -37,13 +37,13 @@ public:
class VertexPinCollector : public VertexVisitor
{
public:
VertexPinCollector(PinSet *pins);
PinSet *pins() const { return pins_; }
VertexPinCollector(PinSet &pins);
const PinSet &pins() const { return pins_; }
void visit(Vertex *vertex);
virtual VertexVisitor *copy() const;
protected:
PinSet *pins_;
PinSet &pins_;
};
} // namespace

57
liberty/Liberty.cc
View File

@ -132,16 +132,17 @@ LibertyLibrary::findLibertyCell(const char *name) const
return static_cast<LibertyCell*>(findCell(name));
}
void
LibertyLibrary::findLibertyCellsMatching(PatternMatch *pattern,
LibertyCellSeq *cells)
LibertyCellSeq
LibertyLibrary::findLibertyCellsMatching(PatternMatch *pattern)
{
LibertyCellSeq matches;
LibertyCellIterator cell_iter(this);
while (cell_iter.hasNext()) {
LibertyCell *cell = cell_iter.next();
if (pattern->match(cell->name()))
cells->push_back(cell);
matches.push_back(cell);
}
return matches;
}
LibertyCellSeq *
@ -790,7 +791,7 @@ LibertyLibrary::checkCorners(LibertyCell *cell,
for (const Corner *corner : *corners) {
for (auto min_max : MinMax::range()) {
if (!cell->checkCornerCell(corner, min_max))
report->error(705, "Liberty cell %s/%s for corner %s/%s not found",
report->error(705, "Liberty cell %s/%s for corner %s/%s not found.",
cell->libertyLibrary()->name(),
cell->name(),
corner->name(),
@ -883,7 +884,7 @@ LibertyCellIterator::next()
LibertyCell::LibertyCell(LibertyLibrary *library,
const char *name,
const char *filename) :
ConcreteCell(library, name, true, filename),
ConcreteCell(name, filename, true, library),
liberty_library_(library),
area_(0.0),
dont_use_(false),
@ -940,16 +941,17 @@ LibertyCell::findLibertyPort(const char *name) const
return static_cast<LibertyPort*>(findPort(name));
}
void
LibertyCell::findLibertyPortsMatching(PatternMatch *pattern,
LibertyPortSeq *ports) const
LibertyPortSeq
LibertyCell::findLibertyPortsMatching(PatternMatch *pattern) const
{
LibertyPortSeq matches;
LibertyCellPortIterator port_iter(this);
while (port_iter.hasNext()) {
LibertyPort *port = port_iter.next();
if (pattern->match(port->name()))
ports->push_back(port);
matches.push_back(port);
}
return matches;
}
void
@ -1570,9 +1572,9 @@ bool
LibertyCell::checkCornerCell(const Corner *corner,
const MinMax *min_max) const
{
int lib_index = corner->libertyIndex(min_max);
unsigned lib_index = corner->libertyIndex(min_max);
return corner_cells_.empty()
|| (lib_index <= static_cast<int>(corner_cells_.size())
|| (lib_index < corner_cells_.size()
&& corner_cells_[lib_index]);
}
@ -1904,7 +1906,7 @@ LibertyPort::LibertyPort(LibertyCell *cell,
int to_index,
bool is_bundle,
ConcretePortSeq *members) :
ConcretePort(cell, name, is_bus, from_index, to_index, is_bundle, members),
ConcretePort(name, is_bus, from_index, to_index, is_bundle, members, cell),
liberty_cell_(cell),
bus_dcl_(bus_dcl),
function_(nullptr),
@ -2492,14 +2494,14 @@ LibertyPort::setRelatedPowerPin(const char *related_power_pin)
////////////////////////////////////////////////////////////////
void
sortLibertyPortSet(LibertyPortSet *set,
LibertyPortSeq &ports)
LibertyPortSeq
sortByName(const LibertyPortSet *set)
{
LibertyPortSet::Iterator port_iter(set);
while (port_iter.hasNext())
ports.push_back(port_iter.next());
LibertyPortSeq ports;
for (LibertyPort *port : *set)
ports.push_back(port);
sort(ports, LibertyPortNameLess());
return ports;
}
bool
@ -2509,22 +2511,15 @@ LibertyPortNameLess::operator()(const LibertyPort *port1,
return stringLess(port1->name(), port2->name());
}
bool
LibertyPortPairLess::operator()(const LibertyPortPair *pair1,
const LibertyPortPair *pair2) const
{
return pair1->first < pair2->first
|| (pair1->first == pair2->first
&& pair1->second < pair2->second);
}
bool
LibertyPortPairLess::operator()(const LibertyPortPair &pair1,
const LibertyPortPair &pair2) const
{
return pair1.first < pair2.first
|| (pair1.first == pair2.first
&& pair1.second < pair2.second);
ObjectId id1 = pair1.first->id();
ObjectId id2 = pair2.first->id();
return id1 < id2
|| (id1 == id2
&& pair1.second->id() < pair2.second->id());
}
////////////////////////////////////////////////////////////////

4
liberty/TimingArc.cc
View File

@ -583,8 +583,8 @@ TimingArc::setIndex(unsigned index)
index_ = index;
}
TimingArc *
TimingArc::cornerArc(int ap_index)
const TimingArc *
TimingArc::cornerArc(int ap_index) const
{
if (ap_index < static_cast<int>(corner_arcs_.size())) {
TimingArc *corner_arc = corner_arcs_[ap_index];

57
network/ConcreteLibrary.cc
View File

@ -21,6 +21,7 @@
#include "PatternMatch.hh"
#include "PortDirection.hh"
#include "ParseBus.hh"
#include "ConcreteNetwork.hh"
namespace sta {
@ -30,6 +31,7 @@ ConcreteLibrary::ConcreteLibrary(const char *name,
const char *filename,
bool is_liberty) :
name_(stringCopy(name)),
id_(ConcreteNetwork::nextObjectId()),
filename_(stringCopy(filename)),
is_liberty_(is_liberty),
bus_brkt_left_('['),
@ -49,7 +51,7 @@ ConcreteLibrary::makeCell(const char *name,
bool is_leaf,
const char *filename)
{
ConcreteCell *cell = new ConcreteCell(this, name, is_leaf, filename);
ConcreteCell *cell = new ConcreteCell(name, filename, is_leaf, this);
addCell(cell);
return cell;
}
@ -87,16 +89,17 @@ ConcreteLibrary::findCell(const char *name) const
return cell_map_.findKey(name);
}
void
ConcreteLibrary::findCellsMatching(const PatternMatch *pattern,
CellSeq *cells) const
CellSeq
ConcreteLibrary::findCellsMatching(const PatternMatch *pattern) const
{
CellSeq matches;
ConcreteLibraryCellIterator cell_iter=ConcreteLibraryCellIterator(cell_map_);
while (cell_iter.hasNext()) {
ConcreteCell *cell = cell_iter.next();
if (pattern->match(cell->name()))
cells->push_back(reinterpret_cast<Cell*>(cell));
matches.push_back(reinterpret_cast<Cell*>(cell));
}
return matches;
}
void
@ -109,13 +112,14 @@ ConcreteLibrary::setBusBrkts(char left,
////////////////////////////////////////////////////////////////
ConcreteCell::ConcreteCell(ConcreteLibrary *library,
const char *name,
ConcreteCell::ConcreteCell(const char *name,
const char *filename,
bool is_leaf,
const char *filename):
library_(library),
ConcreteLibrary *library) :
name_(stringCopy(name)),
id_(ConcreteNetwork::nextObjectId()),
filename_(stringCopy(filename)),
library_(library),
liberty_cell_(nullptr),
ext_cell_(nullptr),
port_bit_count_(0),
@ -155,7 +159,7 @@ ConcreteCell::setExtCell(void *ext_cell)
ConcretePort *
ConcreteCell::makePort(const char *name)
{
ConcretePort *port = new ConcretePort(this, name, false, -1, -1, false, nullptr);
ConcretePort *port = new ConcretePort(name, false, -1, -1, false, nullptr, this);
addPort(port);
return port;
}
@ -164,8 +168,7 @@ ConcretePort *
ConcreteCell::makeBundlePort(const char *name,
ConcretePortSeq *members)
{
ConcretePort *port = new ConcretePort(this, name, false, -1, -1,
true, members);
ConcretePort *port = new ConcretePort(name, false, -1, -1, true, members, this);
addPort(port);
return port;
}
@ -175,8 +178,8 @@ ConcreteCell::makeBusPort(const char *name,
int from_index,
int to_index)
{
ConcretePort *port = new ConcretePort(this, name, true, from_index, to_index,
false, new ConcretePortSeq);
ConcretePort *port = new ConcretePort(name, true, from_index, to_index,
false, new ConcretePortSeq, this);
addPort(port);
makeBusPortBits(port, name, from_index, to_index);
return port;
@ -188,8 +191,8 @@ ConcreteCell::makeBusPort(const char *name,
int to_index,
ConcretePortSeq *members)
{
ConcretePort *port = new ConcretePort(this, name, true, from_index, to_index,
false, members);
ConcretePort *port = new ConcretePort(name, true, from_index, to_index,
false, members, this);
addPort(port);
return port;
}
@ -230,8 +233,8 @@ ConcretePort *
ConcreteCell::makePort(const char *bit_name,
int bit_index)
{
ConcretePort *port = new ConcretePort(this, bit_name, false, bit_index,
bit_index, false, nullptr);
ConcretePort *port = new ConcretePort(bit_name, false, bit_index,
bit_index, false, nullptr, this);
addPortBit(port);
return port;
}
@ -270,10 +273,10 @@ ConcreteCell::portCount() const
return ports_.size();
}
void
ConcreteCell::findPortsMatching(const PatternMatch *pattern,
PortSeq *ports) const
PortSeq
ConcreteCell::findPortsMatching(const PatternMatch *pattern) const
{
PortSeq matches;
char bus_brkt_right = library_->busBrktRight();
const char *pattern1 = pattern->pattern();
bool bus_pattern = (pattern1[strlen(pattern1) - 1] == bus_brkt_right);
@ -285,14 +288,15 @@ ConcreteCell::findPortsMatching(const PatternMatch *pattern,
while (member_iter->hasNext()) {
ConcretePort *port_bit = member_iter->next();
if (pattern->match(port_bit->name()))
ports->push_back(reinterpret_cast<Port*>(port_bit));
matches.push_back(reinterpret_cast<Port*>(port_bit));
}
delete member_iter;
}
else if (pattern->match(port->name()))
ports->push_back(reinterpret_cast<Port*>(port));
matches.push_back(reinterpret_cast<Port*>(port));
}
delete port_iter;
return matches;
}
ConcreteCellPortIterator *
@ -456,14 +460,15 @@ ConcreteCell::groupBusPorts(const char bus_brkt_left,
////////////////////////////////////////////////////////////////
ConcretePort::ConcretePort(ConcreteCell *cell,
const char *name,
ConcretePort::ConcretePort(const char *name,
bool is_bus,
int from_index,
int to_index,
bool is_bundle,
ConcretePortSeq *member_ports) :
ConcretePortSeq *member_ports,
ConcreteCell *cell) :
name_(stringCopy(name)),
id_(ConcreteNetwork::nextObjectId()),
cell_(cell),
direction_(PortDirection::unknown()),
liberty_port_(nullptr),

107
network/ConcreteNetwork.cc
View File

@ -39,6 +39,9 @@ makeClonePins(Instance *proto,
ConcreteBindingTbl *parent_bindings,
NetworkReader *network);
////////////////////////////////////////////////////////////////
NetworkReader *
makeConcreteNetwork()
{
@ -243,9 +246,12 @@ ConcreteNetTermIterator::next()
////////////////////////////////////////////////////////////////
ObjectId ConcreteNetwork::object_id_ = 0;
ConcreteNetwork::ConcreteNetwork() :
NetworkReader(),
top_instance_(nullptr),
constant_nets_{NetSet(this), NetSet(this)},
link_func_(nullptr)
{
}
@ -443,6 +449,14 @@ ConcreteNetwork::name(const Library *library) const
return clib->name();
}
ObjectId
ConcreteNetwork::id(const Library *library) const
{
const ConcreteLibrary *clib =
reinterpret_cast<const ConcreteLibrary*>(library);
return clib->id();
}
LibertyLibrary *
ConcreteNetwork::findLiberty(const char *name)
{
@ -501,14 +515,13 @@ ConcreteNetwork::findAnyCell(const char *name)
return nullptr;
}
void
CellSeq
ConcreteNetwork::findCellsMatching(const Library *library,
const PatternMatch *pattern,
CellSeq *cells) const
const PatternMatch *pattern) const
{
const ConcreteLibrary *clib =
reinterpret_cast<const ConcreteLibrary*>(library);
clib->findCellsMatching(pattern, cells);
return clib->findCellsMatching(pattern);
}
void
@ -528,6 +541,13 @@ ConcreteNetwork::name(const Cell *cell) const
return ccell->name();
}
ObjectId
ConcreteNetwork::id(const Cell *cell) const
{
const ConcreteCell *ccell = reinterpret_cast<const ConcreteCell*>(cell);
return ccell->id();
}
void
ConcreteNetwork::setName(Cell *cell,
const char *name)
@ -592,13 +612,12 @@ ConcreteNetwork::findPort(const Cell *cell,
return reinterpret_cast<Port*>(ccell->findPort(name));
}
void
PortSeq
ConcreteNetwork::findPortsMatching(const Cell *cell,
const PatternMatch *pattern,
PortSeq *ports) const
const PatternMatch *pattern) const
{
const ConcreteCell *ccell = reinterpret_cast<const ConcreteCell*>(cell);
ccell->findPortsMatching(pattern, ports);
return ccell->findPortsMatching(pattern);
}
bool
@ -635,7 +654,8 @@ ConcreteNetwork::groupBusPorts(Cell *cell,
Library *lib = library(cell);
ConcreteLibrary *clib = reinterpret_cast<ConcreteLibrary*>(lib);
ConcreteCell *ccell = reinterpret_cast<ConcreteCell*>(cell);
ccell->groupBusPorts(clib->busBrktLeft(), clib->busBrktRight(), port_msb_first);
ccell->groupBusPorts(clib->busBrktLeft(), clib->busBrktRight(),
port_msb_first);
}
Port *
@ -657,6 +677,12 @@ ConcreteNetwork::setDirection(Port *port,
cport->setDirection(dir);
}
ObjectId
ConcreteNetwork::nextObjectId()
{
return object_id_++;
}
////////////////////////////////////////////////////////////////
class ConcreteCellPortIterator1 : public CellPortIterator
@ -747,6 +773,13 @@ ConcreteNetwork::name(const Port *port) const
return cport->name();
}
ObjectId
ConcreteNetwork::id(const Port *port) const
{
const ConcretePort *cport = reinterpret_cast<const ConcretePort*>(port);
return cport->id();
}
Cell *
ConcreteNetwork::cell(const Port *port) const
{
@ -881,6 +914,14 @@ ConcreteNetwork::name(const Instance *instance) const
return inst->name();
}
ObjectId
ConcreteNetwork::id(const Instance *instance) const
{
const ConcreteInstance *inst =
reinterpret_cast<const ConcreteInstance*>(instance);
return inst->id();
}
Cell *
ConcreteNetwork::cell(const Instance *instance) const
{
@ -945,11 +986,11 @@ ConcreteNetwork::findNet(const Instance *instance,
void
ConcreteNetwork::findInstNetsMatching(const Instance *instance,
const PatternMatch *pattern,
NetSeq *nets) const
NetSeq &matches) const
{
const ConcreteInstance *inst =
reinterpret_cast<const ConcreteInstance*>(instance);
inst->findNetsMatching(pattern, nets);
return inst->findNetsMatching(pattern, matches);
}
////////////////////////////////////////////////////////////////
@ -982,6 +1023,13 @@ ConcreteNetwork::netIterator(const Instance *instance) const
////////////////////////////////////////////////////////////////
ObjectId
ConcreteNetwork::id(const Pin *pin) const
{
const ConcretePin *cpin = reinterpret_cast<const ConcretePin*>(pin);
return cpin->id();
}
Instance *
ConcreteNetwork::instance(const Pin *pin) const
{
@ -1035,6 +1083,13 @@ ConcreteNetwork::setVertexId(Pin *pin,
////////////////////////////////////////////////////////////////
ObjectId
ConcreteNetwork::id(const Term *term) const
{
const ConcreteTerm *cterm = reinterpret_cast<const ConcreteTerm*>(term);
return cterm->id();
}
Net *
ConcreteNetwork::net(const Term *term) const
{
@ -1058,6 +1113,13 @@ ConcreteNetwork::name(const Net *net) const
return cnet->name();
}
ObjectId
ConcreteNetwork::id(const Net *net) const
{
const ConcreteNet *cnet = reinterpret_cast<const ConcreteNet*>(net);
return cnet->id();
}
Instance *
ConcreteNetwork::instance(const Net *net) const
{
@ -1140,7 +1202,7 @@ ConcreteNetwork::makeConcreteInstance(ConcreteCell *cell,
{
ConcreteInstance *cparent =
reinterpret_cast<ConcreteInstance*>(parent);
ConcreteInstance *inst = new ConcreteInstance(cell, name, cparent);
ConcreteInstance *inst = new ConcreteInstance(name, cell, cparent);
if (parent)
cparent->addChild(inst);
return reinterpret_cast<Instance*>(inst);
@ -1176,6 +1238,7 @@ ConcreteNetwork::replaceCell(Instance *inst,
if (cport) {
rpins[cport->pinIndex()] = cpin;
cpin->port_ = cport;
cpin->id_ = ConcreteNetwork::nextObjectId();
}
}
}
@ -1443,7 +1506,7 @@ ConcreteNetwork::constantPinIterator()
void
ConcreteNetwork::visitConnectedPins(const Net *net,
PinVisitor &visitor,
ConstNetSet &visited_nets) const
NetSet &visited_nets) const
{
if (!visited_nets.hasKey(net)) {
visited_nets.insert(net);
@ -1477,11 +1540,12 @@ ConcreteNetwork::visitConnectedPins(const Net *net,
////////////////////////////////////////////////////////////////
ConcreteInstance::ConcreteInstance(ConcreteCell *cell,
const char *name,
ConcreteInstance *parent) :
cell_(cell),
ConcreteInstance::ConcreteInstance(const char *name,
ConcreteCell *cell,
ConcreteInstance *parent) :
name_(stringCopy(name)),
id_(ConcreteNetwork::nextObjectId()),
cell_(cell),
parent_(parent),
children_(nullptr),
nets_(nullptr)
@ -1556,7 +1620,7 @@ ConcreteInstance::findNet(const char *net_name) const
void
ConcreteInstance::findNetsMatching(const PatternMatch *pattern,
NetSeq *nets) const
NetSeq &matches) const
{
if (pattern->hasWildcards()) {
ConcreteInstanceNetMap::Iterator net_iter(nets_);
@ -1565,13 +1629,13 @@ ConcreteInstance::findNetsMatching(const PatternMatch *pattern,
ConcreteNet *cnet;
net_iter.next(net_name, cnet);
if (pattern->match(net_name))
nets->push_back(reinterpret_cast<Net*>(cnet));
matches.push_back(reinterpret_cast<Net*>(cnet));
}
}
else {
ConcreteNet *cnet = findNet(pattern->pattern());
if (cnet)
nets->push_back(reinterpret_cast<Net*>(cnet));
matches.push_back(reinterpret_cast<Net*>(cnet));
}
}
@ -1654,6 +1718,7 @@ ConcretePin::ConcretePin(ConcreteInstance *instance,
port_(port),
net_(net),
term_(nullptr),
id_(ConcreteNetwork::nextObjectId()),
net_next_(nullptr),
net_prev_(nullptr),
vertex_id_(vertex_id_null)
@ -1687,6 +1752,7 @@ ConcreteTerm::ConcreteTerm(ConcretePin *pin,
ConcreteNet *net) :
pin_(pin),
net_(net),
id_(ConcreteNetwork::nextObjectId()),
net_next_(nullptr)
{
}
@ -1696,6 +1762,7 @@ ConcreteTerm::ConcreteTerm(ConcretePin *pin,
ConcreteNet::ConcreteNet(const char *name,
ConcreteInstance *instance) :
name_(stringCopy(name)),
id_(ConcreteNetwork::nextObjectId()),
instance_(instance),
pins_(nullptr),
terms_(nullptr),

30
network/HpinDrvrLoad.cc
View File

@ -51,10 +51,10 @@ visitHpinDrvrLoads(const Pin *pin,
const Network *network,
HpinDrvrLoadVisitor *visitor)
{
NetSet visited;
NetSet visited(network);
HpinDrvrLoads above_drvrs;
HpinDrvrLoads above_loads;
PinSet hpin_path;
PinSet hpin_path(network);
Net *above_net = network->net(pin);
if (above_net) {
visitPinsAboveNet2(pin, above_net, visited,
@ -113,7 +113,7 @@ visitPinsAboveNet2(const Pin *hpin,
// Visit above net pins.
NetPinIterator *pin_iter = network->pinIterator(above_net);
while (pin_iter->hasNext()) {
Pin *above_pin = pin_iter->next();
const Pin *above_pin = pin_iter->next();
if (above_pin != hpin) {
if (network->isDriver(above_pin)) {
HpinDrvrLoad *drvr = new HpinDrvrLoad(above_pin, nullptr,
@ -185,7 +185,7 @@ visitPinsBelowNet2(const Pin *hpin,
// Visit below net pins.
NetPinIterator *pin_iter = network->pinIterator(below_net);
while (pin_iter->hasNext()) {
Pin *below_pin = pin_iter->next();
const Pin *below_pin = pin_iter->next();
if (below_pin != hpin) {
if (above_net && !visited.hasKey(above_net))
visitPinsAboveNet2(below_pin, above_net,
@ -260,8 +260,8 @@ visitHpinDrvrLoads(HpinDrvrLoads drvrs,
////////////////////////////////////////////////////////////////
HpinDrvrLoad::HpinDrvrLoad(Pin *drvr,
Pin *load,
HpinDrvrLoad::HpinDrvrLoad(const Pin *drvr,
const Pin *load,
PinSet *hpins_from_drvr,
PinSet *hpins_to_load) :
drvr_(drvr),
@ -271,8 +271,8 @@ HpinDrvrLoad::HpinDrvrLoad(Pin *drvr,
{
}
HpinDrvrLoad::HpinDrvrLoad(Pin *drvr,
Pin *load) :
HpinDrvrLoad::HpinDrvrLoad(const Pin *drvr,
const Pin *load) :
drvr_(drvr),
load_(load)
{
@ -292,20 +292,20 @@ HpinDrvrLoad::report(const Network *network)
load_ ? network->pathName(load_) : "-");
PinSet::Iterator pin_iter(hpins_from_drvr_);
while (pin_iter.hasNext()) {
Pin *pin = pin_iter.next();
const Pin *pin = pin_iter.next();
printf("%s ", network->pathName(pin));
}
printf("* ");
PinSet::Iterator pin_iter2(hpins_to_load_);
while (pin_iter2.hasNext()) {
Pin *pin = pin_iter2.next();
const Pin *pin = pin_iter2.next();
printf("%s ", network->pathName(pin));
}
printf("\n");
}
void
HpinDrvrLoad::setDrvr(Pin *drvr)
HpinDrvrLoad::setDrvr(const Pin *drvr)
{
drvr_ = drvr;
}
@ -314,11 +314,11 @@ bool
HpinDrvrLoadLess::operator()(const HpinDrvrLoad *drvr_load1,
const HpinDrvrLoad *drvr_load2) const
{
Pin *load1 = drvr_load1->load();
Pin *load2 = drvr_load2->load();
const Pin *load1 = drvr_load1->load();
const Pin *load2 = drvr_load2->load();
if (load1 == load2) {
Pin *drvr1 = drvr_load1->drvr();
Pin *drvr2 = drvr_load2->drvr();
const Pin *drvr1 = drvr_load1->drvr();
const Pin *drvr2 = drvr_load2->drvr();
return drvr1 < drvr2;
}
else

447
network/Network.cc
View File

@ -191,10 +191,10 @@ Network::hasMembers(const Port *port) const
const char *
Network::pathName(const Instance *instance) const
{
ConstInstanceSeq inst_path;
InstanceSeq inst_path;
path(instance, inst_path);
size_t name_length = 0;
ConstInstanceSeq::Iterator path_iter1(inst_path);
InstanceSeq::Iterator path_iter1(inst_path);
while (path_iter1.hasNext()) {
const Instance *inst = path_iter1.next();
name_length += strlen(name(inst)) + 1;
@ -234,8 +234,8 @@ Network::pathNameCmp(const Instance *inst1,
else if (inst1 == inst2)
return 0;
else {
ConstInstanceSeq path1;
ConstInstanceSeq path2;
InstanceSeq path1;
InstanceSeq path2;
path(inst1, path1);
path(inst2, path2);
while (!path1.empty() && !path2.empty()) {
@ -259,7 +259,7 @@ Network::pathNameCmp(const Instance *inst1,
void
Network::path(const Instance *inst,
// Return value.
ConstInstanceSeq &path) const
InstanceSeq &path) const
{
while (!isTopInstance(inst)) {
path.push_back(inst);
@ -454,16 +454,16 @@ Network::highestNetAbove(Net *net) const
return highest_net;
}
Net *
const Net *
Network::highestConnectedNet(Net *net) const
{
NetSet nets;
NetSet nets(this);
connectedNets(net, &nets);
Net *highest_net = net;
const Net *highest_net = net;
int highest_level = hierarchyLevel(net);
NetSet::Iterator net_iter(nets);
while (net_iter.hasNext()) {
Net *net1 = net_iter.next();
const Net *net1 = net_iter.next();
int level = hierarchyLevel(net1);
if (level < highest_level
|| (level == highest_level
@ -497,7 +497,7 @@ Network::connectedNets(Net *net,
// Search down from net pins.
NetPinIterator *pin_iter = pinIterator(net);
while (pin_iter->hasNext()) {
Pin *pin1 = pin_iter->next();
const Pin *pin1 = pin_iter->next();
Term *below_term = term(pin1);
if (below_term) {
Net *below_net = this->net(below_term);
@ -653,30 +653,31 @@ Network::findInstanceRelative(const Instance *inst,
return findChild(inst, path_name);
}
void
InstanceSeq
Network::findInstancesMatching(const Instance *context,
const PatternMatch *pattern,
InstanceSeq *insts) const
const PatternMatch *pattern) const
{
InstanceSeq matches;
if (pattern->hasWildcards()) {
size_t context_name_length = 0;
if (context != topInstance())
// Add one for the trailing divider.
context_name_length = strlen(pathName(context)) + 1;
findInstancesMatching1(context, context_name_length, pattern, insts);
findInstancesMatching1(context, context_name_length, pattern, matches);
}
else {
Instance *inst = findInstanceRelative(context, pattern->pattern());
if (inst)
insts->push_back(inst);
matches.push_back(inst);
}
return matches;
}
void
Network::findInstancesMatching1(const Instance *context,
size_t context_name_length,
const PatternMatch *pattern,
InstanceSeq *insts) const
InstanceSeq &matches) const
{
InstanceChildIterator *child_iter = childIterator(context);
while (child_iter->hasNext()) {
@ -685,26 +686,34 @@ Network::findInstancesMatching1(const Instance *context,
// Remove context prefix from the name.
const char *child_context_name = &child_name[context_name_length];
if (pattern->match(child_context_name))
insts->push_back(child);
matches.push_back(child);
if (!isLeaf(child))
findInstancesMatching1(child, context_name_length, pattern, insts);
findInstancesMatching1(child, context_name_length, pattern, matches);
}
delete child_iter;
}
void
InstanceSeq
Network::findInstancesHierMatching(const Instance *instance,
const PatternMatch *pattern,
// Return value.
InstanceSeq *insts) const
const PatternMatch *pattern) const
{
InstanceSeq matches;
findInstancesHierMatching1(instance, pattern, matches);
return matches;
}
void
Network::findInstancesHierMatching1(const Instance *instance,
const PatternMatch *pattern,
InstanceSeq &matches) const
{
InstanceChildIterator *child_iter = childIterator(instance);
while (child_iter->hasNext()) {
Instance *child = child_iter->next();
if (pattern->match(name(child)))
insts->push_back(child);
matches.push_back(child);
if (!isLeaf(child))
findInstancesHierMatching(child, pattern, insts);
findInstancesHierMatching1(child, pattern, matches);
}
delete child_iter;
}
@ -712,21 +721,21 @@ Network::findInstancesHierMatching(const Instance *instance,
void
Network::findChildrenMatching(const Instance *parent,
const PatternMatch *pattern,
InstanceSeq *insts) const
InstanceSeq &matches) const
{
if (pattern->hasWildcards()) {
InstanceChildIterator *child_iter = childIterator(parent);
while (child_iter->hasNext()) {
Instance *child = child_iter->next();
if (pattern->match(name(child)))
insts->push_back(child);
matches.push_back(child);
}
delete child_iter;
}
else {
Instance *child = findChild(parent, pattern->pattern());
if (child)
insts->push_back(child);
matches.push_back(child);
}
}
@ -834,10 +843,19 @@ Network::findNetLinear(const Instance *instance,
return nullptr;
}
NetSeq
Network::findNetsMatching(const Instance *context,
const PatternMatch *pattern) const
{
NetSeq matches;
findNetsMatching(context, pattern, matches);
return matches;
}
void
Network::findNetsMatching(const Instance *context,
const PatternMatch *pattern,
NetSeq *nets) const
NetSeq &matches) const
{
if (pattern->hasWildcards()) {
char *inst_path, *net_name;
@ -845,99 +863,116 @@ Network::findNetsMatching(const Instance *context,
if (inst_path) {
PatternMatch inst_pattern(inst_path, pattern);
PatternMatch net_pattern(net_name, pattern);
InstanceSeq insts;
findInstancesMatching(context, &inst_pattern, &insts);
InstanceSeq insts = findInstancesMatching(context, &inst_pattern);
InstanceSeq::Iterator inst_iter(insts);
while (inst_iter.hasNext()) {
Instance *inst = inst_iter.next();
findNetsMatching(inst, &net_pattern, nets);
const Instance *inst = inst_iter.next();
findNetsMatching(inst, &net_pattern, matches);
}
stringDelete(inst_path);
stringDelete(net_name);
}
else
// Top level net.
findInstNetsMatching(context, pattern, nets);
findInstNetsMatching(context, pattern, matches);
}
else {
Net *net = findNet(pattern->pattern());
if (net)
nets->push_back(net);
matches.push_back(net);
}
}
NetSeq
Network::findNetsHierMatching(const Instance *instance,
const PatternMatch *pattern) const
{
NetSeq matches;
findNetsHierMatching(instance, pattern, matches);
return matches;
}
void
Network::findNetsHierMatching(const Instance *instance,
const PatternMatch *pattern,
// Return value.
NetSeq *nets) const
NetSeq &matches) const
{
findInstNetsMatching(instance, pattern, nets);
findInstNetsMatching(instance, pattern, matches);
InstanceChildIterator *child_iter = childIterator(instance);
while (child_iter->hasNext()) {
Instance *child = child_iter->next();
findNetsHierMatching(child, pattern, nets);
findNetsHierMatching(child, pattern, matches);
}
delete child_iter;
}
void
NetSeq
Network::findNetsMatchingLinear(const Instance *instance,
const PatternMatch *pattern,
NetSeq *nets) const
const PatternMatch *pattern) const
{
NetSeq matches;
InstanceNetIterator *net_iter = netIterator(instance);
while (net_iter->hasNext()) {
Net *net = net_iter->next();
if (pattern->match(name(net)))
nets->push_back(net);
matches.push_back(net);
}
delete net_iter;
return matches;
}
void
PinSeq
Network::findPinsMatching(const Instance *instance,
const PatternMatch *pattern,
PinSeq *pins) const
const PatternMatch *pattern) const
{
PinSeq matches;
if (pattern->hasWildcards()) {
char *inst_path, *port_name;
pathNameLast(pattern->pattern(), inst_path, port_name);
if (inst_path) {
PatternMatch inst_pattern(inst_path, pattern);
PatternMatch port_pattern(port_name, pattern);
InstanceSeq insts;
findInstancesMatching(instance, &inst_pattern, &insts);
InstanceSeq insts = findInstancesMatching(instance, &inst_pattern);
InstanceSeq::Iterator inst_iter(insts);
while (inst_iter.hasNext()) {
Instance *inst = inst_iter.next();
findInstPinsMatching(inst, &port_pattern, pins);
const Instance *inst = inst_iter.next();
findInstPinsMatching(inst, &port_pattern, matches);
}
stringDelete(inst_path);
stringDelete(port_name);
}
else
// Top level pin.
findInstPinsMatching(instance, pattern, pins);
findInstPinsMatching(instance, pattern, matches);
}
else {
Pin *pin = findPin(pattern->pattern());
if (pin)
pins->push_back(pin);
matches.push_back(pin);
}
return matches;
}
PinSeq
Network::findPinsHierMatching(const Instance *instance,
const PatternMatch *pattern) const
{
PinSeq matches;
findPinsHierMatching(instance, pattern, matches);
return matches;
}
void
Network::findPinsHierMatching(const Instance *instance,
const PatternMatch *pattern,
// Return value.
PinSeq *pins) const
// Return value.
PinSeq &matches) const
{
InstanceChildIterator *child_iter = childIterator(instance);
while (child_iter->hasNext()) {
Instance *child = child_iter->next();
findInstPinsHierMatching(child, pattern, pins);
findPinsHierMatching(child, pattern, pins);
findInstPinsHierMatching(child, pattern, matches);
findPinsHierMatching(child, pattern, matches);
}
delete child_iter;
}
@ -946,17 +981,17 @@ void
Network::findInstPinsHierMatching(const Instance *instance,
const PatternMatch *pattern,
// Return value.
PinSeq *pins) const
PinSeq &matches) const
{
const char *inst_name = name(instance);
InstancePinIterator *pin_iter = pinIterator(instance);
while (pin_iter->hasNext()) {
Pin *pin = pin_iter->next();
const Pin *pin = pin_iter->next();
const char *port_name = name(port(pin));
string pin_name;
stringPrint(pin_name, "%s%c%s", inst_name,divider_, port_name);
if (pattern->match(pin_name.c_str()))
pins->push_back(pin);
matches.push_back(pin);
}
delete pin_iter;
}
@ -964,21 +999,21 @@ Network::findInstPinsHierMatching(const Instance *instance,
void
Network::findInstPinsMatching(const Instance *instance,
const PatternMatch *pattern,
PinSeq *pins) const
PinSeq &matches) const
{
if (pattern->hasWildcards()) {
InstancePinIterator *pin_iter = pinIterator(instance);
while (pin_iter->hasNext()) {
Pin *pin = pin_iter->next();
const Pin *pin = pin_iter->next();
if (pattern->match(name(pin)))
pins->push_back(pin);
matches.push_back(pin);
}
delete pin_iter;
}
else {
Pin *pin = findPin(instance, pattern->pattern());
if (pin)
pins->push_back(pin);
matches.push_back(pin);
}
}
@ -1188,10 +1223,10 @@ Network::leafInstanceIterator(const Instance *hier_inst) const
////////////////////////////////////////////////////////////////
void
Network::visitConnectedPins(Pin *pin,
Network::visitConnectedPins(const Pin *pin,
PinVisitor &visitor) const
{
ConstNetSet visited_nets;
NetSet visited_nets(network_);
Net *pin_net = net(pin);
Term *pin_term = term(pin);
if (pin_net)
@ -1212,14 +1247,14 @@ void
Network::visitConnectedPins(const Net *net,
PinVisitor &visitor) const
{
ConstNetSet visited_nets;
NetSet visited_nets(this);
visitConnectedPins(net, visitor, visited_nets);
}
void
Network::visitConnectedPins(const Net *net,
PinVisitor &visitor,
ConstNetSet &visited_nets) const
NetSet &visited_nets) const
{
if (!visited_nets.hasKey(net)) {
visited_nets.insert(net);
@ -1241,7 +1276,7 @@ Network::visitConnectedPins(const Net *net,
// Search down from net pins.
NetPinIterator *pin_iter = pinIterator(net);
while (pin_iter->hasNext()) {
Pin *pin = pin_iter->next();
const Pin *pin = pin_iter->next();
visitor(pin);
Term *below_term = term(pin);
if (below_term) {
@ -1262,7 +1297,7 @@ public:
explicit ConnectedPinIterator1(PinSet *pins);
virtual ~ConnectedPinIterator1();
virtual bool hasNext();
virtual Pin *next();
virtual const Pin *next();
protected:
PinSet::Iterator pin_iter_;
@ -1284,7 +1319,7 @@ ConnectedPinIterator1::hasNext()
return pin_iter_.hasNext();
}
Pin *
const Pin *
ConnectedPinIterator1::next()
{
return pin_iter_.next();
@ -1294,7 +1329,7 @@ class FindConnectedPins : public PinVisitor
{
public:
explicit FindConnectedPins(PinSet *pins);
virtual void operator()(Pin *pin);
virtual void operator()(const Pin *pin);
protected:
PinSet *pins_;
@ -1307,7 +1342,7 @@ FindConnectedPins::FindConnectedPins(PinSet *pins) :
}
void
FindConnectedPins::operator()(Pin *pin)
FindConnectedPins::operator()(const Pin *pin)
{
pins_->insert(pin);
}
@ -1315,7 +1350,7 @@ FindConnectedPins::operator()(Pin *pin)
NetConnectedPinIterator *
Network::connectedPinIterator(const Net *net) const
{
PinSet *pins = new PinSet;
PinSet *pins = new PinSet(this);
FindConnectedPins visitor(pins);
visitConnectedPins(net, visitor);
return new ConnectedPinIterator1(pins);
@ -1324,7 +1359,7 @@ Network::connectedPinIterator(const Net *net) const
PinConnectedPinIterator *
Network::connectedPinIterator(const Pin *pin) const
{
PinSet *pins = new PinSet;
PinSet *pins = new PinSet(this);
pins->insert(const_cast<Pin*>(pin));
FindConnectedPins visitor(pins);
@ -1351,7 +1386,7 @@ Network::isConnected(const Net *net,
if (this->net(pin) == net)
return true;
else {
ConstNetSet nets;
NetSet nets(this);
return isConnected(net, pin, nets);
}
}
@ -1359,7 +1394,7 @@ Network::isConnected(const Net *net,
bool
Network::isConnected(const Net *net,
const Pin *pin,
ConstNetSet &nets) const
NetSet &nets) const
{
if (!nets.hasKey(net)) {
nets.insert(net);
@ -1387,7 +1422,7 @@ Network::isConnected(const Net *net,
// Search down from net pins.
NetPinIterator *pin_iter = pinIterator(net);
while (pin_iter->hasNext()) {
Pin *pin1 = pin_iter->next();
const Pin *pin1 = pin_iter->next();
if (pin1 == pin) {
delete pin_iter;
return true;
@ -1412,14 +1447,14 @@ bool
Network::isConnected(const Net *net1,
const Net *net2) const
{
ConstNetSet nets;
NetSet nets(this);
return isConnected(net1, net2, nets);
}
bool
Network::isConnected(const Net *net1,
const Net *net2,
ConstNetSet &nets) const
NetSet &nets) const
{
if (net1 == net2)
return true;
@ -1443,7 +1478,7 @@ Network::isConnected(const Net *net1,
// Search down from net pins.
NetPinIterator *pin_iter = pinIterator(net1);
while (pin_iter->hasNext()) {
Pin *pin1 = pin_iter->next();
const Pin *pin1 = pin_iter->next();
Term *below_term = term(pin1);
if (below_term) {
Net *below_net = net(below_term);
@ -1465,7 +1500,7 @@ class FindDrvrPins : public PinVisitor
public:
explicit FindDrvrPins(PinSet *pins,
const Network *network);
virtual void operator()(Pin *pin);
virtual void operator()(const Pin *pin);
protected:
PinSet *pins_;
@ -1481,7 +1516,7 @@ FindDrvrPins::FindDrvrPins(PinSet *pins,
}
void
FindDrvrPins::operator()(Pin *pin)
FindDrvrPins::operator()(const Pin *pin)
{
if (network_->isDriver(pin))
pins_->insert(pin);
@ -1508,7 +1543,7 @@ Network::drivers(const Net *net)
{
PinSet *drvrs = net_drvr_pin_map_.findKey(net);
if (drvrs == nullptr) {
drvrs = new PinSet;
drvrs = new PinSet(this);
FindDrvrPins visitor(drvrs, this);
visitConnectedPins(net, visitor);
net_drvr_pin_map_[net] = drvrs;
@ -1601,7 +1636,8 @@ NetworkConstantPinIterator(const Network *network,
NetSet &zero_nets,
NetSet &one_nets) :
ConstantPinIterator(),
network_(network)
network_(network),
constant_pins_{PinSet(network), PinSet(network)}
{
findConstantPins(zero_nets, constant_pins_[0]);
findConstantPins(one_nets, constant_pins_[1]);
@ -1623,7 +1659,7 @@ NetworkConstantPinIterator::findConstantPins(NetSet &nets,
const Net *net = net_iter.next();
NetConnectedPinIterator *pin_iter = network_->connectedPinIterator(net);
while (pin_iter->hasNext()) {
Pin *pin = pin_iter->next();
const Pin *pin = pin_iter->next();
pins.insert(pin);
}
delete pin_iter;
@ -1646,7 +1682,7 @@ NetworkConstantPinIterator::hasNext()
}
void
NetworkConstantPinIterator::next(Pin *&pin,
NetworkConstantPinIterator::next(const Pin *&pin,
LogicValue &value)
{
pin = pin_iter_->next();
@ -1655,7 +1691,7 @@ NetworkConstantPinIterator::next(Pin *&pin,
////////////////////////////////////////////////////////////////
FindNetDrvrLoads::FindNetDrvrLoads(Pin *drvr_pin,
FindNetDrvrLoads::FindNetDrvrLoads(const Pin *drvr_pin,
PinSet &visited_drvrs,
PinSeq &loads,
PinSeq &drvrs,
@ -1669,7 +1705,7 @@ FindNetDrvrLoads::FindNetDrvrLoads(Pin *drvr_pin,
}
void
FindNetDrvrLoads::operator()(Pin *pin)
FindNetDrvrLoads::operator()(const Pin *pin)
{
if (network_->isLoad(pin))
loads_.push_back(pin);
@ -1694,7 +1730,7 @@ visitPinsAboveNet1(const Pin *hpin,
// Visit above net pins.
NetPinIterator *pin_iter = network->pinIterator(above_net);
while (pin_iter->hasNext()) {
Pin *above_pin = pin_iter->next();
const Pin *above_pin = pin_iter->next();
if (above_pin != hpin) {
if (network->isDriver(above_pin))
above_drvrs.insert(above_pin);
@ -1743,9 +1779,9 @@ visitPinsBelowNet1(const Pin *hpin,
// Visit below net pins.
NetPinIterator *pin_iter = network->pinIterator(below_net);
while (pin_iter->hasNext()) {
Pin *below_pin = pin_iter->next();
const Pin *below_pin = pin_iter->next();
if (below_pin != hpin) {
NetSet visited_above;
NetSet visited_above(network);
if (network->isDriver(below_pin))
below_drvrs.insert(below_pin);
if (network->isLoad(below_pin))
@ -1771,10 +1807,10 @@ visitDrvrLoads(PinSet drvrs,
{
PinSet::Iterator drvr_iter(drvrs);
while (drvr_iter.hasNext()) {
Pin *drvr = drvr_iter.next();
const Pin *drvr = drvr_iter.next();
PinSet::Iterator load_iter(loads);
while (load_iter.hasNext()) {
Pin *load = load_iter.next();
const Pin *load = load_iter.next();
visitor->visit(drvr, load);
}
}
@ -1792,13 +1828,13 @@ visitDrvrLoadsThruHierPin(const Pin *hpin,
if (term) {
Net *below_net = network->net(term);
if (below_net) {
NetSet visited;
PinSet above_drvrs;
PinSet above_loads;
NetSet visited(network);
PinSet above_drvrs(network);
PinSet above_loads(network);
visitPinsAboveNet1(hpin, above_net, visited,
above_drvrs, above_loads, network);
PinSet below_drvrs;
PinSet below_loads;
PinSet below_drvrs(network);
PinSet below_loads(network);
visitPinsBelowNet1(hpin, below_net, visited,
below_drvrs, below_loads, network);
visitDrvrLoads(above_drvrs, below_loads, visitor);
@ -1809,20 +1845,20 @@ visitDrvrLoadsThruHierPin(const Pin *hpin,
}
void
visitDrvrLoadsThruNet(Net *net,
visitDrvrLoadsThruNet(const Net *net,
const Network *network,
HierPinThruVisitor *visitor)
{
NetSet visited;
PinSet above_drvrs;
PinSet above_loads;
PinSet below_drvrs;
PinSet below_loads;
PinSet net_drvrs;
PinSet net_loads;
NetSet visited(network);
PinSet above_drvrs(network);
PinSet above_loads(network);
PinSet below_drvrs(network);
PinSet below_loads(network);
PinSet net_drvrs(network);
PinSet net_loads(network);
NetPinIterator *pin_iter = network->pinIterator(net);
while (pin_iter->hasNext()) {
Pin *pin = pin_iter->next();
const Pin *pin = pin_iter->next();
if (network->isHierarchical(pin)) {
// Search down from pin terminal.
const Term *term = network->term(pin);
@ -1877,13 +1913,200 @@ logicValueString(LogicValue value)
return str[int(value)];
}
bool
PortPairLess::operator()(const PortPair *pair1,
const PortPair *pair2) const
////////////////////////////////////////////////////////////////
CellIdLess::CellIdLess(const Network *network) :
network_(network)
{
return pair1->first < pair2->first
|| (pair1->first == pair2->first
&& pair1->second < pair2->second);
}
bool
CellIdLess::operator()(const Cell *cell1,
const Cell *cell2) const
{
return network_->id(cell1) < network_->id(cell2);
}
PortIdLess::PortIdLess(const Network *network) :
network_(network)
{
}
bool
PortIdLess::operator()(const Port *port1,
const Port *port2) const
{
return network_->id(port1) < network_->id(port2);
}
InstanceIdLess::InstanceIdLess(const Network *network) :
network_(network)
{
}
bool
InstanceIdLess::operator()(const Instance *inst1,
const Instance *inst2) const
{
return network_->id(inst1) < network_->id(inst2);
}
PinIdLess::PinIdLess(const Network *network) :
network_(network)
{
}
bool
PinIdLess::operator()(const Pin *pin1,
const Pin *pin2) const
{
return network_->id(pin1) < network_->id(pin2);
}
PinIdHash::PinIdHash(const Network *network) :
network_(network)
{
}
size_t
PinIdHash::operator()(const Pin *pin) const
{
return network_->id(pin);
}
NetIdLess::NetIdLess(const Network *network) :
network_(network)
{
}
bool
NetIdLess::operator()(const Net *net1,
const Net *net2) const
{
return network_->id(net1) < network_->id(net2);
}
////////////////////////////////////////////////////////////////
CellSet::CellSet(const Network *network) :
Set<const Cell*, CellIdLess>(CellIdLess(network))
{
}
PortSet::PortSet(const Network *network) :
Set<const Port*, PortIdLess>(PortIdLess(network))
{
}
InstanceSet::InstanceSet() :
Set<const Instance*, InstanceIdLess>(InstanceIdLess(nullptr))
{
}
InstanceSet::InstanceSet(const Network *network) :
Set<const Instance*, InstanceIdLess>(InstanceIdLess(network))
{
}
int
InstanceSet::compare(const InstanceSet *set1,
const InstanceSet *set2,
const Network *network)
{
size_t size1 = set1 ? set1->size() : 0;
size_t size2 = set2 ? set2->size() : 0;
if (size1 == size2) {
InstanceSet::ConstIterator iter1(set1);
InstanceSet::ConstIterator iter2(set2);
while (iter1.hasNext() && iter2.hasNext()) {
const Instance *inst1 = iter1.next();
const Instance *inst2 = iter2.next();
ObjectId id1 = network->id(inst1);
ObjectId id2 = network->id(inst2);
if (id1 < id2)
return -1;
else if (id1 > id2)
return 1;
}
// Sets are equal.
return 0;
}
else
return (size1 > size2) ? 1 : -1;
}
PinSet::PinSet() :
Set<const Pin*, PinIdLess>(PinIdLess(nullptr))
{
}
PinSet::PinSet(const Network *network) :
Set<const Pin*, PinIdLess>(PinIdLess(network))
{
}
int
PinSet::compare(const PinSet *set1,
const PinSet *set2,
const Network *network)
{
size_t size1 = set1 ? set1->size() : 0;
size_t size2 = set2 ? set2->size() : 0;
if (size1 == size2) {
PinSet::ConstIterator iter1(set1);
PinSet::ConstIterator iter2(set2);
while (iter1.hasNext() && iter2.hasNext()) {
const Pin *pin1 = iter1.next();
const Pin *pin2 = iter2.next();
ObjectId id1 = network->id(pin1);
ObjectId id2 = network->id(pin2);
if (id1 < id2)
return -1;
else if (id1 > id2)
return 1;
}
// Sets are equal.
return 0;
}
else
return (size1 > size2) ? 1 : -1;
}
NetSet::NetSet() :
Set<const Net*, NetIdLess>(NetIdLess(nullptr))
{
}
NetSet::NetSet(const Network *network) :
Set<const Net*, NetIdLess>(NetIdLess(network))
{
}
int
NetSet::compare(const NetSet *set1,
const NetSet *set2,
const Network *network)
{
size_t size1 = set1 ? set1->size() : 0;
size_t size2 = set2 ? set2->size() : 0;
if (size1 == size2) {
NetSet::ConstIterator iter1(set1);
NetSet::ConstIterator iter2(set2);
while (iter1.hasNext() && iter2.hasNext()) {
const Net *net1 = iter1.next();
const Net *net2 = iter2.next();
ObjectId id1 = network->id(net1);
ObjectId id2 = network->id(net2);
if (id1 < id2)
return -1;
else if (id1 > id2)
return 1;
}
// Sets are equal.
return 0;
}
else
return (size1 > size2) ? 1 : -1;
}
} // namespace

58
network/NetworkCmp.cc
View File

@ -74,50 +74,48 @@ InstancePathNameLess::operator()(const Instance *inst1,
////////////////////////////////////////////////////////////////
void
sortPinSet(PinSet *set,
const Network *network,
PinSeq &pins)
PinSeq
sortByPathName(const PinSet *set,
const Network *network)
{
PinSet::Iterator pin_iter(set);
while (pin_iter.hasNext())
pins.push_back(pin_iter.next());
PinSeq pins;
for (const Pin *pin : *set)
pins.push_back(pin);
sort(pins, PinPathNameLess(network));
return pins;
}
void
sortPortSet(PortSet *set,
const Network *network,
PortSeq &ports)
PortSeq
sortByName(const PortSet *set,
const Network *network)
{
PortSet::Iterator port_iter(set);
while (port_iter.hasNext())
ports.push_back(port_iter.next());
PortSeq ports;
for (const Port *port : *set)
ports.push_back(port);
sort(ports, PortNameLess(network));
return ports;
}
void
sortInstanceSet(InstanceSet *set,
const Network *network,
InstanceSeq &insts)
InstanceSeq
sortByPathName(InstanceSet *set,
const Network *network)
{
InstanceSet::Iterator inst_iter(set);
while (inst_iter.hasNext())
insts.push_back(inst_iter.next());
// Sort ports so regression results are portable.
InstanceSeq insts;
for (const Instance *inst : *set)
insts.push_back(inst);
sort(insts, InstancePathNameLess(network));
return insts;
}
void
sortNetSet(NetSet *set,
const Network *network,
NetSeq &nets)
NetSeq
sortByPathName(NetSet *set,
const Network *network)
{
NetSet::Iterator net_iter(set);
while (net_iter.hasNext())
nets.push_back(net_iter.next());
// Sort nets so regression results are netable.
NetSeq nets;
for (const Net *net : *set)
nets.push_back(net);
sort(nets, NetPathNameLess(network));
return nets;
}
} // namespace

147
network/SdcNetwork.cc
View File

@ -86,6 +86,12 @@ NetworkNameAdapter::name(const Library *library) const
return network_->name(library);
}
ObjectId
NetworkNameAdapter::id(const Library *library) const
{
return network_->id(library);
}
Cell *
NetworkNameAdapter::findCell(const Library *library,
const char *name) const
@ -93,12 +99,11 @@ NetworkNameAdapter::findCell(const Library *library,
return network_->findCell(library, name);
}
void
CellSeq
NetworkNameAdapter::findCellsMatching(const Library *library,
const PatternMatch *pattern,
CellSeq *cells) const
const PatternMatch *pattern) const
{
network_->findCellsMatching(library, pattern, cells);
return network_->findCellsMatching(library, pattern);
}
////////////////////////////////////////////////////////////////
@ -109,6 +114,12 @@ NetworkNameAdapter::name(const Cell *cell) const
return network_->name(cell);
}
ObjectId
NetworkNameAdapter::id(const Cell *cell) const
{
return network_->id(cell);
}
Library *
NetworkNameAdapter::library(const Cell *cell) const
{
@ -152,12 +163,11 @@ NetworkNameAdapter::findPort(const Cell *cell,
return network_->findPort(cell, name);
}
void
PortSeq
NetworkNameAdapter::findPortsMatching(const Cell *cell,
const PatternMatch *pattern,
PortSeq *ports) const
const PatternMatch *pattern) const
{
network_->findPortsMatching(cell, pattern, ports);
return network_->findPortsMatching(cell, pattern);
}
bool
@ -192,6 +202,12 @@ NetworkNameAdapter::name(const Port *port) const
return network_->name(port);
}
ObjectId
NetworkNameAdapter::id(const Port *port) const
{
return network_->id(port);
}
Cell *
NetworkNameAdapter::cell(const Port *port) const
{
@ -297,6 +313,12 @@ NetworkNameAdapter::memberIterator(const Port *port) const
////////////////////////////////////////////////////////////////
ObjectId
NetworkNameAdapter::id(const Instance *instance) const
{
return network_->id(instance);
}
Cell *
NetworkNameAdapter::cell(const Instance *instance) const
{
@ -347,6 +369,12 @@ NetworkNameAdapter::netIterator(const Instance *instance) const
return network_->netIterator(instance);
}
ObjectId
NetworkNameAdapter::id(const Pin *pin) const
{
return network_->id(pin);
}
Port *
NetworkNameAdapter::port(const Pin *pin) const
{
@ -377,6 +405,12 @@ NetworkNameAdapter::direction(const Pin *pin) const
return network_->direction(pin);
}
ObjectId
NetworkNameAdapter::id(const Term *term) const
{
return network_->id(term);
}
Net *
NetworkNameAdapter::net(const Term *term) const
{
@ -389,6 +423,12 @@ NetworkNameAdapter::pin(const Term *term) const
return network_->pin(term);
}
ObjectId
NetworkNameAdapter::id(const Net *net) const
{
return network_->id(net);
}
Instance *
NetworkNameAdapter::instance(const Net *net) const
{
@ -611,13 +651,12 @@ SdcNetwork::findPort(const Cell *cell,
return port;
}
void
PortSeq
SdcNetwork::findPortsMatching(const Cell *cell,
const PatternMatch *pattern,
PortSeq *ports) const
const PatternMatch *pattern) const
{
network_->findPortsMatching(cell, pattern, ports);
if (ports->empty()) {
PortSeq matches = network_->findPortsMatching(cell, pattern);
if (matches.empty()) {
// Look for matches after escaping brackets.
char *bus_name;
int index;
@ -625,19 +664,20 @@ SdcNetwork::findPortsMatching(const Cell *cell,
if (bus_name) {
const char *escaped1 = escapeBrackets(pattern->pattern(), this);
PatternMatch escaped_pattern1(escaped1, pattern);
network_->findPortsMatching(cell, &escaped_pattern1, ports);
if (ports->empty()
matches = network_->findPortsMatching(cell, &escaped_pattern1);
if (matches.empty()
&& bus_name[strlen(bus_name) - 1] == ']') {
// Try escaping base foo\[0\][1]
const char *escaped2 = stringPrintTmp("%s[%d]",
escapeBrackets(bus_name, this),
index);
PatternMatch escaped_pattern2(escaped2, pattern);
network_->findPortsMatching(cell, &escaped_pattern2, ports);
matches = network_->findPortsMatching(cell, &escaped_pattern2);
}
stringDelete(bus_name);
}
}
return matches;
}
const char *
@ -704,18 +744,27 @@ SdcNetwork::findInstance(const char *path_name) const
return child;
}
void
InstanceSeq
SdcNetwork::findInstancesMatching(const Instance *context,
const PatternMatch *pattern,
InstanceSeq *insts) const
const PatternMatch *pattern) const
{
InstanceSeq matches;
findInstancesMatching1(context, pattern, matches);
return matches;
}
void
SdcNetwork::findInstancesMatching1(const Instance *context,
const PatternMatch *pattern,
InstanceSeq &matches) const
{
visitMatches(context, pattern,
[&](const Instance *instance,
const PatternMatch *tail)
{
size_t match_count = insts->size();
network_->findChildrenMatching(instance, tail, insts);
return insts->size() != match_count;
size_t match_count = matches.size();
network_->findChildrenMatching(instance, tail, matches);
return matches.size() != match_count;
});
}
@ -756,38 +805,39 @@ SdcNetwork::findNet(const Instance *instance,
return net;
}
void
NetSeq
SdcNetwork::findNetsMatching(const Instance *parent,
const PatternMatch *pattern,
NetSeq *nets) const
const PatternMatch *pattern) const
{
NetSeq matches;
visitMatches(parent, pattern,
[&](const Instance *instance,
const PatternMatch *tail)
{
size_t match_count = nets->size();
network_->findInstNetsMatching(instance, tail, nets);
return nets->size() != match_count;
size_t match_count = matches.size();
network_->findInstNetsMatching(instance, tail, matches);
return matches.size() != match_count;
});
return matches;
}
void
SdcNetwork::findInstNetsMatching(const Instance *instance,
const PatternMatch *pattern,
NetSeq *nets) const
NetSeq &matches) const
{
network_->findInstNetsMatching(instance, pattern, nets);
if (nets->empty()) {
network_->findInstNetsMatching(instance, pattern, matches);
if (matches.empty()) {
// Look for matches after escaping path dividers.
const PatternMatch escaped_dividers(escapeDividers(pattern->pattern(),
this),
pattern);
network_->findInstNetsMatching(instance, &escaped_dividers, nets);
if (nets->empty()) {
network_->findInstNetsMatching(instance, &escaped_dividers, matches);
if (matches.empty()) {
// Look for matches after escaping brackets.
const PatternMatch escaped_brkts(escapeBrackets(pattern->pattern(),this),
pattern);
network_->findInstNetsMatching(instance, &escaped_brkts, nets);
network_->findInstNetsMatching(instance, &escaped_brkts, matches);
}
}
}
@ -833,11 +883,11 @@ SdcNetwork::findPin(const Instance *instance,
}
// Top level ports are not considered pins by get_pins.
void
PinSeq
SdcNetwork::findPinsMatching(const Instance *instance,
const PatternMatch *pattern,
PinSeq *pins) const
const PatternMatch *pattern) const
{
PinSeq matches;
if (stringEq(pattern->pattern(), "*")) {
// Pattern of '*' matches all child instance pins.
InstanceChildIterator *child_iter = childIterator(instance);
@ -845,8 +895,8 @@ SdcNetwork::findPinsMatching(const Instance *instance,
Instance *child = child_iter->next();
InstancePinIterator *pin_iter = pinIterator(child);
while (pin_iter->hasNext()) {
Pin *pin = pin_iter->next();
pins->push_back(pin);
const Pin *pin = pin_iter->next();
matches.push_back(pin);
}
delete pin_iter;
}
@ -857,14 +907,15 @@ SdcNetwork::findPinsMatching(const Instance *instance,
[&](const Instance *instance,
const PatternMatch *tail)
{
return visitPinTail(instance, tail, pins);
return visitPinTail(instance, tail, matches);
});
return matches;
}
bool
SdcNetwork::visitPinTail(const Instance *instance,
const PatternMatch *tail,
PinSeq *pins) const
PinSeq &matches) const
{
bool found_match = false;
if (instance != network_->topInstance()) {
@ -879,17 +930,17 @@ SdcNetwork::visitPinTail(const Instance *instance,
PortMemberIterator *member_iter = network_->memberIterator(port);
while (member_iter->hasNext()) {
Port *member_port = member_iter->next();
Pin *pin = network_->findPin(instance, member_port);
const Pin *pin = network_->findPin(instance, member_port);
if (pin) {
if (bus_matches) {
pins->push_back(pin);
matches.push_back(pin);
found_match = true;
}
else {
const char *member_name = network_->name(member_port);
if (tail->match(member_name)
|| tail->match(escapeDividers(member_name, network_))) {
pins->push_back(pin);
matches.push_back(pin);
found_match = true;
}
}
@ -901,7 +952,7 @@ SdcNetwork::visitPinTail(const Instance *instance,
|| tail->match(escapeDividers(port_name, network_))) {
Pin *pin = network_->findPin(instance, port);
if (pin) {
pins->push_back(pin);
matches.push_back(pin);
found_match = true;
}
}
@ -1067,19 +1118,19 @@ SdcNetwork::visitMatches(const Instance *parent,
*p = '\0';
PatternMatch matcher(inst_path, pattern);
InstanceSeq matches;
findChildrenMatching(parent, &matcher, &matches);
findChildrenMatching(parent, &matcher, matches);
if (has_brkts && matches.empty()) {
// Look for matches after escaping brackets.
const PatternMatch escaped_brkts(escapeBrackets(inst_path, this),
pattern);
network_->findChildrenMatching(parent, &escaped_brkts, &matches);
network_->findChildrenMatching(parent, &escaped_brkts, matches);
}
if (!matches.empty()) {
// Found instance matches for the sub-path up to this divider.
const PatternMatch tail_pattern(s + 1, pattern);
InstanceSeq::Iterator match_iter(matches);
while (match_iter.hasNext()) {
Instance *match = match_iter.next();
const Instance *match = match_iter.next();
// Recurse to save the iterator state so we can iterate over
// multiple nested partial matches.
found_match |= visitMatches(match, &tail_pattern, visit_tail);

46
parasitics/ConcreteParasitics.cc
View File

@ -692,7 +692,7 @@ ConcreteParasiticNetwork::deleteNodes()
{
ConcreteParasiticSubNodeMap::Iterator node_iter1(sub_nodes_);
while (node_iter1.hasNext()) {
NetId *net_id;
NetIdPair *net_id;
ConcreteParasiticSubNode *node;
node_iter1.next(net_id, node);
delete net_id;
@ -782,11 +782,11 @@ ConcreteParasiticNode *
ConcreteParasiticNetwork::ensureParasiticNode(const Net *net,
int id)
{
NetId net_id(net, id);
NetIdPair net_id(net, id);
ConcreteParasiticSubNode *node = sub_nodes_.findKey(&net_id);
if (node == nullptr) {
node = new ConcreteParasiticSubNode(net, id);
sub_nodes_[new NetId(net, id)] = node;
sub_nodes_[new NetIdPair(net, id)] = node;
max_node_id_ = max((int) max_node_id_, id);
}
return node;
@ -800,7 +800,7 @@ ConcreteParasiticNetwork::findNode(const Pin *pin)
void
ConcreteParasiticNetwork::disconnectPin(const Pin *pin,
Net *net)
const Net *net)
{
ConcreteParasiticNode *node = pin_nodes_.findKey(pin);
if (node) {
@ -831,8 +831,8 @@ ConcreteParasiticNetwork::ensureParasiticNode(const Pin *pin)
}
bool
NetIdLess::operator()(const NetId *net_id1,
const NetId *net_id2) const
NetIdPairLess::operator()(const NetIdPair *net_id1,
const NetIdPair *net_id2) const
{
const Net *net1 = net_id1->first;
const Net *net2 = net_id2->first;
@ -957,9 +957,9 @@ ConcreteParasitics::capacitance(Parasitic *parasitic) const
}
bool
ConcreteParasitics::isReducedParasiticNetwork(Parasitic *parasitic) const
ConcreteParasitics::isReducedParasiticNetwork(const Parasitic *parasitic) const
{
ConcreteParasitic *cparasitic = static_cast<ConcreteParasitic*>(parasitic);
const ConcreteParasitic *cparasitic = static_cast<const ConcreteParasitic*>(parasitic);
return cparasitic->isReducedParasiticNetwork();
}
@ -977,7 +977,7 @@ ConcreteParasitics::disconnectPinBefore(const Pin *pin)
if (haveParasitics()) {
deleteReducedParasitics(pin);
Net *net = findParasiticNet(pin);
const Net *net = findParasiticNet(pin);
if (net) {
ConcreteParasiticNetwork **parasitics = parasitic_network_map_[net];
if (parasitics) {
@ -1056,9 +1056,9 @@ ConcreteParasitics::deleteDrvrReducedParasitics(const Pin *drvr_pin,
////////////////////////////////////////////////////////////////
bool
ConcreteParasitics::isPiElmore(Parasitic *parasitic) const
ConcreteParasitics::isPiElmore(const Parasitic *parasitic) const
{
ConcreteParasitic *cparasitic = static_cast<ConcreteParasitic*>(parasitic);
const ConcreteParasitic *cparasitic = static_cast<const ConcreteParasitic*>(parasitic);
return cparasitic && cparasitic->isPiElmore();
}
@ -1126,19 +1126,19 @@ ConcreteParasitics::makePiElmore(const Pin *drvr_pin,
////////////////////////////////////////////////////////////////
bool
ConcreteParasitics::isPiModel(Parasitic *parasitic) const
ConcreteParasitics::isPiModel(const Parasitic *parasitic) const
{
ConcreteParasitic *cparasitic = static_cast<ConcreteParasitic*>(parasitic);
const ConcreteParasitic *cparasitic = static_cast<const ConcreteParasitic*>(parasitic);
return cparasitic && cparasitic->isPiModel();
}
void
ConcreteParasitics::piModel(Parasitic *parasitic,
ConcreteParasitics::piModel(const Parasitic *parasitic,
float &c2,
float &rpi,
float &c1) const
{
ConcreteParasitic *cparasitic = static_cast<ConcreteParasitic*>(parasitic);
const ConcreteParasitic *cparasitic = static_cast<const ConcreteParasitic*>(parasitic);
cparasitic->piModel(c2, rpi, c1);
}
@ -1155,12 +1155,12 @@ ConcreteParasitics::setPiModel(Parasitic *parasitic,
////////////////////////////////////////////////////////////////
void
ConcreteParasitics::findElmore(Parasitic *parasitic,
ConcreteParasitics::findElmore(const Parasitic *parasitic,
const Pin *load_pin,
float &elmore,
bool &exists) const
{
ConcreteParasitic *cparasitic = static_cast<ConcreteParasitic*>(parasitic);
const ConcreteParasitic *cparasitic = static_cast<const ConcreteParasitic*>(parasitic);
cparasitic->findElmore(load_pin, elmore, exists);
}
@ -1176,9 +1176,9 @@ ConcreteParasitics::setElmore(Parasitic *parasitic,
////////////////////////////////////////////////////////////////
bool
ConcreteParasitics::isPiPoleResidue(Parasitic* parasitic) const
ConcreteParasitics::isPiPoleResidue(const Parasitic* parasitic) const
{
ConcreteParasitic *cparasitic = static_cast<ConcreteParasitic*>(parasitic);
const ConcreteParasitic *cparasitic = static_cast<const ConcreteParasitic*>(parasitic);
return cparasitic && cparasitic->isPiPoleResidue();
}
@ -1324,7 +1324,7 @@ ConcreteParasitics::findParasiticNetwork(const Pin *pin,
UniqueLock lock(lock_);
if (!parasitic_network_map_.empty()) {
// Only call findParasiticNet if parasitics exist.
Net *net = findParasiticNet(pin);
const Net *net = findParasiticNet(pin);
ConcreteParasiticNetwork **parasitics=parasitic_network_map_.findKey(net);
if (parasitics)
return parasitics[ap->index()];
@ -1635,17 +1635,17 @@ ConcreteParasitics::unannotatedLoads(Parasitic *parasitic_network,
ParasiticNode *drvr_node = findNode(parasitic_network, drvr_pin);
if (drvr_node)
return checkAnnotation1(drvr_pin, drvr_node);
return PinSet();
return PinSet(network_);
}
PinSet
ConcreteParasitics::checkAnnotation1(const Pin *drvr_pin,
ParasiticNode *drvr_node)
{
PinSet loads;
PinSet loads(network_);
NetConnectedPinIterator *pin_iter = network_->connectedPinIterator(drvr_pin);
while (pin_iter->hasNext()) {
Pin *pin = pin_iter->next();
const Pin *pin = pin_iter->next();
if (network_->isLoad(pin) && !network_->isHierarchical(pin))
loads.insert(pin);
}

30
parasitics/ConcreteParasitics.hh
View File

@ -55,32 +55,42 @@ public:
const ParasiticAnalysisPt *ap);
virtual void deleteUnsavedParasitic(Parasitic *parasitic);
virtual bool isReducedParasiticNetwork(Parasitic *parasitic) const;
virtual bool isReducedParasiticNetwork(const Parasitic *parasitic) const;
virtual void setIsReducedParasiticNetwork(Parasitic *parasitic,
bool is_reduced);
virtual float capacitance(Parasitic *parasitic) const;
virtual bool isPiElmore(Parasitic *parasitic) const;
virtual bool isPiElmore(const Parasitic *parasitic) const;
virtual Parasitic *findPiElmore(const Pin *drvr_pin,
const RiseFall *rf,
const ParasiticAnalysisPt *ap) const;
virtual Parasitic *makePiElmore(const Pin *drvr_pin,
const RiseFall *rf,
const ParasiticAnalysisPt *ap,
float c2, float rpi, float c1);
float c2,
float rpi,
float c1);
virtual bool isPiModel(Parasitic *parasitic) const;
virtual void piModel(Parasitic *parasitic, float &c2, float &rpi,
virtual bool isPiModel(const Parasitic *parasitic) const;
virtual void piModel(const Parasitic *parasitic,
float &c2,
float &rpi,
float &c1) const;
virtual void setPiModel(Parasitic *parasitic, float c2, float rpi, float c1);
virtual void setPiModel(Parasitic *parasitic,
float c2,
float rpi,
float c1);
virtual void findElmore(Parasitic *parasitic, const Pin *load_pin,
float &elmore, bool &exists) const;
virtual void setElmore(Parasitic *parasitic, const Pin *load_pin,
virtual void findElmore(const Parasitic *parasitic,
const Pin *load_pin,
float &elmore,
bool &exists) const;
virtual void setElmore(Parasitic *parasitic,
const Pin *load_pin,
float elmore);
virtual bool isPiPoleResidue(Parasitic* parasitic) const;
virtual bool isPiPoleResidue(const Parasitic* parasitic) const;
virtual Parasitic *findPiPoleResidue(const Pin *drvr_pin,
const RiseFall *rf,
const ParasiticAnalysisPt *ap) const;

14
parasitics/ConcreteParasiticsPvt.hh
View File

@ -29,14 +29,14 @@ class ConcreteParasiticNode;
typedef Map<const Pin*, float> ConcreteElmoreLoadMap;
typedef ConcreteElmoreLoadMap::Iterator ConcretePiElmoreLoadIterator;
typedef Map<const Pin*, ConcretePoleResidue*> ConcretePoleResidueMap;
typedef std::pair<const Net*, int> NetId;
struct NetIdLess
typedef std::pair<const Net*, int> NetIdPair;
struct NetIdPairLess
{
bool operator()(const NetId *net_id1,
const NetId *net_id2) const;
bool operator()(const NetIdPair *net_id1,
const NetIdPair *net_id2) const;
};
typedef Map<NetId*, ConcreteParasiticSubNode*,
NetIdLess > ConcreteParasiticSubNodeMap;
typedef Map<NetIdPair*, ConcreteParasiticSubNode*,
NetIdPairLess > ConcreteParasiticSubNodeMap;
typedef Map<const Pin*,
ConcreteParasiticPinNode*> ConcreteParasiticPinNodeMap;
typedef Vector<ConcreteParasiticDevice*> ConcreteParasiticDeviceSeq;
@ -427,7 +427,7 @@ public:
ConcreteParasiticPinNodeMap *pinNodes() { return &pin_nodes_; }
ConcreteParasiticSubNodeMap *subNodes() { return &sub_nodes_; }
void disconnectPin(const Pin *pin,
Net *net);
const Net *net);
virtual ParasiticDeviceIterator *deviceIterator();
virtual ParasiticNodeIterator *nodeIterator();
virtual void devices(// Return value.

2
parasitics/EstimateParasitics.cc
View File

@ -183,7 +183,7 @@ EstimateParasitics::estimatePiElmoreBalanced(const Pin *drvr_pin,
load_cap = sdc->pinCapacitance(load_pin, rf, op_cond,
corner, min_max);
else if (network->isTopLevelPort(load_pin))
load_cap = sdc->portExtCap(port, rf, min_max);
load_cap = sdc->portExtCap(port, rf, corner, min_max);
else
report->critical(597, "load pin not leaf or top level");
double cap = load_cap + cap_fanout;

12
parasitics/NullParasitics.cc
View File

@ -97,13 +97,13 @@ NullParasitics::makePiElmore(const Pin *,
}
bool
NullParasitics::isPiElmore(Parasitic *) const
NullParasitics::isPiElmore(const Parasitic *) const
{
return false;
}
bool
NullParasitics::isReducedParasiticNetwork(Parasitic *) const
NullParasitics::isReducedParasiticNetwork(const Parasitic *) const
{
return false;
}
@ -115,7 +115,7 @@ NullParasitics::setIsReducedParasiticNetwork(Parasitic *,
}
void
NullParasitics::piModel(Parasitic *,
NullParasitics::piModel(const Parasitic *,
float &,
float &,
float &) const
@ -131,7 +131,7 @@ NullParasitics::setPiModel(Parasitic *,
}
void
NullParasitics::findElmore(Parasitic *,
NullParasitics::findElmore(const Parasitic *,
const Pin *,
float &,
bool &) const
@ -146,13 +146,13 @@ NullParasitics::setElmore(Parasitic *,
}
bool
NullParasitics::isPiModel(Parasitic*) const
NullParasitics::isPiModel(const Parasitic*) const
{
return false;
}
bool
NullParasitics::isPiPoleResidue(Parasitic* ) const
NullParasitics::isPiPoleResidue(const Parasitic* ) const
{
return false;
}

2
parasitics/Parasitics.cc
View File

@ -32,7 +32,7 @@ Parasitics::Parasitics(StaState *sta) :
{
}
Net *
const Net *
Parasitics::findParasiticNet(const Pin *pin) const
{
Net *net = network_->net(pin);

13
parasitics/Parasitics.i
View File

@ -27,7 +27,6 @@ using sta::MinMaxAll;
using sta::ReducedParasiticType;
using sta::RiseFall;
using sta::Pin;
using sta::TmpFloatSeq;
%}
@ -60,7 +59,7 @@ report_parasitic_annotation_cmd(bool report_unannotated,
Sta::sta()->reportParasiticAnnotation(report_unannotated, corner);
}
TmpFloatSeq *
FloatSeq
find_pi_elmore(Pin *drvr_pin,
RiseFall *rf,
MinMax *min_max)
@ -68,13 +67,13 @@ find_pi_elmore(Pin *drvr_pin,
float c2, rpi, c1;
bool exists;
Sta::sta()->findPiElmore(drvr_pin, rf, min_max, c2, rpi, c1, exists);
TmpFloatSeq *floats = new FloatSeq;
FloatSeq pi_elmore;
if (exists) {
floats->push_back(c2);
floats->push_back(rpi);
floats->push_back(c1);
pi_elmore.push_back(c2);
pi_elmore.push_back(rpi);
pi_elmore.push_back(c1);
}
return floats;
return pi_elmore;
}
float

4
parasitics/ReduceParasitics.cc
View File

@ -226,7 +226,7 @@ ReduceToPi::pinCapacitance(ParasiticNode *node)
}
}
else if (network_->isTopLevelPort(pin))
pin_cap = sdc_->portExtCap(port, rf_, cnst_min_max_);
pin_cap = sdc_->portExtCap(port, rf_, corner_, cnst_min_max_);
}
return pin_cap;
}
@ -535,7 +535,7 @@ ReduceToPiPoleResidue2::findPolesResidues(Parasitic *parasitic_network,
PinConnectedPinIterator *pin_iter = network_->connectedPinIterator(drvr_pin);
while (pin_iter->hasNext()) {
Pin *pin = pin_iter->next();
const Pin *pin = pin_iter->next();
if (network_->isLoad(pin)) {
ParasiticNode *load_node = parasitics_->findNode(parasitic_network, pin);
if (load_node) {

6
parasitics/ReportParasiticAnnotation.cc
View File

@ -83,7 +83,7 @@ ReportParasiticAnnotation::reportAnnotationCounts()
report_->reportLine("Found %lu unannotated drivers.", unannotated_.size());
if (report_unannotated_) {
sort(unannotated_, PinPathNameLess(network_));
for (Pin *drvr_pin : unannotated_)
for (const Pin *drvr_pin : unannotated_)
report_->reportLine(" %s", network_->pathName(drvr_pin));
}
@ -91,12 +91,12 @@ ReportParasiticAnnotation::reportAnnotationCounts()
partially_annotated_.size());
if (report_unannotated_) {
sort(partially_annotated_, PinPathNameLess(network_));
for (Pin *drvr_pin : partially_annotated_) {
for (const Pin *drvr_pin : partially_annotated_) {
report_->reportLine(" %s", network_->pathName(drvr_pin));
Parasitic *parasitic = parasitics_->findParasiticNetwork(drvr_pin, parasitic_ap_);
PinSet unannotated_loads = parasitics_->unannotatedLoads(parasitic, drvr_pin);
for (Pin *load_pin : unannotated_loads)
for (const Pin *load_pin : unannotated_loads)
report_->reportLine(" %s", network_->pathName(load_pin));
}
}

32
power/Power.cc
View File

@ -74,6 +74,7 @@ Power::Power(StaState *sta) :
StaState(sta),
global_activity_{0.0, 0.0, PwrActivityOrigin::unknown},
input_activity_{0.1, 0.5, PwrActivityOrigin::input},
seq_activity_map_(100, SeqPinHash(network_), SeqPinEqual()),
activities_valid_(false)
{
}
@ -173,10 +174,15 @@ Power::seqActivity(const Instance *reg,
return seq_activity_map_[SeqPin(reg, output)];
}
SeqPinHash::SeqPinHash(const Network *network) :
network_(network)
{
}
size_t
SeqPinHash::operator()(const SeqPin &pin) const
{
return hashSum(hashPtr(pin.first), hashPtr(pin.second));
return hashSum(network_->id(pin.first), pin.second->id());
}
bool
@ -210,8 +216,7 @@ Power::power(const Corner *corner,
Instance *inst = inst_iter->next();
LibertyCell *cell = network_->libertyCell(inst);
if (cell) {
PowerResult inst_power;
power(inst, cell, corner, inst_power);
PowerResult inst_power = power(inst, cell, corner);
if (cell->isMacro()
|| cell->isMemory())
macro.incr(inst_power);
@ -227,17 +232,16 @@ Power::power(const Corner *corner,
delete inst_iter;
}
void
PowerResult
Power::power(const Instance *inst,
const Corner *corner,
// Return values.
PowerResult &result)
const Corner *corner)
{
LibertyCell *cell = network_->libertyCell(inst);
if (cell) {
ensureActivities();
power(inst, cell, corner, result);
return power(inst, cell, corner);
}
return PowerResult();
}
////////////////////////////////////////////////////////////////
@ -306,7 +310,7 @@ PropActivityVisitor::copy() const
void
PropActivityVisitor::init()
{
visited_regs_ = new InstanceSet;
visited_regs_ = new InstanceSet(network_);
found_reg_without_activity_ = false;
}
@ -546,7 +550,7 @@ Power::ensureActivities()
InstanceSet *regs = visitor.stealVisitedRegs();
InstanceSet::Iterator reg_iter(regs);
while (reg_iter.hasNext()) {
Instance *reg = reg_iter.next();
const Instance *reg = reg_iter.next();
// Propagate activiities across register D->Q.
seedRegOutputActivities(reg, bfs);
}
@ -636,13 +640,12 @@ Power::seedRegOutputActivities(const Instance *reg,
////////////////////////////////////////////////////////////////
void
PowerResult
Power::power(const Instance *inst,
LibertyCell *cell,
const Corner *corner,
// Return values.
PowerResult &result)
const Corner *corner)
{
PowerResult result;
MinMax *mm = MinMax::max();
const DcalcAnalysisPt *dcalc_ap = corner->findDcalcAnalysisPt(mm);
const Clock *inst_clk = findInstClk(inst);
@ -667,6 +670,7 @@ Power::power(const Instance *inst,
}
delete pin_iter;
findLeakagePower(inst, cell, corner, result);
return result;
}
const Clock *

18
power/Power.hh
View File

@ -38,7 +38,11 @@ typedef std::pair<const Instance*, LibertyPort*> SeqPin;
class SeqPinHash
{
public:
SeqPinHash(const Network *network);
size_t operator()(const SeqPin &pin) const;
private:
const Network *network_;
};
class SeqPinEqual
@ -65,10 +69,8 @@ public:
PowerResult &combinational,
PowerResult &macro,
PowerResult &pad);
void power(const Instance *inst,
const Corner *corner,
// Return values.
PowerResult &result);
PowerResult power(const Instance *inst,
const Corner *corner);
void setGlobalActivity(float activity,
float duty);
void setInputActivity(float activity,
@ -99,11 +101,9 @@ protected:
void setActivity(const Pin *pin,
PwrActivity &activity);
void power(const Instance *inst,
LibertyCell *cell,
const Corner *corner,
// Return values.
PowerResult &result);
PowerResult power(const Instance *inst,
LibertyCell *cell,
const Corner *corner);
void findInputInternalPower(const Pin *to_pin,
const LibertyPort *to_port,
const Instance *inst,

62
power/Power.i
View File

@ -23,59 +23,49 @@
#include "power/VcdReader.hh"
#include "power/ReadVcdActivities.hh"
namespace sta {
typedef FloatSeq TmpFloatSeq;
} // namespace
using namespace sta;
%}
%typemap(out) TmpFloatSeq* {
FloatSeq *floats = $1;
Tcl_Obj *list = Tcl_NewListObj(0, nullptr);
if (floats) {
for (unsigned i = 0; i < floats->size(); i++) {
Tcl_Obj *obj = Tcl_NewDoubleObj((*floats)[i]);
Tcl_ListObjAppendElement(interp, list, obj);
}
delete floats;
}
Tcl_SetObjResult(interp, list);
}
%inline %{
TmpFloatSeq *
static void
pushPowerResultFloats(PowerResult &power,
FloatSeq &powers)
{
powers.push_back(power.internal());
powers.push_back(power.switching());
powers.push_back(power.leakage());
powers.push_back(power.total());
}
FloatSeq
design_power(const Corner *corner)
{
cmdLinkedNetwork();
PowerResult total, sequential, combinational, macro, pad;
Sta::sta()->power(corner, total, sequential, combinational, macro, pad);
FloatSeq *floats = new FloatSeq;
pushPowerResultFloats(total, floats);
pushPowerResultFloats(sequential, floats);
pushPowerResultFloats(combinational, floats);
pushPowerResultFloats(macro, floats);
pushPowerResultFloats(pad, floats);
return floats;
FloatSeq powers;
pushPowerResultFloats(total, powers);
pushPowerResultFloats(sequential, powers);
pushPowerResultFloats(combinational, powers);
pushPowerResultFloats(macro, powers);
pushPowerResultFloats(pad, powers);
return powers;
}
TmpFloatSeq *
FloatSeq
instance_power(Instance *inst,
const Corner *corner)
{
cmdLinkedNetwork();
PowerResult power;
Sta::sta()->power(inst, corner, power);
FloatSeq *floats = new FloatSeq;
floats->push_back(power.internal());
floats->push_back(power.switching());
floats->push_back(power.leakage());
floats->push_back(power.total());
return floats;
PowerResult power = Sta::sta()->power(inst, corner);
FloatSeq powers;
powers.push_back(power.internal());
powers.push_back(power.switching());
powers.push_back(power.leakage());
powers.push_back(power.total());
return powers;
}
void

82
sdc/Clock.cc
View File

@ -33,9 +33,12 @@ static bool
isPowerOfTwo(int i);
Clock::Clock(const char *name,
int index) :
int index,
const Network *network) :
name_(stringCopy(name)),
pins_(network),
add_to_pins_(false),
leaf_pins_(network),
period_(0.0),
waveform_(nullptr),
waveform_valid_(false),
@ -99,7 +102,7 @@ Clock::makeLeafPins(const Network *network)
leaf_pins_.clear();
PinSet::Iterator pin_iter(pins_);
while (pin_iter.hasNext()) {
Pin *pin = pin_iter.next();
const Pin *pin = pin_iter.next();
findLeafDriverPins(pin, network, &leaf_pins_);
}
}
@ -135,14 +138,14 @@ Clock::~Clock()
}
void
Clock::addPin(Pin *pin)
Clock::addPin(const Pin *pin)
{
pins_.insert(pin);
leaf_pins_.insert(pin);
}
void
Clock::deletePin(Pin *pin)
Clock::deletePin(const Pin *pin)
{
pins_.erase(pin);
}
@ -167,7 +170,7 @@ Clock::setClkEdgeTime(const RiseFall *rf)
clk_edges_[rf->index()]->setTime(time);
}
Pin *
const Pin *
Clock::defaultPin() const
{
PinSet::ConstIterator pin_iter(leaf_pins_);
@ -493,11 +496,11 @@ Clock::srcPinVertices(VertexSet &src_vertices,
{
if (network->isHierarchical(src_pin_)) {
// Use the clocks on a non-hierarchical pin on the same net.
PinSet leaf_pins;
PinSet leaf_pins(network);
findLeafDriverPins(src_pin_, network, &leaf_pins);
PinSet::Iterator pin_iter(leaf_pins);
while (pin_iter.hasNext()) {
Pin *pin = pin_iter.next();
const Pin *pin = pin_iter.next();
Vertex *vertex, *bidirect_drvr_vertex;
graph->pinVertices(pin, vertex, bidirect_drvr_vertex);
if (vertex)
@ -585,8 +588,8 @@ clkCmp(const Clock *clk1,
}
int
clkEdgeCmp(ClockEdge *clk_edge1,
ClockEdge *clk_edge2)
clkEdgeCmp(const ClockEdge *clk_edge1,
const ClockEdge *clk_edge2)
{
if (clk_edge1 == nullptr && clk_edge2)
return -1;
@ -607,8 +610,8 @@ clkEdgeCmp(ClockEdge *clk_edge1,
}
bool
clkEdgeLess(ClockEdge *clk_edge1,
ClockEdge *clk_edge2)
clkEdgeLess(const ClockEdge *clk_edge1,
const ClockEdge *clk_edge2)
{
return clkEdgeCmp(clk_edge1, clk_edge2) < 0;
}
@ -683,14 +686,59 @@ ClockNameLess::operator()(const Clock *clk1,
return stringLess(clk1->name(), clk2->name());
}
void
sortClockSet(ClockSet *set,
ClockSeq &clks)
bool
ClockIndexLess::operator()(const Clock *clk1,
const Clock *clk2) const
{
ClockSet::Iterator clk_iter(set);
while (clk_iter.hasNext())
clks.push_back(clk_iter.next());
return (clk1 == nullptr && clk2)
|| (clk1 && clk2
&& clk1->index() < clk2->index());
}
ClockSeq
sortByName(ClockSet *set)
{
ClockSeq clks;
for (Clock *clk : *set)
clks.push_back(clk);
sort(clks, ClockNameLess());
return clks;
}
////////////////////////////////////////////////////////////////
bool
ClockSetLess::operator()(const ClockSet *set1,
const ClockSet *set2) const
{
return sta::compare(set1, set2) < 0;
}
int
compare(const ClockSet *set1,
const ClockSet *set2)
{
size_t size1 = set1 ? set1->size() : 0;
size_t size2 = set2 ? set2->size() : 0;
if (size1 == size2) {
ClockSet::ConstIterator iter1(set1);
ClockSet::ConstIterator iter2(set2);
while (iter1.hasNext() && iter2.hasNext()) {
Clock *clk1 = iter1.next();
Clock *clk2 = iter2.next();
int id1 = clk1->index();
int id2 = clk2->index();
if (id1 < id2)
return -1;
else if (id1 > id2)
return 1;
}
// Sets are equal.
return 0;
}
else
return (size1 > size2) ? 1 : -1;
}
} // namespace

38
sdc/ClockGroups.cc
View File

@ -20,24 +20,6 @@
namespace sta {
ClockGroup::ClockGroup(ClockSet *clks) :
clks_(clks)
{
}
ClockGroup::~ClockGroup()
{
delete clks_;
}
bool
ClockGroup::isMember(const Clock *clk)
{
return clks_->hasKey(const_cast<Clock*>(clk));
}
////////////////////////////////////////////////////////////////
ClockGroups::ClockGroups(const char *name,
bool logically_exclusive,
bool physically_exclusive,
@ -59,26 +41,24 @@ ClockGroups::~ClockGroups()
groups_.deleteContentsClear();
}
ClockGroup *
void
ClockGroups::makeClockGroup(ClockSet *clks)
{
ClockGroup *group = new ClockGroup(clks);
groups_.insert(group);
return group;
groups_.insert(clks);
}
void
ClockGroups::removeClock(Clock *clk)
{
ClockGroupSet::Iterator group_iter(groups_);
while (group_iter.hasNext()) {
ClockGroup *group = group_iter.next();
ClockSet *clks = group->clks();
clks->erase(clk);
if (clks->empty()) {
groups_.erase(group);
for (auto itr = groups_.cbegin(); itr != groups_.cend(); ) {
ClockGroup *group = *itr;
group->erase(clk);
if (group->empty()) {
itr = groups_.erase(itr);
delete group;
}
else
itr++;
}
}

14
sdc/DataCheck.cc
View File

@ -17,6 +17,7 @@
#include "DataCheck.hh"
#include "Clock.hh"
#include "Network.hh"
namespace sta {
@ -56,14 +57,14 @@ DataCheck::removeMargin(const RiseFallBoth *from_rf,
const RiseFallBoth *to_rf,
const SetupHoldAll *setup_hold)
{
for (auto from_rf_index : from_rf->rangeIndex())
for (int from_rf_index : from_rf->rangeIndex())
margins_[from_rf_index].removeValue(to_rf, setup_hold);
}
bool
DataCheck::empty() const
{
for (auto tr_index : RiseFall::rangeIndex()) {
for (int tr_index : RiseFall::rangeIndex()) {
if (!margins_[tr_index].empty())
return false;
}
@ -90,7 +91,7 @@ DataCheck::marginIsOneValue(SetupHold *setup_hold,
////////////////////////////////////////////////////////////////
DataCheckLess::DataCheckLess(const Network *network) :
pin_less_(network)
network_(network)
{
}
@ -104,12 +105,11 @@ DataCheckLess::operator()(const DataCheck *check1,
const Pin *to2 = check2->to();
const Clock *clk1 = check1->clk();
const Clock *clk2 = check2->clk();
int clk_cmp = clkCmp(clk1, clk2);
return pin_less_(from1, from2)
return network_->id(from1) < network_->id(from2)
|| (from1 == from2
&& (pin_less_(to1, to2)
&& (network_->id(to1) < network_->id(to2)
|| (to1 == to2
&& clk_cmp < 0)));
&& clkCmp(clk1, clk2) < 0)));
}
} // namespace

88
sdc/DisabledPorts.cc
View File

@ -37,10 +37,7 @@ DisabledPorts::~DisabledPorts()
{
delete from_;
delete to_;
if (from_to_) {
from_to_->deleteContents();
delete from_to_;
}
delete from_to_;
}
void
@ -92,10 +89,7 @@ DisabledPorts::setDisabledFromTo(LibertyPort *from,
if (from_to_ == nullptr)
from_to_ = new LibertyPortPairSet;
LibertyPortPair pair(from, to);
if (!from_to_->hasKey(&pair)) {
LibertyPortPair *pair = new LibertyPortPair(from, to);
from_to_->insert(pair);
}
from_to_->insert(pair);
}
void
@ -103,12 +97,8 @@ DisabledPorts::removeDisabledFromTo(LibertyPort *from,
LibertyPort *to)
{
if (from_to_) {
LibertyPortPair probe(from, to);
LibertyPortPair *pair = from_to_->findKey(&probe);
if (pair) {
from_to_->erase(pair);
delete pair;
}
LibertyPortPair from_to(from, to);
from_to_->erase(from_to);
}
}
@ -117,12 +107,12 @@ DisabledPorts::isDisabled(LibertyPort *from,
LibertyPort *to,
const TimingRole *role)
{
LibertyPortPair pair(from, to);
LibertyPortPair from_to(from, to);
// set_disable_timing instance does not disable timing checks.
return (all_ && !role->isTimingCheck())
|| (from_ && from_->hasKey(from))
|| (to_ && to_->hasKey(to))
|| (from_to_ && from_to_->hasKey(&pair));
|| (from_to_ && from_to_->hasKey(from_to));
}
////////////////////////////////////////////////////////////////
@ -182,14 +172,16 @@ DisabledCellPortsLess::operator()(const DisabledCellPorts *disable1,
disable2->cell()->name());
}
void
sortDisabledCellPortsMap(DisabledCellPortsMap *cell_map,
DisabledCellPortsSeq &disables)
DisabledCellPortsSeq
sortByName(DisabledCellPortsMap *cell_map)
{
DisabledCellPortsMap::Iterator disabled_iter(cell_map);
while (disabled_iter.hasNext())
disables.push_back(disabled_iter.next());
DisabledCellPortsSeq disables;
for (auto cell_disable : *cell_map) {
DisabledCellPorts *disable = cell_disable.second;
disables.push_back(disable);
}
sort(disables, DisabledCellPortsLess());
return disables;
}
////////////////////////////////////////////////////////////////
@ -203,36 +195,38 @@ DisabledInstancePorts::DisabledInstancePorts(Instance *inst) :
class DisabledInstPortsLess
{
public:
explicit DisabledInstPortsLess(Network *network);
explicit DisabledInstPortsLess(const Network *network);
bool operator()(const DisabledInstancePorts *disable1,
const DisabledInstancePorts *disable2);
private:
Network *network_;
const Network *network_;
};
DisabledInstPortsLess::DisabledInstPortsLess(Network *network) :
DisabledInstPortsLess::DisabledInstPortsLess(const Network *network) :
network_(network)
{
}
bool
DisabledInstPortsLess::operator()(const DisabledInstancePorts *disable1,
const DisabledInstancePorts *disable2)
const DisabledInstancePorts *disable2)
{
return stringLess(network_->pathName(disable1->instance()),
network_->pathName(disable2->instance()));
}
void
sortDisabledInstancePortsMap(DisabledInstancePortsMap *inst_map,
Network *network,
DisabledInstancePortsSeq &disables)
DisabledInstancePortsSeq
sortByPathName(const DisabledInstancePortsMap *inst_map,
const Network *network)
{
DisabledInstancePortsMap::Iterator disabled_iter(inst_map);
while (disabled_iter.hasNext())
disables.push_back(disabled_iter.next());
DisabledInstancePortsSeq disables;
for (auto inst_disable : *inst_map) {
DisabledInstancePorts *disable = inst_disable.second;
disables.push_back(disable);
}
sort(disables, DisabledInstPortsLess(network));
return disables;
}
////////////////////////////////////////////////////////////////
@ -240,30 +234,30 @@ sortDisabledInstancePortsMap(DisabledInstancePortsMap *inst_map,
class LibertyPortPairNameLess
{
public:
bool operator()(const LibertyPortPair *pair1,
const LibertyPortPair *pair2);
bool operator()(const LibertyPortPair &pair1,
const LibertyPortPair &pair2);
};
bool
LibertyPortPairNameLess::operator()(const LibertyPortPair *pair1,
const LibertyPortPair *pair2)
LibertyPortPairNameLess::operator()(const LibertyPortPair &pair1,
const LibertyPortPair &pair2)
{
const char *from1 = pair1->first->name();
const char *from2 = pair2->first->name();
const char *to1 = pair1->second->name();
const char *to2 = pair2->second->name();
const char *from1 = pair1.first->name();
const char *from2 = pair2.first->name();
const char *to1 = pair1.second->name();
const char *to2 = pair2.second->name();
return stringLess(from1, from2)
|| (stringEq(from1, from2) && stringLess(to1, to2));
}
void
sortLibertyPortPairSet(LibertyPortPairSet *sets,
LibertyPortPairSeq &pairs)
LibertyPortPairSeq
sortByName(const LibertyPortPairSet *set)
{
LibertyPortPairSet::Iterator pair_iter(sets);
while (pair_iter.hasNext())
pairs.push_back(pair_iter.next());
LibertyPortPairSeq pairs;
for (const LibertyPortPair &pair : *set)
pairs.push_back(pair);
sort(pairs, LibertyPortPairNameLess());
return pairs;
}
}

837
sdc/ExceptionPath.cc
View File

File diff suppressed because it is too large Load Diff

32
sdc/InputDrive.cc
View File

@ -78,11 +78,11 @@ InputDrive::driveResistanceMinMaxEqual(const RiseFall *rf)
}
void
InputDrive::setDriveCell(LibertyLibrary *library,
LibertyCell *cell,
LibertyPort *from_port,
InputDrive::setDriveCell(const LibertyLibrary *library,
const LibertyCell *cell,
const LibertyPort *from_port,
float *from_slews,
LibertyPort *to_port,
const LibertyPort *to_port,
const RiseFallBoth *rf,
const MinMaxAll *min_max)
{
@ -109,10 +109,10 @@ void
InputDrive::driveCell(const RiseFall *rf,
const MinMax *min_max,
// Return values.
LibertyCell *&cell,
LibertyPort *&from_port,
const LibertyCell *&cell,
const LibertyPort *&from_port,
float *&from_slews,
LibertyPort *&to_port)
const LibertyPort *&to_port)
{
InputDriveCell *drive = drive_cells_[rf->index()][min_max->index()];
if (drive) {
@ -170,11 +170,11 @@ InputDrive::slew(const RiseFall *rf,
////////////////////////////////////////////////////////////////
InputDriveCell::InputDriveCell(LibertyLibrary *library,
LibertyCell *cell,
LibertyPort *from_port,
InputDriveCell::InputDriveCell(const LibertyLibrary *library,
const LibertyCell *cell,
const LibertyPort *from_port,
float *from_slews,
LibertyPort *to_port) :
const LibertyPort *to_port) :
library_(library),
cell_(cell),
from_port_(from_port),
@ -184,25 +184,25 @@ InputDriveCell::InputDriveCell(LibertyLibrary *library,
}
void
InputDriveCell::setLibrary(LibertyLibrary *library)
InputDriveCell::setLibrary(const LibertyLibrary *library)
{
library_ = library;
}
void
InputDriveCell::setCell(LibertyCell *cell)
InputDriveCell::setCell(const LibertyCell *cell)
{
cell_ = cell;
}
void
InputDriveCell::setFromPort(LibertyPort *from_port)
InputDriveCell::setFromPort(const LibertyPort *from_port)
{
from_port_ = from_port;
}
void
InputDriveCell::setToPort(LibertyPort *to_port)
InputDriveCell::setToPort(const LibertyPort *to_port)
{
to_port_ = to_port;
}
@ -215,7 +215,7 @@ InputDriveCell::setFromSlews(float *from_slews)
}
bool
InputDriveCell::equal(InputDriveCell *drive) const
InputDriveCell::equal(const InputDriveCell *drive) const
{
int rise_index = RiseFall::riseIndex();
int fall_index = RiseFall::fallIndex();

51
sdc/PinPair.cc
View File

@ -16,32 +16,57 @@
#include "PinPair.hh"
#include "Network.hh"
namespace sta {
bool
PinPairLess::operator()(const PinPair *pair1,
const PinPair *pair2) const
PinPairLess::PinPairLess(const Network *network) :
network_(network)
{
return pair1->first < pair2->first
|| (pair1->first == pair2->first
&& pair1->second < pair2->second);
}
bool
PinPairEqual::operator()(const PinPair *pair1,
const PinPair *pair2) const
PinPairLess::operator()(const PinPair &pair1,
const PinPair &pair2) const
{
const Pin *pair1_pin1 = pair1.first;
const Pin *pair1_pin2 = pair1.second;
const Pin *pair2_pin1 = pair2.first;
const Pin *pair2_pin2 = pair2.second;
return (pair1_pin1 == nullptr && pair2_pin1)
|| (pair1_pin1 && pair2_pin1
&& (network_->id(pair1_pin1) < network_->id(pair2_pin1)
|| (pair1_pin1 == pair2_pin1
&& ((pair1_pin2 == nullptr && pair2_pin2)
|| (pair1_pin2 && pair2_pin2
&& network_->id(pair1_pin2) < network_->id(pair2_pin2))))));
}
bool
PinPairEqual::operator()(const PinPair &pair1,
const PinPair &pair2) const
{
return pair1.first == pair2.first
&& pair1.second == pair2.second;
}
PinPairHash::PinPairHash(const Network *network) :
network_(network)
{
return pair1->first == pair2->first
&& pair1->second == pair2->second;
}
size_t
PinPairHash::operator()(const PinPair *pair) const
PinPairHash::operator()(const PinPair &pair) const
{
size_t hash = hash_init_value;
hashIncr(hash, hashPtr(pair->first));
hashIncr(hash, hashPtr(pair->second));
hashIncr(hash, network_->id(pair.first));
hashIncr(hash, network_->id(pair.second));
return hash;
}
PinPairSet::PinPairSet(const Network *network) :
Set<PinPair, PinPairLess>(PinPairLess(network))
{
}
} // namespace

41
sdc/PortDelay.cc
View File

@ -21,15 +21,16 @@
namespace sta {
PortDelay::PortDelay(Pin *pin,
ClockEdge *clk_edge,
Pin *ref_pin) :
PortDelay::PortDelay(const Pin *pin,
const ClockEdge *clk_edge,
const Network *network) :
pin_(pin),
clk_edge_(clk_edge),
source_latency_included_(false),
network_latency_included_(false),
ref_pin_(ref_pin),
delays_()
ref_pin_(nullptr),
delays_(),
leaf_pins_(network)
{
}
@ -42,6 +43,12 @@ PortDelay::clock() const
return nullptr;
}
void
PortDelay::setRefPin(const Pin *ref_pin)
{
ref_pin_ = ref_pin;
}
bool
PortDelay::sourceLatencyIncluded() const
{
@ -76,22 +83,20 @@ PortDelay::refTransition() const
return RiseFall::rise();
}
InputDelay::InputDelay(Pin *pin,
ClockEdge *clk_edge,
Pin *ref_pin,
InputDelay::InputDelay(const Pin *pin,
const ClockEdge *clk_edge,
int index,
Network *network) :
PortDelay(pin, clk_edge, ref_pin),
const Network *network) :
PortDelay(pin, clk_edge, network),
index_(index)
{
findLeafLoadPins(pin, network, &leaf_pins_);
}
OutputDelay::OutputDelay(Pin *pin,
ClockEdge *clk_edge,
Pin *ref_pin,
Network *network) :
PortDelay(pin, clk_edge, ref_pin)
OutputDelay::OutputDelay(const Pin *pin,
const ClockEdge *clk_edge,
const Network *network) :
PortDelay(pin, clk_edge, network)
{
if (network)
findLeafDriverPins(pin, network, &leaf_pins_);
@ -106,10 +111,10 @@ PortDelayLess::PortDelayLess(const Network *network) :
bool
PortDelayLess::operator() (const PortDelay *delay1,
const PortDelay *delay2) const
const PortDelay *delay2) const
{
Pin *pin1 = delay1->pin();
Pin *pin2 = delay2->pin();
const Pin *pin1 = delay1->pin();
const Pin *pin2 = delay2->pin();
int pin_cmp = network_->pathNameCmp(pin1, pin2);
if (pin_cmp < 0)
return true;

2
sdc/PortExtCap.cc
View File

@ -18,7 +18,7 @@
namespace sta {
PortExtCap::PortExtCap(Port *port) :
PortExtCap::PortExtCap(const Port *port) :
port_(port)
{
}

1901
sdc/Sdc.cc
View File

File diff suppressed because it is too large Load Diff

70
sdc/SdcGraph.cc
View File

@ -26,8 +26,8 @@
namespace sta {
static void
annotateGraphDisabledWireEdge(Pin *from_pin,
Pin *to_pin,
annotateGraphDisabledWireEdge(const Pin *from_pin,
const Pin *to_pin,
Graph *graph);
// Annotate constraints to the timing graph.
@ -64,7 +64,7 @@ Sdc::annotateDisables()
{
PinSet::Iterator pin_iter(disabled_pins_);
while (pin_iter.hasNext()) {
Pin *pin = pin_iter.next();
const Pin *pin = pin_iter.next();
annotateGraphDisabled(pin);
}
@ -82,22 +82,16 @@ Sdc::annotateDisables()
Instance *top_inst = network_->topInstance();
PortSet::Iterator port_iter(disabled_ports_);
while (port_iter.hasNext()) {
Port *port = port_iter.next();
const Port *port = port_iter.next();
Pin *pin = network_->findPin(top_inst, port);
annotateGraphDisabled(pin);
}
PinPairSet::Iterator pair_iter(disabled_wire_edges_);
while (pair_iter.hasNext()) {
PinPair *pair = pair_iter.next();
annotateGraphDisabledWireEdge(pair->first, pair->second, graph_);
}
for (const PinPair &pair : disabled_wire_edges_)
annotateGraphDisabledWireEdge(pair.first, pair.second, graph_);
EdgeSet::Iterator edge_iter(disabled_edges_);
while (edge_iter.hasNext()) {
Edge *edge = edge_iter.next();
for (Edge *edge : disabled_edges_)
edge->setIsDisabledConstraint(true);
}
DisabledInstancePortsMap::Iterator disable_inst_iter(disabled_inst_ports_);
while (disable_inst_iter.hasNext()) {
@ -110,8 +104,8 @@ class DisableHpinEdgeVisitor : public HierPinThruVisitor
{
public:
DisableHpinEdgeVisitor(Graph *graph);
virtual void visit(Pin *from_pin,
Pin *to_pin);
virtual void visit(const Pin *from_pin,
const Pin *to_pin);
protected:
bool annotate_;
@ -125,15 +119,15 @@ DisableHpinEdgeVisitor::DisableHpinEdgeVisitor(Graph *graph) :
}
void
DisableHpinEdgeVisitor::visit(Pin *from_pin,
Pin *to_pin)
DisableHpinEdgeVisitor::visit(const Pin *from_pin,
const Pin *to_pin)
{
annotateGraphDisabledWireEdge(from_pin, to_pin, graph_);
}
static void
annotateGraphDisabledWireEdge(Pin *from_pin,
Pin *to_pin,
annotateGraphDisabledWireEdge(const Pin *from_pin,
const Pin *to_pin,
Graph *graph)
{
Vertex *from_vertex = graph->pinDrvrVertex(from_pin);
@ -208,24 +202,24 @@ Sdc::setEdgeDisabledInstPorts(DisabledPorts *disabled_port,
}
// Disable from/to pins.
LibertyPortPairSet::Iterator from_to_iter(disabled_port->fromTo());
while (from_to_iter.hasNext()) {
LibertyPortPair *pair = from_to_iter.next();
const LibertyPort *from_port = pair->first;
const LibertyPort *to_port = pair->second;
Pin *from_pin = network_->findPin(inst, from_port);
Pin *to_pin = network_->findPin(inst, to_port);
if (from_pin && network_->direction(from_pin)->isAnyInput()
&& to_pin) {
Vertex *from_vertex = graph_->pinLoadVertex(from_pin);
Vertex *to_vertex = graph_->pinDrvrVertex(to_pin);
if (from_vertex && to_vertex) {
VertexOutEdgeIterator edge_iter(from_vertex, graph_);
while (edge_iter.hasNext()) {
Edge *edge = edge_iter.next();
if (edge->to(graph_) == to_vertex)
edge->setIsDisabledConstraint(true);
}
if (disabled_port->fromTo()) {
for (const LibertyPortPair &from_to : *disabled_port->fromTo()) {
const LibertyPort *from_port = from_to.first;
const LibertyPort *to_port = from_to.second;
Pin *from_pin = network_->findPin(inst, from_port);
Pin *to_pin = network_->findPin(inst, to_port);
if (from_pin && network_->direction(from_pin)->isAnyInput()
&& to_pin) {
Vertex *from_vertex = graph_->pinLoadVertex(from_pin);
Vertex *to_vertex = graph_->pinDrvrVertex(to_pin);
if (from_vertex && to_vertex) {
VertexOutEdgeIterator edge_iter(from_vertex, graph_);
while (edge_iter.hasNext()) {
Edge *edge = edge_iter.next();
if (edge->to(graph_) == to_vertex)
edge->setIsDisabledConstraint(true);
}
}
}
}
}
@ -253,7 +247,7 @@ void
Sdc::annotateGraphOutputDelays()
{
for (OutputDelay *output_delay : output_delays_) {
for (Pin *lpin : output_delay->leafPins())
for (const Pin *lpin : output_delay->leafPins())
annotateGraphConstrained(lpin);
}
}

459
sdc/WriteSdc.cc
View File

@ -46,6 +46,7 @@
#include "Sdc.hh"
#include "Fuzzy.hh"
#include "StaState.hh"
#include "Corner.hh"
#include "WriteSdcPvt.hh"
namespace sta {
@ -465,9 +466,9 @@ WriteSdc::writeGeneratedClock(Clock *clk) const
}
void
WriteSdc::writeClockPins(Clock *clk) const
WriteSdc::writeClockPins(const Clock *clk) const
{
PinSet &pins = clk->pins();
const PinSet &pins = clk->pins();
if (!pins.empty()) {
if (pins.size() > 1)
gzprintf(stream_, "\\\n ");
@ -476,16 +477,16 @@ WriteSdc::writeClockPins(Clock *clk) const
}
void
WriteSdc::writeClockSlews(Clock *clk) const
WriteSdc::writeClockSlews(const Clock *clk) const
{
WriteGetClock write_clk(clk, this);
RiseFallMinMax *slews = clk->slews();
if (slews->hasValue())
writeRiseFallMinMaxTimeCmd("set_clock_transition", slews, write_clk);
const RiseFallMinMax slews = clk->slews();
if (slews.hasValue())
writeRiseFallMinMaxTimeCmd("set_clock_transition", &slews, write_clk);
}
void
WriteSdc::writeClockUncertainty(Clock *clk) const
WriteSdc::writeClockUncertainty(const Clock *clk) const
{
float setup;
bool setup_exists;
@ -504,7 +505,7 @@ WriteSdc::writeClockUncertainty(Clock *clk) const
}
void
WriteSdc::writeClockUncertainty(Clock *clk,
WriteSdc::writeClockUncertainty(const Clock *clk,
const char *setup_hold,
float value) const
{
@ -586,9 +587,7 @@ WriteSdc::writeClockLatencies() const
void
WriteSdc::writeClockInsertions() const
{
ClockInsertions::Iterator insert_iter(sdc_->clockInsertions());
while (insert_iter.hasNext()) {
ClockInsertion *insert = insert_iter.next();
for (ClockInsertion *insert : sdc_->clockInsertions()) {
const Pin *pin = insert->pin();
const Clock *clk = insert->clock();
if (pin && clk) {
@ -719,14 +718,10 @@ WriteSdc::writeOutputDelays() const
for (OutputDelay *output_delay : sdc_->outputDelays())
delays.push_back(output_delay);
PortDelayLess port_delay_less(sdc_network_);
sort(delays, port_delay_less);
sort(delays, PortDelayLess(sdc_network_));
PortDelaySeq::Iterator delay_iter(delays);
while (delay_iter.hasNext()) {
PortDelay *output_delay = delay_iter.next();
for (PortDelay *output_delay : delays)
writePortDelay(output_delay, false, "set_output_delay");
}
}
void
@ -803,7 +798,7 @@ WriteSdc::writePortDelay(PortDelay *port_delay,
{
gzprintf(stream_, "%s ", sdc_cmd);
writeTime(delay);
ClockEdge *clk_edge = port_delay->clkEdge();
const ClockEdge *clk_edge = port_delay->clkEdge();
if (clk_edge) {
writeClockKey(clk_edge->clock());
if (clk_edge->transition() == RiseFall::fall())
@ -812,7 +807,7 @@ WriteSdc::writePortDelay(PortDelay *port_delay,
gzprintf(stream_, "%s%s -add_delay ",
transRiseFallFlag(rf),
minMaxFlag(min_max));
Pin *ref_pin = port_delay->refPin();
const Pin *ref_pin = port_delay->refPin();
if (ref_pin) {
gzprintf(stream_, "-reference_pin ");
writeGetPin(ref_pin, true);
@ -906,24 +901,21 @@ bool
ClockGroupLess::operator()(const ClockGroup *clk_group1,
const ClockGroup *clk_group2) const
{
ClockSet *clk_set1 = clk_group1->clks();
ClockSet *clk_set2 = clk_group2->clks();
size_t size1 = clk_set1->size();
size_t size2 = clk_set2->size();
size_t size1 = clk_group1->size();
size_t size2 = clk_group2->size();
if (size1 < size2)
return true;
else if (size1 > size2)
return false;
else {
ClockSeq clks1, clks2;
ClockSet::Iterator clk_iter1(clk_set1);
while (clk_iter1.hasNext())
clks1.push_back(clk_iter1.next());
ClockSeq clks1;
for (Clock *clk1 : *clk_group1)
clks1.push_back(clk1);
sort(clks1, ClockNameLess());
ClockSet::Iterator clk_iter2(clk_set2);
while (clk_iter2.hasNext())
clks2.push_back(clk_iter2.next());
ClockSeq clks2;
for (Clock *clk2 : *clk_group2)
clks2.push_back(clk2);
sort(clks2, ClockNameLess());
ClockSeq::Iterator clk_iter3(clks1);
@ -977,7 +969,7 @@ WriteSdc::writeClockGroups(ClockGroups *clk_groups) const
if (!first)
gzprintf(stream_, "\\\n");
gzprintf(stream_, " -group ");
writeGetClocks(clk_group->clks());
writeGetClocks(clk_group);
first = false;
}
writeCmdComment(clk_groups);
@ -1000,25 +992,19 @@ WriteSdc::writeDisables() const
void
WriteSdc::writeDisabledCells() const
{
DisabledCellPortsSeq disables;
sortDisabledCellPortsMap(sdc_->disabledCellPorts(), disables);
DisabledCellPortsSeq::Iterator disabled_iter(disables);
while (disabled_iter.hasNext()) {
DisabledCellPorts *disable = disabled_iter.next();
LibertyCell *cell = disable->cell();
DisabledCellPortsSeq disables = sortByName(sdc_->disabledCellPorts());
for (const DisabledCellPorts *disable : disables) {
const LibertyCell *cell = disable->cell();
if (disable->all()) {
gzprintf(stream_, "set_disable_timing ");
writeGetLibCell(cell);
gzprintf(stream_, "\n");
}
if (disable->fromTo()) {
LibertyPortPairSeq pairs;
sortLibertyPortPairSet(disable->fromTo(), pairs);
LibertyPortPairSeq::Iterator pair_iter(pairs);
while (pair_iter.hasNext()) {
LibertyPortPair *from_to = pair_iter.next();
const LibertyPort *from = from_to->first;
const LibertyPort *to = from_to->second;
LibertyPortPairSeq from_tos = sortByName(disable->fromTo());
for (const LibertyPortPair &from_to : from_tos) {
const LibertyPort *from = from_to.first;
const LibertyPort *to = from_to.second;
gzprintf(stream_, "set_disable_timing -from {%s} -to {%s} ",
from->name(),
to->name());
@ -1027,11 +1013,8 @@ WriteSdc::writeDisabledCells() const
}
}
if (disable->from()) {
LibertyPortSeq from;
sortLibertyPortSet(disable->from(), from);
LibertyPortSeq::Iterator from_iter(from);
while (from_iter.hasNext()) {
LibertyPort *from_port = from_iter.next();
LibertyPortSeq from = sortByName(disable->from());
for (const LibertyPort *from_port : from) {
gzprintf(stream_, "set_disable_timing -from {%s} ",
from_port->name());
writeGetLibCell(cell);
@ -1039,11 +1022,8 @@ WriteSdc::writeDisabledCells() const
}
}
if (disable->to()) {
LibertyPortSeq to;
sortLibertyPortSet(disable->to(), to);
LibertyPortSeq::Iterator to_iter(to);
while (to_iter.hasNext()) {
LibertyPort *to_port = to_iter.next();
LibertyPortSeq to = sortByName(disable->to());
for (const LibertyPort *to_port : to) {
gzprintf(stream_, "set_disable_timing -to {%s} ",
to_port->name());
writeGetLibCell(cell);
@ -1063,11 +1043,8 @@ WriteSdc::writeDisabledCells() const
void
WriteSdc::writeDisabledPorts() const
{
PortSeq ports;
sortPortSet(sdc_->disabledPorts(), sdc_network_, ports);
PortSeq::Iterator port_iter(ports);
while (port_iter.hasNext()) {
Port *port = port_iter.next();
const PortSeq ports = sortByName(sdc_->disabledPorts(), sdc_network_);
for (const Port *port : ports) {
gzprintf(stream_, "set_disable_timing ");
writeGetPort(port);
gzprintf(stream_, "\n");
@ -1077,11 +1054,8 @@ WriteSdc::writeDisabledPorts() const
void
WriteSdc::writeDisabledLibPorts() const
{
LibertyPortSeq ports;
sortLibertyPortSet(sdc_->disabledLibPorts(), ports);
LibertyPortSeq::Iterator port_iter(ports);
while (port_iter.hasNext()) {
LibertyPort *port = port_iter.next();
LibertyPortSeq ports = sortByName(sdc_->disabledLibPorts());
for (LibertyPort *port : ports) {
gzprintf(stream_, "set_disable_timing ");
writeGetLibPin(port);
gzprintf(stream_, "\n");
@ -1091,12 +1065,9 @@ WriteSdc::writeDisabledLibPorts() const
void
WriteSdc::writeDisabledInstances() const
{
DisabledInstancePortsSeq disables;
sortDisabledInstancePortsMap(sdc_->disabledInstancePorts(),
sdc_network_, disables);
DisabledInstancePortsSeq::Iterator disabled_iter(disables);
while (disabled_iter.hasNext()) {
DisabledInstancePorts *disable = disabled_iter.next();
DisabledInstancePortsSeq disables = sortByPathName(sdc_->disabledInstancePorts(),
sdc_network_);
for (DisabledInstancePorts *disable : disables) {
Instance *inst = disable->instance();
if (disable->all()) {
gzprintf(stream_, "set_disable_timing ");
@ -1104,13 +1075,10 @@ WriteSdc::writeDisabledInstances() const
gzprintf(stream_, "\n");
}
else if (disable->fromTo()) {
LibertyPortPairSeq pairs;
sortLibertyPortPairSet(disable->fromTo(), pairs);
LibertyPortPairSeq::Iterator pair_iter(pairs);
while (pair_iter.hasNext()) {
LibertyPortPair *from_to = pair_iter.next();
const LibertyPort *from_port = from_to->first;
const LibertyPort *to_port = from_to->second;
LibertyPortPairSeq from_tos = sortByName(disable->fromTo());
for (LibertyPortPair &from_to : from_tos) {
const LibertyPort *from_port = from_to.first;
const LibertyPort *to_port = from_to.second;
gzprintf(stream_, "set_disable_timing -from {%s} -to {%s} ",
from_port->name(),
to_port->name());
@ -1119,11 +1087,8 @@ WriteSdc::writeDisabledInstances() const
}
}
if (disable->from()) {
LibertyPortSeq from;
sortLibertyPortSet(disable->from(), from);
LibertyPortSeq::Iterator from_iter(from);
while (from_iter.hasNext()) {
LibertyPort *from_port = from_iter.next();
LibertyPortSeq from = sortByName(disable->from());
for (const LibertyPort *from_port : from) {
gzprintf(stream_, "set_disable_timing -from {%s} ",
from_port->name());
writeGetInstance(inst);
@ -1131,11 +1096,8 @@ WriteSdc::writeDisabledInstances() const
}
}
if (disable->to()) {
LibertyPortSeq to;
sortLibertyPortSet(disable->to(), to);
LibertyPortSeq::Iterator to_iter(to);
while (to_iter.hasNext()) {
LibertyPort *to_port = to_iter.next();
LibertyPortSeq to = sortByName(disable->to());
for (const LibertyPort *to_port : to) {
gzprintf(stream_, "set_disable_timing -to {%s} ",
to_port->name());
writeGetInstance(inst);
@ -1148,11 +1110,8 @@ WriteSdc::writeDisabledInstances() const
void
WriteSdc::writeDisabledPins() const
{
PinSeq pins;
sortPinSet(sdc_->disabledPins(), sdc_network_, pins);
PinSeq::Iterator pin_iter(pins);
while (pin_iter.hasNext()) {
Pin *pin = pin_iter.next();
PinSeq pins = sortByPathName(sdc_->disabledPins(), sdc_network_);
for (const Pin *pin : pins) {
gzprintf(stream_, "set_disable_timing ");
writeGetPin(pin, false);
gzprintf(stream_, "\n");
@ -1163,15 +1122,10 @@ void
WriteSdc::writeDisabledEdges() const
{
EdgeSeq edges;
EdgeSet::Iterator edge_iter(sdc_->disabledEdges());
while (edge_iter.hasNext()) {
Edge *edge = edge_iter.next();
for (Edge *edge : *sdc_->disabledEdges())
edges.push_back(edge);
}
sortEdges(&edges, sdc_network_, graph_);
EdgeSeq::Iterator edge_iter2(edges);
while (edge_iter2.hasNext()) {
Edge *edge = edge_iter2.next();
for (Edge *edge : edges) {
EdgeSet matches;
findMatchingEdges(edge, matches);
if (matches.size() == 1)
@ -1200,9 +1154,7 @@ bool
WriteSdc::edgeSenseIsUnique(Edge *edge,
EdgeSet &matches) const
{
EdgeSet::Iterator match_iter(matches);
while (match_iter.hasNext()) {
Edge *match = match_iter.next();
for (Edge *match : matches) {
if (match != edge
&& match->sense() == edge->sense())
return false;
@ -1235,10 +1187,10 @@ void
WriteSdc::writeExceptions() const
{
ExceptionPathSeq exceptions;
sortExceptions(sdc_->exceptions(), exceptions, sdc_network_);
ExceptionPathSeq::Iterator except_iter(exceptions);
while (except_iter.hasNext()) {
ExceptionPath *exception = except_iter.next();
for (ExceptionPath *exception : *sdc_->exceptions())
exceptions.push_back(exception);
sort(exceptions, ExceptionPathLess(network_));
for (ExceptionPath *exception : exceptions) {
if (!exception->isFilter()
&& !exception->isLoop())
writeException(exception);
@ -1252,11 +1204,8 @@ WriteSdc::writeException(ExceptionPath *exception) const
if (exception->from())
writeExceptionFrom(exception->from());
if (exception->thrus()) {
ExceptionThruSeq::Iterator thru_iter(exception->thrus());
while (thru_iter.hasNext()) {
ExceptionThru *thru = thru_iter.next();
for (ExceptionThru *thru : *exception->thrus())
writeExceptionThru(thru);
}
}
if (exception->to())
writeExceptionTo(exception->to());
@ -1353,11 +1302,8 @@ WriteSdc::writeExceptionFromTo(ExceptionFromTo *from_to,
gzprintf(stream_, "[list ");
bool first = true;
if (from_to->pins()) {
PinSeq pins;
sortPinSet(from_to->pins(), sdc_network_, pins);
PinSeq::Iterator pin_iter(pins);
while (pin_iter.hasNext()) {
Pin *pin = pin_iter.next();
PinSeq pins = sortByPathName(from_to->pins(), sdc_network_);
for (const Pin *pin : pins) {
if (multi_objs && !first)
gzprintf(stream_, "\\\n ");
writeGetPin(pin, map_hpin_to_drvr);
@ -1367,11 +1313,8 @@ WriteSdc::writeExceptionFromTo(ExceptionFromTo *from_to,
if (from_to->clks())
writeGetClocks(from_to->clks(), multi_objs, first);
if (from_to->instances()) {
InstanceSeq insts;
sortInstanceSet(from_to->instances(), sdc_network_, insts);
InstanceSeq::Iterator inst_iter(insts);
while (inst_iter.hasNext()) {
Instance *inst = inst_iter.next();
InstanceSeq insts = sortByPathName(from_to->instances(), sdc_network_);
for (const Instance *inst : insts) {
if (multi_objs && !first)
gzprintf(stream_, "\\\n ");
writeGetInstance(inst);
@ -1402,9 +1345,7 @@ WriteSdc::writeExceptionThru(ExceptionThru *thru) const
gzprintf(stream_, "[list ");
bool first = true;
sort(pins, PinPathNameLess(network_));
PinSeq::Iterator pin_iter(pins);
while (pin_iter.hasNext()) {
Pin *pin = pin_iter.next();
for (const Pin *pin : pins) {
if (multi_objs && !first)
gzprintf(stream_, "\\\n ");
writeGetPin(pin);
@ -1412,11 +1353,8 @@ WriteSdc::writeExceptionThru(ExceptionThru *thru) const
}
if (thru->nets()) {
NetSeq nets;
sortNetSet(thru->nets(), sdc_network_, nets);
NetSeq::Iterator net_iter(nets);
while (net_iter.hasNext()) {
Net *net = net_iter.next();
NetSeq nets = sortByPathName(thru->nets(), sdc_network_);
for (const Net *net : nets) {
if (multi_objs && !first)
gzprintf(stream_, "\\\n ");
writeGetNet(net);
@ -1424,11 +1362,8 @@ WriteSdc::writeExceptionThru(ExceptionThru *thru) const
}
}
if (thru->instances()) {
InstanceSeq insts;
sortInstanceSet(thru->instances(), sdc_network_, insts);
InstanceSeq::Iterator inst_iter(insts);
while (inst_iter.hasNext()) {
Instance *inst = inst_iter.next();
InstanceSeq insts = sortByPathName(thru->instances(), sdc_network_);
for (const Instance *inst : insts) {
if (multi_objs && !first)
gzprintf(stream_, "\\\n ");
writeGetInstance(inst);
@ -1444,14 +1379,14 @@ WriteSdc::mapThruHpins(ExceptionThru *thru,
PinSeq &pins) const
{
if (thru->pins()) {
for (Pin *pin : *thru->pins()) {
for (const Pin *pin : *thru->pins()) {
// Map hierarical pins to load pins outside of outputs or inside of inputs.
if (network_->isHierarchical(pin)) {
Instance *hinst = network_->instance(pin);
bool hpin_is_output = network_->direction(pin)->isAnyOutput();
PinConnectedPinIterator *cpin_iter = network_->connectedPinIterator(pin);
while (cpin_iter->hasNext()) {
Pin *cpin = cpin_iter->next();
const Pin *cpin = cpin_iter->next();
if (network_->isLoad(cpin)
&& ((hpin_is_output
&& !network_->isInside(network_->instance(cpin), hinst))
@ -1473,21 +1408,14 @@ void
WriteSdc::writeDataChecks() const
{
Vector<DataCheck*> checks;
DataChecksMap::Iterator checks_iter(sdc_->data_checks_to_map_);
while (checks_iter.hasNext()) {
DataCheckSet *checks1 = checks_iter.next();
DataCheckSet::Iterator check_iter(checks1);
while (check_iter.hasNext()) {
DataCheck *check = check_iter.next();
for (auto pin_checks : sdc_->data_checks_to_map_) {
DataCheckSet *checks1 = pin_checks.second;
for (DataCheck *check : *checks1)
checks.push_back(check);
}
}
sort(checks, DataCheckLess(sdc_network_));
Vector<DataCheck*>::Iterator check_iter(checks);
while (check_iter.hasNext()) {
DataCheck *check = check_iter.next();
for (DataCheck *check : checks)
writeDataCheck(check);
}
}
void
@ -1582,29 +1510,28 @@ WriteSdc::writeWireload() const
void
WriteSdc::writeNetLoads() const
{
if (sdc_->net_wire_cap_map_) {
for (auto net_cap : *sdc_->net_wire_cap_map_) {
Net *net = net_cap.first;
MinMaxFloatValues &caps = net_cap.second;
float min_cap, max_cap;
bool min_exists, max_exists;
caps.value(MinMax::min(), min_cap, min_exists);
caps.value(MinMax::max(), max_cap, max_exists);
if (min_exists && max_exists
&& min_cap == max_cap)
writeNetLoad(net, MinMaxAll::all(), min_cap);
else {
if (min_exists)
writeNetLoad(net, MinMaxAll::min(), min_cap);
if (max_exists)
writeNetLoad(net, MinMaxAll::max(), max_cap);
}
int corner_index = 0; // missing corner arg
for (auto net_cap : sdc_->net_wire_cap_maps_[corner_index]) {
const Net *net = net_cap.first;
MinMaxFloatValues &caps = net_cap.second;
float min_cap, max_cap;
bool min_exists, max_exists;
caps.value(MinMax::min(), min_cap, min_exists);
caps.value(MinMax::max(), max_cap, max_exists);
if (min_exists && max_exists
&& min_cap == max_cap)
writeNetLoad(net, MinMaxAll::all(), min_cap);
else {
if (min_exists)
writeNetLoad(net, MinMaxAll::min(), min_cap);
if (max_exists)
writeNetLoad(net, MinMaxAll::max(), max_cap);
}
}
}
void
WriteSdc::writeNetLoad(Net *net,
WriteSdc::writeNetLoad(const Net *net,
const MinMaxAll *min_max,
float cap) const
{
@ -1628,9 +1555,10 @@ WriteSdc::writePortLoads() const
}
void
WriteSdc::writePortLoads(Port *port) const
WriteSdc::writePortLoads(const Port *port) const
{
PortExtCap *ext_cap = sdc_->portExtCap(port);
const Corner *corner = corners_->findCorner(0); // missing corner arg
PortExtCap *ext_cap = sdc_->portExtCap(port, corner);
if (ext_cap) {
WriteGetPort write_port(port, this);
writeRiseFallMinMaxCapCmd("set_load -pin_load",
@ -1748,11 +1676,11 @@ WriteSdc::writeDrivingCell(Port *port,
const RiseFall *rf,
const MinMax *min_max) const
{
LibertyCell *cell = drive_cell->cell();
LibertyPort *from_port = drive_cell->fromPort();
LibertyPort *to_port = drive_cell->toPort();
const LibertyCell *cell = drive_cell->cell();
const LibertyPort *from_port = drive_cell->fromPort();
const LibertyPort *to_port = drive_cell->toPort();
float *from_slews = drive_cell->fromSlews();
LibertyLibrary *lib = drive_cell->library();
const LibertyLibrary *lib = drive_cell->library();
gzprintf(stream_, "set_driving_cell");
if (rf)
gzprintf(stream_, " %s", transRiseFallFlag(rf));
@ -1795,19 +1723,13 @@ WriteSdc::writeInputTransitions() const
void
WriteSdc::writeNetResistances() const
{
NetResistanceMap *net_res_map = sdc_->netResistances();
NetSeq nets;
NetResistanceMap::Iterator res_iter(net_res_map);
while (res_iter.hasNext()) {
Net *net;
MinMaxFloatValues values;
res_iter.next(net, values);
for (auto net_res : sdc_->netResistances()) {
const Net *net = net_res.first;
nets.push_back(net);
}
sort(nets, NetPathNameLess(sdc_network_));
NetSeq::Iterator net_iter(nets);
while (net_iter.hasNext()) {
Net *net = net_iter.next();
for (const Net *net : nets) {
float min_res, max_res;
bool min_exists, max_exists;
sdc_->resistance(net, MinMax::min(), min_res, min_exists);
@ -1825,7 +1747,7 @@ WriteSdc::writeNetResistances() const
}
void
WriteSdc::writeNetResistance(Net *net,
WriteSdc::writeNetResistance(const Net *net,
const MinMaxAll *min_max,
float res) const
{
@ -1841,15 +1763,12 @@ WriteSdc::writeConstants() const
{
PinSeq pins;
sortedLogicValuePins(sdc_->logicValues(), pins);
PinSeq::Iterator pin_iter(pins);
while (pin_iter.hasNext()) {
Pin *pin = pin_iter.next();
for (const Pin *pin : pins)
writeConstant(pin);
}
}
void
WriteSdc::writeConstant(Pin *pin) const
WriteSdc::writeConstant(const Pin *pin) const
{
const char *cmd = setConstantCmd(pin);
gzprintf(stream_, "%s ", cmd);
@ -1858,7 +1777,7 @@ WriteSdc::writeConstant(Pin *pin) const
}
const char *
WriteSdc::setConstantCmd(Pin *pin) const
WriteSdc::setConstantCmd(const Pin *pin) const
{
LogicValue value;
bool exists;
@ -1883,16 +1802,13 @@ WriteSdc::writeCaseAnalysis() const
{
PinSeq pins;
sortedLogicValuePins(sdc_->caseLogicValues(), pins);
PinSeq::Iterator pin_iter(pins);
while (pin_iter.hasNext()) {
Pin *pin = pin_iter.next();
for (const Pin *pin : pins)
writeCaseAnalysis(pin);
}
}
void
WriteSdc::writeCaseAnalysis(Pin *pin) const
WriteSdc::writeCaseAnalysis(const Pin *pin) const
{
const char *value_str = caseAnalysisValueStr(pin);
gzprintf(stream_, "set_case_analysis %s ", value_str);
@ -1901,7 +1817,7 @@ WriteSdc::writeCaseAnalysis(Pin *pin) const
}
const char *
WriteSdc::caseAnalysisValueStr(Pin *pin) const
WriteSdc::caseAnalysisValueStr(const Pin *pin) const
{
LogicValue value;
bool exists;
@ -1923,15 +1839,12 @@ WriteSdc::caseAnalysisValueStr(Pin *pin) const
}
void
WriteSdc::sortedLogicValuePins(LogicValueMap *value_map,
WriteSdc::sortedLogicValuePins(LogicValueMap &value_map,
PinSeq &pins) const
{
LogicValueMap::ConstIterator value_iter(value_map);
while (value_iter.hasNext()) {
LogicValue value;
const Pin *pin;
value_iter.next(pin, value);
pins.push_back(const_cast<Pin*>(pin));
for (auto pin_value : value_map) {
const Pin *pin = pin_value.first;
pins.push_back(pin);
}
// Sort pins.
sort(pins, PinPathNameLess(sdc_network_));
@ -1946,11 +1859,9 @@ WriteSdc::writeDeratings() const
if (factors)
writeDerating(factors);
NetDeratingFactorsMap::Iterator net_iter(sdc_->net_derating_factors_);
while (net_iter.hasNext()) {
const Net *net;
DeratingFactorsNet *factors;
net_iter.next(net, factors);
for (auto net_derating : sdc_->net_derating_factors_) {
const Net *net = net_derating.first;
DeratingFactorsNet *factors = net_derating.second;
WriteGetNet write_net(net, this);
for (auto early_late : EarlyLate::range()) {
writeDerating(factors, TimingDerateType::net_delay, early_late,
@ -1958,20 +1869,16 @@ WriteSdc::writeDeratings() const
}
}
InstDeratingFactorsMap::Iterator inst_iter(sdc_->inst_derating_factors_);
while (inst_iter.hasNext()) {
const Instance *inst;
DeratingFactorsCell *factors;
inst_iter.next(inst, factors);
for (auto inst_derating : sdc_->inst_derating_factors_) {
const Instance *inst = inst_derating.first;
DeratingFactorsCell *factors = inst_derating.second;
WriteGetInstance write_inst(inst, this);
writeDerating(factors, &write_inst);
}
CellDeratingFactorsMap::Iterator cell_iter(sdc_->cell_derating_factors_);
while (cell_iter.hasNext()) {
const LibertyCell *cell;
DeratingFactorsCell *factors;
cell_iter.next(cell, factors);
for (auto cell_derating : sdc_->cell_derating_factors_) {
const LibertyCell *cell = cell_derating.first;
DeratingFactorsCell *factors = cell_derating.second;
WriteGetLibCell write_cell(cell, this);
writeDerating(factors, &write_cell);
}
@ -2120,30 +2027,23 @@ WriteSdc::writeDesignRules() const
void
WriteSdc::writeMinPulseWidths() const
{
PinMinPulseWidthMap::Iterator
pin_iter(sdc_->pin_min_pulse_width_map_);
while (pin_iter.hasNext()) {
const Pin *pin;
RiseFallValues *min_widths;
pin_iter.next(pin, min_widths);
for (auto pin_widths : sdc_->pin_min_pulse_width_map_) {
const Pin *pin = pin_widths.first;
RiseFallValues *min_widths = pin_widths.second;
WriteGetPin write_obj(pin, false, this);
writeMinPulseWidths(min_widths, write_obj);
}
InstMinPulseWidthMap::Iterator
inst_iter(sdc_->inst_min_pulse_width_map_);
while (inst_iter.hasNext()) {
const Instance *inst;
RiseFallValues *min_widths;
inst_iter.next(inst, min_widths);
for (auto inst_widths : sdc_->inst_min_pulse_width_map_) {
const Instance *inst = inst_widths.first;
RiseFallValues *min_widths = inst_widths.second;
WriteGetInstance write_obj(inst, this);
writeMinPulseWidths(min_widths, write_obj);
}
ClockMinPulseWidthMap::Iterator
clk_iter(sdc_->clk_min_pulse_width_map_);
while (clk_iter.hasNext()) {
const Clock *clk;
RiseFallValues *min_widths;
clk_iter.next(clk, min_widths);
for (auto clk_widths : sdc_->clk_min_pulse_width_map_) {
const Clock *clk = clk_widths.first;
RiseFallValues *min_widths = clk_widths.second;
WriteGetClock write_obj(clk, this);
writeMinPulseWidths(min_widths, write_obj);
}
@ -2185,36 +2085,29 @@ WriteSdc::writeMinPulseWidth(const char *hi_low,
void
WriteSdc::writeLatchBorowLimits() const
{
PinLatchBorrowLimitMap::Iterator
pin_iter(sdc_->pin_latch_borrow_limit_map_);
while (pin_iter.hasNext()) {
const Pin *pin;
float limit;
pin_iter.next(pin, limit);
for (auto pin_borrow : sdc_->pin_latch_borrow_limit_map_) {
const Pin *pin = pin_borrow.first;
float limit = pin_borrow.second;
gzprintf(stream_, "set_max_time_borrow ");
writeTime(limit);
gzprintf(stream_, " ");
writeGetPin(pin, false);
gzprintf(stream_, "\n");
}
InstLatchBorrowLimitMap::Iterator
inst_iter(sdc_->inst_latch_borrow_limit_map_);
while (inst_iter.hasNext()) {
const Instance *inst;
float limit;
inst_iter.next(inst, limit);
for (auto inst_borrow : sdc_->inst_latch_borrow_limit_map_) {
const Instance *inst = inst_borrow.first;
float limit = inst_borrow.second;
gzprintf(stream_, "set_max_time_borrow ");
writeTime(limit);
gzprintf(stream_, " ");
writeGetInstance(inst);
gzprintf(stream_, "\n");
}
ClockLatchBorrowLimitMap::Iterator
clk_iter(sdc_->clk_latch_borrow_limit_map_);
while (clk_iter.hasNext()) {
const Clock *clk;
float limit;
clk_iter.next(clk, limit);
for (auto clk_borrow : sdc_->clk_latch_borrow_limit_map_) {
const Clock *clk = clk_borrow.first;
float limit = clk_borrow.second;
gzprintf(stream_, "set_max_time_borrow ");
writeTime(limit);
gzprintf(stream_, " ");
@ -2261,9 +2154,7 @@ WriteSdc::writeClkSlewLimits() const
const MinMax *min_max = MinMax::max();
ClockSeq clks;
sdc_->sortedClocks(clks);
ClockSeq::Iterator clk_iter(clks);
while (clk_iter.hasNext()) {
Clock *clk = clk_iter.next();
for (const Clock *clk : clks) {
float rise_clk_limit, fall_clk_limit, rise_data_limit, fall_data_limit;
bool rise_clk_exists, fall_clk_exists, rise_data_exists, fall_data_exists;
clk->slewLimit(RiseFall::rise(), PathClkOrData::clk, min_max,
@ -2337,11 +2228,9 @@ WriteSdc::writeCapLimits(const MinMax *min_max,
gzprintf(stream_, " [current_design]\n");
}
PortCapLimitMap::Iterator port_iter(sdc_->port_cap_limit_map_);
while (port_iter.hasNext()) {
Port *port;
MinMaxFloatValues values;
port_iter.next(port, values);
for (auto port_limit : sdc_->port_cap_limit_map_) {
const Port *port = port_limit.first;
MinMaxFloatValues values = port_limit.second;
float cap;
bool exists;
values.value(min_max, cap, exists);
@ -2354,11 +2243,9 @@ WriteSdc::writeCapLimits(const MinMax *min_max,
}
}
PinCapLimitMap::Iterator pin_iter(sdc_->pin_cap_limit_map_);
while (pin_iter.hasNext()) {
Pin *pin;
MinMaxFloatValues values;
pin_iter.next(pin, values);
for (auto pin_limit : sdc_->pin_cap_limit_map_) {
const Pin *pin = pin_limit.first;
MinMaxFloatValues values = pin_limit.second;
float cap;
bool exists;
values.value(min_max, cap, exists);
@ -2441,7 +2328,7 @@ WriteSdc::writeVariables() const
////////////////////////////////////////////////////////////////
void
WriteSdc::writeGetTimingArcsOfOjbects(LibertyCell *cell) const
WriteSdc::writeGetTimingArcsOfOjbects(const LibertyCell *cell) const
{
gzprintf(stream_, "[%s -of_objects ", getTimingArcsCmd());
writeGetLibCell(cell);
@ -2513,11 +2400,8 @@ WriteSdc::writeGetClocks(ClockSet *clks,
bool multiple,
bool &first) const
{
ClockSeq clks1;
sortClockSet(clks, clks1);
ClockSeq::Iterator clk_iter(clks1);
while (clk_iter.hasNext()) {
Clock *clk = clk_iter.next();
ClockSeq clks1 = sortByName(clks);
for (const Clock *clk : clks1) {
if (multiple && !first)
gzprintf(stream_, "\\\n ");
writeGetClock(clk);
@ -2539,13 +2423,12 @@ WriteSdc::writeGetPort(const Port *port) const
}
void
WriteSdc::writeGetPins(PinSet *pins,
WriteSdc::writeGetPins(const PinSet *pins,
bool map_hpin_to_drvr) const
{
PinSeq pins1;
if (map_hpins_) {
PinSet leaf_pins;
for (Pin *pin : *pins) {
PinSet leaf_pins(network_);;
for (const Pin *pin : *pins) {
if (network_->isHierarchical(pin)) {
if (map_hpin_to_drvr)
findLeafDriverPins(const_cast<Pin*>(pin), network_, &leaf_pins);
@ -2555,11 +2438,13 @@ WriteSdc::writeGetPins(PinSet *pins,
else
leaf_pins.insert(pin);
}
sortPinSet(&leaf_pins, sdc_network_, pins1);
PinSeq pins1 = sortByPathName(&leaf_pins, sdc_network_);
writeGetPins1(&pins1);
}
else {
PinSeq pins1 = sortByPathName(pins, sdc_network_);
writeGetPins1(&pins1);
}
else
sortPinSet(pins, sdc_network_, pins1);
writeGetPins1(&pins1);
}
void
@ -2568,10 +2453,8 @@ WriteSdc::writeGetPins1(PinSeq *pins) const
bool multiple = pins->size() > 1;
if (multiple)
gzprintf(stream_, "[list ");
PinSeq::Iterator pin_iter(pins);
bool first = true;
while (pin_iter.hasNext()) {
Pin *pin = pin_iter.next();
for (const Pin *pin : *pins) {
if (multiple && !first)
gzprintf(stream_, "\\\n ");
writeGetPin(pin);
@ -2595,7 +2478,7 @@ WriteSdc::writeGetPin(const Pin *pin,
bool map_hpin_to_drvr) const
{
if (map_hpins_ && network_->isHierarchical(pin)) {
PinSet pins;
PinSet pins(network_);
pins.insert(const_cast<Pin*>(pin));
writeGetPins(&pins, map_hpin_to_drvr);
}
@ -2663,7 +2546,7 @@ WriteSdc::writeCommentSeparator() const
void
WriteSdc::writeRiseFallMinMaxTimeCmd(const char *sdc_cmd,
RiseFallMinMax *values,
const RiseFallMinMax *values,
WriteSdcObject &write_object) const
{
writeRiseFallMinMaxCmd(sdc_cmd, values, units_->timeUnit()->scale(),
@ -2672,7 +2555,7 @@ WriteSdc::writeRiseFallMinMaxTimeCmd(const char *sdc_cmd,
void
WriteSdc::writeRiseFallMinMaxCapCmd(const char *sdc_cmd,
RiseFallMinMax *values,
const RiseFallMinMax *values,
WriteSdcObject &write_object) const
{
writeRiseFallMinMaxCmd(sdc_cmd, values, units_->capacitanceUnit()->scale(),
@ -2681,7 +2564,7 @@ WriteSdc::writeRiseFallMinMaxCapCmd(const char *sdc_cmd,
void
WriteSdc::writeRiseFallMinMaxCmd(const char *sdc_cmd,
RiseFallMinMax *values,
const RiseFallMinMax *values,
float scale,
WriteSdcObject &write_object) const
{
@ -2897,10 +2780,8 @@ WriteSdc::writeFloatSeq(FloatSeq *floats,
float scale) const
{
gzprintf(stream_, "{");
FloatSeq::ConstIterator iter(floats);
bool first = true;
while (iter.hasNext()) {
float flt = iter.next();
for (float flt : *floats) {
if (!first)
gzprintf(stream_, " ");
writeFloat(flt * scale);
@ -2913,10 +2794,8 @@ void
WriteSdc::writeIntSeq(IntSeq *ints) const
{
gzprintf(stream_, "{");
IntSeq::ConstIterator iter(ints);
bool first = true;
while (iter.hasNext()) {
int i = iter.next();
for (int i : *ints) {
if (!first)
gzprintf(stream_, " ");
gzprintf(stream_, "%d", i);

36
sdc/WriteSdcPvt.hh
View File

@ -60,13 +60,13 @@ public:
void writeClocks() const;
void writeClock(Clock *clk) const;
void writeGeneratedClock(Clock *clk) const;
void writeClockPins(Clock *clk) const;
void writeClockPins(const Clock *clk) const;
void writeFloatSeq(FloatSeq *floats,
float scale) const;
void writeIntSeq(IntSeq *ints) const;
void writeClockSlews(Clock *clk) const;
void writeClockUncertainty(Clock *clk) const;
void writeClockUncertainty(Clock *clk,
void writeClockSlews(const Clock *clk) const;
void writeClockUncertainty(const Clock *clk) const;
void writeClockUncertainty(const Clock *clk,
const char *setup_hold,
float value) const;
void writeClockUncertaintyPins() const;
@ -121,12 +121,12 @@ public:
void writeOperatingConditions() const;
void writeWireload() const;
virtual void writeNetLoads() const;
void writeNetLoad(Net *net,
void writeNetLoad(const Net *net,
const MinMaxAll *min_max,
float cap) const;
void writePortLoads() const;
void writePortLoads(Port *port) const;
void writePortFanout(Port *port) const;
void writePortLoads(const Port *port) const;
void writePortFanout(const Port *port) const;
void writeDriveResistances() const;
void writeDrivingCells() const;
void writeInputTransitions() const;
@ -135,15 +135,15 @@ public:
const RiseFall *rf,
const MinMax *min_max) const;
void writeConstants() const;
virtual void writeConstant(Pin *pin) const;
const char *setConstantCmd(Pin *pin) const;
virtual void writeConstant(const Pin *pin) const;
const char *setConstantCmd(const Pin *pin) const;
void writeCaseAnalysis() const;
virtual void writeCaseAnalysis(Pin *pin) const;
const char *caseAnalysisValueStr(Pin *pin) const;
void sortedLogicValuePins(LogicValueMap *value_map,
virtual void writeCaseAnalysis(const Pin *pin) const;
const char *caseAnalysisValueStr(const Pin *pin) const;
void sortedLogicValuePins(LogicValueMap &value_map,
PinSeq &pins) const;
void writeNetResistances() const;
void writeNetResistance(Net *net,
void writeNetResistance(const Net *net,
const MinMaxAll *min_max,
float res) const;
void writeDesignRules() const;
@ -177,7 +177,7 @@ public:
void writeCommentSection(const char *line) const;
void writeCommentSeparator() const;
void writeGetTimingArcsOfOjbects(LibertyCell *cell) const;
void writeGetTimingArcsOfOjbects(const LibertyCell *cell) const;
void writeGetTimingArcs(Edge *edge) const;
void writeGetTimingArcs(Edge *edge,
const char *filter) const;
@ -195,7 +195,7 @@ public:
virtual void writeGetPin(const Pin *pin) const;
void writeGetPin(const Pin *pin,
bool map_hpin_to_drvr) const;
void writeGetPins(PinSet *pins,
void writeGetPins(const PinSet *pins,
bool map_hpin_to_drvr) const;
void writeGetPins1(PinSeq *pins) const;
void writeClockKey(const Clock *clk) const;
@ -213,13 +213,13 @@ public:
const Clock *clk,
float limit) const;
void writeRiseFallMinMaxTimeCmd(const char *sdc_cmd,
RiseFallMinMax *values,
const RiseFallMinMax *values,
WriteSdcObject &write_object) const;
void writeRiseFallMinMaxCapCmd(const char *sdc_cmd,
RiseFallMinMax *values,
const RiseFallMinMax *values,
WriteSdcObject &write_object) const;
void writeRiseFallMinMaxCmd(const char *sdc_cmd,
RiseFallMinMax *values,
const RiseFallMinMax *values,
float scale,
WriteSdcObject &write_object) const;
void writeRiseFallMinMaxCmd(const char *sdc_cmd,

22
sdf/ReportAnnotation.cc
View File

@ -78,7 +78,7 @@ protected:
void reportArcs(Vertex *vertex,
bool report_annotated,
int &i);
void reportWidthPeriodArcs(Pin *pin,
void reportWidthPeriodArcs(const Pin *pin,
bool report_annotated,
int &i);
void reportCount(const char *title,
@ -140,7 +140,9 @@ ReportAnnotated::ReportAnnotated(bool report_cells,
max_lines_(max_lines),
list_annotated_(list_annotated),
list_unannotated_(list_unannotated),
report_constant_arcs_(report_constant_arcs)
report_constant_arcs_(report_constant_arcs),
unannotated_pins_(sta->network()),
annotated_pins_(sta->network())
{
init();
report_role_[TimingRole::sdfIopath()->index()] = report_cells;
@ -224,7 +226,9 @@ ReportAnnotated::ReportAnnotated(bool report_setup,
max_lines_(max_lines),
list_annotated_(list_annotated),
list_unannotated_(list_unannotated),
report_constant_arcs_(report_constant_arcs)
report_constant_arcs_(report_constant_arcs),
unannotated_pins_(sta->network()),
annotated_pins_(sta->network())
{
init();
report_role_[TimingRole::setup()->index()] = report_setup;
@ -464,19 +468,17 @@ ReportAnnotated::reportArcs(const char *header,
{
report_->reportBlankLine();
report_->reportLineString(header);
PinSeq sorted_pins;
sortPinSet(&pins, network_, sorted_pins);
PinSeq pins1 = sortByPathName(&pins, network_);
int i = 0;
PinSeq::Iterator pin_iter(sorted_pins);
while (pin_iter.hasNext()
&& (max_lines_ == 0 || i < max_lines_)) {
Pin *pin = pin_iter.next();
for (const Pin *pin : pins1) {
Vertex *vertex, *bidirect_drvr_vertex;
graph_->pinVertices(pin, vertex, bidirect_drvr_vertex);
reportArcs(vertex, report_annotated, i);
if (bidirect_drvr_vertex)
reportArcs(bidirect_drvr_vertex, report_annotated, i);
reportWidthPeriodArcs(pin, report_annotated, i);
if (max_lines_ != 0 && i > max_lines_)
break;
}
}
@ -519,7 +521,7 @@ ReportAnnotated::reportArcs(Vertex *vertex,
}
void
ReportAnnotated::reportWidthPeriodArcs(Pin *pin,
ReportAnnotated::reportWidthPeriodArcs(const Pin *pin,
bool report_annotated,
int &i)
{

28
sdf/Sdf.tcl
View File

@ -59,11 +59,11 @@ proc_redirect read_sdf {
################################################################
define_cmd_args "report_annotated_delay" \
{[-cell] [-net] [-from_in_ports] [-to_out_ports] [-max_line lines]\
{[-cell] [-net] [-from_in_ports] [-to_out_ports] [-max_lines liness]\
[-list_annotated] [-list_not_annotated] [-constant_arcs]}
proc_redirect report_annotated_delay {
parse_key_args "report_annotated_delay" args keys {-max_line} \
parse_key_args "report_annotated_delay" args keys {-max_lines} \
flags {-cell -net -from_in_ports -to_out_ports -list_annotated \
-list_not_annotated -constant_arcs}
if { [info exists flags(-cell)] || [info exists flags(-net)] \
@ -80,26 +80,26 @@ proc_redirect report_annotated_delay {
set report_out_nets 1
}
set max_line 0
if { [info exists keys(-max_line)] } {
set max_line $keys(-max_line)
check_positive_integer "-max_line" $max_line
set max_lines 0
if { [info exists keys(-max_lines)] } {
set max_lines $keys(-max_lines)
check_positive_integer "-max_lines" $max_lines
}
report_annotated_delay_cmd $report_cells $report_nets \
$report_in_nets $report_out_nets \
$max_line [info exists flags(-list_annotated)] \
$max_lines [info exists flags(-list_annotated)] \
[info exists flags(-list_not_annotated)] \
[info exists flags(-constant_arcs)]
}
define_cmd_args "report_annotated_check" \
{[-setup] [-hold] [-recovery] [-removal] [-nochange] [-width] [-period]\
[-max_skew] [-max_line lines] [-list_annotated] [-list_not_annotated]\
[-max_skew] [-max_lines liness] [-list_annotated] [-list_not_annotated]\
[-constant_arcs]}
proc_redirect report_annotated_check {
parse_key_args "report_annotated_check" args keys {-max_line} \
parse_key_args "report_annotated_check" args keys {-max_lines} \
flags {-setup -hold -recovery -removal -nochange -width -period \
-max_skew -list_annotated -list_not_annotated -constant_arcs}
if { [info exists flags(-setup)] || [info exists flags(-hold)] \
@ -125,16 +125,16 @@ proc_redirect report_annotated_check {
set report_max_skew 1
}
set max_line 0
if { [info exists keys(-max_line)] } {
set max_line $keys(-max_line)
check_positive_integer "-max_line" $max_line
set max_lines 0
if { [info exists keys(-max_lines)] } {
set max_lines $keys(-max_lines)
check_positive_integer "-max_lines" $max_lines
}
report_annotated_check_cmd $report_setup $report_hold \
$report_recovery $report_removal $report_nochange \
$report_width $report_period $report_max_skew \
$max_line [info exists flags(-list_annotated)] \
$max_lines [info exists flags(-list_annotated)] \
[info exists flags(-list_not_annotated)] \
[info exists flags(-constant_arcs)]
}

4
sdf/SdfWriter.cc
View File

@ -740,10 +740,10 @@ SdfWriter::sdfPathName(const Pin *pin)
char *
SdfWriter::sdfPathName(const Instance *instance)
{
ConstInstanceSeq inst_path;
InstanceSeq inst_path;
network_->path(instance, inst_path);
size_t name_length = 0;
ConstInstanceSeq::Iterator path_iter1(inst_path);
InstanceSeq::Iterator path_iter1(inst_path);
while (path_iter1.hasNext()) {
const Instance *inst = path_iter1.next();
name_length += strlen(sdfName(inst)) + 1;

44
search/CheckCapacitanceLimits.cc
View File

@ -39,8 +39,8 @@ public:
const MinMax *min_max,
CheckCapacitanceLimits *check_capacitance_limit,
const StaState *sta);
bool operator()(Pin *pin1,
Pin *pin2) const;
bool operator()(const Pin *pin1,
const Pin *pin2) const;
private:
const Corner *corner_;
@ -62,8 +62,8 @@ PinCapacitanceLimitSlackLess::PinCapacitanceLimitSlackLess(const Corner *corner,
}
bool
PinCapacitanceLimitSlackLess::operator()(Pin *pin1,
Pin *pin2) const
PinCapacitanceLimitSlackLess::operator()(const Pin *pin1,
const Pin *pin2) const
{
const Corner *corner1, *corner2;
const RiseFall *rf1, *rf2;
@ -168,13 +168,13 @@ CheckCapacitanceLimits::findLimit(const Pin *pin,
InputDrive *drive = sdc->findInputDrive(port);
if (drive) {
for (auto rf : RiseFall::range()) {
LibertyCell *cell;
LibertyPort *from_port;
const LibertyCell *cell;
const LibertyPort *from_port;
float *from_slews;
LibertyPort *to_port;
const LibertyPort *to_port;
drive->driveCell(rf, min_max, cell, from_port, from_slews, to_port);
if (to_port) {
LibertyPort *corner_port = to_port->cornerPort(corner, min_max);
const LibertyPort *corner_port = to_port->cornerPort(corner, min_max);
corner_port->capacitanceLimit(min_max, limit1, exists1);
if (!exists1
&& corner_port->direction()->isAnyOutput()
@ -250,19 +250,19 @@ CheckCapacitanceLimits::checkCapacitance(const Pin *pin,
////////////////////////////////////////////////////////////////
PinSeq *
CheckCapacitanceLimits::checkCapacitanceLimits(Net *net,
PinSeq
CheckCapacitanceLimits::checkCapacitanceLimits(const Net *net,
bool violators,
const Corner *corner,
const MinMax *min_max)
{
const Network *network = sta_->network();
PinSeq *cap_pins = new PinSeq;
PinSeq cap_pins;
float min_slack = MinMax::min()->initValue();
if (net) {
NetPinIterator *pin_iter = network->pinIterator(net);
while (pin_iter->hasNext()) {
Pin *pin = pin_iter->next();
const Pin *pin = pin_iter->next();
checkCapLimits(pin, violators, corner, min_max, cap_pins, min_slack);
}
delete pin_iter;
@ -280,17 +280,17 @@ CheckCapacitanceLimits::checkCapacitanceLimits(Net *net,
}
sort(cap_pins, PinCapacitanceLimitSlackLess(corner, min_max, this, sta_));
// Keep the min slack pin unless all violators or net pins.
if (!cap_pins->empty() && !violators && net == nullptr)
cap_pins->resize(1);
if (!cap_pins.empty() && !violators && net == nullptr)
cap_pins.resize(1);
return cap_pins;
}
void
CheckCapacitanceLimits::checkCapLimits(Instance *inst,
CheckCapacitanceLimits::checkCapLimits(const Instance *inst,
bool violators,
const Corner *corner,
const MinMax *min_max,
PinSeq *cap_pins,
PinSeq &cap_pins,
float &min_slack)
{
const Network *network = sta_->network();
@ -303,11 +303,11 @@ CheckCapacitanceLimits::checkCapLimits(Instance *inst,
}
void
CheckCapacitanceLimits::checkCapLimits(Pin *pin,
CheckCapacitanceLimits::checkCapLimits(const Pin *pin,
bool violators,
const Corner *corner,
const MinMax *min_max,
PinSeq *cap_pins,
PinSeq &cap_pins,
float &min_slack)
{
if (checkPin(pin)) {
@ -318,12 +318,12 @@ CheckCapacitanceLimits::checkCapLimits(Pin *pin,
if (!fuzzyInf(slack)) {
if (violators) {
if (slack < 0.0)
cap_pins->push_back(pin);
cap_pins.push_back(pin);
}
else {
if (cap_pins->empty()
if (cap_pins.empty()
|| slack < min_slack) {
cap_pins->push_back(pin);
cap_pins.push_back(pin);
min_slack = slack;
}
}
@ -332,7 +332,7 @@ CheckCapacitanceLimits::checkCapLimits(Pin *pin,
}
bool
CheckCapacitanceLimits::checkPin(Pin *pin)
CheckCapacitanceLimits::checkPin(const Pin *pin)
{
const Network *network = sta_->network();
const Sim *sim = sta_->sim();

18
search/CheckCapacitanceLimits.hh
View File

@ -45,10 +45,10 @@ public:
// Return pins with the min/max cap limit slack.
// net=null check all nets
// corner=nullptr checks all corners.
PinSeq *checkCapacitanceLimits(Net *net,
bool violators,
const Corner *corner,
const MinMax *min_max);
PinSeq checkCapacitanceLimits(const Net *net,
bool violators,
const Corner *corner,
const MinMax *min_max);
protected:
void checkCapacitance(const Pin *pin,
@ -77,19 +77,19 @@ protected:
// Return values.
float &limit,
bool &limit_exists) const;
void checkCapLimits(Instance *inst,
void checkCapLimits(const Instance *inst,
bool violators,
const Corner *corner,
const MinMax *min_max,
PinSeq *cap_pins,
PinSeq &cap_pins,
float &min_slack);
void checkCapLimits(Pin *pin,
void checkCapLimits(const Pin *pin,
bool violators,
const Corner *corner,
const MinMax *min_max,
PinSeq *cap_pins,
PinSeq &cap_pins,
float &min_slack);
bool checkPin(Pin *pin);
bool checkPin(const Pin *pin);
const Sta *sta_;
};

48
search/CheckFanoutLimits.cc
View File

@ -34,8 +34,8 @@ public:
PinFanoutLimitSlackLess(const MinMax *min_max,
CheckFanoutLimits *check_fanout_limit,
const StaState *sta);
bool operator()(Pin *pin1,
Pin *pin2) const;
bool operator()(const Pin *pin1,
const Pin *pin2) const;
private:
const MinMax *min_max_;
@ -54,8 +54,8 @@ PinFanoutLimitSlackLess::PinFanoutLimitSlackLess(const MinMax *min_max,
}
bool
PinFanoutLimitSlackLess::operator()(Pin *pin1,
Pin *pin2) const
PinFanoutLimitSlackLess::operator()(const Pin *pin1,
const Pin *pin2) const
{
float fanout1, fanout2;
float limit1, limit2, slack1, slack2;
@ -130,10 +130,10 @@ CheckFanoutLimits::findLimit(const Pin *pin,
InputDrive *drive = sdc->findInputDrive(port);
if (drive) {
for (auto rf : RiseFall::range()) {
LibertyCell *cell;
LibertyPort *from_port;
const LibertyCell *cell;
const LibertyPort *from_port;
float *from_slews;
LibertyPort *to_port;
const LibertyPort *to_port;
drive->driveCell(rf, min_max, cell, from_port, from_slews, to_port);
if (to_port) {
to_port->fanoutLimit(min_max, limit1, exists1);
@ -205,7 +205,7 @@ CheckFanoutLimits::fanoutLoad(const Pin *pin) const
const Network *network = sta_->network();
NetConnectedPinIterator *pin_iter = network->connectedPinIterator(pin);
while (pin_iter->hasNext()) {
Pin *fanout_pin = pin_iter->next();
const Pin *fanout_pin = pin_iter->next();
if (network->isLoad(fanout_pin)
&& !network->isTopLevelPort(fanout_pin)) {
LibertyPort *port = network->libertyPort(fanout_pin);
@ -230,18 +230,18 @@ CheckFanoutLimits::fanoutLoad(const Pin *pin) const
////////////////////////////////////////////////////////////////
PinSeq *
CheckFanoutLimits::checkFanoutLimits(Net *net,
PinSeq
CheckFanoutLimits::checkFanoutLimits(const Net *net,
bool violators,
const MinMax *min_max)
{
const Network *network = sta_->network();
PinSeq *fanout_pins = new PinSeq;
PinSeq fanout_pins;
float min_slack = MinMax::min()->initValue();
if (net) {
NetPinIterator *pin_iter = network->pinIterator(net);
while (pin_iter->hasNext()) {
Pin *pin = pin_iter->next();
const Pin *pin = pin_iter->next();
checkFanoutLimits(pin, violators, min_max, fanout_pins, min_slack);
}
delete pin_iter;
@ -249,7 +249,7 @@ CheckFanoutLimits::checkFanoutLimits(Net *net,
else {
LeafInstanceIterator *inst_iter = network->leafInstanceIterator();
while (inst_iter->hasNext()) {
Instance *inst = inst_iter->next();
const Instance *inst = inst_iter->next();
checkFanoutLimits(inst, violators, min_max, fanout_pins, min_slack);
}
delete inst_iter;
@ -259,32 +259,32 @@ CheckFanoutLimits::checkFanoutLimits(Net *net,
}
sort(fanout_pins, PinFanoutLimitSlackLess(min_max, this, sta_));
// Keep the min slack pin unless all violators or net pins.
if (!fanout_pins->empty() && !violators && net == nullptr)
fanout_pins->resize(1);
if (!fanout_pins.empty() && !violators && net == nullptr)
fanout_pins.resize(1);
return fanout_pins;
}
void
CheckFanoutLimits::checkFanoutLimits(Instance *inst,
CheckFanoutLimits::checkFanoutLimits(const Instance *inst,
bool violators,
const MinMax *min_max,
PinSeq *fanout_pins,
PinSeq &fanout_pins,
float &min_slack)
{
const Network *network = sta_->network();
InstancePinIterator *pin_iter = network->pinIterator(inst);
while (pin_iter->hasNext()) {
Pin *pin = pin_iter->next();
const Pin *pin = pin_iter->next();
checkFanoutLimits(pin, violators, min_max, fanout_pins, min_slack);
}
delete pin_iter;
}
void
CheckFanoutLimits::checkFanoutLimits(Pin *pin,
CheckFanoutLimits::checkFanoutLimits(const Pin *pin,
bool violators,
const MinMax *min_max,
PinSeq *fanout_pins,
PinSeq &fanout_pins,
float &min_slack)
{
if (checkPin(pin)) {
@ -294,12 +294,12 @@ CheckFanoutLimits::checkFanoutLimits(Pin *pin,
if (!fuzzyInf(slack)) {
if (violators) {
if (slack < 0.0)
fanout_pins->push_back(pin);
fanout_pins.push_back(pin);
}
else {
if (fanout_pins->empty()
if (fanout_pins.empty()
|| slack < min_slack) {
fanout_pins->push_back(pin);
fanout_pins.push_back(pin);
min_slack = slack;
}
}
@ -308,7 +308,7 @@ CheckFanoutLimits::checkFanoutLimits(Pin *pin,
}
bool
CheckFanoutLimits::checkPin(Pin *pin)
CheckFanoutLimits::checkPin(const Pin *pin)
{
const Network *network = sta_->network();
const Sim *sim = sta_->sim();

16
search/CheckFanoutLimits.hh
View File

@ -38,9 +38,9 @@ public:
// Return pins with the min/max fanout limit slack.
// net=null check all nets
// corner=nullptr checks all corners.
PinSeq *checkFanoutLimits(Net *net,
bool violators,
const MinMax *min_max);
PinSeq checkFanoutLimits(const Net *net,
bool violators,
const MinMax *min_max);
protected:
void checkFanout(const Pin *pin,
@ -56,17 +56,17 @@ protected:
float &limit,
bool &limit_exists) const;
float fanoutLoad(const Pin *pin) const;
void checkFanoutLimits(Instance *inst,
void checkFanoutLimits(const Instance *inst,
bool violators,
const MinMax *min_max,
PinSeq *fanout_pins,
PinSeq &fanout_pins,
float &min_slack);
void checkFanoutLimits(Pin *pin,
void checkFanoutLimits(const Pin *pin,
bool violators,
const MinMax *min_max,
PinSeq *fanout_pins,
PinSeq &fanout_pins,
float &min_slack);
bool checkPin(Pin *pin);
bool checkPin(const Pin *pin);
const Sta *sta_;
};

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