Updated testing harness for the fix

Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>

test/regression_vars.tcl

@@ -166,6 +166,7 @@ record_public_tests {
   report_json1
   report_json2
   suppress_msg
+  test_write_verilog_escape
   verilog_attribute
   verilog_specify
 }

test/test_write_verilog_escape.ok

@@ -0,0 +1,17 @@
+module multi_sink (clk);
+ input clk;
+
+ wire \alu_adder_result_ex[0] ;
+
+ hier_block \h1\x  (.childclk(clk),
+    .\Y[2:1] ({\alu_adder_result_ex[0] ,
+    \alu_adder_result_ex[0] }));
+endmodule
+module hier_block (childclk,
+    \Y[2:1] );
+ input childclk;
+ output [1:0] \Y[2:1] ;
+
+
+ BUFx2_ASAP7_75t_R \ff0/name  (.A(childclk));
+endmodule

test/test_write_verilog_escape.tcl

@@ -1,11 +1,14 @@
 # Check if "h1\x" and \Y[2:1] are correctly processed from input to output of Verilog
-
-
 read_liberty gf180mcu_sram.lib.gz
 read_liberty asap7_small.lib.gz
-
 read_verilog test_write_verilog_escape.v
-
 link_design multi_sink
-
 write_verilog test_write_verilog_escape_out.v
+set input_file "test_write_verilog_escape_out.v"
+set fp [open $input_file r]
+while {[gets $fp line] >= 0} {
+    puts $line
+}
+close $fp
+file delete "test_write_verilog_escape_out.v"
+