From 2d8605ebc9f266e58e1bb4d0880987ac16921c70 Mon Sep 17 00:00:00 2001 From: dsengupta0628 Date: Tue, 10 Feb 2026 16:51:00 +0000 Subject: [PATCH] Updated testing harness for the fix Signed-off-by: dsengupta0628 --- test/regression_vars.tcl | 1 + test/test_write_verilog_escape.ok | 17 +++++++++++++++++ test/test_write_verilog_escape.tcl | 13 ++++++++----- 3 files changed, 26 insertions(+), 5 deletions(-) create mode 100644 test/test_write_verilog_escape.ok diff --git a/test/regression_vars.tcl b/test/regression_vars.tcl index acf6906b..581b3f14 100644 --- a/test/regression_vars.tcl +++ b/test/regression_vars.tcl @@ -166,6 +166,7 @@ record_public_tests { report_json1 report_json2 suppress_msg + test_write_verilog_escape verilog_attribute verilog_specify } diff --git a/test/test_write_verilog_escape.ok b/test/test_write_verilog_escape.ok new file mode 100644 index 00000000..7c2442cb --- /dev/null +++ b/test/test_write_verilog_escape.ok @@ -0,0 +1,17 @@ +module multi_sink (clk); + input clk; + + wire \alu_adder_result_ex[0] ; + + hier_block \h1\x (.childclk(clk), + .\Y[2:1] ({\alu_adder_result_ex[0] , + \alu_adder_result_ex[0] })); +endmodule +module hier_block (childclk, + \Y[2:1] ); + input childclk; + output [1:0] \Y[2:1] ; + + + BUFx2_ASAP7_75t_R \ff0/name (.A(childclk)); +endmodule diff --git a/test/test_write_verilog_escape.tcl b/test/test_write_verilog_escape.tcl index 2a4d684d..cad6cce3 100644 --- a/test/test_write_verilog_escape.tcl +++ b/test/test_write_verilog_escape.tcl @@ -1,11 +1,14 @@ # Check if "h1\x" and \Y[2:1] are correctly processed from input to output of Verilog - - read_liberty gf180mcu_sram.lib.gz read_liberty asap7_small.lib.gz - read_verilog test_write_verilog_escape.v - link_design multi_sink - write_verilog test_write_verilog_escape_out.v +set input_file "test_write_verilog_escape_out.v" +set fp [open $input_file r] +while {[gets $fp line] >= 0} { + puts $line +} +close $fp +file delete "test_write_verilog_escape_out.v" +