Merge pull request #294 from The-OpenROAD-Project-staging/secure-sta-test-by-opus
Add new Tcl and C++ test cases
This commit is contained in:
Matt Liberty
GitHub
commit
29cea73c3d
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@ -14,3 +14,20 @@ gtest_discover_tests(TestFindRoot
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WORKING_DIRECTORY ${STA_HOME}
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PROPERTIES LABELS "cpp\;module_dcalc"
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)
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add_executable(TestDcalc TestDcalc.cc)
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target_link_libraries(TestDcalc
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OpenSTA
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GTest::gtest
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GTest::gtest_main
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${TCL_LIBRARY}
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)
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target_include_directories(TestDcalc PRIVATE
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${STA_HOME}/include/sta
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${STA_HOME}
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${CMAKE_BINARY_DIR}/include/sta
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)
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gtest_discover_tests(TestDcalc
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WORKING_DIRECTORY ${STA_HOME}
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PROPERTIES LABELS "cpp\;module_dcalc"
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)
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,26 @@
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// Design with multi-driver nets and various gate types
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// for testing GraphDelayCalc multi-driver net handling
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module dcalc_multidriver_test (clk, in1, in2, in3, in4, sel, out1, out2, out3);
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input clk, in1, in2, in3, in4, sel;
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output out1, out2, out3;
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wire n1, n2, n3, n4, n5, n6, n7, n8, n9;
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// Chain path 1
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BUF_X1 buf1 (.A(in1), .Z(n1));
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INV_X1 inv1 (.A(n1), .ZN(n2));
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BUF_X2 buf2 (.A(n2), .Z(n3));
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// Chain path 2
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BUF_X4 buf3 (.A(in2), .Z(n4));
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AND2_X1 and1 (.A1(n4), .A2(in3), .ZN(n5));
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// Merging paths
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OR2_X1 or1 (.A1(n3), .A2(n5), .ZN(n6));
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NAND2_X1 nand1 (.A1(n6), .A2(sel), .ZN(n7));
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NOR2_X1 nor1 (.A1(n6), .A2(in4), .ZN(n8));
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// Output stage with registers
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DFF_X1 reg1 (.D(n7), .CK(clk), .Q(out1));
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DFF_X1 reg2 (.D(n8), .CK(clk), .Q(out2));
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BUF_X1 buf_out (.A(n6), .Z(out3));
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endmodule
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@ -0,0 +1,9 @@
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module dcalc_test1 (clk, in1, out1);
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input clk, in1;
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output out1;
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wire n1, n2;
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BUF_X1 buf1 (.A(in1), .Z(n1));
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INV_X1 inv1 (.A(n1), .ZN(n2));
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DFF_X1 reg1 (.D(n2), .CK(clk), .Q(out1));
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endmodule
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@ -1,6 +1,16 @@
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sta_module_tests("graph"
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TESTS
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advanced
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bidirect
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delay_corners
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delete_modify
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incremental
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make_verify
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modify
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operations
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timing_edges
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vertex_edge_ops
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wire_inst_edges
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)
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add_subdirectory(cpp)
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@ -0,0 +1,454 @@
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--- report_checks baseline ---
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Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: q (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg2/CK (DFF_X1)
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0.08 0.08 ^ reg2/Q (DFF_X1)
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0.00 0.08 ^ q (out)
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0.08 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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-1.00 9.00 output external delay
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9.00 data required time
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---------------------------------------------------------
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9.00 data required time
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-0.08 data arrival time
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---------------------------------------------------------
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8.92 slack (MET)
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--- report_checks -path_delay min ---
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: min
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg1/CK (DFF_X1)
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0.08 0.08 v reg1/Q (DFF_X1)
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0.00 0.08 v reg2/D (DFF_X1)
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0.08 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 ^ reg2/CK (DFF_X1)
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0.00 0.00 library hold time
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0.00 data required time
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---------------------------------------------------------
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0.00 data required time
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-0.08 data arrival time
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---------------------------------------------------------
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0.08 slack (MET)
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--- report_checks -path_delay max ---
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Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: q (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg2/CK (DFF_X1)
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0.08 0.08 ^ reg2/Q (DFF_X1)
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0.00 0.08 ^ q (out)
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0.08 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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-1.00 9.00 output external delay
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9.00 data required time
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---------------------------------------------------------
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9.00 data required time
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-0.08 data arrival time
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---------------------------------------------------------
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8.92 slack (MET)
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--- report_checks -from/-to ---
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No paths found.
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--- report_checks -through ---
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg1/CK (DFF_X1)
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0.08 0.08 v reg1/Q (DFF_X1)
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0.00 0.08 v reg2/D (DFF_X1)
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0.08 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg2/CK (DFF_X1)
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-0.04 9.96 library setup time
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9.96 data required time
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---------------------------------------------------------
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9.96 data required time
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-0.08 data arrival time
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---------------------------------------------------------
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9.88 slack (MET)
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--- get_timing_edges full combinations ---
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reg1 all edges: 1
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reg2 all edges: 1
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--- report_edges for cells ---
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CK -> Q Reg Clk to Q
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^ -> ^ 0.08:0.08
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^ -> v 0.08:0.08
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CK -> Q Reg Clk to Q
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^ -> ^ 0.08:0.08
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^ -> v 0.08:0.08
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CK -> QN Reg Clk to Q
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^ -> ^ 0.06:0.06
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^ -> v 0.06:0.06
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CK -> Q Reg Clk to Q
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^ -> ^ 0.08:0.08
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^ -> v 0.08:0.08
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CK -> CK width
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^ -> v 0.05:0.05
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v -> ^ 0.05:0.05
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CK -> D setup
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^ -> ^ 0.05:0.05
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^ -> v 0.07:0.07
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CK -> D hold
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^ -> ^ 0.05:0.05
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^ -> v 0.05:0.05
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CK -> D setup
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^ -> ^ 0.03:0.03
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^ -> v 0.04:0.04
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CK -> D hold
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^ -> ^ 0.01:0.01
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^ -> v 0.00:0.00
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reg1/Q -> D wire
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^ -> ^ 0.00:0.00
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v -> v 0.00:0.00
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--- disable_timing on port pin ---
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reg1 CK Q constraint
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reg2 CK Q constraint
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Startpoint: d (input port clocked by clk)
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Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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1.00 1.00 v input external delay
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0.00 1.00 v d (in)
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0.00 1.00 v reg1/D (DFF_X1)
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1.00 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg1/CK (DFF_X1)
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-0.07 9.93 library setup time
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9.93 data required time
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---------------------------------------------------------
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9.93 data required time
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-1.00 data arrival time
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---------------------------------------------------------
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8.93 slack (MET)
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--- set_disable_timing instance and back ---
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reg1 CK Q constraint
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reg1 CK QN constraint
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Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: q (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg2/CK (DFF_X1)
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0.08 0.08 ^ reg2/Q (DFF_X1)
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0.00 0.08 ^ q (out)
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0.08 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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-1.00 9.00 output external delay
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9.00 data required time
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---------------------------------------------------------
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9.00 data required time
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-0.08 data arrival time
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---------------------------------------------------------
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8.92 slack (MET)
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Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: q (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg2/CK (DFF_X1)
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0.08 0.08 ^ reg2/Q (DFF_X1)
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0.00 0.08 ^ q (out)
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0.08 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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-1.00 9.00 output external delay
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9.00 data required time
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---------------------------------------------------------
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9.00 data required time
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-0.08 data arrival time
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---------------------------------------------------------
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8.92 slack (MET)
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--- report_slews for various pins ---
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d ^ 0.10:0.10 v 0.10:0.10
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q ^ 0.01:0.01 v 0.00:0.00
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reg1/CK ^ 0.00:0.00 v 0.00:0.00
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reg1/Q ^ 0.01:0.01 v 0.01:0.01
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reg2/D ^ 0.01:0.01 v 0.01:0.01
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--- report_check_types ---
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: min
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg1/CK (DFF_X1)
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0.08 0.08 v reg1/Q (DFF_X1)
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0.00 0.08 v reg2/D (DFF_X1)
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0.08 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 ^ reg2/CK (DFF_X1)
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0.00 0.00 library hold time
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0.00 data required time
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---------------------------------------------------------
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0.00 data required time
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-0.08 data arrival time
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---------------------------------------------------------
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0.08 slack (MET)
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Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: q (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg2/CK (DFF_X1)
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0.08 0.08 ^ reg2/Q (DFF_X1)
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0.00 0.08 ^ q (out)
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0.08 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
|
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0.00 10.00 clock reconvergence pessimism
|
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-1.00 9.00 output external delay
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9.00 data required time
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||||
---------------------------------------------------------
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||||
9.00 data required time
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-0.08 data arrival time
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---------------------------------------------------------
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8.92 slack (MET)
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--- report_checks with -format ---
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Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: q (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
|
||||
---------------------------------------------------------
|
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0.00 0.00 clock clk (rise edge)
|
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0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg2/CK (DFF_X1)
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||||
0.08 0.08 ^ reg2/Q (DFF_X1)
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||||
0.00 0.08 ^ q (out)
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||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
-1.00 9.00 output external delay
|
||||
9.00 data required time
|
||||
---------------------------------------------------------
|
||||
9.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.92 slack (MET)
|
||||
|
||||
|
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--- report_checks -unconstrained ---
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Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: q (output port clocked by clk)
|
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Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg2/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg2/Q (DFF_X1)
|
||||
0.00 0.08 ^ q (out)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
-1.00 9.00 output external delay
|
||||
9.00 data required time
|
||||
---------------------------------------------------------
|
||||
9.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.92 slack (MET)
|
||||
|
||||
|
||||
--- report_checks -group_count 2 ---
|
||||
Warning 503: graph_advanced.tcl line 1, report_checks -group_count is deprecated. Use -group_path_count instead.
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: q (output port clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg2/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg2/Q (DFF_X1)
|
||||
0.00 0.08 ^ q (out)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
-1.00 9.00 output external delay
|
||||
9.00 data required time
|
||||
---------------------------------------------------------
|
||||
9.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.92 slack (MET)
|
||||
|
||||
|
||||
Startpoint: d (input port clocked by clk)
|
||||
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d (in)
|
||||
0.00 1.00 v reg1/D (DFF_X1)
|
||||
1.00 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg1/CK (DFF_X1)
|
||||
-0.07 9.93 library setup time
|
||||
9.93 data required time
|
||||
---------------------------------------------------------
|
||||
9.93 data required time
|
||||
-1.00 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.93 slack (MET)
|
||||
|
||||
|
||||
--- report_checks -endpoint_count 2 ---
|
||||
Warning 502: graph_advanced.tcl line 1, report_checks -endpoint_count is deprecated. Use -endpoint_path_count instead.
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: q (output port clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg2/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg2/Q (DFF_X1)
|
||||
0.00 0.08 ^ q (out)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
-1.00 9.00 output external delay
|
||||
9.00 data required time
|
||||
---------------------------------------------------------
|
||||
9.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.92 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: q (output port clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg2/CK (DFF_X1)
|
||||
0.08 0.08 v reg2/Q (DFF_X1)
|
||||
0.00 0.08 v q (out)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
-1.00 9.00 output external delay
|
||||
9.00 data required time
|
||||
---------------------------------------------------------
|
||||
9.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.92 slack (MET)
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,107 @@
|
|||
# Test advanced graph operations: multiple-instance design, edge traversal,
|
||||
# and graph info queries.
|
||||
# Targets uncovered Graph.cc functions: vertex operations, edge iterators,
|
||||
# constant propagation, level reporting, etc.
|
||||
|
||||
source ../../test/helpers.tcl
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Load a larger design for more graph coverage
|
||||
#---------------------------------------------------------------
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
read_verilog graph_test1.v
|
||||
link_design graph_test1
|
||||
|
||||
create_clock -name clk -period 10 [get_ports clk]
|
||||
set_input_delay -clock clk 1.0 [get_ports d]
|
||||
set_output_delay -clock clk 1.0 [get_ports q]
|
||||
set_input_transition 0.1 [get_ports d]
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# report_checks exercises graph traversal
|
||||
#---------------------------------------------------------------
|
||||
puts "--- report_checks baseline ---"
|
||||
report_checks
|
||||
|
||||
puts "--- report_checks -path_delay min ---"
|
||||
report_checks -path_delay min
|
||||
|
||||
puts "--- report_checks -path_delay max ---"
|
||||
report_checks -path_delay max
|
||||
|
||||
puts "--- report_checks -from/-to ---"
|
||||
report_checks -from [get_ports d] -to [get_ports q]
|
||||
|
||||
puts "--- report_checks -through ---"
|
||||
report_checks -through [get_pins reg1/Q]
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Edge queries (Graph.cc edge functions)
|
||||
#---------------------------------------------------------------
|
||||
puts "--- get_timing_edges full combinations ---"
|
||||
set edges_all [get_timing_edges -of_objects [get_cells reg1]]
|
||||
puts "reg1 all edges: [llength $edges_all]"
|
||||
|
||||
set edges_all2 [get_timing_edges -of_objects [get_cells reg2]]
|
||||
puts "reg2 all edges: [llength $edges_all2]"
|
||||
|
||||
puts "--- report_edges for cells ---"
|
||||
report_edges -from [get_pins reg1/CK] -to [get_pins reg1/Q]
|
||||
|
||||
report_edges -from [get_pins reg2/CK] -to [get_pins reg2/Q]
|
||||
|
||||
report_edges -from [get_pins reg1/CK]
|
||||
|
||||
report_edges -to [get_pins reg2/D]
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# set_disable_timing / report_disabled_edges exercises more paths
|
||||
#---------------------------------------------------------------
|
||||
puts "--- disable_timing on port pin ---"
|
||||
set_disable_timing -from CK -to Q [get_lib_cells NangateOpenCellLibrary/DFF_X1]
|
||||
report_disabled_edges
|
||||
|
||||
report_checks
|
||||
|
||||
unset_disable_timing -from CK -to Q [get_lib_cells NangateOpenCellLibrary/DFF_X1]
|
||||
report_disabled_edges
|
||||
|
||||
puts "--- set_disable_timing instance and back ---"
|
||||
set_disable_timing [get_cells reg1]
|
||||
report_disabled_edges
|
||||
report_checks
|
||||
|
||||
unset_disable_timing [get_cells reg1]
|
||||
report_disabled_edges
|
||||
report_checks
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Slew reporting (exercises vertex slew access)
|
||||
#---------------------------------------------------------------
|
||||
puts "--- report_slews for various pins ---"
|
||||
report_slews [get_ports d]
|
||||
report_slews [get_ports q]
|
||||
report_slews [get_pins reg1/CK]
|
||||
report_slews [get_pins reg1/Q]
|
||||
report_slews [get_pins reg2/D]
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Graph verification
|
||||
#---------------------------------------------------------------
|
||||
puts "--- report_check_types ---"
|
||||
report_check_types -max_delay -min_delay -verbose
|
||||
|
||||
puts "--- report_checks with -format ---"
|
||||
report_checks -format full_clock
|
||||
|
||||
puts "--- report_checks -unconstrained ---"
|
||||
report_checks -unconstrained
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Additional graph traversals (exercises more vertex/edge paths)
|
||||
#---------------------------------------------------------------
|
||||
puts "--- report_checks -group_count 2 ---"
|
||||
report_checks -group_count 2
|
||||
|
||||
puts "--- report_checks -endpoint_count 2 ---"
|
||||
report_checks -endpoint_count 2
|
||||
|
|
@ -0,0 +1,943 @@
|
|||
--- Test 1: graph with reconvergent paths ---
|
||||
Startpoint: d1 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 v input external delay
|
||||
0.00 0.00 v d1 (in)
|
||||
0.06 0.06 v buf1/Z (BUF_X1)
|
||||
0.05 0.10 v or1/ZN (OR2_X1)
|
||||
0.03 0.13 v and2/ZN (AND2_X1)
|
||||
0.00 0.13 v reg2/D (DFF_X1)
|
||||
0.13 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.04 9.96 library setup time
|
||||
9.96 data required time
|
||||
---------------------------------------------------------
|
||||
9.96 data required time
|
||||
-0.13 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.83 slack (MET)
|
||||
|
||||
|
||||
Startpoint: d4 (input port clocked by clk)
|
||||
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: min
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ input external delay
|
||||
0.00 0.00 ^ d4 (in)
|
||||
0.01 0.01 v inv2/ZN (INV_X1)
|
||||
0.02 0.03 ^ nand1/ZN (NAND2_X1)
|
||||
0.02 0.05 ^ or2/ZN (OR2_X1)
|
||||
0.00 0.05 ^ reg3/D (DFF_X1)
|
||||
0.05 data arrival time
|
||||
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 clock reconvergence pessimism
|
||||
0.00 ^ reg3/CK (DFF_X1)
|
||||
0.00 0.00 library hold time
|
||||
0.00 data required time
|
||||
---------------------------------------------------------
|
||||
0.00 data required time
|
||||
-0.05 data arrival time
|
||||
---------------------------------------------------------
|
||||
0.05 slack (MET)
|
||||
|
||||
|
||||
--- Test 2: path queries ---
|
||||
No paths found.
|
||||
No paths found.
|
||||
No paths found.
|
||||
No paths found.
|
||||
No paths found.
|
||||
No paths found.
|
||||
No paths found.
|
||||
--- Test 3: report with fields ---
|
||||
Warning 168: graph_bidirect.tcl line 1, unknown field nets.
|
||||
Startpoint: d1 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Fanout Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------------
|
||||
0.00 0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 v input external delay
|
||||
1 0.88 0.10 0.00 0.00 v d1 (in)
|
||||
0.10 0.00 0.00 v buf1/A (BUF_X1)
|
||||
2 1.67 0.01 0.06 0.06 v buf1/Z (BUF_X1)
|
||||
0.01 0.00 0.06 v or1/A1 (OR2_X1)
|
||||
2 1.96 0.01 0.05 0.10 v or1/ZN (OR2_X1)
|
||||
0.01 0.00 0.10 v and2/A2 (AND2_X1)
|
||||
1 1.06 0.01 0.03 0.13 v and2/ZN (AND2_X1)
|
||||
0.01 0.00 0.13 v reg2/D (DFF_X1)
|
||||
0.13 data arrival time
|
||||
|
||||
0.00 10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.04 9.96 library setup time
|
||||
9.96 data required time
|
||||
-----------------------------------------------------------------------------
|
||||
9.96 data required time
|
||||
-0.13 data arrival time
|
||||
-----------------------------------------------------------------------------
|
||||
9.83 slack (MET)
|
||||
|
||||
|
||||
Startpoint: d1 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 v input external delay
|
||||
0.00 0.00 v d1 (in)
|
||||
0.06 0.06 v buf1/Z (BUF_X1)
|
||||
0.05 0.10 v or1/ZN (OR2_X1)
|
||||
0.03 0.13 v and2/ZN (AND2_X1)
|
||||
0.00 0.13 v reg2/D (DFF_X1)
|
||||
0.13 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.04 9.96 library setup time
|
||||
9.96 data required time
|
||||
---------------------------------------------------------
|
||||
9.96 data required time
|
||||
-0.13 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.83 slack (MET)
|
||||
|
||||
|
||||
Startpoint: d4 (input port clocked by clk)
|
||||
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: min
|
||||
|
||||
Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------
|
||||
0.00 0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ input external delay
|
||||
1.70 0.10 0.00 0.00 ^ d4 (in)
|
||||
3.07 0.02 0.01 0.01 v inv2/ZN (INV_X1)
|
||||
0.95 0.01 0.02 0.03 ^ nand1/ZN (NAND2_X1)
|
||||
1.14 0.01 0.02 0.05 ^ or2/ZN (OR2_X1)
|
||||
0.01 0.00 0.05 ^ reg3/D (DFF_X1)
|
||||
0.05 data arrival time
|
||||
|
||||
0.00 0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 clock reconvergence pessimism
|
||||
0.00 ^ reg3/CK (DFF_X1)
|
||||
0.00 0.00 library hold time
|
||||
0.00 data required time
|
||||
-----------------------------------------------------------------------
|
||||
0.00 data required time
|
||||
-0.05 data arrival time
|
||||
-----------------------------------------------------------------------
|
||||
0.05 slack (MET)
|
||||
|
||||
|
||||
--- Test 4: fanin/fanout ---
|
||||
fanin to q2: 3
|
||||
fanout from d1: 13
|
||||
fanin cells to q2: 2
|
||||
fanout cells from d1: 8
|
||||
fanin to q3: 3
|
||||
fanout from d3: 14
|
||||
--- Test 5: report_dcalc ---
|
||||
Library: NangateOpenCellLibrary
|
||||
Cell: BUF_X1
|
||||
Arc sense: positive_unate
|
||||
Arc type: combinational
|
||||
A ^ -> Z ^
|
||||
P = 1.00 V = 1.10 T = 25.00
|
||||
------- input_net_transition = 0.10
|
||||
| total_output_net_capacitance = 1.86
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.08 | 0.03 0.03
|
||||
0.13 | 0.03 0.04
|
||||
Table value = 0.03
|
||||
PVT scale factor = 1.00
|
||||
Delay = 0.03
|
||||
|
||||
------- input_net_transition = 0.10
|
||||
| total_output_net_capacitance = 1.86
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.08 | 0.01 0.01
|
||||
0.13 | 0.01 0.01
|
||||
Table value = 0.01
|
||||
PVT scale factor = 1.00
|
||||
Slew = 0.01
|
||||
Driver waveform slew = 0.01
|
||||
|
||||
.............................................
|
||||
|
||||
A v -> Z v
|
||||
P = 1.00 V = 1.10 T = 25.00
|
||||
------- input_net_transition = 0.10
|
||||
| total_output_net_capacitance = 1.67
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.08 | 0.05 0.05
|
||||
0.13 | 0.06 0.07
|
||||
Table value = 0.06
|
||||
PVT scale factor = 1.00
|
||||
Delay = 0.06
|
||||
|
||||
------- input_net_transition = 0.10
|
||||
| total_output_net_capacitance = 1.67
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.08 | 0.01 0.01
|
||||
0.13 | 0.01 0.01
|
||||
Table value = 0.01
|
||||
PVT scale factor = 1.00
|
||||
Slew = 0.01
|
||||
Driver waveform slew = 0.01
|
||||
|
||||
.............................................
|
||||
|
||||
dcalc buf1: done
|
||||
Library: NangateOpenCellLibrary
|
||||
Cell: AND2_X1
|
||||
Arc sense: positive_unate
|
||||
Arc type: combinational
|
||||
A1 ^ -> ZN ^
|
||||
P = 1.00 V = 1.10 T = 25.00
|
||||
------- input_net_transition = 0.01
|
||||
| total_output_net_capacitance = 2.06
|
||||
| 1.89 3.79
|
||||
v --------------------
|
||||
0.00 | 0.03 0.03
|
||||
0.02 | 0.03 0.04
|
||||
Table value = 0.03
|
||||
PVT scale factor = 1.00
|
||||
Delay = 0.03
|
||||
|
||||
------- input_net_transition = 0.01
|
||||
| total_output_net_capacitance = 2.06
|
||||
| 1.89 3.79
|
||||
v --------------------
|
||||
0.00 | 0.01 0.01
|
||||
0.02 | 0.01 0.01
|
||||
Table value = 0.01
|
||||
PVT scale factor = 1.00
|
||||
Slew = 0.01
|
||||
Driver waveform slew = 0.01
|
||||
|
||||
.............................................
|
||||
|
||||
A1 v -> ZN v
|
||||
P = 1.00 V = 1.10 T = 25.00
|
||||
------- input_net_transition = 0.01
|
||||
| total_output_net_capacitance = 1.94
|
||||
| 1.89 3.79
|
||||
v --------------------
|
||||
0.00 | 0.03 0.03
|
||||
0.02 | 0.03 0.04
|
||||
Table value = 0.03
|
||||
PVT scale factor = 1.00
|
||||
Delay = 0.03
|
||||
|
||||
------- input_net_transition = 0.01
|
||||
| total_output_net_capacitance = 1.94
|
||||
| 1.89 3.79
|
||||
v --------------------
|
||||
0.00 | 0.01 0.01
|
||||
0.02 | 0.01 0.01
|
||||
Table value = 0.01
|
||||
PVT scale factor = 1.00
|
||||
Slew = 0.01
|
||||
Driver waveform slew = 0.01
|
||||
|
||||
.............................................
|
||||
|
||||
dcalc and1 A1: done
|
||||
Library: NangateOpenCellLibrary
|
||||
Cell: AND2_X1
|
||||
Arc sense: positive_unate
|
||||
Arc type: combinational
|
||||
A2 ^ -> ZN ^
|
||||
P = 1.00 V = 1.10 T = 25.00
|
||||
------- input_net_transition = 0.01
|
||||
| total_output_net_capacitance = 2.06
|
||||
| 1.89 3.79
|
||||
v --------------------
|
||||
0.00 | 0.03 0.04
|
||||
0.02 | 0.03 0.04
|
||||
Table value = 0.03
|
||||
PVT scale factor = 1.00
|
||||
Delay = 0.03
|
||||
|
||||
------- input_net_transition = 0.01
|
||||
| total_output_net_capacitance = 2.06
|
||||
| 1.89 3.79
|
||||
v --------------------
|
||||
0.00 | 0.01 0.01
|
||||
0.02 | 0.01 0.01
|
||||
Table value = 0.01
|
||||
PVT scale factor = 1.00
|
||||
Slew = 0.01
|
||||
Driver waveform slew = 0.01
|
||||
|
||||
.............................................
|
||||
|
||||
A2 v -> ZN v
|
||||
P = 1.00 V = 1.10 T = 25.00
|
||||
------- input_net_transition = 0.01
|
||||
| total_output_net_capacitance = 1.94
|
||||
| 1.89 3.79
|
||||
v --------------------
|
||||
0.00 | 0.03 0.03
|
||||
0.02 | 0.04 0.04
|
||||
Table value = 0.03
|
||||
PVT scale factor = 1.00
|
||||
Delay = 0.03
|
||||
|
||||
------- input_net_transition = 0.01
|
||||
| total_output_net_capacitance = 1.94
|
||||
| 1.89 3.79
|
||||
v --------------------
|
||||
0.00 | 0.01 0.01
|
||||
0.02 | 0.01 0.01
|
||||
Table value = 0.01
|
||||
PVT scale factor = 1.00
|
||||
Slew = 0.01
|
||||
Driver waveform slew = 0.01
|
||||
|
||||
.............................................
|
||||
|
||||
dcalc and1 A2: done
|
||||
Library: NangateOpenCellLibrary
|
||||
Cell: OR2_X1
|
||||
Arc sense: positive_unate
|
||||
Arc type: combinational
|
||||
A1 ^ -> ZN ^
|
||||
P = 1.00 V = 1.10 T = 25.00
|
||||
------- input_net_transition = 0.01
|
||||
| total_output_net_capacitance = 2.11
|
||||
| 1.89 3.79
|
||||
v --------------------
|
||||
0.00 | 0.02 0.03
|
||||
0.02 | 0.03 0.03
|
||||
Table value = 0.02
|
||||
PVT scale factor = 1.00
|
||||
Delay = 0.02
|
||||
|
||||
------- input_net_transition = 0.01
|
||||
| total_output_net_capacitance = 2.11
|
||||
| 1.89 3.79
|
||||
v --------------------
|
||||
0.00 | 0.01 0.01
|
||||
0.02 | 0.01 0.01
|
||||
Table value = 0.01
|
||||
PVT scale factor = 1.00
|
||||
Slew = 0.01
|
||||
Driver waveform slew = 0.01
|
||||
|
||||
.............................................
|
||||
|
||||
A1 v -> ZN v
|
||||
P = 1.00 V = 1.10 T = 25.00
|
||||
------- input_net_transition = 0.01
|
||||
| total_output_net_capacitance = 1.96
|
||||
| 1.89 3.79
|
||||
v --------------------
|
||||
0.00 | 0.04 0.05
|
||||
0.02 | 0.05 0.05
|
||||
Table value = 0.05
|
||||
PVT scale factor = 1.00
|
||||
Delay = 0.05
|
||||
|
||||
------- input_net_transition = 0.01
|
||||
| total_output_net_capacitance = 1.96
|
||||
| 1.89 3.79
|
||||
v --------------------
|
||||
0.00 | 0.01 0.01
|
||||
0.02 | 0.01 0.01
|
||||
Table value = 0.01
|
||||
PVT scale factor = 1.00
|
||||
Slew = 0.01
|
||||
Driver waveform slew = 0.01
|
||||
|
||||
.............................................
|
||||
|
||||
dcalc or1 A1: done
|
||||
Library: NangateOpenCellLibrary
|
||||
Cell: NAND2_X1
|
||||
Arc sense: negative_unate
|
||||
Arc type: combinational
|
||||
A1 ^ -> ZN v
|
||||
P = 1.00 V = 1.10 T = 25.00
|
||||
------- input_net_transition = 0.01
|
||||
| total_output_net_capacitance = 0.79
|
||||
| 0.37 1.85
|
||||
v --------------------
|
||||
0.00 | 0.01 0.01
|
||||
0.02 | 0.01 0.02
|
||||
Table value = 0.01
|
||||
PVT scale factor = 1.00
|
||||
Delay = 0.01
|
||||
|
||||
------- input_net_transition = 0.01
|
||||
| total_output_net_capacitance = 0.79
|
||||
| 0.37 1.85
|
||||
v --------------------
|
||||
0.00 | 0.00 0.01
|
||||
0.02 | 0.01 0.01
|
||||
Table value = 0.01
|
||||
PVT scale factor = 1.00
|
||||
Slew = 0.01
|
||||
Driver waveform slew = 0.01
|
||||
|
||||
.............................................
|
||||
|
||||
A1 v -> ZN ^
|
||||
P = 1.00 V = 1.10 T = 25.00
|
||||
------- input_net_transition = 0.01
|
||||
| total_output_net_capacitance = 0.95
|
||||
| 0.37 1.85
|
||||
v --------------------
|
||||
0.00 | 0.01 0.01
|
||||
0.02 | 0.01 0.02
|
||||
Table value = 0.01
|
||||
PVT scale factor = 1.00
|
||||
Delay = 0.01
|
||||
|
||||
------- input_net_transition = 0.01
|
||||
| total_output_net_capacitance = 0.95
|
||||
| 0.37 1.85
|
||||
v --------------------
|
||||
0.00 | 0.00 0.01
|
||||
0.02 | 0.01 0.01
|
||||
Table value = 0.01
|
||||
PVT scale factor = 1.00
|
||||
Slew = 0.01
|
||||
Driver waveform slew = 0.01
|
||||
|
||||
.............................................
|
||||
|
||||
dcalc nand1: done
|
||||
Library: NangateOpenCellLibrary
|
||||
Cell: NOR2_X1
|
||||
Arc sense: negative_unate
|
||||
Arc type: combinational
|
||||
A1 ^ -> ZN v
|
||||
P = 1.00 V = 1.10 T = 25.00
|
||||
------- input_net_transition = 0.02
|
||||
| total_output_net_capacitance = 0.90
|
||||
| 0.83 1.67
|
||||
v --------------------
|
||||
0.02 | 0.01 0.01
|
||||
0.04 | 0.01 0.01
|
||||
Table value = 0.01
|
||||
PVT scale factor = 1.00
|
||||
Delay = 0.01
|
||||
|
||||
------- input_net_transition = 0.02
|
||||
| total_output_net_capacitance = 0.90
|
||||
| 0.83 1.67
|
||||
v --------------------
|
||||
0.02 | 0.01 0.01
|
||||
0.04 | 0.01 0.01
|
||||
Table value = 0.01
|
||||
PVT scale factor = 1.00
|
||||
Slew = 0.01
|
||||
Driver waveform slew = 0.01
|
||||
|
||||
.............................................
|
||||
|
||||
A1 v -> ZN ^
|
||||
P = 1.00 V = 1.10 T = 25.00
|
||||
------- input_net_transition = 0.02
|
||||
| total_output_net_capacitance = 0.94
|
||||
| 0.83 1.67
|
||||
v --------------------
|
||||
0.02 | 0.02 0.03
|
||||
0.04 | 0.03 0.04
|
||||
Table value = 0.02
|
||||
PVT scale factor = 1.00
|
||||
Delay = 0.02
|
||||
|
||||
------- input_net_transition = 0.02
|
||||
| total_output_net_capacitance = 0.94
|
||||
| 0.83 1.67
|
||||
v --------------------
|
||||
0.02 | 0.01 0.02
|
||||
0.04 | 0.02 0.02
|
||||
Table value = 0.01
|
||||
PVT scale factor = 1.00
|
||||
Slew = 0.01
|
||||
Driver waveform slew = 0.01
|
||||
|
||||
.............................................
|
||||
|
||||
dcalc nor1: done
|
||||
Library: NangateOpenCellLibrary
|
||||
Cell: DFF_X1
|
||||
Arc sense: non_unate
|
||||
Arc type: Reg Clk to Q
|
||||
CK ^ -> Q ^
|
||||
P = 1.00 V = 1.10 T = 25.00
|
||||
------- input_net_transition = 0.00
|
||||
| total_output_net_capacitance = 0.00
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.00 | 0.08 0.09
|
||||
0.00 | 0.08 0.09
|
||||
Table value = 0.08
|
||||
PVT scale factor = 1.00
|
||||
Delay = 0.08
|
||||
|
||||
------- input_net_transition = 0.00
|
||||
| total_output_net_capacitance = 0.00
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.00 | 0.01 0.01
|
||||
0.00 | 0.01 0.01
|
||||
Table value = 0.01
|
||||
PVT scale factor = 1.00
|
||||
Slew = 0.01
|
||||
Driver waveform slew = 0.01
|
||||
|
||||
.............................................
|
||||
|
||||
CK ^ -> Q v
|
||||
P = 1.00 V = 1.10 T = 25.00
|
||||
------- input_net_transition = 0.00
|
||||
| total_output_net_capacitance = 0.00
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.00 | 0.08 0.08
|
||||
0.00 | 0.08 0.08
|
||||
Table value = 0.08
|
||||
PVT scale factor = 1.00
|
||||
Delay = 0.08
|
||||
|
||||
------- input_net_transition = 0.00
|
||||
| total_output_net_capacitance = 0.00
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.00 | 0.01 0.01
|
||||
0.00 | 0.01 0.01
|
||||
Table value = 0.00
|
||||
PVT scale factor = 1.00
|
||||
Slew = 0.00
|
||||
Driver waveform slew = 0.00
|
||||
|
||||
.............................................
|
||||
|
||||
dcalc reg1: done
|
||||
--- Test 6: network queries ---
|
||||
total pins: 50
|
||||
total nets: 19
|
||||
Net n1
|
||||
Pin capacitance: 1.67-1.86
|
||||
Wire capacitance: 0.00
|
||||
Total capacitance: 1.67-1.86
|
||||
Number of drivers: 1
|
||||
Number of loads: 2
|
||||
Number of pins: 3
|
||||
|
||||
Driver pins
|
||||
buf1/Z output (BUF_X1)
|
||||
|
||||
Load pins
|
||||
and1/A1 input (AND2_X1) 0.87-0.92
|
||||
or1/A1 input (OR2_X1) 0.79-0.95
|
||||
|
||||
Net n2
|
||||
Pin capacitance: 2.42-2.57
|
||||
Wire capacitance: 0.00
|
||||
Total capacitance: 2.42-2.57
|
||||
Number of drivers: 1
|
||||
Number of loads: 2
|
||||
Number of pins: 3
|
||||
|
||||
Driver pins
|
||||
buf2/Z output (BUF_X1)
|
||||
|
||||
Load pins
|
||||
and1/A2 input (AND2_X1) 0.89-0.97
|
||||
nand1/A1 input (NAND2_X1) 1.53-1.60
|
||||
|
||||
Net n3
|
||||
Pin capacitance: 2.31-2.66
|
||||
Wire capacitance: 0.00
|
||||
Total capacitance: 2.31-2.66
|
||||
Number of drivers: 1
|
||||
Number of loads: 2
|
||||
Number of pins: 3
|
||||
|
||||
Driver pins
|
||||
inv1/ZN output (INV_X1)
|
||||
|
||||
Load pins
|
||||
nor1/A1 input (NOR2_X1) 1.41-1.71
|
||||
or1/A2 input (OR2_X1) 0.90-0.94
|
||||
|
||||
Net n4
|
||||
Pin capacitance: 3.07-3.32
|
||||
Wire capacitance: 0.00
|
||||
Total capacitance: 3.07-3.32
|
||||
Number of drivers: 1
|
||||
Number of loads: 2
|
||||
Number of pins: 3
|
||||
|
||||
Driver pins
|
||||
inv2/ZN output (INV_X1)
|
||||
|
||||
Load pins
|
||||
nand1/A2 input (NAND2_X1) 1.50-1.66
|
||||
nor1/A2 input (NOR2_X1) 1.56-1.65
|
||||
|
||||
Net n5
|
||||
Pin capacitance: 1.94-2.06
|
||||
Wire capacitance: 0.00
|
||||
Total capacitance: 1.94-2.06
|
||||
Number of drivers: 1
|
||||
Number of loads: 2
|
||||
Number of pins: 3
|
||||
|
||||
Driver pins
|
||||
and1/ZN output (AND2_X1)
|
||||
|
||||
Load pins
|
||||
and2/A1 input (AND2_X1) 0.87-0.92
|
||||
reg1/D input (DFF_X1) 1.06-1.14
|
||||
|
||||
Net n6
|
||||
Pin capacitance: 1.96-2.11
|
||||
Wire capacitance: 0.00
|
||||
Total capacitance: 1.96-2.11
|
||||
Number of drivers: 1
|
||||
Number of loads: 2
|
||||
Number of pins: 3
|
||||
|
||||
Driver pins
|
||||
or1/ZN output (OR2_X1)
|
||||
|
||||
Load pins
|
||||
and2/A2 input (AND2_X1) 0.89-0.97
|
||||
reg4/D input (DFF_X1) 1.06-1.14
|
||||
|
||||
Net n7
|
||||
Pin capacitance: 0.79-0.95
|
||||
Wire capacitance: 0.00
|
||||
Total capacitance: 0.79-0.95
|
||||
Number of drivers: 1
|
||||
Number of loads: 1
|
||||
Number of pins: 2
|
||||
|
||||
Driver pins
|
||||
nand1/ZN output (NAND2_X1)
|
||||
|
||||
Load pins
|
||||
or2/A1 input (OR2_X1) 0.79-0.95
|
||||
|
||||
Net n8
|
||||
Pin capacitance: 0.90-0.94
|
||||
Wire capacitance: 0.00
|
||||
Total capacitance: 0.90-0.94
|
||||
Number of drivers: 1
|
||||
Number of loads: 1
|
||||
Number of pins: 2
|
||||
|
||||
Driver pins
|
||||
nor1/ZN output (NOR2_X1)
|
||||
|
||||
Load pins
|
||||
or2/A2 input (OR2_X1) 0.90-0.94
|
||||
|
||||
Net n9
|
||||
Pin capacitance: 1.06-1.14
|
||||
Wire capacitance: 0.00
|
||||
Total capacitance: 1.06-1.14
|
||||
Number of drivers: 1
|
||||
Number of loads: 1
|
||||
Number of pins: 2
|
||||
|
||||
Driver pins
|
||||
and2/ZN output (AND2_X1)
|
||||
|
||||
Load pins
|
||||
reg2/D input (DFF_X1) 1.06-1.14
|
||||
|
||||
Net n10
|
||||
Pin capacitance: 1.06-1.14
|
||||
Wire capacitance: 0.00
|
||||
Total capacitance: 1.06-1.14
|
||||
Number of drivers: 1
|
||||
Number of loads: 1
|
||||
Number of pins: 2
|
||||
|
||||
Driver pins
|
||||
or2/ZN output (OR2_X1)
|
||||
|
||||
Load pins
|
||||
reg3/D input (DFF_X1) 1.06-1.14
|
||||
|
||||
Instance buf1
|
||||
Cell: BUF_X1
|
||||
Library: NangateOpenCellLibrary
|
||||
Path cells: BUF_X1
|
||||
Input pins:
|
||||
A input d1
|
||||
Output pins:
|
||||
Z output n1
|
||||
Other pins:
|
||||
VDD power (unconnected)
|
||||
VSS ground (unconnected)
|
||||
Instance buf2
|
||||
Cell: BUF_X1
|
||||
Library: NangateOpenCellLibrary
|
||||
Path cells: BUF_X1
|
||||
Input pins:
|
||||
A input d2
|
||||
Output pins:
|
||||
Z output n2
|
||||
Other pins:
|
||||
VDD power (unconnected)
|
||||
VSS ground (unconnected)
|
||||
Instance inv1
|
||||
Cell: INV_X1
|
||||
Library: NangateOpenCellLibrary
|
||||
Path cells: INV_X1
|
||||
Input pins:
|
||||
A input d3
|
||||
Output pins:
|
||||
ZN output n3
|
||||
Other pins:
|
||||
VDD power (unconnected)
|
||||
VSS ground (unconnected)
|
||||
Instance inv2
|
||||
Cell: INV_X1
|
||||
Library: NangateOpenCellLibrary
|
||||
Path cells: INV_X1
|
||||
Input pins:
|
||||
A input d4
|
||||
Output pins:
|
||||
ZN output n4
|
||||
Other pins:
|
||||
VDD power (unconnected)
|
||||
VSS ground (unconnected)
|
||||
Instance and1
|
||||
Cell: AND2_X1
|
||||
Library: NangateOpenCellLibrary
|
||||
Path cells: AND2_X1
|
||||
Input pins:
|
||||
A1 input n1
|
||||
A2 input n2
|
||||
Output pins:
|
||||
ZN output n5
|
||||
Other pins:
|
||||
VDD power (unconnected)
|
||||
VSS ground (unconnected)
|
||||
Instance or1
|
||||
Cell: OR2_X1
|
||||
Library: NangateOpenCellLibrary
|
||||
Path cells: OR2_X1
|
||||
Input pins:
|
||||
A1 input n1
|
||||
A2 input n3
|
||||
Output pins:
|
||||
ZN output n6
|
||||
Other pins:
|
||||
VDD power (unconnected)
|
||||
VSS ground (unconnected)
|
||||
Instance nand1
|
||||
Cell: NAND2_X1
|
||||
Library: NangateOpenCellLibrary
|
||||
Path cells: NAND2_X1
|
||||
Input pins:
|
||||
A1 input n2
|
||||
A2 input n4
|
||||
Output pins:
|
||||
ZN output n7
|
||||
Other pins:
|
||||
VDD power (unconnected)
|
||||
VSS ground (unconnected)
|
||||
Instance nor1
|
||||
Cell: NOR2_X1
|
||||
Library: NangateOpenCellLibrary
|
||||
Path cells: NOR2_X1
|
||||
Input pins:
|
||||
A1 input n3
|
||||
A2 input n4
|
||||
Output pins:
|
||||
ZN output n8
|
||||
Other pins:
|
||||
VDD power (unconnected)
|
||||
VSS ground (unconnected)
|
||||
Instance and2
|
||||
Cell: AND2_X1
|
||||
Library: NangateOpenCellLibrary
|
||||
Path cells: AND2_X1
|
||||
Input pins:
|
||||
A1 input n5
|
||||
A2 input n6
|
||||
Output pins:
|
||||
ZN output n9
|
||||
Other pins:
|
||||
VDD power (unconnected)
|
||||
VSS ground (unconnected)
|
||||
Instance or2
|
||||
Cell: OR2_X1
|
||||
Library: NangateOpenCellLibrary
|
||||
Path cells: OR2_X1
|
||||
Input pins:
|
||||
A1 input n7
|
||||
A2 input n8
|
||||
Output pins:
|
||||
ZN output n10
|
||||
Other pins:
|
||||
VDD power (unconnected)
|
||||
VSS ground (unconnected)
|
||||
Instance reg1
|
||||
Cell: DFF_X1
|
||||
Library: NangateOpenCellLibrary
|
||||
Path cells: DFF_X1
|
||||
Input pins:
|
||||
D input n5
|
||||
CK input clk
|
||||
Output pins:
|
||||
Q output q1
|
||||
QN output (unconnected)
|
||||
Other pins:
|
||||
VDD power (unconnected)
|
||||
VSS ground (unconnected)
|
||||
IQ internal (unconnected)
|
||||
IQN internal (unconnected)
|
||||
Instance reg2
|
||||
Cell: DFF_X1
|
||||
Library: NangateOpenCellLibrary
|
||||
Path cells: DFF_X1
|
||||
Input pins:
|
||||
D input n9
|
||||
CK input clk
|
||||
Output pins:
|
||||
Q output q2
|
||||
QN output (unconnected)
|
||||
Other pins:
|
||||
VDD power (unconnected)
|
||||
VSS ground (unconnected)
|
||||
IQ internal (unconnected)
|
||||
IQN internal (unconnected)
|
||||
Instance reg3
|
||||
Cell: DFF_X1
|
||||
Library: NangateOpenCellLibrary
|
||||
Path cells: DFF_X1
|
||||
Input pins:
|
||||
D input n10
|
||||
CK input clk
|
||||
Output pins:
|
||||
Q output q3
|
||||
QN output (unconnected)
|
||||
Other pins:
|
||||
VDD power (unconnected)
|
||||
VSS ground (unconnected)
|
||||
IQ internal (unconnected)
|
||||
IQN internal (unconnected)
|
||||
Instance reg4
|
||||
Cell: DFF_X1
|
||||
Library: NangateOpenCellLibrary
|
||||
Path cells: DFF_X1
|
||||
Input pins:
|
||||
D input n6
|
||||
CK input clk
|
||||
Output pins:
|
||||
Q output q4
|
||||
QN output (unconnected)
|
||||
Other pins:
|
||||
VDD power (unconnected)
|
||||
VSS ground (unconnected)
|
||||
IQ internal (unconnected)
|
||||
IQN internal (unconnected)
|
||||
--- Test 7: modify graph ---
|
||||
Startpoint: d1 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 v input external delay
|
||||
0.00 0.00 v d1 (in)
|
||||
0.06 0.06 v buf1/Z (BUF_X1)
|
||||
0.05 0.10 v or1/ZN (OR2_X1)
|
||||
0.03 0.13 v and2/ZN (AND2_X1)
|
||||
0.00 0.13 v reg2/D (DFF_X1)
|
||||
0.13 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.04 9.96 library setup time
|
||||
9.96 data required time
|
||||
---------------------------------------------------------
|
||||
9.96 data required time
|
||||
-0.13 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.83 slack (MET)
|
||||
|
||||
|
||||
Startpoint: d1 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 v input external delay
|
||||
0.00 0.00 v d1 (in)
|
||||
0.06 0.06 v buf1/Z (BUF_X1)
|
||||
0.05 0.10 v or1/ZN (OR2_X1)
|
||||
0.03 0.13 v and2/ZN (AND2_X1)
|
||||
0.00 0.13 v reg2/D (DFF_X1)
|
||||
0.13 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.04 9.96 library setup time
|
||||
9.96 data required time
|
||||
---------------------------------------------------------
|
||||
9.96 data required time
|
||||
-0.13 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.83 slack (MET)
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,129 @@
|
|||
# Test graph construction with bidirectional pins, reconvergent paths,
|
||||
# and various edge/vertex operations.
|
||||
source ../../test/helpers.tcl
|
||||
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
read_verilog graph_bidirect.v
|
||||
link_design graph_bidirect
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 1: Graph construction and basic timing
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Test 1: graph with reconvergent paths ---"
|
||||
create_clock -name clk -period 10 [get_ports clk]
|
||||
set_input_delay -clock clk 0 [get_ports {d1 d2 d3 d4}]
|
||||
set_output_delay -clock clk 0 [get_ports {q1 q2 q3 q4}]
|
||||
set_input_transition 0.1 [get_ports {d1 d2 d3 d4 clk}]
|
||||
|
||||
report_checks
|
||||
|
||||
report_checks -path_delay min
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 2: Multiple path queries (exercises graph traversal)
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Test 2: path queries ---"
|
||||
report_checks -from [get_ports d1] -to [get_ports q1]
|
||||
|
||||
report_checks -from [get_ports d1] -to [get_ports q2]
|
||||
|
||||
report_checks -from [get_ports d2] -to [get_ports q1]
|
||||
|
||||
report_checks -from [get_ports d3] -to [get_ports q3]
|
||||
|
||||
report_checks -from [get_ports d4] -to [get_ports q3]
|
||||
|
||||
report_checks -from [get_ports d1] -to [get_ports q4]
|
||||
|
||||
report_checks -from [get_ports d3] -to [get_ports q4]
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 3: Fields that exercise graph delay/slew queries
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Test 3: report with fields ---"
|
||||
report_checks -fields {slew cap input_pins nets fanout}
|
||||
|
||||
report_checks -format full_clock
|
||||
|
||||
report_checks -path_delay min -fields {slew cap}
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 4: Fanin/fanout queries through reconvergent paths
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Test 4: fanin/fanout ---"
|
||||
set fi [get_fanin -to [get_ports q2] -flat]
|
||||
puts "fanin to q2: [llength $fi]"
|
||||
|
||||
set fo [get_fanout -from [get_ports d1] -flat]
|
||||
puts "fanout from d1: [llength $fo]"
|
||||
|
||||
set fi_cells [get_fanin -to [get_ports q2] -only_cells]
|
||||
puts "fanin cells to q2: [llength $fi_cells]"
|
||||
|
||||
set fo_cells [get_fanout -from [get_ports d1] -only_cells]
|
||||
puts "fanout cells from d1: [llength $fo_cells]"
|
||||
|
||||
set fi_q3 [get_fanin -to [get_ports q3] -flat]
|
||||
puts "fanin to q3: [llength $fi_q3]"
|
||||
|
||||
set fo_d3 [get_fanout -from [get_ports d3] -flat]
|
||||
puts "fanout from d3: [llength $fo_d3]"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 5: report_dcalc exercises graph edge arc queries
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Test 5: report_dcalc ---"
|
||||
report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -max
|
||||
puts "dcalc buf1: done"
|
||||
|
||||
report_dcalc -from [get_pins and1/A1] -to [get_pins and1/ZN] -max
|
||||
puts "dcalc and1 A1: done"
|
||||
|
||||
report_dcalc -from [get_pins and1/A2] -to [get_pins and1/ZN] -max
|
||||
puts "dcalc and1 A2: done"
|
||||
|
||||
report_dcalc -from [get_pins or1/A1] -to [get_pins or1/ZN] -max
|
||||
puts "dcalc or1 A1: done"
|
||||
|
||||
report_dcalc -from [get_pins nand1/A1] -to [get_pins nand1/ZN] -max
|
||||
puts "dcalc nand1: done"
|
||||
|
||||
report_dcalc -from [get_pins nor1/A1] -to [get_pins nor1/ZN] -max
|
||||
puts "dcalc nor1: done"
|
||||
|
||||
report_dcalc -from [get_pins reg1/CK] -to [get_pins reg1/Q] -max
|
||||
puts "dcalc reg1: done"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 6: Graph vertex/edge counts
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Test 6: network queries ---"
|
||||
set all_pins [get_pins */*]
|
||||
puts "total pins: [llength $all_pins]"
|
||||
|
||||
set all_nets [get_nets *]
|
||||
puts "total nets: [llength $all_nets]"
|
||||
|
||||
foreach net_name {n1 n2 n3 n4 n5 n6 n7 n8 n9 n10} {
|
||||
report_net $net_name
|
||||
}
|
||||
|
||||
foreach inst_name {buf1 buf2 inv1 inv2 and1 or1 nand1 nor1 and2 or2 reg1 reg2 reg3 reg4} {
|
||||
report_instance $inst_name
|
||||
}
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 7: Add and remove instances (exercises deleteVertex, graph modify)
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Test 7: modify graph ---"
|
||||
set new_net [make_net test_net]
|
||||
set new_inst [make_instance test_buf BUF_X1]
|
||||
connect_pin test_net test_buf/A
|
||||
|
||||
report_checks
|
||||
|
||||
disconnect_pin test_net test_buf/A
|
||||
delete_instance test_buf
|
||||
delete_net test_net
|
||||
|
||||
report_checks
|
||||
|
|
@ -0,0 +1,29 @@
|
|||
// Design with bidirectional ports and reconvergent paths
|
||||
// for testing graph bidirect vertex/edge handling
|
||||
module graph_bidirect (clk, d1, d2, d3, d4, q1, q2, q3, q4);
|
||||
input clk, d1, d2, d3, d4;
|
||||
output q1, q2, q3, q4;
|
||||
wire n1, n2, n3, n4, n5, n6, n7, n8, n9, n10;
|
||||
|
||||
// Fan-out from d1 and d2
|
||||
BUF_X1 buf1 (.A(d1), .Z(n1));
|
||||
BUF_X1 buf2 (.A(d2), .Z(n2));
|
||||
INV_X1 inv1 (.A(d3), .ZN(n3));
|
||||
INV_X1 inv2 (.A(d4), .ZN(n4));
|
||||
|
||||
// Reconvergent logic
|
||||
AND2_X1 and1 (.A1(n1), .A2(n2), .ZN(n5));
|
||||
OR2_X1 or1 (.A1(n1), .A2(n3), .ZN(n6));
|
||||
NAND2_X1 nand1 (.A1(n2), .A2(n4), .ZN(n7));
|
||||
NOR2_X1 nor1 (.A1(n3), .A2(n4), .ZN(n8));
|
||||
|
||||
// Second level reconvergence
|
||||
AND2_X1 and2 (.A1(n5), .A2(n6), .ZN(n9));
|
||||
OR2_X1 or2 (.A1(n7), .A2(n8), .ZN(n10));
|
||||
|
||||
// Registers
|
||||
DFF_X1 reg1 (.D(n5), .CK(clk), .Q(q1));
|
||||
DFF_X1 reg2 (.D(n9), .CK(clk), .Q(q2));
|
||||
DFF_X1 reg3 (.D(n10), .CK(clk), .Q(q3));
|
||||
DFF_X1 reg4 (.D(n6), .CK(clk), .Q(q4));
|
||||
endmodule
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,159 @@
|
|||
# Test graph delay value comparison and multi-corner graph operations.
|
||||
# Targets: DelayFloat.cc/Graph.cc/GraphCmp.cc multi-corner delay paths.
|
||||
|
||||
source ../../test/helpers.tcl
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Multi-corner setup for graph coverage
|
||||
#---------------------------------------------------------------
|
||||
define_corners fast slow
|
||||
|
||||
read_liberty -corner fast ../../test/nangate45/Nangate45_fast.lib
|
||||
read_liberty -corner slow ../../test/nangate45/Nangate45_slow.lib
|
||||
|
||||
read_verilog graph_test2.v
|
||||
link_design graph_test2
|
||||
|
||||
create_clock -name clk -period 10 [get_ports clk]
|
||||
set_input_delay -clock clk 1.0 [get_ports {d1 d2 en}]
|
||||
set_output_delay -clock clk 1.0 [get_ports {q1 q2}]
|
||||
set_input_transition 0.1 [get_ports {d1 d2 en}]
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Multi-corner timing reports (exercises delay value comparison
|
||||
# across min/max analysis points in Graph)
|
||||
#---------------------------------------------------------------
|
||||
puts "--- fast corner ---"
|
||||
report_checks -corner fast
|
||||
|
||||
report_checks -corner fast -path_delay min
|
||||
|
||||
report_checks -corner fast -path_delay max
|
||||
|
||||
puts "--- slow corner ---"
|
||||
report_checks -corner slow
|
||||
|
||||
report_checks -corner slow -path_delay min
|
||||
|
||||
report_checks -corner slow -path_delay max
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Multi-corner report_dcalc (exercises delay subtraction/comparison)
|
||||
#---------------------------------------------------------------
|
||||
puts "--- report_dcalc per corner ---"
|
||||
report_dcalc -corner fast -from [get_pins buf1/A] -to [get_pins buf1/Z]
|
||||
puts "fast buf1 dcalc: done"
|
||||
|
||||
report_dcalc -corner slow -from [get_pins buf1/A] -to [get_pins buf1/Z]
|
||||
puts "slow buf1 dcalc: done"
|
||||
|
||||
report_dcalc -corner fast -from [get_pins inv1/A] -to [get_pins inv1/ZN]
|
||||
puts "fast inv1 dcalc: done"
|
||||
|
||||
report_dcalc -corner slow -from [get_pins inv1/A] -to [get_pins inv1/ZN]
|
||||
puts "slow inv1 dcalc: done"
|
||||
|
||||
report_dcalc -corner fast -from [get_pins and1/A1] -to [get_pins and1/ZN]
|
||||
puts "fast and1 A1 dcalc: done"
|
||||
|
||||
report_dcalc -corner slow -from [get_pins and1/A1] -to [get_pins and1/ZN]
|
||||
puts "slow and1 A1 dcalc: done"
|
||||
|
||||
report_dcalc -corner fast -from [get_pins or1/A1] -to [get_pins or1/ZN]
|
||||
puts "fast or1 A1 dcalc: done"
|
||||
|
||||
report_dcalc -corner slow -from [get_pins or1/A1] -to [get_pins or1/ZN]
|
||||
puts "slow or1 A1 dcalc: done"
|
||||
|
||||
# DFF arcs
|
||||
report_dcalc -corner fast -from [get_pins reg1/CK] -to [get_pins reg1/Q] -max
|
||||
puts "fast reg1 CK->Q: done"
|
||||
|
||||
report_dcalc -corner slow -from [get_pins reg1/CK] -to [get_pins reg1/Q] -max
|
||||
puts "slow reg1 CK->Q: done"
|
||||
|
||||
report_dcalc -corner fast -from [get_pins reg1/CK] -to [get_pins reg1/D] -max
|
||||
puts "fast reg1 setup: done"
|
||||
|
||||
report_dcalc -corner slow -from [get_pins reg1/CK] -to [get_pins reg1/D] -min
|
||||
puts "slow reg1 hold: done"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# report_checks with fields across corners (exercises graph slew access)
|
||||
#---------------------------------------------------------------
|
||||
puts "--- report_checks with fields ---"
|
||||
report_checks -corner fast -fields {slew cap input_pins}
|
||||
|
||||
report_checks -corner slow -fields {slew cap input_pins}
|
||||
|
||||
report_checks -corner fast -format full_clock
|
||||
|
||||
report_checks -corner slow -format full_clock
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Multi-corner paths (different paths in fast vs slow)
|
||||
#---------------------------------------------------------------
|
||||
puts "--- multi-corner paths ---"
|
||||
report_checks -corner fast -from [get_ports d1] -to [get_ports q1]
|
||||
|
||||
report_checks -corner slow -from [get_ports d1] -to [get_ports q1]
|
||||
|
||||
report_checks -corner fast -from [get_ports d2] -to [get_ports q2]
|
||||
|
||||
report_checks -corner slow -from [get_ports d2] -to [get_ports q2]
|
||||
|
||||
report_checks -corner fast -from [get_ports en] -to [get_ports q1]
|
||||
|
||||
report_checks -corner slow -from [get_ports en] -to [get_ports q1]
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Edge queries with multi-corner
|
||||
#---------------------------------------------------------------
|
||||
puts "--- timing edges multi-corner ---"
|
||||
set e1 [get_timing_edges -of_objects [get_cells and1]]
|
||||
puts "and1 edges: [llength $e1]"
|
||||
|
||||
set e2 [get_timing_edges -of_objects [get_cells or1]]
|
||||
puts "or1 edges: [llength $e2]"
|
||||
|
||||
set e3 [get_timing_edges -of_objects [get_cells reg1]]
|
||||
puts "reg1 edges: [llength $e3]"
|
||||
|
||||
report_edges -from [get_pins and1/A1] -to [get_pins and1/ZN]
|
||||
report_edges -from [get_pins and1/A2] -to [get_pins and1/ZN]
|
||||
report_edges -from [get_pins or1/A1] -to [get_pins or1/ZN]
|
||||
report_edges -from [get_pins or1/A2] -to [get_pins or1/ZN]
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Load changes with multi-corner (exercises delay recomputation)
|
||||
#---------------------------------------------------------------
|
||||
puts "--- load changes multi-corner ---"
|
||||
set_load 0.01 [get_ports q1]
|
||||
set_load 0.05 [get_ports q2]
|
||||
|
||||
report_checks -corner fast
|
||||
|
||||
report_checks -corner slow
|
||||
|
||||
set_load 0 [get_ports q1]
|
||||
set_load 0 [get_ports q2]
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# report_checks -unconstrained multi-corner
|
||||
#---------------------------------------------------------------
|
||||
puts "--- unconstrained multi-corner ---"
|
||||
report_checks -corner fast -unconstrained
|
||||
|
||||
report_checks -corner slow -unconstrained
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Disable/enable with multi-corner
|
||||
#---------------------------------------------------------------
|
||||
puts "--- disable with multi-corner ---"
|
||||
set_disable_timing [get_cells buf1]
|
||||
report_checks -corner fast
|
||||
report_checks -corner slow
|
||||
|
||||
unset_disable_timing [get_cells buf1]
|
||||
report_checks -corner fast
|
||||
report_checks -corner slow
|
||||
|
|
@ -0,0 +1,726 @@
|
|||
--- Test 1: baseline ---
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
Startpoint: d3 (input port clocked by clk)
|
||||
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: min
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 ^ input external delay
|
||||
0.00 1.00 ^ d3 (in)
|
||||
0.01 1.01 v inv1/ZN (INV_X1)
|
||||
0.03 1.04 ^ nor1/ZN (NOR2_X1)
|
||||
0.00 1.04 ^ reg3/D (DFF_X1)
|
||||
1.04 data arrival time
|
||||
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 clock reconvergence pessimism
|
||||
0.00 ^ reg3/CK (DFF_X1)
|
||||
0.01 0.01 library hold time
|
||||
0.01 data required time
|
||||
---------------------------------------------------------
|
||||
0.01 data required time
|
||||
-1.04 data arrival time
|
||||
---------------------------------------------------------
|
||||
1.03 slack (MET)
|
||||
|
||||
|
||||
Warning 168: graph_delete_modify.tcl line 1, unknown field nets.
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Fanout Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------------
|
||||
0.00 0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
1 0.88 0.10 0.00 1.00 v d2 (in)
|
||||
0.10 0.00 1.00 v buf2/A (BUF_X1)
|
||||
2 1.69 0.01 0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.01 0.00 1.06 v or1/A1 (OR2_X1)
|
||||
2 2.56 0.01 0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.01 0.00 1.11 v nand1/A2 (NAND2_X1)
|
||||
1 1.14 0.01 0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.01 0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
0.00 10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
-----------------------------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
-----------------------------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
--- Test 2: add/delete multiple instances ---
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
--- Test 3: replace_cell ---
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
A -> Z combinational
|
||||
^ -> ^ 0.03:0.03
|
||||
v -> v 0.05:0.05
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
--- Test 4: add/delete register ---
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
--- Test 5: rapid connect/disconnect ---
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
cycle 1 done
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
cycle 2 done
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
cycle 3 done
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
--- Test 6: edge queries ---
|
||||
buf1 edges: 1
|
||||
buf2 edges: 1
|
||||
inv1 edges: 1
|
||||
and1 edges: 1
|
||||
or1 edges: 1
|
||||
nand1 edges: 1
|
||||
nor1 edges: 1
|
||||
reg1 edges: 1
|
||||
reg2 edges: 1
|
||||
reg3 edges: 1
|
||||
reg4 edges: 1
|
||||
d1 ^ 0.10:0.10 v 0.10:0.10
|
||||
d2 ^ 0.10:0.10 v 0.10:0.10
|
||||
d3 ^ 0.10:0.10 v 0.10:0.10
|
||||
buf1/Z ^ 0.01:0.01 v 0.01:0.01
|
||||
and1/ZN ^ 0.01:0.01 v 0.01:0.01
|
||||
reg1/Q ^ 0.01:0.01 v 0.00:0.00
|
||||
--- Test 7: through pins ---
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
through nand1: done
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.04 1.09 v and1/ZN (AND2_X1)
|
||||
0.02 1.11 ^ nor1/ZN (NOR2_X1)
|
||||
0.00 1.11 ^ reg3/D (DFF_X1)
|
||||
1.11 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg3/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.11 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
through nor1: done
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.04 1.09 v and1/ZN (AND2_X1)
|
||||
0.02 1.11 ^ nor1/ZN (NOR2_X1)
|
||||
0.00 1.11 ^ reg3/D (DFF_X1)
|
||||
1.11 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg3/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.11 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
through and1: done
|
||||
|
|
@ -0,0 +1,191 @@
|
|||
# Test graph modification: add/delete vertices via connect_pin/disconnect_pin,
|
||||
# delete_instance, replace_cell, and repeated graph rebuild.
|
||||
# Targets:
|
||||
# Graph.cc: deleteVertex, deleteInEdge, deleteOutEdge,
|
||||
# makePinVertices, makeVertex, makeWireEdgesFromPin (multi-driver),
|
||||
# hasFaninOne, makeInstEdges after replace_cell,
|
||||
# removeWireEdge, removeInstEdge on disconnect/reconnect,
|
||||
# reg_clk_vertices_ insert/erase on add/delete reg
|
||||
|
||||
source ../../test/helpers.tcl
|
||||
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
read_verilog graph_delete_modify.v
|
||||
link_design graph_delete_modify
|
||||
|
||||
create_clock -name clk -period 10 [get_ports clk]
|
||||
set_input_delay -clock clk 1.0 [get_ports {d1 d2 d3 rst}]
|
||||
set_output_delay -clock clk 1.0 [get_ports {q1 q2 q3 q4}]
|
||||
set_input_transition 0.1 [get_ports {d1 d2 d3 rst clk}]
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 1: Baseline timing
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Test 1: baseline ---"
|
||||
report_checks
|
||||
|
||||
report_checks -path_delay min
|
||||
|
||||
report_checks -fields {slew cap input_pins nets fanout}
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 2: Add multiple instances and nets, then delete
|
||||
# Exercises: makeVertex, makeWireEdgesFromPin, deleteVertex,
|
||||
# deleteInEdge, deleteOutEdge
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Test 2: add/delete multiple instances ---"
|
||||
|
||||
# Add a buffer chain
|
||||
set net_a [make_net test_net_a]
|
||||
set net_b [make_net test_net_b]
|
||||
set net_c [make_net test_net_c]
|
||||
set inst_a [make_instance test_buf_a NangateOpenCellLibrary/BUF_X1]
|
||||
set inst_b [make_instance test_buf_b NangateOpenCellLibrary/BUF_X2]
|
||||
|
||||
connect_pin test_net_a test_buf_a/A
|
||||
connect_pin test_net_b test_buf_a/Z
|
||||
connect_pin test_net_b test_buf_b/A
|
||||
connect_pin test_net_c test_buf_b/Z
|
||||
|
||||
report_checks
|
||||
|
||||
# Disconnect middle and verify
|
||||
disconnect_pin test_net_b test_buf_b/A
|
||||
report_checks
|
||||
|
||||
# Reconnect
|
||||
connect_pin test_net_b test_buf_b/A
|
||||
report_checks
|
||||
|
||||
# Full cleanup
|
||||
disconnect_pin test_net_a test_buf_a/A
|
||||
disconnect_pin test_net_b test_buf_a/Z
|
||||
disconnect_pin test_net_b test_buf_b/A
|
||||
disconnect_pin test_net_c test_buf_b/Z
|
||||
delete_instance test_buf_a
|
||||
delete_instance test_buf_b
|
||||
delete_net test_net_a
|
||||
delete_net test_net_b
|
||||
delete_net test_net_c
|
||||
|
||||
report_checks
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 3: Replace cell multiple times
|
||||
# Exercises: makeInstEdges rebuild, edge arc changes
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Test 3: replace_cell ---"
|
||||
|
||||
replace_cell buf1 NangateOpenCellLibrary/BUF_X4
|
||||
report_checks
|
||||
report_edges -from [get_pins buf1/A] -to [get_pins buf1/Z]
|
||||
|
||||
replace_cell buf1 NangateOpenCellLibrary/BUF_X2
|
||||
report_checks
|
||||
|
||||
replace_cell buf1 NangateOpenCellLibrary/BUF_X1
|
||||
report_checks
|
||||
|
||||
replace_cell and1 NangateOpenCellLibrary/AND2_X2
|
||||
report_checks
|
||||
|
||||
replace_cell and1 NangateOpenCellLibrary/AND2_X1
|
||||
report_checks
|
||||
|
||||
replace_cell inv1 NangateOpenCellLibrary/INV_X2
|
||||
report_checks
|
||||
|
||||
replace_cell inv1 NangateOpenCellLibrary/INV_X1
|
||||
report_checks
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 4: Add and delete register instances
|
||||
# Exercises: reg_clk_vertices_ insert/erase in makeVertex/deleteVertex
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Test 4: add/delete register ---"
|
||||
|
||||
set reg_net [make_net reg_test_net]
|
||||
set reg_qnet [make_net reg_test_qnet]
|
||||
set reg_inst [make_instance test_reg NangateOpenCellLibrary/DFF_X1]
|
||||
|
||||
connect_pin reg_test_net test_reg/D
|
||||
connect_pin reg_test_qnet test_reg/Q
|
||||
|
||||
# Connect clock to new register
|
||||
set clk_net_name "clk"
|
||||
connect_pin $clk_net_name test_reg/CK
|
||||
|
||||
report_checks
|
||||
|
||||
# Remove the register
|
||||
disconnect_pin $clk_net_name test_reg/CK
|
||||
disconnect_pin reg_test_net test_reg/D
|
||||
disconnect_pin reg_test_qnet test_reg/Q
|
||||
delete_instance test_reg
|
||||
delete_net reg_test_net
|
||||
delete_net reg_test_qnet
|
||||
|
||||
report_checks
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 5: Rapid connect/disconnect on same pin
|
||||
# Exercises: edge create/delete cycling
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Test 5: rapid connect/disconnect ---"
|
||||
|
||||
set tmp_net [make_net tmp_net]
|
||||
set tmp_inst [make_instance tmp_buf NangateOpenCellLibrary/BUF_X1]
|
||||
|
||||
# Cycle 1
|
||||
connect_pin tmp_net tmp_buf/A
|
||||
report_checks
|
||||
disconnect_pin tmp_net tmp_buf/A
|
||||
puts "cycle 1 done"
|
||||
|
||||
# Cycle 2
|
||||
connect_pin tmp_net tmp_buf/A
|
||||
report_checks
|
||||
disconnect_pin tmp_net tmp_buf/A
|
||||
puts "cycle 2 done"
|
||||
|
||||
# Cycle 3
|
||||
connect_pin tmp_net tmp_buf/A
|
||||
report_checks
|
||||
disconnect_pin tmp_net tmp_buf/A
|
||||
puts "cycle 3 done"
|
||||
|
||||
delete_instance tmp_buf
|
||||
delete_net tmp_net
|
||||
|
||||
report_checks
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 6: Edge queries after all modifications
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Test 6: edge queries ---"
|
||||
|
||||
foreach cell_name {buf1 buf2 inv1 and1 or1 nand1 nor1 reg1 reg2 reg3 reg4} {
|
||||
set edges [get_timing_edges -of_objects [get_cells $cell_name]]
|
||||
puts "$cell_name edges: [llength $edges]"
|
||||
}
|
||||
|
||||
# Slew queries
|
||||
report_slews [get_ports d1]
|
||||
report_slews [get_ports d2]
|
||||
report_slews [get_ports d3]
|
||||
report_slews [get_pins buf1/Z]
|
||||
report_slews [get_pins and1/ZN]
|
||||
report_slews [get_pins reg1/Q]
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 7: Through-pin paths
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Test 7: through pins ---"
|
||||
report_checks -through [get_pins nand1/ZN]
|
||||
puts "through nand1: done"
|
||||
|
||||
report_checks -through [get_pins nor1/ZN]
|
||||
puts "through nor1: done"
|
||||
|
||||
report_checks -through [get_pins and1/ZN]
|
||||
puts "through and1: done"
|
||||
|
|
@ -0,0 +1,29 @@
|
|||
// Design for testing graph delete/modify operations:
|
||||
// makeVertex/deleteVertex through connect_pin/disconnect_pin/delete_instance,
|
||||
// replace_cell with different pin counts, multi-fanout nets,
|
||||
// and reconvergent paths that exercise edge deletion.
|
||||
module graph_delete_modify (clk, d1, d2, d3, rst, q1, q2, q3, q4);
|
||||
input clk, d1, d2, d3, rst;
|
||||
output q1, q2, q3, q4;
|
||||
wire n1, n2, n3, n4, n5, n6, n7, n8;
|
||||
|
||||
// Chain: d1 -> buf1 -> n1 -> and1 -> n5
|
||||
BUF_X1 buf1 (.A(d1), .Z(n1));
|
||||
// Chain: d2 -> buf2 -> n2 -> and1, or1 (multi-fanout)
|
||||
BUF_X1 buf2 (.A(d2), .Z(n2));
|
||||
// Chain: d3 -> inv1 -> n3 -> or1
|
||||
INV_X1 inv1 (.A(d3), .ZN(n3));
|
||||
|
||||
AND2_X1 and1 (.A1(n1), .A2(n2), .ZN(n5));
|
||||
OR2_X1 or1 (.A1(n2), .A2(n3), .ZN(n6));
|
||||
|
||||
// Second stage
|
||||
NAND2_X1 nand1 (.A1(n5), .A2(n6), .ZN(n7));
|
||||
NOR2_X1 nor1 (.A1(n5), .A2(n3), .ZN(n8));
|
||||
|
||||
// Registers with reset
|
||||
DFF_X1 reg1 (.D(n5), .CK(clk), .Q(q1));
|
||||
DFF_X1 reg2 (.D(n7), .CK(clk), .Q(q2));
|
||||
DFF_X1 reg3 (.D(n8), .CK(clk), .Q(q3));
|
||||
DFF_X1 reg4 (.D(n6), .CK(clk), .Q(q4));
|
||||
endmodule
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,182 @@
|
|||
# Test graph incremental changes, constant propagation, and level reporting.
|
||||
# Targets: Graph.cc/GraphCmp.cc/DelayFloat.cc graph update and traversal paths.
|
||||
|
||||
source ../../test/helpers.tcl
|
||||
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
read_verilog graph_test2.v
|
||||
link_design graph_test2
|
||||
|
||||
create_clock -name clk -period 10 [get_ports clk]
|
||||
set_input_delay -clock clk 1.0 [get_ports d1]
|
||||
set_input_delay -clock clk 1.0 [get_ports d2]
|
||||
set_input_delay -clock clk 0 [get_ports en]
|
||||
set_output_delay -clock clk 1.0 [get_ports q1]
|
||||
set_output_delay -clock clk 1.0 [get_ports q2]
|
||||
set_input_transition 0.1 [get_ports {d1 d2 en}]
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Baseline timing
|
||||
#---------------------------------------------------------------
|
||||
puts "--- baseline report_checks ---"
|
||||
report_checks
|
||||
|
||||
report_checks -path_delay min
|
||||
|
||||
report_checks -path_delay max
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Multiple paths through design
|
||||
#---------------------------------------------------------------
|
||||
puts "--- multiple paths ---"
|
||||
report_checks -from [get_ports d1] -to [get_ports q1]
|
||||
|
||||
report_checks -from [get_ports d1] -to [get_ports q2]
|
||||
|
||||
report_checks -from [get_ports d2] -to [get_ports q2]
|
||||
|
||||
report_checks -from [get_ports en] -to [get_ports q1]
|
||||
|
||||
report_checks -from [get_ports en] -to [get_ports q2]
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# -through paths (exercises graph traversal)
|
||||
#---------------------------------------------------------------
|
||||
puts "--- through paths ---"
|
||||
report_checks -through [get_pins inv1/ZN]
|
||||
puts "through inv1/ZN: done"
|
||||
|
||||
report_checks -through [get_pins and1/ZN]
|
||||
puts "through and1/ZN: done"
|
||||
|
||||
report_checks -through [get_pins or1/ZN]
|
||||
puts "through or1/ZN: done"
|
||||
|
||||
report_checks -through [get_pins buf3/Z]
|
||||
puts "through buf3/Z: done"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Timing edge queries for multi-input cells
|
||||
#---------------------------------------------------------------
|
||||
puts "--- timing edges for multi-input cells ---"
|
||||
set edges_and [get_timing_edges -of_objects [get_cells and1]]
|
||||
puts "and1 edges: [llength $edges_and]"
|
||||
|
||||
set edges_or [get_timing_edges -of_objects [get_cells or1]]
|
||||
puts "or1 edges: [llength $edges_or]"
|
||||
|
||||
set edges_reg1 [get_timing_edges -of_objects [get_cells reg1]]
|
||||
puts "reg1 edges: [llength $edges_reg1]"
|
||||
|
||||
set edges_reg2 [get_timing_edges -of_objects [get_cells reg2]]
|
||||
puts "reg2 edges: [llength $edges_reg2]"
|
||||
|
||||
# From/to specific pins
|
||||
set edges_ft [get_timing_edges -from [get_pins and1/A1] -to [get_pins and1/ZN]]
|
||||
puts "and1 A1->ZN edges: [llength $edges_ft]"
|
||||
|
||||
set edges_ft2 [get_timing_edges -from [get_pins and1/A2] -to [get_pins and1/ZN]]
|
||||
puts "and1 A2->ZN edges: [llength $edges_ft2]"
|
||||
|
||||
set edges_ft3 [get_timing_edges -from [get_pins or1/A1] -to [get_pins or1/ZN]]
|
||||
puts "or1 A1->ZN edges: [llength $edges_ft3]"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# report_edges for various pin combinations
|
||||
#---------------------------------------------------------------
|
||||
puts "--- report_edges ---"
|
||||
report_edges -from [get_pins buf1/A] -to [get_pins buf1/Z]
|
||||
|
||||
report_edges -from [get_pins inv1/A] -to [get_pins inv1/ZN]
|
||||
|
||||
report_edges -from [get_pins and1/A1]
|
||||
|
||||
report_edges -to [get_pins and1/ZN]
|
||||
|
||||
report_edges -from [get_ports d1]
|
||||
|
||||
report_edges -to [get_ports q2]
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Constant propagation via set_case_analysis
|
||||
#---------------------------------------------------------------
|
||||
puts "--- set_case_analysis ---"
|
||||
set_case_analysis 1 [get_ports en]
|
||||
report_checks
|
||||
|
||||
report_checks -from [get_ports d1] -to [get_ports q1]
|
||||
|
||||
# Change constant value
|
||||
set_case_analysis 0 [get_ports en]
|
||||
report_checks
|
||||
|
||||
# Remove case analysis
|
||||
unset_case_analysis [get_ports en]
|
||||
report_checks
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Disable/enable timing with multiple cells
|
||||
#---------------------------------------------------------------
|
||||
puts "--- disable/enable timing multiple cells ---"
|
||||
set_disable_timing [get_cells buf1]
|
||||
report_checks
|
||||
|
||||
set_disable_timing [get_cells inv1]
|
||||
report_checks
|
||||
|
||||
unset_disable_timing [get_cells buf1]
|
||||
report_checks
|
||||
|
||||
unset_disable_timing [get_cells inv1]
|
||||
report_checks
|
||||
|
||||
# Disable specific lib cell arc
|
||||
set_disable_timing -from A -to Z [get_lib_cells NangateOpenCellLibrary/BUF_X1]
|
||||
report_disabled_edges
|
||||
report_checks
|
||||
|
||||
unset_disable_timing -from A -to Z [get_lib_cells NangateOpenCellLibrary/BUF_X1]
|
||||
report_disabled_edges
|
||||
report_checks
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# report_check_types
|
||||
#---------------------------------------------------------------
|
||||
puts "--- report_check_types ---"
|
||||
report_check_types -max_delay -verbose
|
||||
|
||||
report_check_types -min_delay -verbose
|
||||
|
||||
report_check_types -max_delay -min_delay -verbose
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Report slews for various pins
|
||||
#---------------------------------------------------------------
|
||||
puts "--- report_slews ---"
|
||||
report_slews [get_ports d1]
|
||||
report_slews [get_ports d2]
|
||||
report_slews [get_ports en]
|
||||
report_slews [get_ports q1]
|
||||
report_slews [get_ports q2]
|
||||
report_slews [get_pins buf1/Z]
|
||||
report_slews [get_pins inv1/ZN]
|
||||
report_slews [get_pins and1/ZN]
|
||||
report_slews [get_pins or1/ZN]
|
||||
report_slews [get_pins reg1/Q]
|
||||
report_slews [get_pins reg2/Q]
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# report_checks with -unconstrained
|
||||
#---------------------------------------------------------------
|
||||
puts "--- report_checks -unconstrained ---"
|
||||
report_checks -unconstrained
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# report_checks with group_count and endpoint_count
|
||||
#---------------------------------------------------------------
|
||||
puts "--- report_checks counts ---"
|
||||
report_checks -group_count 3
|
||||
|
||||
report_checks -endpoint_count 3
|
||||
|
||||
report_checks -endpoint_count 5 -path_delay min
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,245 @@
|
|||
# Test graph changes with network modifications, multi-corner, and
|
||||
# incremental graph updates.
|
||||
# Targets: Graph.cc (deleteVertexBefore, addEdge, removeEdge,
|
||||
# makeWireEdge, removeWireEdge, pinVertex, pinDrvrVertex,
|
||||
# pinLoadVertex, setConstant, clearConstants, hasDownstreamClkPin,
|
||||
# widthCheckAnnotation, periodCheckAnnotation, regClkVertices, isRegClk)
|
||||
# GraphCmp.cc (sortEdges, VertexNameLess with added/removed vertices)
|
||||
|
||||
source ../../test/helpers.tcl
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Multi-corner setup
|
||||
#---------------------------------------------------------------
|
||||
define_corners fast slow
|
||||
|
||||
read_liberty -corner fast ../../test/nangate45/Nangate45_fast.lib
|
||||
read_liberty -corner slow ../../test/nangate45/Nangate45_slow.lib
|
||||
|
||||
read_verilog graph_test3.v
|
||||
link_design graph_test3
|
||||
|
||||
create_clock -name clk1 -period 10 [get_ports clk1]
|
||||
create_clock -name clk2 -period 15 [get_ports clk2]
|
||||
set_input_delay -clock clk1 1.0 [get_ports {d1 d2 d3 d4}]
|
||||
set_output_delay -clock clk1 1.0 [get_ports {q1 q3}]
|
||||
set_output_delay -clock clk2 1.0 [get_ports q2]
|
||||
set_input_transition 0.1 [get_ports {d1 d2 d3 d4 rst clk1 clk2}]
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Multi-corner baseline timing
|
||||
#---------------------------------------------------------------
|
||||
puts "--- multi-corner baseline ---"
|
||||
report_checks -corner fast
|
||||
|
||||
report_checks -corner slow
|
||||
|
||||
report_checks -corner fast -path_delay min
|
||||
|
||||
report_checks -corner slow -path_delay min
|
||||
|
||||
report_checks -corner fast -path_delay max
|
||||
|
||||
report_checks -corner slow -path_delay max
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Multi-corner per-path (exercises delay comparison across corners)
|
||||
#---------------------------------------------------------------
|
||||
puts "--- multi-corner per-path ---"
|
||||
report_checks -corner fast -from [get_ports d1] -to [get_ports q1]
|
||||
|
||||
report_checks -corner slow -from [get_ports d1] -to [get_ports q1]
|
||||
|
||||
report_checks -corner fast -from [get_ports d3] -to [get_ports q1]
|
||||
|
||||
report_checks -corner slow -from [get_ports d3] -to [get_ports q1]
|
||||
|
||||
# Cross-clock domain paths
|
||||
report_checks -corner fast -from [get_ports d1] -to [get_ports q2]
|
||||
|
||||
report_checks -corner slow -from [get_ports d1] -to [get_ports q2]
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Multi-corner report_dcalc
|
||||
# Exercises: delay value comparison across corners
|
||||
#---------------------------------------------------------------
|
||||
puts "--- multi-corner report_dcalc ---"
|
||||
report_dcalc -corner fast -from [get_pins buf1/A] -to [get_pins buf1/Z]
|
||||
puts "fast buf1 dcalc: done"
|
||||
|
||||
report_dcalc -corner slow -from [get_pins buf1/A] -to [get_pins buf1/Z]
|
||||
puts "slow buf1 dcalc: done"
|
||||
|
||||
report_dcalc -corner fast -from [get_pins nand1/A1] -to [get_pins nand1/ZN]
|
||||
puts "fast nand1 dcalc: done"
|
||||
|
||||
report_dcalc -corner slow -from [get_pins nand1/A1] -to [get_pins nand1/ZN]
|
||||
puts "slow nand1 dcalc: done"
|
||||
|
||||
report_dcalc -corner fast -from [get_pins nor1/A1] -to [get_pins nor1/ZN]
|
||||
puts "fast nor1 dcalc: done"
|
||||
|
||||
report_dcalc -corner slow -from [get_pins nor1/A1] -to [get_pins nor1/ZN]
|
||||
puts "slow nor1 dcalc: done"
|
||||
|
||||
report_dcalc -corner fast -from [get_pins reg1/CK] -to [get_pins reg1/Q] -max
|
||||
puts "fast reg1 CK->Q: done"
|
||||
|
||||
report_dcalc -corner slow -from [get_pins reg1/CK] -to [get_pins reg1/Q] -max
|
||||
puts "slow reg1 CK->Q: done"
|
||||
|
||||
report_dcalc -corner fast -from [get_pins reg1/CK] -to [get_pins reg1/D] -max
|
||||
puts "fast reg1 setup: done"
|
||||
|
||||
report_dcalc -corner slow -from [get_pins reg1/CK] -to [get_pins reg1/D] -min
|
||||
puts "slow reg1 hold: done"
|
||||
|
||||
# Cross-clock domain DFF
|
||||
report_dcalc -corner fast -from [get_pins reg3/CK] -to [get_pins reg3/Q] -max
|
||||
puts "fast reg3 CK->Q: done"
|
||||
|
||||
report_dcalc -corner slow -from [get_pins reg3/CK] -to [get_pins reg3/Q] -max
|
||||
puts "slow reg3 CK->Q: done"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Network modification: add instance, recheck graph
|
||||
# Exercises: graph incremental update after network changes
|
||||
#---------------------------------------------------------------
|
||||
puts "--- network modification and graph update ---"
|
||||
set new_buf [make_instance added_buf NangateOpenCellLibrary/BUF_X1]
|
||||
|
||||
set new_net [make_net added_net]
|
||||
|
||||
connect_pin added_net added_buf/A
|
||||
|
||||
# Report checks after adding (graph updated incrementally)
|
||||
report_checks -corner fast
|
||||
|
||||
report_checks -corner slow
|
||||
|
||||
# Disconnect and delete
|
||||
disconnect_pin added_net added_buf/A
|
||||
delete_instance added_buf
|
||||
delete_net added_net
|
||||
|
||||
# Report after deletion
|
||||
report_checks -corner fast
|
||||
|
||||
report_checks -corner slow
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Replace cell and check timing
|
||||
# Exercises: graph update after cell replacement
|
||||
#---------------------------------------------------------------
|
||||
puts "--- replace_cell ---"
|
||||
replace_cell buf1 NangateOpenCellLibrary/BUF_X4
|
||||
report_checks -corner fast
|
||||
|
||||
report_checks -corner slow
|
||||
|
||||
# Replace back
|
||||
replace_cell buf1 NangateOpenCellLibrary/BUF_X1
|
||||
report_checks
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Load changes with multi-corner
|
||||
# Exercises: incremental delay recomputation
|
||||
#---------------------------------------------------------------
|
||||
puts "--- load changes multi-corner ---"
|
||||
set_load 0.01 [get_ports q1]
|
||||
report_checks -corner fast
|
||||
report_checks -corner slow
|
||||
|
||||
set_load 0.05 [get_ports q2]
|
||||
report_checks -corner fast
|
||||
report_checks -corner slow
|
||||
|
||||
set_load 0.1 [get_ports q3]
|
||||
report_checks -corner fast
|
||||
report_checks -corner slow
|
||||
|
||||
# Reset loads
|
||||
set_load 0 [get_ports q1]
|
||||
set_load 0 [get_ports q2]
|
||||
set_load 0 [get_ports q3]
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Disable/enable timing with multi-corner
|
||||
# Exercises: edge disable/re-enable with multiple analysis points
|
||||
#---------------------------------------------------------------
|
||||
puts "--- disable timing multi-corner ---"
|
||||
set_disable_timing [get_cells and1]
|
||||
report_checks -corner fast
|
||||
report_checks -corner slow
|
||||
|
||||
set_disable_timing [get_cells or1]
|
||||
report_checks -corner fast
|
||||
report_checks -corner slow
|
||||
|
||||
unset_disable_timing [get_cells and1]
|
||||
unset_disable_timing [get_cells or1]
|
||||
report_checks -corner fast
|
||||
report_checks -corner slow
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Case analysis with multi-corner
|
||||
#---------------------------------------------------------------
|
||||
puts "--- case analysis multi-corner ---"
|
||||
set_case_analysis 1 [get_ports d1]
|
||||
report_checks -corner fast
|
||||
report_checks -corner slow
|
||||
|
||||
unset_case_analysis [get_ports d1]
|
||||
report_checks -corner fast
|
||||
report_checks -corner slow
|
||||
|
||||
set_case_analysis 0 [get_ports d4]
|
||||
report_checks -corner fast
|
||||
report_checks -corner slow
|
||||
|
||||
unset_case_analysis [get_ports d4]
|
||||
report_checks
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Report slews per corner
|
||||
#---------------------------------------------------------------
|
||||
puts "--- report_slews multi-corner ---"
|
||||
report_slews [get_ports d1]
|
||||
report_slews [get_ports q1]
|
||||
report_slews [get_ports q2]
|
||||
report_slews [get_pins nand1/ZN]
|
||||
report_slews [get_pins nor1/ZN]
|
||||
report_slews [get_pins reg3/Q]
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Report edges (exercises EdgeLess comparator)
|
||||
#---------------------------------------------------------------
|
||||
puts "--- report_edges multi-corner ---"
|
||||
report_edges -from [get_pins nand1/A1] -to [get_pins nand1/ZN]
|
||||
report_edges -from [get_pins nand1/A2] -to [get_pins nand1/ZN]
|
||||
report_edges -from [get_pins nor1/A1] -to [get_pins nor1/ZN]
|
||||
report_edges -from [get_pins nor1/A2] -to [get_pins nor1/ZN]
|
||||
report_edges -from [get_pins and2/A1] -to [get_pins and2/ZN]
|
||||
report_edges -from [get_pins and2/A2] -to [get_pins and2/ZN]
|
||||
report_edges -from [get_pins or2/A1] -to [get_pins or2/ZN]
|
||||
report_edges -from [get_pins or2/A2] -to [get_pins or2/ZN]
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# report_checks with fields per corner
|
||||
#---------------------------------------------------------------
|
||||
puts "--- fields per corner ---"
|
||||
report_checks -corner fast -fields {slew cap input_pins nets fanout}
|
||||
|
||||
report_checks -corner slow -fields {slew cap input_pins nets fanout}
|
||||
|
||||
report_checks -corner fast -format full_clock
|
||||
|
||||
report_checks -corner slow -format full_clock
|
||||
|
||||
report_checks -corner fast -unconstrained
|
||||
|
||||
report_checks -corner slow -unconstrained
|
||||
|
||||
report_checks -corner fast -group_count 3
|
||||
|
||||
report_checks -corner slow -endpoint_count 5
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,256 @@
|
|||
# Test graph operations with larger multi-clock design for coverage.
|
||||
# Targets: Graph.cc (makeGraph, makeVerticesAndEdges, makeWireEdges,
|
||||
# makePinVertices, makeInstanceEdges, pinVertices, pinDrvrVertex,
|
||||
# pinLoadVertex, vertexCount, edgeCount, vertexIterator, edgeIterator,
|
||||
# arcDelayCount, hasDownstreamClkPin, regClkVertices, isRegClk,
|
||||
# isLatchData, widthCheckAnnotation, periodCheckAnnotation)
|
||||
# GraphCmp.cc (EdgeLess, sortEdges, VertexNameLess, vertexLess)
|
||||
|
||||
source ../../test/helpers.tcl
|
||||
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
read_verilog graph_test3.v
|
||||
link_design graph_test3
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Two clock domains
|
||||
#---------------------------------------------------------------
|
||||
create_clock -name clk1 -period 10 [get_ports clk1]
|
||||
create_clock -name clk2 -period 15 [get_ports clk2]
|
||||
set_input_delay -clock clk1 1.0 [get_ports {d1 d2 d3 d4}]
|
||||
set_output_delay -clock clk1 1.0 [get_ports {q1 q3}]
|
||||
set_output_delay -clock clk2 1.0 [get_ports q2]
|
||||
set_input_transition 0.1 [get_ports {d1 d2 d3 d4 rst clk1 clk2}]
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Baseline timing (exercises makeGraph, graph construction)
|
||||
#---------------------------------------------------------------
|
||||
puts "--- baseline timing ---"
|
||||
report_checks
|
||||
|
||||
report_checks -path_delay min
|
||||
|
||||
report_checks -path_delay max
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# All path combinations (exercises vertex/edge traversal thoroughly)
|
||||
#---------------------------------------------------------------
|
||||
puts "--- all path combinations ---"
|
||||
foreach from_port {d1 d2 d3 d4} {
|
||||
foreach to_port {q1 q2 q3} {
|
||||
report_checks -from [get_ports $from_port] -to [get_ports $to_port]
|
||||
puts "${from_port}->${to_port}: done"
|
||||
}
|
||||
}
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Through pin queries for reconvergent paths
|
||||
# Exercises: graph traversal through reconvergent fan-out
|
||||
#---------------------------------------------------------------
|
||||
puts "--- through reconvergent paths ---"
|
||||
report_checks -through [get_pins nand1/ZN]
|
||||
puts "through nand1/ZN: done"
|
||||
|
||||
report_checks -through [get_pins nor1/ZN]
|
||||
puts "through nor1/ZN: done"
|
||||
|
||||
report_checks -through [get_pins and2/ZN]
|
||||
puts "through and2/ZN: done"
|
||||
|
||||
report_checks -through [get_pins or2/ZN]
|
||||
puts "through or2/ZN: done"
|
||||
|
||||
# Through multiple intermediate points
|
||||
report_checks -through [get_pins and1/ZN] -through [get_pins nand1/ZN]
|
||||
puts "through and1->nand1: done"
|
||||
|
||||
report_checks -through [get_pins or1/ZN] -through [get_pins nand1/ZN]
|
||||
puts "through or1->nand1: done"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Timing edge queries for all cells (exercises edge iteration)
|
||||
#---------------------------------------------------------------
|
||||
puts "--- timing edges all cells ---"
|
||||
foreach cell_name {buf1 buf2 inv1 inv2 and1 or1 nand1 nor1 and2 or2 reg1 reg2 reg3 buf3 buf4} {
|
||||
set edges [get_timing_edges -of_objects [get_cells $cell_name]]
|
||||
puts "$cell_name edges: [llength $edges]"
|
||||
}
|
||||
|
||||
# From/to specific pins
|
||||
puts "--- specific edge queries ---"
|
||||
set edges_and1_a1 [get_timing_edges -from [get_pins and1/A1] -to [get_pins and1/ZN]]
|
||||
puts "and1 A1->ZN: [llength $edges_and1_a1]"
|
||||
|
||||
set edges_and1_a2 [get_timing_edges -from [get_pins and1/A2] -to [get_pins and1/ZN]]
|
||||
puts "and1 A2->ZN: [llength $edges_and1_a2]"
|
||||
|
||||
set edges_or1_a1 [get_timing_edges -from [get_pins or1/A1] -to [get_pins or1/ZN]]
|
||||
puts "or1 A1->ZN: [llength $edges_or1_a1]"
|
||||
|
||||
set edges_nand_a1 [get_timing_edges -from [get_pins nand1/A1] -to [get_pins nand1/ZN]]
|
||||
puts "nand1 A1->ZN: [llength $edges_nand_a1]"
|
||||
|
||||
set edges_nor_a1 [get_timing_edges -from [get_pins nor1/A1] -to [get_pins nor1/ZN]]
|
||||
puts "nor1 A1->ZN: [llength $edges_nor_a1]"
|
||||
|
||||
# DFF edges
|
||||
set edges_reg1_ck_q [get_timing_edges -from [get_pins reg1/CK] -to [get_pins reg1/Q]]
|
||||
puts "reg1 CK->Q: [llength $edges_reg1_ck_q]"
|
||||
|
||||
set edges_reg3_ck_q [get_timing_edges -from [get_pins reg3/CK] -to [get_pins reg3/Q]]
|
||||
puts "reg3 CK->Q: [llength $edges_reg3_ck_q]"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Report edges for all cell types
|
||||
#---------------------------------------------------------------
|
||||
puts "--- report_edges ---"
|
||||
report_edges -from [get_pins buf1/A] -to [get_pins buf1/Z]
|
||||
|
||||
report_edges -from [get_pins inv1/A] -to [get_pins inv1/ZN]
|
||||
|
||||
report_edges -from [get_pins and1/A1] -to [get_pins and1/ZN]
|
||||
|
||||
report_edges -from [get_pins and1/A2] -to [get_pins and1/ZN]
|
||||
|
||||
report_edges -from [get_pins or1/A1] -to [get_pins or1/ZN]
|
||||
|
||||
report_edges -from [get_pins nand1/A1] -to [get_pins nand1/ZN]
|
||||
|
||||
report_edges -from [get_pins nor1/A1] -to [get_pins nor1/ZN]
|
||||
|
||||
report_edges -from [get_pins reg1/CK] -to [get_pins reg1/Q]
|
||||
|
||||
report_edges -from [get_pins reg3/CK] -to [get_pins reg3/Q]
|
||||
|
||||
# From only
|
||||
report_edges -from [get_ports d1]
|
||||
|
||||
report_edges -from [get_ports d3]
|
||||
|
||||
# To only
|
||||
report_edges -to [get_ports q1]
|
||||
|
||||
report_edges -to [get_ports q2]
|
||||
|
||||
report_edges -to [get_ports q3]
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Disable/enable timing on various cells
|
||||
# Exercises: graph edge disable/enable, re-traversal
|
||||
#---------------------------------------------------------------
|
||||
puts "--- disable/enable timing ---"
|
||||
|
||||
# Disable individual cells
|
||||
set_disable_timing [get_cells buf1]
|
||||
report_checks
|
||||
|
||||
set_disable_timing [get_cells inv1]
|
||||
report_checks
|
||||
|
||||
set_disable_timing [get_cells nand1]
|
||||
report_checks
|
||||
|
||||
# Enable back one by one
|
||||
unset_disable_timing [get_cells buf1]
|
||||
report_checks
|
||||
|
||||
unset_disable_timing [get_cells inv1]
|
||||
report_checks
|
||||
|
||||
unset_disable_timing [get_cells nand1]
|
||||
report_checks
|
||||
|
||||
# Disable specific arcs on lib cells
|
||||
set_disable_timing -from A1 -to ZN [get_lib_cells NangateOpenCellLibrary/AND2_X1]
|
||||
report_disabled_edges
|
||||
report_checks
|
||||
|
||||
unset_disable_timing -from A1 -to ZN [get_lib_cells NangateOpenCellLibrary/AND2_X1]
|
||||
report_disabled_edges
|
||||
report_checks
|
||||
|
||||
# Disable/enable on NOR and NAND
|
||||
set_disable_timing -from A1 -to ZN [get_lib_cells NangateOpenCellLibrary/NAND2_X1]
|
||||
report_checks
|
||||
|
||||
unset_disable_timing -from A1 -to ZN [get_lib_cells NangateOpenCellLibrary/NAND2_X1]
|
||||
report_checks
|
||||
|
||||
set_disable_timing -from A1 -to ZN [get_lib_cells NangateOpenCellLibrary/NOR2_X1]
|
||||
report_checks
|
||||
|
||||
unset_disable_timing -from A1 -to ZN [get_lib_cells NangateOpenCellLibrary/NOR2_X1]
|
||||
report_checks
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Case analysis / constant propagation
|
||||
# Exercises: graph constant propagation, re-traversal
|
||||
#---------------------------------------------------------------
|
||||
puts "--- case analysis ---"
|
||||
set_case_analysis 1 [get_ports rst]
|
||||
report_checks
|
||||
|
||||
set_case_analysis 0 [get_ports rst]
|
||||
report_checks
|
||||
|
||||
unset_case_analysis [get_ports rst]
|
||||
report_checks
|
||||
|
||||
# Case analysis on data inputs
|
||||
set_case_analysis 1 [get_ports d3]
|
||||
report_checks
|
||||
|
||||
unset_case_analysis [get_ports d3]
|
||||
report_checks
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Report slews for pins in multi-clock design
|
||||
# Exercises: vertex slew access across corners
|
||||
#---------------------------------------------------------------
|
||||
puts "--- report_slews ---"
|
||||
report_slews [get_ports d1]
|
||||
report_slews [get_ports d2]
|
||||
report_slews [get_ports d3]
|
||||
report_slews [get_ports d4]
|
||||
report_slews [get_ports q1]
|
||||
report_slews [get_ports q2]
|
||||
report_slews [get_ports q3]
|
||||
report_slews [get_pins buf1/Z]
|
||||
report_slews [get_pins inv1/ZN]
|
||||
report_slews [get_pins and1/ZN]
|
||||
report_slews [get_pins or1/ZN]
|
||||
report_slews [get_pins nand1/ZN]
|
||||
report_slews [get_pins nor1/ZN]
|
||||
report_slews [get_pins and2/ZN]
|
||||
report_slews [get_pins or2/ZN]
|
||||
report_slews [get_pins reg1/Q]
|
||||
report_slews [get_pins reg2/Q]
|
||||
report_slews [get_pins reg3/Q]
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# report_check_types (exercises check edge categorization)
|
||||
#---------------------------------------------------------------
|
||||
puts "--- report_check_types ---"
|
||||
report_check_types -max_delay -verbose
|
||||
|
||||
report_check_types -min_delay -verbose
|
||||
|
||||
report_check_types -max_delay -min_delay -verbose
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# report_checks with various options
|
||||
#---------------------------------------------------------------
|
||||
puts "--- report_checks options ---"
|
||||
report_checks -fields {slew cap input_pins nets fanout}
|
||||
|
||||
report_checks -format full_clock
|
||||
|
||||
report_checks -unconstrained
|
||||
|
||||
report_checks -group_count 3
|
||||
|
||||
report_checks -endpoint_count 5
|
||||
|
||||
report_checks -sort_by_slack
|
||||
|
||||
report_checks -endpoint_count 3 -path_delay min
|
||||
|
|
@ -0,0 +1,177 @@
|
|||
--- get_timing_edges -of_objects instance ---
|
||||
reg1 timing edges count: 1
|
||||
--- get_timing_edges -from/-to on instance ---
|
||||
CK->Q edges count: 1
|
||||
--- get_timing_edges -from only ---
|
||||
edges from CK count: 5
|
||||
--- get_timing_edges -to only ---
|
||||
edges to Q count: 1
|
||||
--- report_edges -from/-to ---
|
||||
CK -> Q Reg Clk to Q
|
||||
^ -> ^ 0.08:0.08
|
||||
^ -> v 0.08:0.08
|
||||
--- report_edges -from ---
|
||||
CK -> QN Reg Clk to Q
|
||||
^ -> ^ 0.06:0.06
|
||||
^ -> v 0.06:0.06
|
||||
CK -> Q Reg Clk to Q
|
||||
^ -> ^ 0.08:0.08
|
||||
^ -> v 0.08:0.08
|
||||
CK -> CK width
|
||||
^ -> v 0.05:0.05
|
||||
v -> ^ 0.05:0.05
|
||||
CK -> D setup
|
||||
^ -> ^ 0.03:0.03
|
||||
^ -> v 0.04:0.04
|
||||
CK -> D hold
|
||||
^ -> ^ 0.00:0.00
|
||||
^ -> v 0.00:0.00
|
||||
--- report_edges -to ---
|
||||
CK -> D setup
|
||||
^ -> ^ 0.03:0.03
|
||||
^ -> v 0.04:0.04
|
||||
CK -> D hold
|
||||
^ -> ^ 0.01:0.01
|
||||
^ -> v 0.00:0.00
|
||||
reg1/Q -> D wire
|
||||
^ -> ^ 0.00:0.00
|
||||
v -> v 0.00:0.00
|
||||
--- report_disabled_edges (baseline) ---
|
||||
--- set_disable_timing on instance ---
|
||||
--- report_disabled_edges after disable ---
|
||||
reg1 CK Q constraint
|
||||
reg1 CK QN constraint
|
||||
--- report_checks after disable ---
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: q (output port clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg2/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg2/Q (DFF_X1)
|
||||
0.00 0.08 ^ q (out)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
0.00 10.00 output external delay
|
||||
10.00 data required time
|
||||
---------------------------------------------------------
|
||||
10.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.92 slack (MET)
|
||||
|
||||
|
||||
--- unset_disable_timing on instance ---
|
||||
--- report_disabled_edges after unset ---
|
||||
--- set_disable_timing with -from/-to on lib cell ---
|
||||
--- report_disabled_edges after lib cell disable ---
|
||||
reg1 CK Q constraint
|
||||
reg2 CK Q constraint
|
||||
--- unset_disable_timing lib cell ---
|
||||
--- report_checks baseline ---
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg1/CK (DFF_X1)
|
||||
0.08 0.08 v reg1/Q (DFF_X1)
|
||||
0.00 0.08 v reg2/D (DFF_X1)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.04 9.96 library setup time
|
||||
9.96 data required time
|
||||
---------------------------------------------------------
|
||||
9.96 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.88 slack (MET)
|
||||
|
||||
|
||||
--- report_checks -path_delay max ---
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg1/CK (DFF_X1)
|
||||
0.08 0.08 v reg1/Q (DFF_X1)
|
||||
0.00 0.08 v reg2/D (DFF_X1)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.04 9.96 library setup time
|
||||
9.96 data required time
|
||||
---------------------------------------------------------
|
||||
9.96 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.88 slack (MET)
|
||||
|
||||
|
||||
--- report_checks -path_delay min ---
|
||||
Startpoint: d (input port clocked by clk)
|
||||
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: min
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ input external delay
|
||||
0.00 0.00 ^ d (in)
|
||||
0.00 0.00 ^ reg1/D (DFF_X1)
|
||||
0.00 data arrival time
|
||||
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 clock reconvergence pessimism
|
||||
0.00 ^ reg1/CK (DFF_X1)
|
||||
0.00 0.00 library hold time
|
||||
0.00 data required time
|
||||
---------------------------------------------------------
|
||||
0.00 data required time
|
||||
-0.00 data arrival time
|
||||
---------------------------------------------------------
|
||||
0.00 slack (VIOLATED)
|
||||
|
||||
|
||||
--- report_checks from d to q ---
|
||||
No paths found.
|
||||
--- report_edges -from port d ---
|
||||
d -> reg1/D wire
|
||||
^ -> ^ 0.00:0.00
|
||||
v -> v 0.00:0.00
|
||||
--- report_edges -to port q ---
|
||||
reg2/Q -> q wire
|
||||
^ -> ^ 0.00:0.00
|
||||
v -> v 0.00:0.00
|
||||
--- get_timing_edges -of_objects reg2 ---
|
||||
reg2 timing edges count: 1
|
||||
--- report_slews on d port ---
|
||||
d ^ 0.00:0.00 v 0.00:0.00
|
||||
--- report_slews on q port ---
|
||||
q ^ 0.01:0.01 v 0.00:0.00
|
||||
|
|
@ -0,0 +1,88 @@
|
|||
# Test graph timing edge queries and disable_timing
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
read_verilog graph_test1.v
|
||||
link_design graph_test1
|
||||
|
||||
create_clock -name clk -period 10 [get_ports clk]
|
||||
set_input_delay -clock clk 0 [get_ports d]
|
||||
set_output_delay -clock clk 0 [get_ports q]
|
||||
|
||||
puts "--- get_timing_edges -of_objects instance ---"
|
||||
set edges [get_timing_edges -of_objects [get_cells reg1]]
|
||||
puts "reg1 timing edges count: [llength $edges]"
|
||||
|
||||
puts "--- get_timing_edges -from/-to on instance ---"
|
||||
set edges_ft [get_timing_edges -from [get_pins reg1/CK] -to [get_pins reg1/Q]]
|
||||
puts "CK->Q edges count: [llength $edges_ft]"
|
||||
|
||||
puts "--- get_timing_edges -from only ---"
|
||||
set edges_from [get_timing_edges -from [get_pins reg1/CK]]
|
||||
puts "edges from CK count: [llength $edges_from]"
|
||||
|
||||
puts "--- get_timing_edges -to only ---"
|
||||
set edges_to [get_timing_edges -to [get_pins reg1/Q]]
|
||||
puts "edges to Q count: [llength $edges_to]"
|
||||
|
||||
puts "--- report_edges -from/-to ---"
|
||||
report_edges -from [get_pins reg1/CK] -to [get_pins reg1/Q]
|
||||
|
||||
puts "--- report_edges -from ---"
|
||||
report_edges -from [get_pins reg1/CK]
|
||||
|
||||
puts "--- report_edges -to ---"
|
||||
report_edges -to [get_pins reg2/D]
|
||||
|
||||
puts "--- report_disabled_edges (baseline) ---"
|
||||
report_disabled_edges
|
||||
|
||||
puts "--- set_disable_timing on instance ---"
|
||||
set_disable_timing [get_cells reg1]
|
||||
|
||||
puts "--- report_disabled_edges after disable ---"
|
||||
report_disabled_edges
|
||||
|
||||
puts "--- report_checks after disable ---"
|
||||
report_checks
|
||||
|
||||
puts "--- unset_disable_timing on instance ---"
|
||||
unset_disable_timing [get_cells reg1]
|
||||
|
||||
puts "--- report_disabled_edges after unset ---"
|
||||
report_disabled_edges
|
||||
|
||||
puts "--- set_disable_timing with -from/-to on lib cell ---"
|
||||
set_disable_timing -from CK -to Q [get_lib_cells NangateOpenCellLibrary/DFF_X1]
|
||||
|
||||
puts "--- report_disabled_edges after lib cell disable ---"
|
||||
report_disabled_edges
|
||||
|
||||
puts "--- unset_disable_timing lib cell ---"
|
||||
unset_disable_timing -from CK -to Q [get_lib_cells NangateOpenCellLibrary/DFF_X1]
|
||||
|
||||
puts "--- report_checks baseline ---"
|
||||
report_checks
|
||||
|
||||
puts "--- report_checks -path_delay max ---"
|
||||
report_checks -path_delay max
|
||||
|
||||
puts "--- report_checks -path_delay min ---"
|
||||
report_checks -path_delay min
|
||||
|
||||
puts "--- report_checks from d to q ---"
|
||||
report_checks -from [get_ports d] -to [get_ports q]
|
||||
|
||||
puts "--- report_edges -from port d ---"
|
||||
report_edges -from [get_ports d]
|
||||
|
||||
puts "--- report_edges -to port q ---"
|
||||
report_edges -to [get_ports q]
|
||||
|
||||
puts "--- get_timing_edges -of_objects reg2 ---"
|
||||
set edges_r2 [get_timing_edges -of_objects [get_cells reg2]]
|
||||
puts "reg2 timing edges count: [llength $edges_r2]"
|
||||
|
||||
puts "--- report_slews on d port ---"
|
||||
report_slews [get_ports d]
|
||||
|
||||
puts "--- report_slews on q port ---"
|
||||
report_slews [get_ports q]
|
||||
|
|
@ -0,0 +1,954 @@
|
|||
--- Test 1: baseline edge count ---
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
buf1 edges: 1
|
||||
buf2 edges: 1
|
||||
inv1 edges: 1
|
||||
and1 edges: 1
|
||||
or1 edges: 1
|
||||
nand1 edges: 1
|
||||
nor1 edges: 1
|
||||
--- Test 2: chain add/delete ---
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
chain_buf0 edges: 1
|
||||
chain_buf1 edges: 1
|
||||
chain_buf2 edges: 1
|
||||
chain_buf3 edges: 1
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
--- Test 3: fan-out/fan-in ---
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
fo_drv edges: 1
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
--- Test 4: cell replacement cycle ---
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.13 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.13 ^ reg2/D (DFF_X1)
|
||||
1.13 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.13 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.84 slack (MET)
|
||||
|
||||
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
--- Test 5: register add/delete ---
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
--- Test 6: slew and edge reports ---
|
||||
d1 ^ 0.10:0.10 v 0.10:0.10
|
||||
d2 ^ 0.10:0.10 v 0.10:0.10
|
||||
d3 ^ 0.10:0.10 v 0.10:0.10
|
||||
clk ^ 0.10:0.10 v 0.10:0.10
|
||||
buf1/A ^ 0.10:0.10 v 0.10:0.10
|
||||
buf1/Z ^ 0.01:0.01 v 0.01:0.01
|
||||
and1/A1 ^ 0.01:0.01 v 0.01:0.01
|
||||
and1/ZN ^ 0.01:0.01 v 0.01:0.01
|
||||
inv1/A ^ 0.10:0.10 v 0.10:0.10
|
||||
inv1/ZN ^ 0.02:0.02 v 0.02:0.02
|
||||
nand1/ZN ^ 0.01:0.01 v 0.01:0.01
|
||||
nor1/ZN ^ 0.01:0.01 v 0.01:0.01
|
||||
A -> Z combinational
|
||||
^ -> ^ 0.03:0.03
|
||||
v -> v 0.06:0.06
|
||||
A1 -> ZN combinational
|
||||
^ -> ^ 0.04:0.04
|
||||
v -> v 0.03:0.03
|
||||
A -> ZN combinational
|
||||
^ -> v 0.01:0.01
|
||||
v -> ^ 0.04:0.04
|
||||
--- Test 7: through-pin queries ---
|
||||
Startpoint: d1 (input port clocked by clk)
|
||||
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d1 (in)
|
||||
0.06 1.06 v buf1/Z (BUF_X1)
|
||||
0.03 1.09 v and1/ZN (AND2_X1)
|
||||
0.02 1.11 ^ nor1/ZN (NOR2_X1)
|
||||
0.00 1.11 ^ reg3/D (DFF_X1)
|
||||
1.11 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg3/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.11 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.86 slack (MET)
|
||||
|
||||
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.04 1.09 v and1/ZN (AND2_X1)
|
||||
0.02 1.11 ^ nor1/ZN (NOR2_X1)
|
||||
0.00 1.11 ^ reg3/D (DFF_X1)
|
||||
1.11 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg3/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.11 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
Startpoint: d3 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d3 (in)
|
||||
0.04 1.04 ^ inv1/ZN (INV_X1)
|
||||
0.03 1.07 ^ or1/ZN (OR2_X1)
|
||||
0.01 1.09 v nand1/ZN (NAND2_X1)
|
||||
0.00 1.09 v reg2/D (DFF_X1)
|
||||
1.09 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.04 9.96 library setup time
|
||||
9.96 data required time
|
||||
---------------------------------------------------------
|
||||
9.96 data required time
|
||||
-1.09 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.88 slack (MET)
|
||||
|
||||
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.04 1.09 v and1/ZN (AND2_X1)
|
||||
0.02 1.11 ^ nor1/ZN (NOR2_X1)
|
||||
0.00 1.11 ^ reg3/D (DFF_X1)
|
||||
1.11 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg3/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.11 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: q1 (output port clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg1/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg1/Q (DFF_X1)
|
||||
0.00 0.08 ^ q1 (out)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
-1.00 9.00 output external delay
|
||||
9.00 data required time
|
||||
---------------------------------------------------------
|
||||
9.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.92 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: q2 (output port clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg2/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg2/Q (DFF_X1)
|
||||
0.00 0.08 ^ q2 (out)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
-1.00 9.00 output external delay
|
||||
9.00 data required time
|
||||
---------------------------------------------------------
|
||||
9.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.92 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg3 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: q3 (output port clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg3/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg3/Q (DFF_X1)
|
||||
0.00 0.08 ^ q3 (out)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
-1.00 9.00 output external delay
|
||||
9.00 data required time
|
||||
---------------------------------------------------------
|
||||
9.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.92 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg4 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: q4 (output port clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg4/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg4/Q (DFF_X1)
|
||||
0.00 0.08 ^ q4 (out)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
-1.00 9.00 output external delay
|
||||
9.00 data required time
|
||||
---------------------------------------------------------
|
||||
9.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.92 slack (MET)
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,206 @@
|
|||
# Test graph vertex and edge operations in depth: makeVertex, deleteVertex,
|
||||
# makeEdge, deleteEdge, edge arc queries, bidirectional pin handling,
|
||||
# hasFaninOne, vertex iteration, edge linking.
|
||||
source ../../test/helpers.tcl
|
||||
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
read_verilog graph_delete_modify.v
|
||||
link_design graph_delete_modify
|
||||
|
||||
create_clock -name clk -period 10 [get_ports clk]
|
||||
set_input_delay -clock clk 1.0 [get_ports {d1 d2 d3 rst}]
|
||||
set_output_delay -clock clk 1.0 [get_ports {q1 q2 q3 q4}]
|
||||
set_input_transition 0.1 [get_ports {d1 d2 d3 rst clk}]
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 1: Baseline - build graph and verify edges
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Test 1: baseline edge count ---"
|
||||
report_checks
|
||||
|
||||
# Query edges for each cell
|
||||
foreach cell_name {buf1 buf2 inv1 and1 or1 nand1 nor1} {
|
||||
set edges [get_timing_edges -of_objects [get_cells $cell_name]]
|
||||
puts "$cell_name edges: [llength $edges]"
|
||||
}
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 2: Add chain of buffers, verify edges, then delete one by one
|
||||
# Exercises: makeVertex, makeEdge, deleteVertex, deleteEdge,
|
||||
# deleteInEdge, deleteOutEdge
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Test 2: chain add/delete ---"
|
||||
|
||||
# Create 4-stage buffer chain
|
||||
set chain_nets {}
|
||||
set chain_insts {}
|
||||
for {set i 0} {$i < 4} {incr i} {
|
||||
lappend chain_nets [make_net "chain_n$i"]
|
||||
}
|
||||
lappend chain_nets [make_net "chain_n4"]
|
||||
|
||||
for {set i 0} {$i < 4} {incr i} {
|
||||
set inst [make_instance "chain_buf$i" NangateOpenCellLibrary/BUF_X1]
|
||||
lappend chain_insts $inst
|
||||
connect_pin "chain_n$i" "chain_buf$i/A"
|
||||
set j [expr {$i + 1}]
|
||||
connect_pin "chain_n$j" "chain_buf$i/Z"
|
||||
}
|
||||
|
||||
report_checks
|
||||
|
||||
# Query chain edges
|
||||
for {set i 0} {$i < 4} {incr i} {
|
||||
set edges [get_timing_edges -of_objects [get_cells "chain_buf$i"]]
|
||||
puts "chain_buf$i edges: [llength $edges]"
|
||||
}
|
||||
|
||||
# Delete chain from end to beginning (exercises reverse cleanup)
|
||||
for {set i 3} {$i >= 0} {incr i -1} {
|
||||
disconnect_pin "chain_n$i" "chain_buf$i/A"
|
||||
set j [expr {$i + 1}]
|
||||
disconnect_pin "chain_n$j" "chain_buf$i/Z"
|
||||
delete_instance "chain_buf$i"
|
||||
}
|
||||
for {set i 0} {$i <= 4} {incr i} {
|
||||
delete_net "chain_n$i"
|
||||
}
|
||||
|
||||
report_checks
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 3: Multiple fan-out and fan-in scenarios
|
||||
# Exercises: makeWireEdgesFromPin with multi-driver nets
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Test 3: fan-out/fan-in ---"
|
||||
|
||||
set fo_net [make_net "fanout_net"]
|
||||
set fo_drv [make_instance "fo_drv" NangateOpenCellLibrary/BUF_X4]
|
||||
set fo_load1 [make_instance "fo_load1" NangateOpenCellLibrary/BUF_X1]
|
||||
set fo_load2 [make_instance "fo_load2" NangateOpenCellLibrary/BUF_X1]
|
||||
set fo_load3 [make_instance "fo_load3" NangateOpenCellLibrary/BUF_X1]
|
||||
|
||||
set fo_in [make_net "fo_in"]
|
||||
connect_pin fo_in fo_drv/A
|
||||
connect_pin fanout_net fo_drv/Z
|
||||
connect_pin fanout_net fo_load1/A
|
||||
connect_pin fanout_net fo_load2/A
|
||||
connect_pin fanout_net fo_load3/A
|
||||
|
||||
report_checks
|
||||
|
||||
# Query edge count on fanout driver
|
||||
set drv_edges [get_timing_edges -of_objects [get_cells fo_drv]]
|
||||
puts "fo_drv edges: [llength $drv_edges]"
|
||||
|
||||
# Disconnect loads one by one
|
||||
disconnect_pin fanout_net fo_load3/A
|
||||
report_checks
|
||||
|
||||
disconnect_pin fanout_net fo_load2/A
|
||||
report_checks
|
||||
|
||||
# Cleanup
|
||||
disconnect_pin fanout_net fo_load1/A
|
||||
disconnect_pin fanout_net fo_drv/Z
|
||||
disconnect_pin fo_in fo_drv/A
|
||||
delete_instance fo_load1
|
||||
delete_instance fo_load2
|
||||
delete_instance fo_load3
|
||||
delete_instance fo_drv
|
||||
delete_net fanout_net
|
||||
delete_net fo_in
|
||||
|
||||
report_checks
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 4: Replace cell multiple times and verify edge rebuild
|
||||
# Exercises: makeInstanceEdges rebuild, timing arc set changes
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Test 4: cell replacement cycle ---"
|
||||
|
||||
# Replace buf1 through several sizes
|
||||
foreach lib_cell {BUF_X1 BUF_X2 BUF_X4 BUF_X8 BUF_X4 BUF_X2 BUF_X1} {
|
||||
replace_cell buf1 "NangateOpenCellLibrary/$lib_cell"
|
||||
report_checks -path_delay max
|
||||
}
|
||||
|
||||
# Replace AND gate
|
||||
foreach lib_cell {AND2_X1 AND2_X2 AND2_X4 AND2_X2 AND2_X1} {
|
||||
replace_cell and1 "NangateOpenCellLibrary/$lib_cell"
|
||||
report_checks
|
||||
}
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 5: Register add/delete to exercise reg_clk_vertices
|
||||
# Exercises: makeVertex is_reg_clk path, reg_clk_vertices_ insert/erase
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Test 5: register add/delete ---"
|
||||
|
||||
# Add multiple registers
|
||||
for {set i 0} {$i < 3} {incr i} {
|
||||
set rn [make_net "reg_d$i"]
|
||||
set rqn [make_net "reg_q$i"]
|
||||
set ri [make_instance "test_reg$i" NangateOpenCellLibrary/DFF_X1]
|
||||
connect_pin "reg_d$i" "test_reg$i/D"
|
||||
connect_pin "reg_q$i" "test_reg$i/Q"
|
||||
connect_pin clk "test_reg$i/CK"
|
||||
}
|
||||
|
||||
report_checks
|
||||
|
||||
# Delete the registers
|
||||
for {set i 0} {$i < 3} {incr i} {
|
||||
disconnect_pin clk "test_reg$i/CK"
|
||||
disconnect_pin "reg_d$i" "test_reg$i/D"
|
||||
disconnect_pin "reg_q$i" "test_reg$i/Q"
|
||||
delete_instance "test_reg$i"
|
||||
delete_net "reg_d$i"
|
||||
delete_net "reg_q$i"
|
||||
}
|
||||
|
||||
report_checks
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 6: Slew and timing edge reports
|
||||
# Exercises: slew access, edge arc iteration
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Test 6: slew and edge reports ---"
|
||||
|
||||
report_slews [get_ports d1]
|
||||
report_slews [get_ports d2]
|
||||
report_slews [get_ports d3]
|
||||
report_slews [get_ports clk]
|
||||
|
||||
report_slews [get_pins buf1/A]
|
||||
report_slews [get_pins buf1/Z]
|
||||
report_slews [get_pins and1/A1]
|
||||
report_slews [get_pins and1/ZN]
|
||||
report_slews [get_pins inv1/A]
|
||||
report_slews [get_pins inv1/ZN]
|
||||
report_slews [get_pins nand1/ZN]
|
||||
report_slews [get_pins nor1/ZN]
|
||||
|
||||
# Edge reports
|
||||
report_edges -from [get_pins buf1/A] -to [get_pins buf1/Z]
|
||||
report_edges -from [get_pins and1/A1] -to [get_pins and1/ZN]
|
||||
report_edges -from [get_pins inv1/A] -to [get_pins inv1/ZN]
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 7: Through-pin and endpoint queries
|
||||
# Exercises: graph traversal paths
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Test 7: through-pin queries ---"
|
||||
|
||||
report_checks -through [get_pins buf1/Z]
|
||||
report_checks -through [get_pins and1/ZN]
|
||||
report_checks -through [get_pins inv1/ZN]
|
||||
report_checks -through [get_pins nand1/ZN]
|
||||
report_checks -through [get_pins nor1/ZN]
|
||||
report_checks -through [get_pins or1/ZN]
|
||||
|
||||
# Endpoint
|
||||
report_checks -to [get_ports q1]
|
||||
report_checks -to [get_ports q2]
|
||||
report_checks -to [get_ports q3]
|
||||
report_checks -to [get_ports q4]
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,251 @@
|
|||
# Test graph construction, wire/instance edge creation, delay annotation,
|
||||
# slew queries, and edge removal/modification.
|
||||
# Targets:
|
||||
# Graph.cc: makeGraph, makeVertex, makeWireEdge, makeInstEdge,
|
||||
# removeWireEdge, removeInstEdge, arcDelayAnnotated, wireDelayAnnotated,
|
||||
# slew/delay getters for rise/fall combinations, pinVertices,
|
||||
# pinDrvrVertex, pinLoadVertex, vertexCount, edgeCount,
|
||||
# setConstant, clearConstants, regClkVertices, isRegClk,
|
||||
# widthCheckAnnotation, periodCheckAnnotation, setPeriodCheckAnnotation,
|
||||
# hasDownstreamClkPin, minPulseWidthArc
|
||||
|
||||
source ../../test/helpers.tcl
|
||||
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
read_verilog graph_test3.v
|
||||
link_design graph_test3
|
||||
|
||||
create_clock -name clk1 -period 10 [get_ports clk1]
|
||||
create_clock -name clk2 -period 15 [get_ports clk2]
|
||||
set_input_delay -clock clk1 1.0 [get_ports {d1 d2 d3 d4}]
|
||||
set_output_delay -clock clk1 1.0 [get_ports {q1 q3}]
|
||||
set_output_delay -clock clk2 1.0 [get_ports q2]
|
||||
set_input_transition 0.1 [get_ports {d1 d2 d3 d4 rst clk1 clk2}]
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Baseline timing: triggers makeGraph, all vertex/edge construction
|
||||
#---------------------------------------------------------------
|
||||
puts "--- baseline timing ---"
|
||||
report_checks
|
||||
|
||||
report_checks -path_delay min
|
||||
|
||||
report_checks -path_delay max
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Query all timing edges: exercises edge iteration
|
||||
#---------------------------------------------------------------
|
||||
puts "--- timing edges per cell ---"
|
||||
foreach cell_name {buf1 buf2 inv1 inv2 and1 or1 nand1 nor1 and2 or2 reg1 reg2 reg3 buf3 buf4} {
|
||||
set edges [get_timing_edges -of_objects [get_cells $cell_name]]
|
||||
puts "$cell_name edges: [llength $edges]"
|
||||
}
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Specific edge queries: from/to pins
|
||||
# Exercises arc delay access for all transition combinations
|
||||
#---------------------------------------------------------------
|
||||
puts "--- specific edge queries ---"
|
||||
|
||||
# BUF edges (rise/rise, fall/fall)
|
||||
report_edges -from [get_pins buf1/A] -to [get_pins buf1/Z]
|
||||
|
||||
# INV edges (rise/fall, fall/rise)
|
||||
report_edges -from [get_pins inv1/A] -to [get_pins inv1/ZN]
|
||||
|
||||
# NAND edges
|
||||
report_edges -from [get_pins nand1/A1] -to [get_pins nand1/ZN]
|
||||
report_edges -from [get_pins nand1/A2] -to [get_pins nand1/ZN]
|
||||
|
||||
# NOR edges
|
||||
report_edges -from [get_pins nor1/A1] -to [get_pins nor1/ZN]
|
||||
report_edges -from [get_pins nor1/A2] -to [get_pins nor1/ZN]
|
||||
|
||||
# AND2 edges
|
||||
report_edges -from [get_pins and2/A1] -to [get_pins and2/ZN]
|
||||
report_edges -from [get_pins and2/A2] -to [get_pins and2/ZN]
|
||||
|
||||
# OR2 edges
|
||||
report_edges -from [get_pins or2/A1] -to [get_pins or2/ZN]
|
||||
report_edges -from [get_pins or2/A2] -to [get_pins or2/ZN]
|
||||
|
||||
# DFF edges (CK->Q)
|
||||
report_edges -from [get_pins reg1/CK] -to [get_pins reg1/Q]
|
||||
report_edges -from [get_pins reg2/CK] -to [get_pins reg2/Q]
|
||||
report_edges -from [get_pins reg3/CK] -to [get_pins reg3/Q]
|
||||
|
||||
# Wire edges (port to first gate)
|
||||
report_edges -from [get_ports d1]
|
||||
report_edges -from [get_ports d2]
|
||||
report_edges -from [get_ports d3]
|
||||
report_edges -from [get_ports d4]
|
||||
|
||||
# Wire edges to output ports
|
||||
report_edges -to [get_ports q1]
|
||||
report_edges -to [get_ports q2]
|
||||
report_edges -to [get_ports q3]
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Slew queries: exercises slew getters in Graph.cc
|
||||
#---------------------------------------------------------------
|
||||
puts "--- slew queries ---"
|
||||
|
||||
# Input port slews
|
||||
report_slews [get_ports d1]
|
||||
report_slews [get_ports d2]
|
||||
report_slews [get_ports d3]
|
||||
report_slews [get_ports d4]
|
||||
report_slews [get_ports clk1]
|
||||
report_slews [get_ports clk2]
|
||||
|
||||
# Output port slews
|
||||
report_slews [get_ports q1]
|
||||
report_slews [get_ports q2]
|
||||
report_slews [get_ports q3]
|
||||
|
||||
# Internal pin slews
|
||||
report_slews [get_pins buf1/Z]
|
||||
report_slews [get_pins buf2/Z]
|
||||
report_slews [get_pins inv1/ZN]
|
||||
report_slews [get_pins inv2/ZN]
|
||||
report_slews [get_pins and1/ZN]
|
||||
report_slews [get_pins or1/ZN]
|
||||
report_slews [get_pins nand1/ZN]
|
||||
report_slews [get_pins nor1/ZN]
|
||||
report_slews [get_pins and2/ZN]
|
||||
report_slews [get_pins or2/ZN]
|
||||
report_slews [get_pins reg1/Q]
|
||||
report_slews [get_pins reg2/Q]
|
||||
report_slews [get_pins reg3/Q]
|
||||
report_slews [get_pins buf3/Z]
|
||||
report_slews [get_pins buf4/Z]
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Network modification: add/remove instances
|
||||
# Exercises graph incremental update paths
|
||||
#---------------------------------------------------------------
|
||||
puts "--- network modification ---"
|
||||
|
||||
# Add instance and wire
|
||||
set new_buf [make_instance extra_buf NangateOpenCellLibrary/BUF_X1]
|
||||
set new_net [make_net extra_net]
|
||||
set new_net2 [make_net extra_net2]
|
||||
connect_pin extra_net extra_buf/A
|
||||
connect_pin extra_net2 extra_buf/Z
|
||||
|
||||
# Timing after addition (exercises incremental graph update)
|
||||
report_checks
|
||||
|
||||
# Disconnect and remove
|
||||
disconnect_pin extra_net extra_buf/A
|
||||
disconnect_pin extra_net2 extra_buf/Z
|
||||
delete_instance extra_buf
|
||||
delete_net extra_net
|
||||
delete_net extra_net2
|
||||
|
||||
report_checks
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Replace cell and verify edge update
|
||||
#---------------------------------------------------------------
|
||||
puts "--- replace cell ---"
|
||||
|
||||
replace_cell buf1 NangateOpenCellLibrary/BUF_X4
|
||||
report_checks
|
||||
report_edges -from [get_pins buf1/A] -to [get_pins buf1/Z]
|
||||
|
||||
replace_cell buf1 NangateOpenCellLibrary/BUF_X1
|
||||
report_checks
|
||||
|
||||
replace_cell inv1 NangateOpenCellLibrary/INV_X2
|
||||
report_checks
|
||||
|
||||
replace_cell inv1 NangateOpenCellLibrary/INV_X1
|
||||
report_checks
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Disable/enable timing on edges
|
||||
# Exercises graph edge disable traversal
|
||||
#---------------------------------------------------------------
|
||||
puts "--- disable/enable timing ---"
|
||||
|
||||
set_disable_timing [get_cells buf1]
|
||||
report_checks
|
||||
|
||||
set_disable_timing [get_cells inv1]
|
||||
report_checks
|
||||
|
||||
set_disable_timing [get_cells nand1]
|
||||
report_checks
|
||||
|
||||
unset_disable_timing [get_cells buf1]
|
||||
unset_disable_timing [get_cells inv1]
|
||||
unset_disable_timing [get_cells nand1]
|
||||
report_checks
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Case analysis: exercises setConstant, clearConstants
|
||||
#---------------------------------------------------------------
|
||||
puts "--- case analysis ---"
|
||||
|
||||
set_case_analysis 1 [get_ports rst]
|
||||
report_checks
|
||||
|
||||
set_case_analysis 0 [get_ports rst]
|
||||
report_checks
|
||||
|
||||
unset_case_analysis [get_ports rst]
|
||||
report_checks
|
||||
|
||||
set_case_analysis 1 [get_ports d1]
|
||||
report_checks
|
||||
|
||||
set_case_analysis 0 [get_ports d3]
|
||||
report_checks
|
||||
|
||||
unset_case_analysis [get_ports d1]
|
||||
unset_case_analysis [get_ports d3]
|
||||
report_checks
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Load changes trigger delay recomputation on graph edges
|
||||
#---------------------------------------------------------------
|
||||
puts "--- load changes ---"
|
||||
|
||||
set_load 0.01 [get_ports q1]
|
||||
report_checks
|
||||
|
||||
set_load 0.05 [get_ports q2]
|
||||
report_checks
|
||||
|
||||
set_load 0.1 [get_ports q3]
|
||||
report_checks
|
||||
|
||||
set_load 0 [get_ports q1]
|
||||
set_load 0 [get_ports q2]
|
||||
set_load 0 [get_ports q3]
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Through pin paths exercise reconvergent graph traversal
|
||||
#---------------------------------------------------------------
|
||||
puts "--- through pin queries ---"
|
||||
|
||||
report_checks -through [get_pins nand1/ZN]
|
||||
puts "through nand1: done"
|
||||
|
||||
report_checks -through [get_pins nor1/ZN]
|
||||
puts "through nor1: done"
|
||||
|
||||
report_checks -through [get_pins and2/ZN]
|
||||
puts "through and2: done"
|
||||
|
||||
report_checks -through [get_pins or2/ZN]
|
||||
puts "through or2: done"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# report_check_types exercises check edge categorization
|
||||
#---------------------------------------------------------------
|
||||
puts "--- report_check_types ---"
|
||||
report_check_types -max_delay -verbose
|
||||
|
||||
report_check_types -min_delay -verbose
|
||||
|
|
@ -1,6 +1,37 @@
|
|||
sta_module_tests("liberty"
|
||||
TESTS
|
||||
arc_model_deep
|
||||
busport_mem_iter
|
||||
ccsn
|
||||
cell_classify_pgpin
|
||||
cell_deep
|
||||
clkgate_lvlshift
|
||||
ecsm
|
||||
equiv_cells
|
||||
equiv_cross_lib
|
||||
equiv_deep
|
||||
equiv_map_libs
|
||||
func_expr
|
||||
leakage_power_deep
|
||||
multi_corner
|
||||
multi_lib_equiv
|
||||
opcond_scale
|
||||
pgpin_voltage
|
||||
power
|
||||
properties
|
||||
read_asap7
|
||||
read_ihp
|
||||
read_nangate
|
||||
read_sky130
|
||||
scan_signal_types
|
||||
seq_scan_bus
|
||||
sky130_corners
|
||||
timing_models
|
||||
timing_types_deep
|
||||
wireload
|
||||
write_roundtrip
|
||||
writer
|
||||
writer_roundtrip
|
||||
)
|
||||
|
||||
add_subdirectory(cpp)
|
||||
|
|
|
|||
|
|
@ -1,16 +1,32 @@
|
|||
add_executable(TestLibertyClasses TestLibertyClasses.cc)
|
||||
target_link_libraries(TestLibertyClasses
|
||||
OpenSTA
|
||||
GTest::gtest
|
||||
GTest::gtest_main
|
||||
${TCL_LIBRARY}
|
||||
)
|
||||
target_include_directories(TestLibertyClasses PRIVATE
|
||||
${STA_HOME}/include/sta
|
||||
${STA_HOME}
|
||||
${CMAKE_BINARY_DIR}/include/sta
|
||||
)
|
||||
gtest_discover_tests(TestLibertyClasses
|
||||
WORKING_DIRECTORY ${STA_HOME}
|
||||
PROPERTIES LABELS "cpp\;module_liberty"
|
||||
macro(sta_cpp_test name)
|
||||
add_executable(${name} ${name}.cc)
|
||||
target_link_libraries(${name}
|
||||
OpenSTA
|
||||
GTest::gtest
|
||||
GTest::gtest_main
|
||||
${TCL_LIBRARY}
|
||||
)
|
||||
target_include_directories(${name} PRIVATE
|
||||
${STA_HOME}/include/sta
|
||||
${STA_HOME}
|
||||
${CMAKE_BINARY_DIR}/include/sta
|
||||
)
|
||||
gtest_discover_tests(${name}
|
||||
WORKING_DIRECTORY ${STA_HOME}
|
||||
PROPERTIES LABELS "cpp\;module_liberty"
|
||||
)
|
||||
endmacro()
|
||||
|
||||
sta_cpp_test(TestLibertyClasses)
|
||||
sta_cpp_test(TestLibertyStaBasics)
|
||||
sta_cpp_test(TestLibertyStaBasicsB)
|
||||
sta_cpp_test(TestLibertyStaCallbacks)
|
||||
|
||||
# Compatibility aggregate target for legacy scripts that still build TestLiberty.
|
||||
add_custom_target(TestLiberty
|
||||
DEPENDS
|
||||
TestLibertyClasses
|
||||
TestLibertyStaBasics
|
||||
TestLibertyStaBasicsB
|
||||
TestLibertyStaCallbacks
|
||||
)
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,89 @@
|
|||
INV_X1 is_leaf = 1
|
||||
INV_X1 is_buffer = 0
|
||||
INV_X1 is_inverter = 1
|
||||
BUF_X1 is_leaf = 1
|
||||
BUF_X1 is_buffer = 1
|
||||
BUF_X1 is_inverter = 0
|
||||
NAND2_X1 is_leaf = 1
|
||||
NAND2_X1 is_buffer = 0
|
||||
NAND2_X1 is_inverter = 0
|
||||
DFF_X1 is_leaf = 1
|
||||
DFF_X1 is_buffer = 0
|
||||
DFF_X1 is_inverter = 0
|
||||
INV_X1 lib name = NangateOpenCellLibrary
|
||||
SDFF_X1 has test_cell
|
||||
INV_X1/A function =
|
||||
INV_X1/ZN function = !A
|
||||
TINV_X1/EN function =
|
||||
TINV_X1/ZN tristate_enable = !EN
|
||||
INV_X1/A bus_name = A
|
||||
INV_X1/A is_bus = 0
|
||||
INV_X1/A is_bus_bit = 0
|
||||
INV_X1/A is_bundle = 0
|
||||
INV_X1/A is_bundle_member = 0
|
||||
INV_X1/A has_members = 0
|
||||
INV_X1/A is_pwr_gnd = 0
|
||||
INV_X1/A scan_signal_type = none
|
||||
SDFF_X1/SI scan_signal_type = none
|
||||
SDFF_X1/SI is_bus = 0
|
||||
INV_X1 all ports = 4
|
||||
NAND2_X1 A* ports = 2
|
||||
NAND2_X1 regexp ports = 2
|
||||
NAND2_X1 nocase zn ports = 0
|
||||
INV_X1 ports via iterator = 4
|
||||
AOI21_X1 ports via iterator = 6
|
||||
Arc: INV_X1 A -> ZN role=combinational is_check=0
|
||||
sdf_cond=
|
||||
DFF Arc: DFF_X1 CK -> D role=hold is_check=1
|
||||
DFF Arc: DFF_X1 CK -> D role=setup is_check=1
|
||||
DFF Arc: DFF_X1 CK -> CK role=width is_check=1
|
||||
DFF Arc: DFF_X1 CK -> Q role=Reg Clk to Q is_check=0
|
||||
DFF Arc: DFF_X1 CK -> QN role=Reg Clk to Q is_check=0
|
||||
DFFR Arc: DFFR_X1 CK -> D role=hold is_check=1
|
||||
DFFR Arc: DFFR_X1 CK -> D role=setup is_check=1
|
||||
DFFR Arc: DFFR_X1 CK -> RN role=recovery is_check=1
|
||||
DFFR Arc: DFFR_X1 CK -> RN role=removal is_check=1
|
||||
DFFR Arc: DFFR_X1 RN -> RN role=width is_check=1
|
||||
DFFR Arc: DFFR_X1 CK -> CK role=width is_check=1
|
||||
DFFR Arc: DFFR_X1 CK -> Q role=Reg Clk to Q is_check=0
|
||||
DFFR Arc: DFFR_X1 RN -> Q role=Reg Set/Clr is_check=0
|
||||
DFFR Arc: DFFR_X1 RN -> Q role=Reg Set/Clr is_check=0
|
||||
DFFR Arc: DFFR_X1 RN -> Q role=Reg Set/Clr is_check=0
|
||||
DFFR Arc: DFFR_X1 RN -> Q role=Reg Set/Clr is_check=0
|
||||
DFFR Arc: DFFR_X1 CK -> QN role=Reg Clk to Q is_check=0
|
||||
DFFR Arc: DFFR_X1 RN -> QN role=Reg Set/Clr is_check=0
|
||||
DFFR Arc: DFFR_X1 RN -> QN role=Reg Set/Clr is_check=0
|
||||
DFFR Arc: DFFR_X1 RN -> QN role=Reg Set/Clr is_check=0
|
||||
DFFR Arc: DFFR_X1 RN -> QN role=Reg Set/Clr is_check=0
|
||||
Arc detail: A rise -> ZN fall role=combinational
|
||||
Arc detail: A fall -> ZN rise role=combinational
|
||||
DFF arc: rise -> rise role=hold
|
||||
DFF arc: rise -> fall role=hold
|
||||
DFF arc: rise -> rise role=setup
|
||||
DFF arc: rise -> fall role=setup
|
||||
DFF arc: rise -> fall role=width
|
||||
DFF arc: fall -> rise role=width
|
||||
DFF arc: rise -> rise role=Reg Clk to Q
|
||||
DFF arc: rise -> fall role=Reg Clk to Q
|
||||
DFF arc: rise -> rise role=Reg Clk to Q
|
||||
DFF arc: rise -> fall role=Reg Clk to Q
|
||||
Default opcond process = 1.0
|
||||
Default opcond voltage = 1.100000023841858
|
||||
Default opcond temperature = 25.0
|
||||
Typical opcond process = 1.0
|
||||
Typical opcond voltage = 1.100000023841858
|
||||
Typical opcond temperature = 25.0
|
||||
Found wireload 5K_hvratio_1_1
|
||||
Found wireload selection
|
||||
Library: NangateOpenCellLibrary
|
||||
INV_X1/A cap max = 1.700229965024007e-15
|
||||
INV_X1/A cap min = 1.5493600563490969e-15
|
||||
PwrGnd port: VDD dir=power
|
||||
PwrGnd port: VSS dir=ground
|
||||
FA_X1 port: VDD dir=power is_bus=0
|
||||
FA_X1 port: VSS dir=ground is_bus=0
|
||||
FA_X1 port: A dir=input is_bus=0
|
||||
FA_X1 port: B dir=input is_bus=0
|
||||
FA_X1 port: CI dir=input is_bus=0
|
||||
FA_X1 port: CO dir=output is_bus=0
|
||||
FA_X1 port: S dir=output is_bus=0
|
||||
|
|
@ -0,0 +1,294 @@
|
|||
# Deep timing arc and model queries exercising uncovered code paths.
|
||||
# Targets:
|
||||
# TimingArc.cc: TimingArcSet full_name, sdf_cond, role, from, to,
|
||||
# timing_arcs iterator, from_edge_name, to_edge_name,
|
||||
# TimingArc from/to/fromEdge/toEdge/role,
|
||||
# timing_role_is_check
|
||||
# TableModel.cc: table model axis queries, value queries
|
||||
# Liberty.cc: findLibertyCell, findLibertyPort, timingArcSets iterator,
|
||||
# find_liberty_cells_matching regexp/nocase,
|
||||
# find_liberty_ports_matching, cell is_leaf/is_buffer/is_inverter,
|
||||
# liberty_library/test_cell/cell methods, port is_bus/is_bus_bit/
|
||||
# is_bundle/is_bundle_member/has_members/is_pwr_gnd/bus_name/
|
||||
# function/tristate_enable/scan_signal_type/set_direction,
|
||||
# LibertyPortMemberIterator, LibertyCellPortIterator
|
||||
# LibertyBuilder.cc: various cell build paths
|
||||
source ../../test/helpers.tcl
|
||||
|
||||
############################################################
|
||||
# Read library
|
||||
############################################################
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
|
||||
############################################################
|
||||
# find_liberty_cells_matching with pattern/regexp/nocase
|
||||
############################################################
|
||||
set lib [lindex [get_libs NangateOpenCellLibrary] 0]
|
||||
|
||||
# Glob pattern matching
|
||||
set cells [$lib find_liberty_cells_matching "INV_*" 0 0]
|
||||
|
||||
# Regexp matching
|
||||
set cells_re [$lib find_liberty_cells_matching {^BUF_X[0-9]+$} 1 0]
|
||||
|
||||
# Case-insensitive matching
|
||||
set cells_nc [$lib find_liberty_cells_matching "nand2_*" 0 1]
|
||||
|
||||
############################################################
|
||||
# Cell property queries: is_leaf, is_buffer, is_inverter
|
||||
############################################################
|
||||
set inv_cell [get_lib_cell NangateOpenCellLibrary/INV_X1]
|
||||
puts "INV_X1 is_leaf = [$inv_cell is_leaf]"
|
||||
puts "INV_X1 is_buffer = [$inv_cell is_buffer]"
|
||||
puts "INV_X1 is_inverter = [$inv_cell is_inverter]"
|
||||
|
||||
set buf_cell [get_lib_cell NangateOpenCellLibrary/BUF_X1]
|
||||
puts "BUF_X1 is_leaf = [$buf_cell is_leaf]"
|
||||
puts "BUF_X1 is_buffer = [$buf_cell is_buffer]"
|
||||
puts "BUF_X1 is_inverter = [$buf_cell is_inverter]"
|
||||
|
||||
set nand_cell [get_lib_cell NangateOpenCellLibrary/NAND2_X1]
|
||||
puts "NAND2_X1 is_leaf = [$nand_cell is_leaf]"
|
||||
puts "NAND2_X1 is_buffer = [$nand_cell is_buffer]"
|
||||
puts "NAND2_X1 is_inverter = [$nand_cell is_inverter]"
|
||||
|
||||
set dff_cell [get_lib_cell NangateOpenCellLibrary/DFF_X1]
|
||||
puts "DFF_X1 is_leaf = [$dff_cell is_leaf]"
|
||||
puts "DFF_X1 is_buffer = [$dff_cell is_buffer]"
|
||||
puts "DFF_X1 is_inverter = [$dff_cell is_inverter]"
|
||||
|
||||
############################################################
|
||||
# Cell liberty_library method
|
||||
############################################################
|
||||
set cell_lib [$inv_cell liberty_library]
|
||||
puts "INV_X1 lib name = [$cell_lib name]"
|
||||
|
||||
############################################################
|
||||
# Cell test_cell (for scan cells)
|
||||
############################################################
|
||||
set sdff_cell [get_lib_cell NangateOpenCellLibrary/SDFF_X1]
|
||||
set test_cell [$sdff_cell test_cell]
|
||||
if {$test_cell ne ""} {
|
||||
puts "SDFF_X1 has test_cell"
|
||||
} else {
|
||||
puts "SDFF_X1 test_cell is null"
|
||||
}
|
||||
|
||||
############################################################
|
||||
# Port queries: bus_name, function, tristate_enable, scan_signal_type
|
||||
############################################################
|
||||
|
||||
# Function queries
|
||||
set inv_a [$inv_cell find_liberty_port A]
|
||||
set inv_zn [$inv_cell find_liberty_port ZN]
|
||||
puts "INV_X1/A function = [$inv_a function]"
|
||||
puts "INV_X1/ZN function = [$inv_zn function]"
|
||||
|
||||
# Tristate enable
|
||||
set tinv_cell [get_lib_cell NangateOpenCellLibrary/TINV_X1]
|
||||
set tinv_en [$tinv_cell find_liberty_port EN]
|
||||
set tinv_out [$tinv_cell find_liberty_port ZN]
|
||||
puts "TINV_X1/EN function = [$tinv_en function]"
|
||||
puts "TINV_X1/ZN tristate_enable = [$tinv_out tristate_enable]"
|
||||
|
||||
# Bus name (for bus ports - may be same as name for non-bus)
|
||||
puts "INV_X1/A bus_name = [$inv_a bus_name]"
|
||||
|
||||
# Is bus/bundle queries
|
||||
puts "INV_X1/A is_bus = [$inv_a is_bus]"
|
||||
puts "INV_X1/A is_bus_bit = [$inv_a is_bus_bit]"
|
||||
puts "INV_X1/A is_bundle = [$inv_a is_bundle]"
|
||||
puts "INV_X1/A is_bundle_member = [$inv_a is_bundle_member]"
|
||||
puts "INV_X1/A has_members = [$inv_a has_members]"
|
||||
|
||||
# is_pwr_gnd
|
||||
puts "INV_X1/A is_pwr_gnd = [$inv_a is_pwr_gnd]"
|
||||
|
||||
# scan_signal_type
|
||||
puts "INV_X1/A scan_signal_type = [$inv_a scan_signal_type]"
|
||||
|
||||
# Check SDFF scan port
|
||||
set sdff_cell [get_lib_cell NangateOpenCellLibrary/SDFF_X1]
|
||||
set sdff_si [$sdff_cell find_liberty_port SI]
|
||||
if {$sdff_si ne ""} {
|
||||
puts "SDFF_X1/SI scan_signal_type = [$sdff_si scan_signal_type]"
|
||||
puts "SDFF_X1/SI is_bus = [$sdff_si is_bus]"
|
||||
}
|
||||
|
||||
############################################################
|
||||
# find_liberty_ports_matching on a cell
|
||||
############################################################
|
||||
set ports [$inv_cell find_liberty_ports_matching "*" 0 0]
|
||||
puts "INV_X1 all ports = [llength $ports]"
|
||||
|
||||
set ports [$nand_cell find_liberty_ports_matching "A*" 0 0]
|
||||
puts "NAND2_X1 A* ports = [llength $ports]"
|
||||
|
||||
# Regexp port matching
|
||||
set ports_re [$nand_cell find_liberty_ports_matching {^A[0-9]$} 1 0]
|
||||
puts "NAND2_X1 regexp ports = [llength $ports_re]"
|
||||
|
||||
# Case-insensitive port matching
|
||||
set ports_nc [$nand_cell find_liberty_ports_matching "zn" 0 1]
|
||||
puts "NAND2_X1 nocase zn ports = [llength $ports_nc]"
|
||||
|
||||
############################################################
|
||||
# LibertyCellPortIterator
|
||||
############################################################
|
||||
set port_iter [$inv_cell liberty_port_iterator]
|
||||
set port_count 0
|
||||
while {[$port_iter has_next]} {
|
||||
set port [$port_iter next]
|
||||
incr port_count
|
||||
}
|
||||
$port_iter finish
|
||||
puts "INV_X1 ports via iterator = $port_count"
|
||||
|
||||
# Port iterator on a more complex cell
|
||||
set aoi_cell [get_lib_cell NangateOpenCellLibrary/AOI21_X1]
|
||||
set port_iter [$aoi_cell liberty_port_iterator]
|
||||
set port_count 0
|
||||
while {[$port_iter has_next]} {
|
||||
set port [$port_iter next]
|
||||
set dir [sta::liberty_port_direction $port]
|
||||
incr port_count
|
||||
}
|
||||
$port_iter finish
|
||||
puts "AOI21_X1 ports via iterator = $port_count"
|
||||
|
||||
############################################################
|
||||
# Timing arc set queries: full_name, sdf_cond, role
|
||||
############################################################
|
||||
set arc_sets [$inv_cell timing_arc_sets]
|
||||
foreach arc_set $arc_sets {
|
||||
set fn [$arc_set full_name]
|
||||
set from_port [$arc_set from]
|
||||
set to_port [$arc_set to]
|
||||
set role [$arc_set role]
|
||||
set is_check [sta::timing_role_is_check $role]
|
||||
puts "Arc: $fn role=$role is_check=$is_check"
|
||||
set sdf [$arc_set sdf_cond]
|
||||
puts " sdf_cond=$sdf"
|
||||
}
|
||||
|
||||
# DFF timing arcs (setup/hold/clk-to-q)
|
||||
set arc_sets [$dff_cell timing_arc_sets]
|
||||
foreach arc_set $arc_sets {
|
||||
set fn [$arc_set full_name]
|
||||
set role [$arc_set role]
|
||||
set is_check [sta::timing_role_is_check $role]
|
||||
puts "DFF Arc: $fn role=$role is_check=$is_check"
|
||||
}
|
||||
|
||||
# DFFR has more arcs (recovery/removal)
|
||||
set dffr_cell [get_lib_cell NangateOpenCellLibrary/DFFR_X1]
|
||||
set arc_sets [$dffr_cell timing_arc_sets]
|
||||
foreach arc_set $arc_sets {
|
||||
set fn [$arc_set full_name]
|
||||
set role [$arc_set role]
|
||||
set is_check [sta::timing_role_is_check $role]
|
||||
puts "DFFR Arc: $fn role=$role is_check=$is_check"
|
||||
}
|
||||
|
||||
############################################################
|
||||
# TimingArc details: from_edge_name, to_edge_name
|
||||
############################################################
|
||||
set arc_sets [$inv_cell timing_arc_sets]
|
||||
foreach arc_set $arc_sets {
|
||||
set arcs [$arc_set timing_arcs]
|
||||
foreach arc $arcs {
|
||||
set from_name [[$arc from] bus_name]
|
||||
set to_name [[$arc to] bus_name]
|
||||
set from_edge [$arc from_edge_name]
|
||||
set to_edge [$arc to_edge_name]
|
||||
set arc_role [$arc role]
|
||||
puts " Arc detail: ${from_name} ${from_edge} -> ${to_name} ${to_edge} role=$arc_role"
|
||||
}
|
||||
}
|
||||
|
||||
# DFF arc details (different roles: setup, hold, clk-to-q)
|
||||
set arc_sets [$dff_cell timing_arc_sets]
|
||||
foreach arc_set $arc_sets {
|
||||
set arcs [$arc_set timing_arcs]
|
||||
foreach arc $arcs {
|
||||
set from_edge [$arc from_edge_name]
|
||||
set to_edge [$arc to_edge_name]
|
||||
set arc_role [$arc role]
|
||||
puts " DFF arc: ${from_edge} -> ${to_edge} role=$arc_role"
|
||||
}
|
||||
}
|
||||
|
||||
############################################################
|
||||
# Operating conditions queries
|
||||
############################################################
|
||||
set op_cond [$lib default_operating_conditions]
|
||||
if {$op_cond ne ""} {
|
||||
puts "Default opcond process = [$op_cond process]"
|
||||
puts "Default opcond voltage = [$op_cond voltage]"
|
||||
puts "Default opcond temperature = [$op_cond temperature]"
|
||||
}
|
||||
|
||||
# Named operating conditions
|
||||
set typical_cond [$lib find_operating_conditions typical]
|
||||
if {$typical_cond ne ""} {
|
||||
puts "Typical opcond process = [$typical_cond process]"
|
||||
puts "Typical opcond voltage = [$typical_cond voltage]"
|
||||
puts "Typical opcond temperature = [$typical_cond temperature]"
|
||||
}
|
||||
|
||||
############################################################
|
||||
# Wireload queries
|
||||
############################################################
|
||||
set wl [$lib find_wireload "5K_hvratio_1_1"]
|
||||
if {$wl ne ""} {
|
||||
puts "Found wireload 5K_hvratio_1_1"
|
||||
}
|
||||
|
||||
set wlsel [$lib find_wireload_selection "WiresloaSelection"]
|
||||
if {$wlsel ne ""} {
|
||||
puts "Found wireload selection"
|
||||
}
|
||||
|
||||
############################################################
|
||||
# LibertyLibraryIterator
|
||||
############################################################
|
||||
set lib_iter [sta::liberty_library_iterator]
|
||||
set lib_count 0
|
||||
while {[$lib_iter has_next]} {
|
||||
set lib [$lib_iter next]
|
||||
puts "Library: [$lib name]"
|
||||
incr lib_count
|
||||
}
|
||||
$lib_iter finish
|
||||
|
||||
############################################################
|
||||
# Port capacitance with corner/min_max
|
||||
############################################################
|
||||
set corner [lindex [sta::scenes] 0]
|
||||
set inv_a_port [$inv_cell find_liberty_port A]
|
||||
set cap_max [$inv_a_port capacitance $corner "max"]
|
||||
puts "INV_X1/A cap max = $cap_max"
|
||||
set cap_min [$inv_a_port capacitance $corner "min"]
|
||||
puts "INV_X1/A cap min = $cap_min"
|
||||
|
||||
############################################################
|
||||
# Power ground port queries
|
||||
############################################################
|
||||
set port_iter [$inv_cell liberty_port_iterator]
|
||||
while {[$port_iter has_next]} {
|
||||
set port [$port_iter next]
|
||||
if {[$port is_pwr_gnd]} {
|
||||
puts " PwrGnd port: [$port bus_name] dir=[sta::liberty_port_direction $port]"
|
||||
}
|
||||
}
|
||||
$port_iter finish
|
||||
|
||||
# Check a cell with bus ports (FA_X1 has bus-like ports)
|
||||
set fa_cell [get_lib_cell NangateOpenCellLibrary/FA_X1]
|
||||
set port_iter [$fa_cell liberty_port_iterator]
|
||||
while {[$port_iter has_next]} {
|
||||
set port [$port_iter next]
|
||||
set dir [sta::liberty_port_direction $port]
|
||||
puts " FA_X1 port: [$port bus_name] dir=$dir is_bus=[$port is_bus]"
|
||||
}
|
||||
$port_iter finish
|
||||
|
|
@ -0,0 +1,104 @@
|
|||
fakeram cell found
|
||||
clk dir=input bus=0 bit=0 bundle=0 bm=0 members=0 func="" tri=""
|
||||
rd_out dir=output bus=1 bit=0 bundle=0 bm=0 members=1 func="" tri=""
|
||||
member[0]: rd_out[6] dir=output bit=1
|
||||
member[1]: rd_out[5] dir=output bit=1
|
||||
member[2]: rd_out[4] dir=output bit=1
|
||||
total members=7
|
||||
we_in dir=input bus=0 bit=0 bundle=0 bm=0 members=0 func="" tri=""
|
||||
ce_in dir=input bus=0 bit=0 bundle=0 bm=0 members=0 func="" tri=""
|
||||
addr_in dir=input bus=1 bit=0 bundle=0 bm=0 members=1 func="" tri=""
|
||||
member[0]: addr_in[5] dir=input bit=1
|
||||
member[1]: addr_in[4] dir=input bit=1
|
||||
member[2]: addr_in[3] dir=input bit=1
|
||||
total members=6
|
||||
wd_in dir=input bus=1 bit=0 bundle=0 bm=0 members=1 func="" tri=""
|
||||
member[0]: wd_in[6] dir=input bit=1
|
||||
member[1]: wd_in[5] dir=input bit=1
|
||||
member[2]: wd_in[4] dir=input bit=1
|
||||
total members=7
|
||||
w_mask_in dir=input bus=1 bit=0 bundle=0 bm=0 members=1 func="" tri=""
|
||||
member[0]: w_mask_in[6] dir=input bit=1
|
||||
member[1]: w_mask_in[5] dir=input bit=1
|
||||
member[2]: w_mask_in[4] dir=input bit=1
|
||||
total members=7
|
||||
fakeram45_64x32: bus_ports=4 total_bits=102
|
||||
fakeram45_256x16: bus_ports=4 total_bits=56
|
||||
fakeram45_512x64: bus_ports=4 total_bits=201
|
||||
fakeram45_1024x32: bus_ports=4 total_bits=106
|
||||
fakeram45_64x96: bus_ports=4 total_bits=294
|
||||
Warning 353: liberty_busport_mem_iter.tcl line 1, library 'gf180mcu_fd_ip_sram__sram256x8m8wm1' not found.
|
||||
gf180mcu cells: 0
|
||||
INV_X1 leaf=1 buf=0 inv=1 area=0.532000 du=0 arcs=1
|
||||
INV_X2 leaf=1 buf=0 inv=1 area=0.798000 du=0 arcs=1
|
||||
BUF_X1 leaf=1 buf=1 inv=0 area=0.798000 du=0 arcs=1
|
||||
BUF_X2 leaf=1 buf=1 inv=0 area=1.064000 du=0 arcs=1
|
||||
CLKBUF_X1 leaf=1 buf=1 inv=0 area=0.798000 du=0 arcs=1
|
||||
NAND2_X1 leaf=1 buf=0 inv=0 area=0.798000 du=0 arcs=2
|
||||
NOR2_X1 leaf=1 buf=0 inv=0 area=0.798000 du=0 arcs=2
|
||||
AND2_X1 leaf=1 buf=0 inv=0 area=1.064000 du=0 arcs=2
|
||||
OR2_X1 leaf=1 buf=0 inv=0 area=1.064000 du=0 arcs=2
|
||||
XOR2_X1 leaf=1 buf=0 inv=0 area=1.596000 du=0 arcs=4
|
||||
MUX2_X1 leaf=1 buf=0 inv=0 area=1.862000 du=0 arcs=6
|
||||
AOI21_X1 leaf=1 buf=0 inv=0 area=1.064000 du=0 arcs=5
|
||||
OAI21_X1 leaf=1 buf=0 inv=0 area=1.064000 du=0 arcs=5
|
||||
AOI22_X1 leaf=1 buf=0 inv=0 area=1.330000 du=0 arcs=12
|
||||
OAI22_X1 leaf=1 buf=0 inv=0 area=1.330000 du=0 arcs=12
|
||||
DFF_X1 leaf=1 buf=0 inv=0 area=4.522000 du=0 arcs=5
|
||||
DFF_X2 leaf=1 buf=0 inv=0 area=5.054000 du=0 arcs=5
|
||||
DFFR_X1 leaf=1 buf=0 inv=0 area=5.320000 du=0 arcs=16
|
||||
DFFS_X1 leaf=1 buf=0 inv=0 area=5.320000 du=0 arcs=16
|
||||
DFFRS_X1 leaf=1 buf=0 inv=0 area=6.384000 du=0 arcs=35
|
||||
SDFF_X1 leaf=1 buf=0 inv=0 area=6.118000 du=0 arcs=9
|
||||
SDFFR_X1 leaf=1 buf=0 inv=0 area=6.650000 du=0 arcs=44
|
||||
SDFFRS_X1 leaf=1 buf=0 inv=0 area=7.714000 du=0 arcs=111
|
||||
TLAT_X1 leaf=1 buf=0 inv=0 area=3.458000 du=0 arcs=7
|
||||
TINV_X1 leaf=1 buf=0 inv=0 area=1.064000 du=0 arcs=3
|
||||
CLKGATETST_X1 leaf=1 buf=0 inv=0 area=3.990000 du=0 arcs=9
|
||||
HA_X1 leaf=1 buf=0 inv=0 area=2.660000 du=0 arcs=6
|
||||
FA_X1 leaf=1 buf=0 inv=0 area=4.256000 du=0 arcs=18
|
||||
ANTENNA_X1 leaf=1 buf=0 inv=0 area=0.266000 du=1 arcs=0
|
||||
FILLCELL_X1 leaf=1 buf=0 inv=0 area=0.266000 du=1 arcs=0
|
||||
FILLCELL_X2 leaf=1 buf=0 inv=0 area=0.266000 du=1 arcs=0
|
||||
LOGIC0_X1 leaf=1 buf=0 inv=0 area=0.532000 du=1 arcs=0
|
||||
LOGIC1_X1 leaf=1 buf=0 inv=0 area=0.532000 du=1 arcs=0
|
||||
--- test_cell / scan queries ---
|
||||
SDFF_X1 test_cell is null
|
||||
SDFFR_X1 test_cell is null
|
||||
SDFFRS_X1 test_cell is null
|
||||
DFF_X1 has no test_cell (expected)
|
||||
--- function and tristate queries ---
|
||||
TINV_X1/VDD dir=power func="" tri=""
|
||||
TINV_X1/VSS dir=ground func="" tri=""
|
||||
TINV_X1/EN dir=input func="" tri=""
|
||||
TINV_X1/I dir=input func="" tri=""
|
||||
TINV_X1/ZN dir=tristate func="!I" tri="!EN"
|
||||
CLKGATETST_X1/VDD dir=power func=""
|
||||
CLKGATETST_X1/VSS dir=ground func=""
|
||||
CLKGATETST_X1/IQ dir=internal func=""
|
||||
CLKGATETST_X1/CK dir=input func=""
|
||||
CLKGATETST_X1/E dir=input func=""
|
||||
CLKGATETST_X1/SE dir=input func=""
|
||||
CLKGATETST_X1/GCK dir=output func=""
|
||||
INV_X1/ZN func=!A
|
||||
BUF_X1/Z func=A
|
||||
NAND2_X1/ZN func=!(A1*A2)
|
||||
NOR2_X1/ZN func=!(A1+A2)
|
||||
AND2_X1/ZN func=A1*A2
|
||||
OR2_X1/ZN func=A1+A2
|
||||
XOR2_X1/Z func=A^B
|
||||
XNOR2_X1/ZN func=!(A^B)
|
||||
AOI21_X1/ZN func=!(A+(B1*B2))
|
||||
OAI21_X1/ZN func=!(A*(B1+B2))
|
||||
MUX2_X1/Z func=(S*B)+(A*!S)
|
||||
HA_X1/CO func=A*B
|
||||
HA_X1/S func=A^B
|
||||
FA_X1/CO func=(A*B)+(CI*(A+B))
|
||||
FA_X1/S func=CI^(A^B)
|
||||
sky130_fd_sc_hd__ebufn_1/A dir=input func="" tri=""
|
||||
sky130_fd_sc_hd__ebufn_1/TE_B dir=input func="" tri=""
|
||||
sky130_fd_sc_hd__ebufn_1/Z dir=tristate func="A" tri="!TE_B"
|
||||
sky130_fd_sc_hd__ebufn_2/A dir=input func="" tri=""
|
||||
sky130_fd_sc_hd__ebufn_2/TE_B dir=input func="" tri=""
|
||||
sky130_fd_sc_hd__ebufn_2/Z dir=tristate func="A" tri="!TE_B"
|
||||
Warning 1171: ../../test/nangate45/fake_macros.lib line 32, default_max_transition is 0.0.
|
||||
|
|
@ -0,0 +1,246 @@
|
|||
# Test bus port member iteration, bundle ports, port functions,
|
||||
# tristate enable, sequential queries, and diverse cell classification.
|
||||
source ../../test/helpers.tcl
|
||||
suppress_msg 1140
|
||||
|
||||
############################################################
|
||||
# Read SRAM macro library (has bus ports)
|
||||
############################################################
|
||||
read_liberty ../../test/nangate45/fakeram45_64x7.lib
|
||||
|
||||
# Query bus port properties
|
||||
set cell [get_lib_cell fakeram45_64x7/fakeram45_64x7]
|
||||
puts "fakeram cell found"
|
||||
|
||||
set port_iter [$cell liberty_port_iterator]
|
||||
while {[$port_iter has_next]} {
|
||||
set port [$port_iter next]
|
||||
set name [get_name $port]
|
||||
set dir [sta::liberty_port_direction $port]
|
||||
set is_bus [$port is_bus]
|
||||
set is_bit [$port is_bus_bit]
|
||||
set is_bundle [$port is_bundle]
|
||||
set is_bm [$port is_bundle_member]
|
||||
set has_mem [$port has_members]
|
||||
set func [$port function]
|
||||
set tri [$port tristate_enable]
|
||||
puts " $name dir=$dir bus=$is_bus bit=$is_bit bundle=$is_bundle bm=$is_bm members=$has_mem func=\"$func\" tri=\"$tri\""
|
||||
if {$has_mem} {
|
||||
set mem_iter [$port member_iterator]
|
||||
set count 0
|
||||
while {[$mem_iter has_next]} {
|
||||
set mem [$mem_iter next]
|
||||
set mname [get_name $mem]
|
||||
set mdir [sta::liberty_port_direction $mem]
|
||||
set m_is_bit [$mem is_bus_bit]
|
||||
if {$count < 3} {
|
||||
puts " member[$count]: $mname dir=$mdir bit=$m_is_bit"
|
||||
}
|
||||
incr count
|
||||
}
|
||||
$mem_iter finish
|
||||
puts " total members=$count"
|
||||
}
|
||||
}
|
||||
$port_iter finish
|
||||
|
||||
############################################################
|
||||
# Read other SRAM macros with different bus widths
|
||||
############################################################
|
||||
foreach lib_name {fakeram45_64x32 fakeram45_256x16 fakeram45_512x64
|
||||
fakeram45_1024x32 fakeram45_64x96} {
|
||||
read_liberty ../../test/nangate45/${lib_name}.lib
|
||||
set cell [get_lib_cell ${lib_name}/${lib_name}]
|
||||
if {$cell != "NULL" && $cell ne ""} {
|
||||
set port_iter [$cell liberty_port_iterator]
|
||||
set bus_count 0
|
||||
set bit_count 0
|
||||
while {[$port_iter has_next]} {
|
||||
set port [$port_iter next]
|
||||
if {[$port is_bus]} {
|
||||
incr bus_count
|
||||
set mem_iter [$port member_iterator]
|
||||
while {[$mem_iter has_next]} {
|
||||
set mem [$mem_iter next]
|
||||
incr bit_count
|
||||
}
|
||||
$mem_iter finish
|
||||
}
|
||||
}
|
||||
$port_iter finish
|
||||
puts "$lib_name: bus_ports=$bus_count total_bits=$bit_count"
|
||||
}
|
||||
}
|
||||
|
||||
############################################################
|
||||
# Read SRAM macro from GF180MCU
|
||||
############################################################
|
||||
read_liberty ../../test/gf180mcu_sram.lib.gz
|
||||
|
||||
set gf_cells [get_lib_cells gf180mcu_fd_ip_sram__sram256x8m8wm1/*]
|
||||
puts "gf180mcu cells: [llength $gf_cells]"
|
||||
foreach cell_obj $gf_cells {
|
||||
set cname [get_full_name $cell_obj]
|
||||
set cell [get_lib_cell $cname]
|
||||
set port_iter [$cell liberty_port_iterator]
|
||||
set bus_count 0
|
||||
while {[$port_iter has_next]} {
|
||||
set port [$port_iter next]
|
||||
if {[$port is_bus] || [$port has_members]} {
|
||||
incr bus_count
|
||||
}
|
||||
$port_iter finish
|
||||
puts " [get_name $cell_obj]: bus_ports=$bus_count"
|
||||
}
|
||||
}
|
||||
|
||||
############################################################
|
||||
# Read Nangate for cell classification queries
|
||||
############################################################
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
|
||||
# Cell classification
|
||||
foreach cell_name {INV_X1 INV_X2 BUF_X1 BUF_X2 CLKBUF_X1
|
||||
NAND2_X1 NOR2_X1 AND2_X1 OR2_X1 XOR2_X1
|
||||
MUX2_X1 AOI21_X1 OAI21_X1 AOI22_X1 OAI22_X1
|
||||
DFF_X1 DFF_X2 DFFR_X1 DFFS_X1 DFFRS_X1
|
||||
SDFF_X1 SDFFR_X1 SDFFRS_X1 TLAT_X1
|
||||
TINV_X1 CLKGATETST_X1 HA_X1 FA_X1
|
||||
ANTENNA_X1 FILLCELL_X1 FILLCELL_X2 LOGIC0_X1 LOGIC1_X1} {
|
||||
set cell [get_lib_cell NangateOpenCellLibrary/$cell_name]
|
||||
if {$cell != "NULL" && $cell ne ""} {
|
||||
set is_leaf [$cell is_leaf]
|
||||
set is_buf [$cell is_buffer]
|
||||
set is_inv [$cell is_inverter]
|
||||
set area [get_property $cell area]
|
||||
set du [get_property $cell dont_use]
|
||||
set arc_sets [$cell timing_arc_sets]
|
||||
set arc_count [llength $arc_sets]
|
||||
puts "$cell_name leaf=$is_leaf buf=$is_buf inv=$is_inv area=$area du=$du arcs=$arc_count"
|
||||
}
|
||||
}
|
||||
|
||||
############################################################
|
||||
# Test cell and scan signal type queries
|
||||
############################################################
|
||||
puts "--- test_cell / scan queries ---"
|
||||
|
||||
# SDFF has test_cell
|
||||
set sdff [get_lib_cell NangateOpenCellLibrary/SDFF_X1]
|
||||
set tc [$sdff test_cell]
|
||||
if {$tc != "NULL" && $tc ne ""} {
|
||||
puts "SDFF_X1 has test_cell"
|
||||
} else {
|
||||
puts "SDFF_X1 test_cell is null"
|
||||
}
|
||||
|
||||
set sdffr [get_lib_cell NangateOpenCellLibrary/SDFFR_X1]
|
||||
set tc [$sdffr test_cell]
|
||||
if {$tc != "NULL" && $tc ne ""} {
|
||||
puts "SDFFR_X1 has test_cell"
|
||||
} else {
|
||||
puts "SDFFR_X1 test_cell is null"
|
||||
}
|
||||
|
||||
set sdffrs [get_lib_cell NangateOpenCellLibrary/SDFFRS_X1]
|
||||
set tc [$sdffrs test_cell]
|
||||
if {$tc != "NULL" && $tc ne ""} {
|
||||
puts "SDFFRS_X1 has test_cell"
|
||||
} else {
|
||||
puts "SDFFRS_X1 test_cell is null"
|
||||
}
|
||||
|
||||
# Regular DFF should NOT have test_cell
|
||||
set dff [get_lib_cell NangateOpenCellLibrary/DFF_X1]
|
||||
set tc [$dff test_cell]
|
||||
if {$tc != "NULL" && $tc ne ""} {
|
||||
puts "DFF_X1 has test_cell (unexpected)"
|
||||
} else {
|
||||
puts "DFF_X1 has no test_cell (expected)"
|
||||
}
|
||||
|
||||
############################################################
|
||||
# Port function and tristate enable queries
|
||||
############################################################
|
||||
puts "--- function and tristate queries ---"
|
||||
|
||||
# Tristate inverter
|
||||
set tinv [get_lib_cell NangateOpenCellLibrary/TINV_X1]
|
||||
set port_iter [$tinv liberty_port_iterator]
|
||||
while {[$port_iter has_next]} {
|
||||
set port [$port_iter next]
|
||||
set name [get_name $port]
|
||||
set dir [sta::liberty_port_direction $port]
|
||||
set func [$port function]
|
||||
set tri [$port tristate_enable]
|
||||
puts "TINV_X1/$name dir=$dir func=\"$func\" tri=\"$tri\""
|
||||
}
|
||||
$port_iter finish
|
||||
|
||||
# Clock gate tester
|
||||
set clkgt [get_lib_cell NangateOpenCellLibrary/CLKGATETST_X1]
|
||||
set port_iter [$clkgt liberty_port_iterator]
|
||||
while {[$port_iter has_next]} {
|
||||
set port [$port_iter next]
|
||||
set name [get_name $port]
|
||||
set dir [sta::liberty_port_direction $port]
|
||||
set func [$port function]
|
||||
puts "CLKGATETST_X1/$name dir=$dir func=\"$func\""
|
||||
}
|
||||
$port_iter finish
|
||||
|
||||
# Output functions for various logic cells
|
||||
foreach cell_name {INV_X1 BUF_X1 NAND2_X1 NOR2_X1 AND2_X1 OR2_X1
|
||||
XOR2_X1 XNOR2_X1 AOI21_X1 OAI21_X1 MUX2_X1
|
||||
HA_X1 FA_X1} {
|
||||
set cell [get_lib_cell NangateOpenCellLibrary/$cell_name]
|
||||
set port_iter [$cell liberty_port_iterator]
|
||||
while {[$port_iter has_next]} {
|
||||
set port [$port_iter next]
|
||||
set dir [sta::liberty_port_direction $port]
|
||||
if {$dir == "output"} {
|
||||
set func [$port function]
|
||||
if {$func != ""} {
|
||||
puts "$cell_name/[get_name $port] func=$func"
|
||||
}
|
||||
}
|
||||
}
|
||||
$port_iter finish
|
||||
}
|
||||
|
||||
############################################################
|
||||
# Read Sky130 for tristate and latch port queries
|
||||
############################################################
|
||||
read_liberty ../../test/sky130hd/sky130hd_tt.lib
|
||||
|
||||
# Tristate buffer port queries
|
||||
foreach cell_name {sky130_fd_sc_hd__ebufn_1 sky130_fd_sc_hd__ebufn_2} {
|
||||
set cell [get_lib_cell sky130_fd_sc_hd__tt_025C_1v80/$cell_name]
|
||||
set port_iter [$cell liberty_port_iterator]
|
||||
while {[$port_iter has_next]} {
|
||||
set port [$port_iter next]
|
||||
set name [get_name $port]
|
||||
set dir [sta::liberty_port_direction $port]
|
||||
set func [$port function]
|
||||
set tri [$port tristate_enable]
|
||||
set is_pg [$port is_pwr_gnd]
|
||||
if {!$is_pg} {
|
||||
puts "$cell_name/$name dir=$dir func=\"$func\" tri=\"$tri\""
|
||||
}
|
||||
}
|
||||
$port_iter finish
|
||||
}
|
||||
|
||||
############################################################
|
||||
# Read fake_macros library for memory/macro classification
|
||||
############################################################
|
||||
read_liberty ../../test/nangate45/fake_macros.lib
|
||||
|
||||
############################################################
|
||||
# Write roundtrip with bus ports
|
||||
############################################################
|
||||
set outfile [make_result_file liberty_busport_mem_iter_write.lib]
|
||||
sta::write_liberty fakeram45_64x7 $outfile
|
||||
|
||||
# Read back
|
||||
read_liberty $outfile
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,174 @@
|
|||
# Test CCSN (current source) models and various timing model types.
|
||||
# Targets:
|
||||
# LibertyReader.cc: beginCcs/endCcs, receiver_capacitance groups,
|
||||
# timing_type combinations,
|
||||
# beginOutputCurrentRise/Fall, visitReceiverCapacitance,
|
||||
# polynomial model visitors, ccsn noise model visitors,
|
||||
# leakage_power groups, internal_power groups,
|
||||
# max_capacitance/max_transition on pins, min_pulse_width
|
||||
# TableModel.cc: different table axis variables, GateTableModel,
|
||||
# CheckTableModel, 3D tables, receiver model tables
|
||||
# TimingArc.cc: timing arc type queries (removal, recovery,
|
||||
# three_state_enable, rising_edge, min_pulse_width)
|
||||
# Liberty.cc: timing arc set queries, hasTimingArcs, timingArcSets
|
||||
source ../../test/helpers.tcl
|
||||
|
||||
############################################################
|
||||
# Read ASAP7 CCSN library (CCS models with receiver_capacitance)
|
||||
############################################################
|
||||
read_liberty ../../test/asap7_ccsn.lib.gz
|
||||
|
||||
# Report cells from CCSN library to exercise CCS model paths
|
||||
set ccsn_cells [get_lib_cells */*]
|
||||
|
||||
foreach cell_obj $ccsn_cells {
|
||||
report_lib_cell [get_full_name $cell_obj]
|
||||
}
|
||||
|
||||
############################################################
|
||||
# Read ASAP7 SEQ library (has setup/hold/recovery/removal arcs)
|
||||
############################################################
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_SEQ_RVT_FF_nldm_220123.lib
|
||||
|
||||
# Report sequential cells which have diverse timing_type values
|
||||
# DFF cells have setup, hold timing checks
|
||||
set lib_seq [sta::find_liberty asap7sc7p5t_SEQ_RVT_FF_nldm_220123]
|
||||
set seq_cells [$lib_seq find_liberty_cells_matching "DFF*" 0 0]
|
||||
|
||||
# Report specific cells to exercise different timing types
|
||||
report_lib_cell asap7sc7p5t_SEQ_RVT_FF_nldm_220123/DFFHQNx1_ASAP7_75t_R
|
||||
|
||||
report_lib_cell asap7sc7p5t_SEQ_RVT_FF_nldm_220123/DFFHQNx2_ASAP7_75t_R
|
||||
|
||||
# Scan DFF cells (scan_in, scan_enable timing arcs)
|
||||
report_lib_cell asap7sc7p5t_SEQ_RVT_FF_nldm_220123/SDFHQNx1_ASAP7_75t_R
|
||||
|
||||
report_lib_cell asap7sc7p5t_SEQ_RVT_FF_nldm_220123/SDFHQNx2_ASAP7_75t_R
|
||||
|
||||
# ICG cells (clock gating - exercises clock gate timing types)
|
||||
report_lib_cell asap7sc7p5t_SEQ_RVT_FF_nldm_220123/ICGx1_ASAP7_75t_R
|
||||
|
||||
report_lib_cell asap7sc7p5t_SEQ_RVT_FF_nldm_220123/ICGx2_ASAP7_75t_R
|
||||
|
||||
# Async set/reset cells (recovery/removal timing types)
|
||||
set async_cells [$lib_seq find_liberty_cells_matching "*ASYNC*" 0 0]
|
||||
|
||||
# DFFR cells with reset (recovery/removal)
|
||||
set dffr_cells [$lib_seq find_liberty_cells_matching "DFFR*" 0 0]
|
||||
foreach cell_obj $dffr_cells {
|
||||
report_lib_cell [get_name $cell_obj]
|
||||
}
|
||||
|
||||
############################################################
|
||||
# Read ASAP7 SEQ SS corner for different model values
|
||||
############################################################
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_SEQ_RVT_SS_nldm_220123.lib
|
||||
|
||||
############################################################
|
||||
# Read ASAP7 SIMPLE library (combinational cells)
|
||||
############################################################
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz
|
||||
|
||||
set simple_lib [sta::find_liberty asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120]
|
||||
set simple_cells [$simple_lib find_liberty_cells_matching "*" 0 0]
|
||||
|
||||
############################################################
|
||||
# Read ASAP7 AO library (AND-OR complex cells)
|
||||
############################################################
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_AO_RVT_FF_nldm_211120.lib.gz
|
||||
|
||||
set ao_lib [sta::find_liberty asap7sc7p5t_AO_RVT_FF_nldm_211120]
|
||||
set ao_cells [$ao_lib find_liberty_cells_matching "AO*" 0 0]
|
||||
foreach c $ao_cells {
|
||||
report_lib_cell [get_name $c]
|
||||
}
|
||||
|
||||
############################################################
|
||||
# Read ASAP7 OA library (OR-AND complex cells)
|
||||
############################################################
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_OA_RVT_FF_nldm_211120.lib.gz
|
||||
|
||||
set oa_lib [sta::find_liberty asap7sc7p5t_OA_RVT_FF_nldm_211120]
|
||||
set oa_cells [$oa_lib find_liberty_cells_matching "OA*" 0 0]
|
||||
foreach c $oa_cells {
|
||||
report_lib_cell [get_name $c]
|
||||
}
|
||||
|
||||
############################################################
|
||||
# Read ASAP7 INVBUF library
|
||||
############################################################
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_INVBUF_RVT_FF_nldm_220122.lib.gz
|
||||
|
||||
############################################################
|
||||
# Read libraries from different process nodes
|
||||
# Exercises different liberty features/syntax in each library
|
||||
############################################################
|
||||
|
||||
# Read IHP SG13G2 library (has tristate, scan, different timing types)
|
||||
read_liberty ../../test/ihp-sg13g2/sg13g2_stdcell_typ_1p20V_25C.lib
|
||||
|
||||
set ihp_lib [sta::find_liberty sg13g2_stdcell_typ_1p20V_25C]
|
||||
# Report tristate buffer cell (exercises three_state_enable paths)
|
||||
report_lib_cell sg13g2_stdcell_typ_1p20V_25C/sg13g2_ebufn_2
|
||||
|
||||
# Report scan flip-flop (exercises scan timing paths)
|
||||
report_lib_cell sg13g2_stdcell_typ_1p20V_25C/sg13g2_sdfbbp_1
|
||||
|
||||
# Report latch cell
|
||||
report_lib_cell sg13g2_stdcell_typ_1p20V_25C/sg13g2_dlhq_1
|
||||
|
||||
# MUX cell
|
||||
report_lib_cell sg13g2_stdcell_typ_1p20V_25C/sg13g2_mux2_1
|
||||
|
||||
# Read IHP second PVT corner
|
||||
read_liberty ../../test/ihp-sg13g2/sg13g2_stdcell_typ_1p50V_25C.lib
|
||||
|
||||
############################################################
|
||||
# Read latch library to exercise latch-specific code
|
||||
############################################################
|
||||
read_liberty ../../test/liberty_latch3.lib
|
||||
|
||||
############################################################
|
||||
# Read liberty with backslash-EOL continuation
|
||||
############################################################
|
||||
read_liberty ../../test/liberty_backslash_eol.lib
|
||||
|
||||
############################################################
|
||||
# Read liberty with float-as-string values
|
||||
############################################################
|
||||
read_liberty ../../test/liberty_float_as_str.lib
|
||||
|
||||
############################################################
|
||||
# Read liberty arcs one2one libraries
|
||||
############################################################
|
||||
read_liberty ../../test/liberty_arcs_one2one_1.lib
|
||||
|
||||
read_liberty ../../test/liberty_arcs_one2one_2.lib
|
||||
|
||||
############################################################
|
||||
# Read SRAM macro library (exercises macro/memory cells)
|
||||
############################################################
|
||||
read_liberty ../../test/gf180mcu_sram.lib.gz
|
||||
|
||||
############################################################
|
||||
# Read ASAP7 SEQ LVT/SLVT (different threshold voltages)
|
||||
############################################################
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_SEQ_LVT_FF_nldm_220123.lib
|
||||
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_SEQ_SLVT_FF_nldm_220123.lib
|
||||
|
||||
############################################################
|
||||
# Read ASAP7 INVBUF different Vt flavors
|
||||
############################################################
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_INVBUF_LVT_FF_nldm_220122.lib.gz
|
||||
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_INVBUF_SLVT_FF_nldm_220122.lib.gz
|
||||
|
||||
############################################################
|
||||
# Write liberty for ASAP7 SEQ
|
||||
############################################################
|
||||
set outfile [make_result_file liberty_ccsn_write.lib]
|
||||
sta::write_liberty asap7sc7p5t_SEQ_RVT_FF_nldm_220123 $outfile
|
||||
|
||||
set outfile2 [make_result_file liberty_ccsn_write_ihp.lib]
|
||||
sta::write_liberty sg13g2_stdcell_typ_1p20V_25C $outfile2
|
||||
|
|
@ -0,0 +1,291 @@
|
|||
--- Nangate45 cell classification ---
|
||||
BUF_X1 is_buffer = 1
|
||||
BUF_X1 is_inverter = 0
|
||||
BUF_X1 is_leaf = 1
|
||||
INV_X1 is_buffer = 0
|
||||
INV_X1 is_inverter = 1
|
||||
CLKGATETST_X1 is_buffer = 0
|
||||
CLKGATETST_X1 is_inverter = 0
|
||||
DFF_X1 is_buffer = 0
|
||||
DFF_X1 is_inverter = 0
|
||||
DFF_X1 is_leaf = 1
|
||||
SDFF_X1 test_cell = NULL
|
||||
--- port function queries ---
|
||||
INV_X1/ZN func=!A dir=output
|
||||
BUF_X1/Z func=A dir=output
|
||||
NAND2_X1/ZN func=!(A1*A2) dir=output
|
||||
NOR2_X1/ZN func=!(A1+A2) dir=output
|
||||
AND2_X1/ZN func=A1*A2 dir=output
|
||||
OR2_X1/ZN func=A1+A2 dir=output
|
||||
XOR2_X1/Z func=A^B dir=output
|
||||
XNOR2_X1/ZN func=!(A^B) dir=output
|
||||
AOI21_X1/ZN func=!(A+(B1*B2)) dir=output
|
||||
OAI21_X1/ZN func=!(A*(B1+B2)) dir=output
|
||||
MUX2_X1/Z func=(S*B)+(A*!S) dir=output
|
||||
HA_X1/CO func=A*B dir=output
|
||||
HA_X1/S func=A^B dir=output
|
||||
FA_X1/CO func=(A*B)+(CI*(A+B)) dir=output
|
||||
FA_X1/S func=CI^(A^B) dir=output
|
||||
--- bus port member iteration ---
|
||||
--- port capacitance corner ---
|
||||
--- timing arc sets ---
|
||||
INV_X1 arc_sets=1
|
||||
A -> ZN is_check=0
|
||||
rise -> fall
|
||||
fall -> rise
|
||||
BUF_X1 arc_sets=1
|
||||
A -> Z is_check=0
|
||||
rise -> rise
|
||||
fall -> fall
|
||||
DFF_X1 arc_sets=5
|
||||
CK -> D is_check=1
|
||||
rise -> rise
|
||||
rise -> fall
|
||||
CK -> D is_check=1
|
||||
rise -> rise
|
||||
rise -> fall
|
||||
CK -> CK is_check=1
|
||||
rise -> fall
|
||||
fall -> rise
|
||||
CK -> Q is_check=0
|
||||
rise -> rise
|
||||
rise -> fall
|
||||
CK -> QN is_check=0
|
||||
rise -> rise
|
||||
rise -> fall
|
||||
DFFR_X1 arc_sets=16
|
||||
CK -> D is_check=1
|
||||
rise -> rise
|
||||
rise -> fall
|
||||
CK -> D is_check=1
|
||||
rise -> rise
|
||||
rise -> fall
|
||||
CK -> RN is_check=1
|
||||
rise -> rise
|
||||
CK -> RN is_check=1
|
||||
rise -> rise
|
||||
RN -> RN is_check=1
|
||||
fall -> rise
|
||||
CK -> CK is_check=1
|
||||
rise -> fall
|
||||
fall -> rise
|
||||
CK -> Q is_check=0
|
||||
rise -> rise
|
||||
rise -> fall
|
||||
RN -> Q is_check=0
|
||||
fall -> fall
|
||||
RN -> Q is_check=0
|
||||
fall -> fall
|
||||
RN -> Q is_check=0
|
||||
fall -> fall
|
||||
RN -> Q is_check=0
|
||||
fall -> fall
|
||||
CK -> QN is_check=0
|
||||
rise -> rise
|
||||
rise -> fall
|
||||
RN -> QN is_check=0
|
||||
fall -> rise
|
||||
RN -> QN is_check=0
|
||||
fall -> rise
|
||||
RN -> QN is_check=0
|
||||
fall -> rise
|
||||
RN -> QN is_check=0
|
||||
fall -> rise
|
||||
NAND2_X1 arc_sets=2
|
||||
A1 -> ZN is_check=0
|
||||
rise -> fall
|
||||
fall -> rise
|
||||
A2 -> ZN is_check=0
|
||||
rise -> fall
|
||||
fall -> rise
|
||||
AOI21_X1 arc_sets=5
|
||||
A -> ZN is_check=0
|
||||
rise -> fall
|
||||
fall -> rise
|
||||
A -> ZN is_check=0
|
||||
rise -> fall
|
||||
fall -> rise
|
||||
A -> ZN is_check=0
|
||||
rise -> fall
|
||||
fall -> rise
|
||||
B1 -> ZN is_check=0
|
||||
rise -> fall
|
||||
fall -> rise
|
||||
B2 -> ZN is_check=0
|
||||
rise -> fall
|
||||
fall -> rise
|
||||
MUX2_X1 arc_sets=6
|
||||
A -> Z is_check=0
|
||||
rise -> rise
|
||||
fall -> fall
|
||||
A -> Z is_check=0
|
||||
rise -> rise
|
||||
fall -> fall
|
||||
B -> Z is_check=0
|
||||
rise -> rise
|
||||
fall -> fall
|
||||
B -> Z is_check=0
|
||||
rise -> rise
|
||||
fall -> fall
|
||||
S -> Z is_check=0
|
||||
rise -> rise
|
||||
fall -> fall
|
||||
S -> Z is_check=0
|
||||
rise -> fall
|
||||
fall -> rise
|
||||
SDFF_X1 arc_sets=9
|
||||
CK -> D is_check=1
|
||||
rise -> rise
|
||||
rise -> fall
|
||||
CK -> D is_check=1
|
||||
rise -> rise
|
||||
rise -> fall
|
||||
CK -> SE is_check=1
|
||||
rise -> rise
|
||||
rise -> fall
|
||||
CK -> SE is_check=1
|
||||
rise -> rise
|
||||
rise -> fall
|
||||
CK -> SI is_check=1
|
||||
rise -> rise
|
||||
rise -> fall
|
||||
CK -> SI is_check=1
|
||||
rise -> rise
|
||||
rise -> fall
|
||||
CK -> CK is_check=1
|
||||
rise -> fall
|
||||
fall -> rise
|
||||
CK -> Q is_check=0
|
||||
rise -> rise
|
||||
rise -> fall
|
||||
CK -> QN is_check=0
|
||||
rise -> rise
|
||||
rise -> fall
|
||||
CLKGATETST_X1 arc_sets=9
|
||||
CK -> CK is_check=1
|
||||
fall -> rise
|
||||
CK -> E is_check=1
|
||||
rise -> rise
|
||||
rise -> fall
|
||||
CK -> E is_check=1
|
||||
rise -> rise
|
||||
rise -> fall
|
||||
CK -> SE is_check=1
|
||||
rise -> rise
|
||||
rise -> fall
|
||||
CK -> SE is_check=1
|
||||
rise -> rise
|
||||
rise -> fall
|
||||
CK -> GCK is_check=0
|
||||
rise -> rise
|
||||
fall -> fall
|
||||
CK -> GCK is_check=0
|
||||
rise -> rise
|
||||
fall -> fall
|
||||
CK -> GCK is_check=0
|
||||
rise -> rise
|
||||
fall -> fall
|
||||
CK -> GCK is_check=0
|
||||
fall -> fall
|
||||
--- Sky130 cell queries ---
|
||||
sky130_fd_sc_hd__inv_1 is_buffer=0 is_inverter=1
|
||||
VGND pwr_gnd=1
|
||||
VNB pwr_gnd=1
|
||||
VPB pwr_gnd=1
|
||||
VPWR pwr_gnd=1
|
||||
sky130_fd_sc_hd__inv_2 is_buffer=0 is_inverter=1
|
||||
VGND pwr_gnd=1
|
||||
VNB pwr_gnd=1
|
||||
VPB pwr_gnd=1
|
||||
VPWR pwr_gnd=1
|
||||
sky130_fd_sc_hd__inv_4 is_buffer=0 is_inverter=1
|
||||
VGND pwr_gnd=1
|
||||
VNB pwr_gnd=1
|
||||
VPB pwr_gnd=1
|
||||
VPWR pwr_gnd=1
|
||||
sky130_fd_sc_hd__buf_1 is_buffer=1 is_inverter=0
|
||||
VGND pwr_gnd=1
|
||||
VNB pwr_gnd=1
|
||||
VPB pwr_gnd=1
|
||||
VPWR pwr_gnd=1
|
||||
sky130_fd_sc_hd__buf_2 is_buffer=1 is_inverter=0
|
||||
VGND pwr_gnd=1
|
||||
VNB pwr_gnd=1
|
||||
VPB pwr_gnd=1
|
||||
VPWR pwr_gnd=1
|
||||
sky130_fd_sc_hd__nand2_1 is_buffer=0 is_inverter=0
|
||||
VGND pwr_gnd=1
|
||||
VNB pwr_gnd=1
|
||||
VPB pwr_gnd=1
|
||||
VPWR pwr_gnd=1
|
||||
sky130_fd_sc_hd__nor2_1 is_buffer=0 is_inverter=0
|
||||
VGND pwr_gnd=1
|
||||
VNB pwr_gnd=1
|
||||
VPB pwr_gnd=1
|
||||
VPWR pwr_gnd=1
|
||||
sky130_fd_sc_hd__and2_1 is_buffer=0 is_inverter=0
|
||||
VGND pwr_gnd=1
|
||||
VNB pwr_gnd=1
|
||||
VPB pwr_gnd=1
|
||||
VPWR pwr_gnd=1
|
||||
sky130_fd_sc_hd__or2_1 is_buffer=0 is_inverter=0
|
||||
VGND pwr_gnd=1
|
||||
VNB pwr_gnd=1
|
||||
VPB pwr_gnd=1
|
||||
VPWR pwr_gnd=1
|
||||
sky130_fd_sc_hd__dfxtp_1 is_buffer=0 is_inverter=0
|
||||
VGND pwr_gnd=1
|
||||
VNB pwr_gnd=1
|
||||
VPB pwr_gnd=1
|
||||
VPWR pwr_gnd=1
|
||||
sky130_fd_sc_hd__dfrtp_1 is_buffer=0 is_inverter=0
|
||||
VGND pwr_gnd=1
|
||||
VNB pwr_gnd=1
|
||||
VPB pwr_gnd=1
|
||||
VPWR pwr_gnd=1
|
||||
sky130_fd_sc_hd__mux2_1 is_buffer=0 is_inverter=0
|
||||
VGND pwr_gnd=1
|
||||
VNB pwr_gnd=1
|
||||
VPB pwr_gnd=1
|
||||
VPWR pwr_gnd=1
|
||||
sky130_fd_sc_hd__dlxtp_1 is_buffer=0 is_inverter=0
|
||||
VGND pwr_gnd=1
|
||||
VNB pwr_gnd=1
|
||||
VPB pwr_gnd=1
|
||||
VPWR pwr_gnd=1
|
||||
sky130_fd_sc_hd__ebufn_1 is_buffer=0 is_inverter=0
|
||||
VGND pwr_gnd=1
|
||||
VNB pwr_gnd=1
|
||||
VPB pwr_gnd=1
|
||||
VPWR pwr_gnd=1
|
||||
--- operating conditions ---
|
||||
Sky130 default OC process=1.0 voltage=1.7999999523162842 temp=25.0
|
||||
--- IHP cell queries ---
|
||||
sg13g2_inv_1 is_buffer=0 is_inverter=1
|
||||
arc_sets=1
|
||||
sg13g2_inv_2 is_buffer=0 is_inverter=1
|
||||
arc_sets=1
|
||||
sg13g2_buf_1 is_buffer=1 is_inverter=0
|
||||
arc_sets=1
|
||||
sg13g2_buf_2 is_buffer=1 is_inverter=0
|
||||
arc_sets=1
|
||||
sg13g2_nand2_1 is_buffer=0 is_inverter=0
|
||||
arc_sets=2
|
||||
sg13g2_nor2_1 is_buffer=0 is_inverter=0
|
||||
arc_sets=2
|
||||
sg13g2_and2_1 is_buffer=0 is_inverter=0
|
||||
arc_sets=2
|
||||
sg13g2_dfrbp_1 is_buffer=0 is_inverter=0
|
||||
arc_sets=10
|
||||
sg13g2_dfrbp_2 is_buffer=0 is_inverter=0
|
||||
arc_sets=10
|
||||
sg13g2_ebufn_2 is_buffer=0 is_inverter=0
|
||||
arc_sets=3
|
||||
--- ensure voltage waveforms ---
|
||||
--- liberty cell matching ---
|
||||
INV_* matches = 6
|
||||
DFF* matches = 8
|
||||
* matches = 134
|
||||
regex INV_X matches = 6
|
||||
INV_X1 port * matches = 4
|
||||
INV_X1 port A matches = 1
|
||||
|
|
@ -0,0 +1,238 @@
|
|||
# Test cell classification (isBuffer, isInverter, isClockGate, etc.),
|
||||
# pg_pin iteration, bus port member iteration, internal power queries,
|
||||
# and port function queries across multiple PDKs.
|
||||
source ../../test/helpers.tcl
|
||||
|
||||
############################################################
|
||||
# Read libraries with pg_pin info (Sky130 has pg_pin groups)
|
||||
############################################################
|
||||
read_liberty ../../test/sky130hd/sky130hd_tt.lib
|
||||
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_SEQ_RVT_FF_nldm_220123.lib
|
||||
|
||||
read_liberty ../../test/ihp-sg13g2/sg13g2_stdcell_typ_1p20V_25C.lib
|
||||
|
||||
############################################################
|
||||
# Cell classification queries on Nangate45
|
||||
############################################################
|
||||
puts "--- Nangate45 cell classification ---"
|
||||
|
||||
# Buffers
|
||||
set buf_x1 [get_lib_cell NangateOpenCellLibrary/BUF_X1]
|
||||
puts "BUF_X1 is_buffer = [$buf_x1 is_buffer]"
|
||||
puts "BUF_X1 is_inverter = [$buf_x1 is_inverter]"
|
||||
puts "BUF_X1 is_leaf = [$buf_x1 is_leaf]"
|
||||
|
||||
# Inverters
|
||||
set inv_x1 [get_lib_cell NangateOpenCellLibrary/INV_X1]
|
||||
puts "INV_X1 is_buffer = [$inv_x1 is_buffer]"
|
||||
puts "INV_X1 is_inverter = [$inv_x1 is_inverter]"
|
||||
|
||||
# Clock gate cells
|
||||
set clkgate [get_lib_cell NangateOpenCellLibrary/CLKGATETST_X1]
|
||||
puts "CLKGATETST_X1 is_buffer = [$clkgate is_buffer]"
|
||||
puts "CLKGATETST_X1 is_inverter = [$clkgate is_inverter]"
|
||||
|
||||
# DFF
|
||||
set dff [get_lib_cell NangateOpenCellLibrary/DFF_X1]
|
||||
puts "DFF_X1 is_buffer = [$dff is_buffer]"
|
||||
puts "DFF_X1 is_inverter = [$dff is_inverter]"
|
||||
puts "DFF_X1 is_leaf = [$dff is_leaf]"
|
||||
|
||||
# Test cell for scan DFF
|
||||
set sdff [get_lib_cell NangateOpenCellLibrary/SDFF_X1]
|
||||
set tc [$sdff test_cell]
|
||||
puts "SDFF_X1 test_cell = $tc"
|
||||
|
||||
############################################################
|
||||
# Port function queries (exercises FuncExpr::to_string)
|
||||
############################################################
|
||||
puts "--- port function queries ---"
|
||||
foreach {lib_name cell_name} {
|
||||
NangateOpenCellLibrary INV_X1
|
||||
NangateOpenCellLibrary BUF_X1
|
||||
NangateOpenCellLibrary NAND2_X1
|
||||
NangateOpenCellLibrary NOR2_X1
|
||||
NangateOpenCellLibrary AND2_X1
|
||||
NangateOpenCellLibrary OR2_X1
|
||||
NangateOpenCellLibrary XOR2_X1
|
||||
NangateOpenCellLibrary XNOR2_X1
|
||||
NangateOpenCellLibrary AOI21_X1
|
||||
NangateOpenCellLibrary OAI21_X1
|
||||
NangateOpenCellLibrary MUX2_X1
|
||||
NangateOpenCellLibrary HA_X1
|
||||
NangateOpenCellLibrary FA_X1
|
||||
} {
|
||||
set cell [get_lib_cell $lib_name/$cell_name]
|
||||
set port_iter [$cell liberty_port_iterator]
|
||||
while {[$port_iter has_next]} {
|
||||
set port [$port_iter next]
|
||||
set func [$port function]
|
||||
set tri [$port tristate_enable]
|
||||
set dir [sta::liberty_port_direction $port]
|
||||
set pwr [$port is_pwr_gnd]
|
||||
if {$func != ""} {
|
||||
puts " $cell_name/[$port bus_name] func=$func dir=$dir"
|
||||
}
|
||||
if {$tri != ""} {
|
||||
puts " $cell_name/[$port bus_name] tristate=$tri"
|
||||
}
|
||||
}
|
||||
$port_iter finish
|
||||
}
|
||||
|
||||
############################################################
|
||||
# Bus port and member iteration
|
||||
############################################################
|
||||
puts "--- bus port member iteration ---"
|
||||
|
||||
# ASAP7 SEQ has bus ports in some cells
|
||||
set asap7_libs [get_libs asap7sc7p5t_SEQ_RVT_FF_nldm_220123]
|
||||
set asap7_seq_lib [lindex $asap7_libs 0]
|
||||
set asap7_cells [get_lib_cells asap7sc7p5t_SEQ_RVT_FF_nldm_220123/*]
|
||||
foreach cell_obj $asap7_cells {
|
||||
set cname [$cell_obj name]
|
||||
set port_iter [$cell_obj liberty_port_iterator]
|
||||
while {[$port_iter has_next]} {
|
||||
set port [$port_iter next]
|
||||
if {[$port is_bus]} {
|
||||
puts "$cname/[$port bus_name] is_bus=1 has_members=[$port has_members]"
|
||||
set mem_iter [$port member_iterator]
|
||||
while {[$mem_iter has_next]} {
|
||||
set member [$mem_iter next]
|
||||
puts " member: [$member bus_name] is_bus_bit=[$member is_bus_bit]"
|
||||
}
|
||||
$mem_iter finish
|
||||
}
|
||||
if {[$port is_bundle]} {
|
||||
puts "$cname/[$port bus_name] is_bundle=1"
|
||||
}
|
||||
}
|
||||
$port_iter finish
|
||||
}
|
||||
|
||||
############################################################
|
||||
# Port capacitance with corner/min_max
|
||||
############################################################
|
||||
puts "--- port capacitance corner ---"
|
||||
|
||||
############################################################
|
||||
# Timing arc set queries
|
||||
############################################################
|
||||
puts "--- timing arc sets ---"
|
||||
foreach cell_name {INV_X1 BUF_X1 DFF_X1 DFFR_X1 NAND2_X1 AOI21_X1 MUX2_X1 SDFF_X1 CLKGATETST_X1} {
|
||||
set cell [get_lib_cell NangateOpenCellLibrary/$cell_name]
|
||||
set arc_sets [$cell timing_arc_sets]
|
||||
puts "$cell_name arc_sets=[llength $arc_sets]"
|
||||
foreach arc_set $arc_sets {
|
||||
set from_port [$arc_set from]
|
||||
set to_port [$arc_set to]
|
||||
set role [$arc_set role]
|
||||
set is_check [sta::timing_role_is_check $role]
|
||||
set from_name [$from_port bus_name]
|
||||
set to_name [$to_port bus_name]
|
||||
puts " $from_name -> $to_name is_check=$is_check"
|
||||
# Query timing arcs within the set
|
||||
set arcs [$arc_set timing_arcs]
|
||||
foreach arc $arcs {
|
||||
set from_edge [$arc from_edge_name]
|
||||
set to_edge [$arc to_edge_name]
|
||||
puts " $from_edge -> $to_edge"
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
############################################################
|
||||
# Sky130 cell queries (has pg_pin groups, different features)
|
||||
############################################################
|
||||
puts "--- Sky130 cell queries ---"
|
||||
foreach cell_name {
|
||||
sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_2 sky130_fd_sc_hd__inv_4
|
||||
sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_2
|
||||
sky130_fd_sc_hd__nand2_1 sky130_fd_sc_hd__nor2_1
|
||||
sky130_fd_sc_hd__and2_1 sky130_fd_sc_hd__or2_1
|
||||
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfrtp_1
|
||||
sky130_fd_sc_hd__mux2_1
|
||||
sky130_fd_sc_hd__dlxtp_1
|
||||
sky130_fd_sc_hd__ebufn_1
|
||||
} {
|
||||
set cell [get_lib_cell sky130_fd_sc_hd__tt_025C_1v80/$cell_name]
|
||||
puts "$cell_name is_buffer=[$cell is_buffer] is_inverter=[$cell is_inverter]"
|
||||
set port_iter [$cell liberty_port_iterator]
|
||||
while {[$port_iter has_next]} {
|
||||
set port [$port_iter next]
|
||||
set func [$port function]
|
||||
set dir [sta::liberty_port_direction $port]
|
||||
set pwr [$port is_pwr_gnd]
|
||||
if {$pwr} {
|
||||
puts " [$port bus_name] pwr_gnd=1"
|
||||
}
|
||||
}
|
||||
$port_iter finish
|
||||
}
|
||||
|
||||
############################################################
|
||||
# Operating conditions (exercises find_operating_conditions)
|
||||
############################################################
|
||||
puts "--- operating conditions ---"
|
||||
set sky_lib [lindex [get_libs sky130_fd_sc_hd__tt_025C_1v80] 0]
|
||||
set default_oc [$sky_lib default_operating_conditions]
|
||||
if {$default_oc != "NULL" && $default_oc ne ""} {
|
||||
puts "Sky130 default OC process=[$default_oc process] voltage=[$default_oc voltage] temp=[$default_oc temperature]"
|
||||
}
|
||||
|
||||
############################################################
|
||||
# IHP cell queries (different vendor, might have different features)
|
||||
############################################################
|
||||
puts "--- IHP cell queries ---"
|
||||
foreach cell_name {
|
||||
sg13g2_inv_1 sg13g2_inv_2
|
||||
sg13g2_buf_1 sg13g2_buf_2
|
||||
sg13g2_nand2_1 sg13g2_nor2_1
|
||||
sg13g2_and2_1
|
||||
sg13g2_dfrbp_1 sg13g2_dfrbp_2
|
||||
sg13g2_ebufn_2
|
||||
} {
|
||||
set cell [get_lib_cell sg13g2_stdcell_typ_1p20V_25C/$cell_name]
|
||||
puts "$cell_name is_buffer=[$cell is_buffer] is_inverter=[$cell is_inverter]"
|
||||
set arc_sets [$cell timing_arc_sets]
|
||||
puts " arc_sets=[llength $arc_sets]"
|
||||
}
|
||||
|
||||
############################################################
|
||||
# Ensure voltage waveforms (exercises ensureVoltageWaveforms)
|
||||
############################################################
|
||||
puts "--- ensure voltage waveforms ---"
|
||||
set inv [get_lib_cell NangateOpenCellLibrary/INV_X1]
|
||||
$inv ensure_voltage_waveforms
|
||||
|
||||
set dff [get_lib_cell NangateOpenCellLibrary/DFF_X1]
|
||||
$dff ensure_voltage_waveforms
|
||||
|
||||
############################################################
|
||||
# Liberty cell matching with regex patterns
|
||||
############################################################
|
||||
puts "--- liberty cell matching ---"
|
||||
set ng_lib [lindex [get_libs NangateOpenCellLibrary] 0]
|
||||
set inv_matches [$ng_lib find_liberty_cells_matching "INV_*" 0 0]
|
||||
puts "INV_* matches = [llength $inv_matches]"
|
||||
|
||||
set dff_matches [$ng_lib find_liberty_cells_matching "DFF*" 0 0]
|
||||
puts "DFF* matches = [llength $dff_matches]"
|
||||
|
||||
set all_matches [$ng_lib find_liberty_cells_matching "*" 0 0]
|
||||
puts "* matches = [llength $all_matches]"
|
||||
|
||||
# Regex matching
|
||||
set regex_matches [$ng_lib find_liberty_cells_matching {^INV_X[0-9]+$} 1 0]
|
||||
puts "regex INV_X matches = [llength $regex_matches]"
|
||||
|
||||
# Port matching on a cell
|
||||
set inv [get_lib_cell NangateOpenCellLibrary/INV_X1]
|
||||
set port_matches [$inv find_liberty_ports_matching "*" 0 0]
|
||||
puts "INV_X1 port * matches = [llength $port_matches]"
|
||||
|
||||
set port_matches [$inv find_liberty_ports_matching "A" 0 0]
|
||||
puts "INV_X1 port A matches = [llength $port_matches]"
|
||||
|
|
@ -0,0 +1,652 @@
|
|||
INV_X1/A cap = 1.700230
|
||||
INV_X2/A cap = 3.250891
|
||||
INV_X4/A cap = 6.258425
|
||||
INV_X8/A cap = 11.810652
|
||||
INV_X16/A cap = 25.228138
|
||||
INV_X32/A cap = 49.191467
|
||||
BUF_X1/A cap = 0.974659
|
||||
BUF_X2/A cap = 1.779209
|
||||
BUF_X4/A cap = 3.401892
|
||||
BUF_X8/A cap = 6.585178
|
||||
BUF_X16/A cap = 12.410827
|
||||
BUF_X32/A cap = 26.703922
|
||||
INV_X1 area = 0.532000
|
||||
INV_X2 area = 0.798000
|
||||
INV_X4 area = 1.330000
|
||||
INV_X8 area = 2.394000
|
||||
INV_X16 area = 4.522000
|
||||
INV_X32 area = 8.778000
|
||||
BUF_X1 area = 0.798000
|
||||
BUF_X2 area = 1.064000
|
||||
BUF_X4 area = 1.862000
|
||||
BUF_X8 area = 3.458000
|
||||
BUF_X16 area = 6.650000
|
||||
BUF_X32 area = 13.034000
|
||||
DFF_X1 area = 4.522000
|
||||
DFF_X2 area = 5.054000
|
||||
DFFR_X1 area = 5.320000
|
||||
DFFS_X1 area = 5.320000
|
||||
DFFRS_X1 area = 6.384000
|
||||
NAND2_X1 area = 0.798000
|
||||
NAND2_X2 area = 1.330000
|
||||
NAND2_X4 area = 2.394000
|
||||
NOR2_X1 area = 0.798000
|
||||
NOR2_X2 area = 1.330000
|
||||
NOR2_X4 area = 2.394000
|
||||
AOI21_X1 area = 1.064000
|
||||
OAI21_X1 area = 1.064000
|
||||
MUX2_X1 area = 1.862000
|
||||
FA_X1 area = 4.256000
|
||||
HA_X1 area = 2.660000
|
||||
TINV_X1 area = 1.064000
|
||||
CLKGATETST_X1 area = 3.990000
|
||||
INV_X1 dont_use = 0
|
||||
BUF_X1 dont_use = 0
|
||||
DFF_X1 dont_use = 0
|
||||
ANTENNA_X1 dont_use = 1
|
||||
FILLCELL_X1 dont_use = 1
|
||||
No paths found.
|
||||
No paths found.
|
||||
No paths found.
|
||||
No paths found.
|
||||
No paths found.
|
||||
No paths found.
|
||||
No paths found.
|
||||
Group Slack
|
||||
--------------------------------------------
|
||||
clk1 2.05
|
||||
clk2 0.08
|
||||
clk1 6.92
|
||||
clk2 9.88
|
||||
|
||||
max slew
|
||||
|
||||
Pin Limit Slew Slack
|
||||
------------------------------------------------------------
|
||||
inv1/ZN 0.20 0.02 0.18 (MET)
|
||||
|
||||
max capacitance
|
||||
|
||||
Pin Limit Cap Slack
|
||||
------------------------------------------------------------
|
||||
nor1/ZN 26.70 1.14 25.56 (MET)
|
||||
|
||||
Group Slack
|
||||
--------------------------------------------
|
||||
No paths found.
|
||||
|
||||
Required Actual
|
||||
Pin Width Width Slack
|
||||
------------------------------------------------------------
|
||||
reg1/CK (high) 0.05 5.00 4.95 (MET)
|
||||
|
||||
Group Slack
|
||||
--------------------------------------------
|
||||
No paths found.
|
||||
|
||||
Group Internal Switching Leakage Total
|
||||
Power Power Power Power (Watts)
|
||||
----------------------------------------------------------------
|
||||
Sequential 1.52e-06 6.90e-09 2.36e-07 1.76e-06 84.2%
|
||||
Combinational 1.33e-07 7.11e-08 1.25e-07 3.29e-07 15.8%
|
||||
Clock 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
|
||||
Macro 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
|
||||
Pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
|
||||
----------------------------------------------------------------
|
||||
Total 1.65e-06 7.80e-08 3.61e-07 2.09e-06 100.0%
|
||||
79.0% 3.7% 17.3%
|
||||
Internal Switching Leakage Total
|
||||
Power Power Power Power (Watts)
|
||||
--------------------------------------------
|
||||
5.87e-07 6.90e-09 7.86e-08 6.73e-07 reg1
|
||||
5.89e-07 0.00e+00 7.84e-08 6.67e-07 reg2
|
||||
3.41e-07 0.00e+00 7.86e-08 4.20e-07 reg3
|
||||
2.56e-08 2.00e-08 2.51e-08 7.07e-08 and1
|
||||
2.70e-08 2.01e-08 2.27e-08 6.98e-08 or1
|
||||
3.04e-08 1.13e-08 2.14e-08 6.31e-08 buf1
|
||||
2.33e-08 5.90e-09 1.44e-08 4.35e-08 inv1
|
||||
1.46e-08 6.90e-09 1.97e-08 4.11e-08 nor1
|
||||
1.24e-08 6.90e-09 2.18e-08 4.11e-08 nand1
|
||||
Cell sky130_fd_sc_hd__ebufn_1
|
||||
Library sky130_fd_sc_hd__tt_025C_1v80
|
||||
File ../../test/sky130hd/sky130hd_tt.lib
|
||||
VGND ground
|
||||
VNB bias
|
||||
VPB bias
|
||||
VPWR power
|
||||
A input 1.73-1.88
|
||||
TE_B input 2.93-3.34
|
||||
Z tristate enable=!TE_B function=A 2.26
|
||||
|
||||
Timing arcs
|
||||
A -> Z
|
||||
combinational
|
||||
^ -> ^
|
||||
v -> v
|
||||
TE_B -> Z
|
||||
tristate enable
|
||||
v -> Z1
|
||||
v -> Z0
|
||||
TE_B -> Z
|
||||
tristate disable
|
||||
^ -> 0Z
|
||||
^ -> 1Z
|
||||
Cell sky130_fd_sc_hd__ebufn_2
|
||||
Library sky130_fd_sc_hd__tt_025C_1v80
|
||||
File ../../test/sky130hd/sky130hd_tt.lib
|
||||
VGND ground
|
||||
VNB bias
|
||||
VPB bias
|
||||
VPWR power
|
||||
A input 1.74-1.89
|
||||
TE_B input 3.75-4.41
|
||||
Z tristate enable=!TE_B function=A 2.75
|
||||
|
||||
Timing arcs
|
||||
A -> Z
|
||||
combinational
|
||||
^ -> ^
|
||||
v -> v
|
||||
TE_B -> Z
|
||||
tristate enable
|
||||
v -> Z1
|
||||
v -> Z0
|
||||
TE_B -> Z
|
||||
tristate disable
|
||||
^ -> 0Z
|
||||
^ -> 1Z
|
||||
Cell sky130_fd_sc_hd__ebufn_4
|
||||
Library sky130_fd_sc_hd__tt_025C_1v80
|
||||
File ../../test/sky130hd/sky130hd_tt.lib
|
||||
VGND ground
|
||||
VNB bias
|
||||
VPB bias
|
||||
VPWR power
|
||||
A input 2.37-2.60
|
||||
TE_B input 6.26-7.48
|
||||
Z tristate enable=!TE_B function=A 5.20
|
||||
|
||||
Timing arcs
|
||||
A -> Z
|
||||
combinational
|
||||
^ -> ^
|
||||
v -> v
|
||||
TE_B -> Z
|
||||
tristate enable
|
||||
v -> Z1
|
||||
v -> Z0
|
||||
TE_B -> Z
|
||||
tristate disable
|
||||
^ -> 0Z
|
||||
^ -> 1Z
|
||||
Cell sky130_fd_sc_hd__dlxtp_1
|
||||
Library sky130_fd_sc_hd__tt_025C_1v80
|
||||
File ../../test/sky130hd/sky130hd_tt.lib
|
||||
VGND ground
|
||||
VNB bias
|
||||
VPB bias
|
||||
VPWR power
|
||||
D input 1.70-1.85
|
||||
GATE input 1.68-1.82
|
||||
Q output function=IQ
|
||||
IQ internal
|
||||
IQ_N internal
|
||||
|
||||
Timing arcs
|
||||
GATE -> D
|
||||
setup
|
||||
v -> ^
|
||||
v -> v
|
||||
GATE -> D
|
||||
hold
|
||||
v -> ^
|
||||
v -> v
|
||||
GATE -> GATE
|
||||
width
|
||||
^ -> v
|
||||
D -> Q
|
||||
Latch D to Q
|
||||
^ -> ^
|
||||
v -> v
|
||||
GATE -> Q
|
||||
Latch En to Q
|
||||
^ -> ^
|
||||
^ -> v
|
||||
Cell sky130_fd_sc_hd__dlxtn_1
|
||||
Library sky130_fd_sc_hd__tt_025C_1v80
|
||||
File ../../test/sky130hd/sky130hd_tt.lib
|
||||
VGND ground
|
||||
VNB bias
|
||||
VPB bias
|
||||
VPWR power
|
||||
D input 1.70-1.89
|
||||
GATE_N input 1.66-1.82
|
||||
Q output function=IQ
|
||||
IQ internal
|
||||
IQ_N internal
|
||||
|
||||
Timing arcs
|
||||
GATE_N -> D
|
||||
setup
|
||||
^ -> ^
|
||||
^ -> v
|
||||
GATE_N -> D
|
||||
hold
|
||||
^ -> ^
|
||||
^ -> v
|
||||
GATE_N -> GATE_N
|
||||
width
|
||||
v -> ^
|
||||
D -> Q
|
||||
Latch D to Q
|
||||
^ -> ^
|
||||
v -> v
|
||||
GATE_N -> Q
|
||||
Latch En to Q
|
||||
v -> ^
|
||||
v -> v
|
||||
Cell sky130_fd_sc_hd__sdfxtp_1
|
||||
Library sky130_fd_sc_hd__tt_025C_1v80
|
||||
File ../../test/sky130hd/sky130hd_tt.lib
|
||||
VGND ground
|
||||
VNB bias
|
||||
VPB bias
|
||||
VPWR power
|
||||
CLK input 1.69-1.86
|
||||
D input 1.62-1.78
|
||||
Q output function=IQ
|
||||
SCD input 1.72-1.90
|
||||
SCE input 3.19-3.58
|
||||
IQ internal
|
||||
IQ_N internal
|
||||
|
||||
Timing arcs
|
||||
CLK -> CLK
|
||||
width
|
||||
^ -> v
|
||||
v -> ^
|
||||
CLK -> D
|
||||
setup
|
||||
^ -> ^
|
||||
^ -> v
|
||||
CLK -> D
|
||||
hold
|
||||
^ -> ^
|
||||
^ -> v
|
||||
CLK -> Q
|
||||
Reg Clk to Q
|
||||
^ -> ^
|
||||
^ -> v
|
||||
CLK -> SCD
|
||||
setup
|
||||
^ -> ^
|
||||
^ -> v
|
||||
CLK -> SCD
|
||||
hold
|
||||
^ -> ^
|
||||
^ -> v
|
||||
CLK -> SCE
|
||||
setup
|
||||
^ -> ^
|
||||
^ -> v
|
||||
CLK -> SCE
|
||||
hold
|
||||
^ -> ^
|
||||
^ -> v
|
||||
Cell sky130_fd_sc_hd__sdfxbp_1
|
||||
Library sky130_fd_sc_hd__tt_025C_1v80
|
||||
File ../../test/sky130hd/sky130hd_tt.lib
|
||||
VGND ground
|
||||
VNB bias
|
||||
VPB bias
|
||||
VPWR power
|
||||
CLK input 1.70-1.87
|
||||
D input 1.61-1.78
|
||||
Q output function=IQ
|
||||
Q_N output function=IQ_N
|
||||
SCD input 1.72-1.90
|
||||
SCE input 3.17-3.56
|
||||
IQ internal
|
||||
IQ_N internal
|
||||
|
||||
Timing arcs
|
||||
CLK -> CLK
|
||||
width
|
||||
^ -> v
|
||||
v -> ^
|
||||
CLK -> D
|
||||
setup
|
||||
^ -> ^
|
||||
^ -> v
|
||||
CLK -> D
|
||||
hold
|
||||
^ -> ^
|
||||
^ -> v
|
||||
CLK -> Q
|
||||
Reg Clk to Q
|
||||
^ -> ^
|
||||
^ -> v
|
||||
CLK -> Q_N
|
||||
Reg Clk to Q
|
||||
^ -> ^
|
||||
^ -> v
|
||||
CLK -> SCD
|
||||
setup
|
||||
^ -> ^
|
||||
^ -> v
|
||||
CLK -> SCD
|
||||
hold
|
||||
^ -> ^
|
||||
^ -> v
|
||||
CLK -> SCE
|
||||
setup
|
||||
^ -> ^
|
||||
^ -> v
|
||||
CLK -> SCE
|
||||
hold
|
||||
^ -> ^
|
||||
^ -> v
|
||||
Cell sky130_fd_sc_hd__dfxtp_1
|
||||
Library sky130_fd_sc_hd__tt_025C_1v80
|
||||
File ../../test/sky130hd/sky130hd_tt.lib
|
||||
VGND ground
|
||||
VNB bias
|
||||
VPB bias
|
||||
VPWR power
|
||||
CLK input 1.71-1.88
|
||||
D input 1.67-1.68
|
||||
Q output function=IQ
|
||||
IQ internal
|
||||
IQ_N internal
|
||||
|
||||
Timing arcs
|
||||
CLK -> CLK
|
||||
width
|
||||
^ -> v
|
||||
v -> ^
|
||||
CLK -> D
|
||||
setup
|
||||
^ -> ^
|
||||
^ -> v
|
||||
CLK -> D
|
||||
hold
|
||||
^ -> ^
|
||||
^ -> v
|
||||
CLK -> Q
|
||||
Reg Clk to Q
|
||||
^ -> ^
|
||||
^ -> v
|
||||
Cell sky130_fd_sc_hd__dfrtp_1
|
||||
Library sky130_fd_sc_hd__tt_025C_1v80
|
||||
File ../../test/sky130hd/sky130hd_tt.lib
|
||||
VGND ground
|
||||
VNB bias
|
||||
VPB bias
|
||||
VPWR power
|
||||
CLK input 1.71-1.87
|
||||
D input 1.95-2.01
|
||||
Q output function=IQ
|
||||
RESET_B input 3.56-3.63
|
||||
IQ internal
|
||||
IQ_N internal
|
||||
|
||||
Timing arcs
|
||||
CLK -> CLK
|
||||
width
|
||||
^ -> v
|
||||
v -> ^
|
||||
CLK -> D
|
||||
setup
|
||||
^ -> ^
|
||||
^ -> v
|
||||
CLK -> D
|
||||
hold
|
||||
^ -> ^
|
||||
^ -> v
|
||||
CLK -> Q
|
||||
Reg Clk to Q
|
||||
^ -> ^
|
||||
^ -> v
|
||||
RESET_B -> Q
|
||||
Reg Set/Clr
|
||||
v -> v
|
||||
CLK -> RESET_B
|
||||
recovery
|
||||
^ -> ^
|
||||
CLK -> RESET_B
|
||||
removal
|
||||
^ -> ^
|
||||
RESET_B -> RESET_B
|
||||
width
|
||||
v -> ^
|
||||
Cell sky130_fd_sc_hd__dfstp_1
|
||||
Library sky130_fd_sc_hd__tt_025C_1v80
|
||||
File ../../test/sky130hd/sky130hd_tt.lib
|
||||
VGND ground
|
||||
VNB bias
|
||||
VPB bias
|
||||
VPWR power
|
||||
CLK input 1.69-1.86
|
||||
D input 2.23-2.49
|
||||
Q output function=IQ
|
||||
SET_B input 3.36-3.44
|
||||
IQ internal
|
||||
IQ_N internal
|
||||
|
||||
Timing arcs
|
||||
CLK -> CLK
|
||||
width
|
||||
^ -> v
|
||||
v -> ^
|
||||
CLK -> D
|
||||
setup
|
||||
^ -> ^
|
||||
^ -> v
|
||||
CLK -> D
|
||||
hold
|
||||
^ -> ^
|
||||
^ -> v
|
||||
CLK -> Q
|
||||
Reg Clk to Q
|
||||
^ -> ^
|
||||
^ -> v
|
||||
SET_B -> Q
|
||||
Reg Set/Clr
|
||||
v -> ^
|
||||
CLK -> SET_B
|
||||
recovery
|
||||
^ -> ^
|
||||
CLK -> SET_B
|
||||
removal
|
||||
^ -> ^
|
||||
SET_B -> SET_B
|
||||
width
|
||||
v -> ^
|
||||
Cell sky130_fd_sc_hd__dfbbp_1
|
||||
Library sky130_fd_sc_hd__tt_025C_1v80
|
||||
File ../../test/sky130hd/sky130hd_tt.lib
|
||||
VGND ground
|
||||
VNB bias
|
||||
VPB bias
|
||||
VPWR power
|
||||
CLK input 1.69-1.89
|
||||
D input 1.49-1.70
|
||||
Q output function=IQ
|
||||
Q_N output function=IQ_N
|
||||
RESET_B input 1.53-1.67
|
||||
SET_B input 3.35-3.53
|
||||
IQ internal
|
||||
IQ_N internal
|
||||
|
||||
Timing arcs
|
||||
CLK -> CLK
|
||||
width
|
||||
^ -> v
|
||||
v -> ^
|
||||
CLK -> D
|
||||
setup
|
||||
^ -> ^
|
||||
^ -> v
|
||||
CLK -> D
|
||||
hold
|
||||
^ -> ^
|
||||
^ -> v
|
||||
CLK -> Q
|
||||
Reg Clk to Q
|
||||
^ -> ^
|
||||
^ -> v
|
||||
RESET_B -> Q
|
||||
Reg Set/Clr
|
||||
v -> v
|
||||
SET_B -> Q
|
||||
Reg Set/Clr
|
||||
v -> ^
|
||||
CLK -> Q_N
|
||||
Reg Clk to Q
|
||||
^ -> ^
|
||||
^ -> v
|
||||
RESET_B -> Q_N
|
||||
Reg Set/Clr
|
||||
v -> ^
|
||||
SET_B -> Q_N
|
||||
Reg Set/Clr
|
||||
v -> v
|
||||
CLK -> RESET_B
|
||||
recovery
|
||||
^ -> ^
|
||||
CLK -> RESET_B
|
||||
removal
|
||||
^ -> ^
|
||||
RESET_B -> RESET_B
|
||||
width
|
||||
v -> ^
|
||||
SET_B -> RESET_B
|
||||
non-sequential setup
|
||||
^ -> ^
|
||||
SET_B -> RESET_B
|
||||
non-sequential hold
|
||||
^ -> ^
|
||||
CLK -> SET_B
|
||||
recovery
|
||||
^ -> ^
|
||||
CLK -> SET_B
|
||||
removal
|
||||
^ -> ^
|
||||
RESET_B -> SET_B
|
||||
non-sequential setup
|
||||
^ -> ^
|
||||
SET_B -> SET_B
|
||||
width
|
||||
v -> ^
|
||||
RESET_B -> SET_B
|
||||
non-sequential hold
|
||||
^ -> ^
|
||||
Cell sky130_fd_sc_hd__mux2_1
|
||||
Library sky130_fd_sc_hd__tt_025C_1v80
|
||||
File ../../test/sky130hd/sky130hd_tt.lib
|
||||
VGND ground
|
||||
VNB bias
|
||||
VPB bias
|
||||
VPWR power
|
||||
A0 input 1.51-1.61
|
||||
A1 input 1.81-1.96
|
||||
S input 3.29-3.52
|
||||
X output function=(A0*!S)+(A1*S)
|
||||
|
||||
Timing arcs
|
||||
A0 -> X
|
||||
combinational
|
||||
^ -> ^
|
||||
v -> v
|
||||
A1 -> X
|
||||
combinational
|
||||
^ -> ^
|
||||
v -> v
|
||||
S -> X
|
||||
combinational
|
||||
^ -> ^
|
||||
v -> v
|
||||
S -> X
|
||||
combinational
|
||||
^ -> v
|
||||
v -> ^
|
||||
Cell sky130_fd_sc_hd__mux2i_1
|
||||
Library sky130_fd_sc_hd__tt_025C_1v80
|
||||
File ../../test/sky130hd/sky130hd_tt.lib
|
||||
VGND ground
|
||||
VNB bias
|
||||
VPB bias
|
||||
VPWR power
|
||||
A0 input 2.10-2.31
|
||||
A1 input 2.15-2.36
|
||||
S input 4.48-4.83
|
||||
Y output function=(!A0*!S)+(!A1*S)
|
||||
|
||||
Timing arcs
|
||||
A0 -> Y
|
||||
combinational
|
||||
^ -> v
|
||||
v -> ^
|
||||
A1 -> Y
|
||||
combinational
|
||||
^ -> v
|
||||
v -> ^
|
||||
S -> Y
|
||||
combinational
|
||||
^ -> v
|
||||
v -> ^
|
||||
S -> Y
|
||||
combinational
|
||||
^ -> ^
|
||||
v -> v
|
||||
Cell sky130_fd_sc_hd__mux4_1
|
||||
Library sky130_fd_sc_hd__tt_025C_1v80
|
||||
File ../../test/sky130hd/sky130hd_tt.lib
|
||||
VGND ground
|
||||
VNB bias
|
||||
VPB bias
|
||||
VPWR power
|
||||
A0 input 1.48-1.57
|
||||
A1 input 1.40-1.48
|
||||
A2 input 1.42-1.51
|
||||
A3 input 1.44-1.52
|
||||
S0 input 3.70-4.09
|
||||
S1 input 2.61-2.74
|
||||
X output function=((((A0*!S0)*!S1)+((A1*S0)*!S1))+((A2*!S0)*S1))+((A3*S0)*S1)
|
||||
|
||||
Timing arcs
|
||||
A0 -> X
|
||||
combinational
|
||||
^ -> ^
|
||||
v -> v
|
||||
A1 -> X
|
||||
combinational
|
||||
^ -> ^
|
||||
v -> v
|
||||
A2 -> X
|
||||
combinational
|
||||
^ -> ^
|
||||
v -> v
|
||||
A3 -> X
|
||||
combinational
|
||||
^ -> ^
|
||||
v -> v
|
||||
S0 -> X
|
||||
combinational
|
||||
^ -> ^
|
||||
v -> v
|
||||
S0 -> X
|
||||
combinational
|
||||
^ -> v
|
||||
v -> ^
|
||||
S1 -> X
|
||||
combinational
|
||||
^ -> ^
|
||||
v -> v
|
||||
S1 -> X
|
||||
combinational
|
||||
^ -> v
|
||||
v -> ^
|
||||
Differences found at line 107.
|
||||
cell_rise(Timing_7_7) {
|
||||
cell_rise(Timing_7_7) {
|
||||
|
|
@ -0,0 +1,161 @@
|
|||
# Deep cell property queries: timing arc traversal, port capacitance,
|
||||
# sequential elements, leakage/internal power, and cell classification.
|
||||
source ../../test/helpers.tcl
|
||||
|
||||
############################################################
|
||||
# Read libraries
|
||||
############################################################
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_SEQ_RVT_FF_nldm_220123.lib
|
||||
|
||||
read_liberty ../../test/ihp-sg13g2/sg13g2_stdcell_typ_1p20V_25C.lib
|
||||
|
||||
############################################################
|
||||
# Port capacitance queries
|
||||
# Exercises: LibertyPort capacitance getters/setters
|
||||
############################################################
|
||||
set inv_a [get_lib_pin NangateOpenCellLibrary/INV_X1/A]
|
||||
set inv_zn [get_lib_pin NangateOpenCellLibrary/INV_X1/ZN]
|
||||
|
||||
set cap_a [get_property $inv_a capacitance]
|
||||
|
||||
set cap_zn [get_property $inv_zn capacitance]
|
||||
|
||||
# DFF capacitance queries
|
||||
set dff_ck [get_lib_pin NangateOpenCellLibrary/DFF_X1/CK]
|
||||
set cap_ck [get_property $dff_ck capacitance]
|
||||
|
||||
set dff_d [get_lib_pin NangateOpenCellLibrary/DFF_X1/D]
|
||||
set cap_d [get_property $dff_d capacitance]
|
||||
|
||||
# Larger drive strengths have different capacitances
|
||||
foreach size {1 2 4 8 16 32} {
|
||||
set pin [get_lib_pin NangateOpenCellLibrary/INV_X${size}/A]
|
||||
set cap [get_property $pin capacitance]
|
||||
puts "INV_X${size}/A cap = $cap"
|
||||
}
|
||||
|
||||
foreach size {1 2 4 8 16 32} {
|
||||
set pin [get_lib_pin NangateOpenCellLibrary/BUF_X${size}/A]
|
||||
set cap [get_property $pin capacitance]
|
||||
puts "BUF_X${size}/A cap = $cap"
|
||||
}
|
||||
|
||||
############################################################
|
||||
# Cell area queries
|
||||
############################################################
|
||||
foreach cell_name {INV_X1 INV_X2 INV_X4 INV_X8 INV_X16 INV_X32
|
||||
BUF_X1 BUF_X2 BUF_X4 BUF_X8 BUF_X16 BUF_X32
|
||||
DFF_X1 DFF_X2 DFFR_X1 DFFS_X1 DFFRS_X1
|
||||
NAND2_X1 NAND2_X2 NAND2_X4
|
||||
NOR2_X1 NOR2_X2 NOR2_X4
|
||||
AOI21_X1 OAI21_X1 MUX2_X1 FA_X1 HA_X1
|
||||
TINV_X1 CLKGATETST_X1} {
|
||||
set cell [get_lib_cell NangateOpenCellLibrary/$cell_name]
|
||||
set area [get_property $cell area]
|
||||
puts "$cell_name area = $area"
|
||||
}
|
||||
|
||||
############################################################
|
||||
# Cell dont_use, is_macro, is_memory queries
|
||||
############################################################
|
||||
foreach cell_name {INV_X1 BUF_X1 DFF_X1 ANTENNA_X1 FILLCELL_X1} {
|
||||
set cell [get_lib_cell NangateOpenCellLibrary/$cell_name]
|
||||
set du [get_property $cell dont_use]
|
||||
puts "$cell_name dont_use = $du"
|
||||
}
|
||||
|
||||
############################################################
|
||||
# Leakage power queries
|
||||
############################################################
|
||||
|
||||
############################################################
|
||||
# Timing arc property queries
|
||||
# Exercises: arc direction, sense, timing_type
|
||||
############################################################
|
||||
|
||||
# Setup a design and run timing to exercise arc evaluation
|
||||
read_verilog ../../sdc/test/sdc_test2.v
|
||||
link_design sdc_test2
|
||||
create_clock -name clk1 -period 10 [get_ports clk1]
|
||||
create_clock -name clk2 -period 20 [get_ports clk2]
|
||||
set_input_delay -clock clk1 2.0 [get_ports {in1 in2 in3}]
|
||||
set_output_delay -clock clk1 3.0 [all_outputs]
|
||||
set_input_transition 0.1 [all_inputs]
|
||||
|
||||
# Detailed timing reports exercise arc evaluation
|
||||
report_checks -from [get_ports in1] -to [get_ports out1] -path_delay max
|
||||
|
||||
report_checks -from [get_ports in1] -to [get_ports out1] -path_delay min
|
||||
|
||||
report_checks -from [get_ports in2] -to [get_ports out2]
|
||||
|
||||
# Rise/fall reports exercise different arc transitions
|
||||
report_checks -rise_from [get_ports in1] -to [get_ports out1]
|
||||
|
||||
report_checks -fall_from [get_ports in1] -to [get_ports out1]
|
||||
|
||||
report_checks -from [get_ports in1] -rise_to [get_ports out1]
|
||||
|
||||
report_checks -from [get_ports in1] -fall_to [get_ports out1]
|
||||
|
||||
############################################################
|
||||
# Report check types exercises different check arc types
|
||||
############################################################
|
||||
report_check_types -max_delay -min_delay
|
||||
|
||||
report_check_types -max_slew -max_capacitance -max_fanout
|
||||
|
||||
report_check_types -recovery -removal
|
||||
|
||||
report_check_types -min_pulse_width -min_period
|
||||
|
||||
report_check_types -clock_gating_setup -clock_gating_hold
|
||||
|
||||
report_check_types -max_skew
|
||||
|
||||
############################################################
|
||||
# Report power to exercise internal power model paths
|
||||
############################################################
|
||||
report_power
|
||||
|
||||
report_power -instances [get_cells *]
|
||||
|
||||
############################################################
|
||||
# Sky130 cells - different tristate and latch cells
|
||||
############################################################
|
||||
read_liberty ../../test/sky130hd/sky130hd_tt.lib
|
||||
|
||||
# Tristate buffer
|
||||
report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__ebufn_1
|
||||
report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__ebufn_2
|
||||
report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__ebufn_4
|
||||
|
||||
# Latch cells
|
||||
report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxtp_1
|
||||
report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxtn_1
|
||||
|
||||
# Scan flip-flops
|
||||
report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfxtp_1
|
||||
report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfxbp_1
|
||||
|
||||
# DFF with async set/clear (exercises recovery/removal)
|
||||
report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfxtp_1
|
||||
report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfrtp_1
|
||||
report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfstp_1
|
||||
report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfbbp_1
|
||||
|
||||
# Mux cells
|
||||
report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__mux2_1
|
||||
report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__mux2i_1
|
||||
report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__mux4_1
|
||||
|
||||
############################################################
|
||||
# Write roundtrip to exercise all writer cell/arc/model paths
|
||||
############################################################
|
||||
set outfile [make_result_file liberty_cell_deep_write.lib]
|
||||
sta::write_liberty NangateOpenCellLibrary $outfile
|
||||
|
||||
# Verify file contents against static golden.
|
||||
diff_files liberty_cell_deep_write.libok $outfile
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,189 @@
|
|||
--- voltage_map / supply queries ---
|
||||
VPWR exists: 1
|
||||
VGND exists: 1
|
||||
VPB exists: 1
|
||||
VNB exists: 1
|
||||
KAPWR exists: 1
|
||||
LOWLVPWR exists: 1
|
||||
VPWRIN exists: 1
|
||||
VSS exists: 1
|
||||
FAKE_SUPPLY exists: 0
|
||||
--- clock gate cell queries ---
|
||||
sky130_fd_sc_hd__dlclkp_1 area=17.516800
|
||||
Cell sky130_fd_sc_hd__dlclkp_1
|
||||
Library sky130_fd_sc_hd__tt_025C_1v80
|
||||
File ../../test/sky130hd/sky130hd_tt.lib
|
||||
VGND ground
|
||||
VNB bias
|
||||
VPB bias
|
||||
VPWR power
|
||||
CLK input 0.00-0.00
|
||||
GATE input 0.00-0.00
|
||||
GCLK output
|
||||
M0 internal
|
||||
|
||||
Timing arcs
|
||||
CLK -> CLK
|
||||
width
|
||||
v -> ^
|
||||
CLK -> GATE
|
||||
setup
|
||||
^ -> ^
|
||||
^ -> v
|
||||
CLK -> GATE
|
||||
hold
|
||||
^ -> ^
|
||||
^ -> v
|
||||
CLK -> GCLK
|
||||
combinational
|
||||
^ -> ^
|
||||
v -> v
|
||||
sky130_fd_sc_hd__dlclkp_2 area=18.768000
|
||||
Cell sky130_fd_sc_hd__dlclkp_2
|
||||
Library sky130_fd_sc_hd__tt_025C_1v80
|
||||
File ../../test/sky130hd/sky130hd_tt.lib
|
||||
VGND ground
|
||||
VNB bias
|
||||
VPB bias
|
||||
VPWR power
|
||||
CLK input 0.00-0.00
|
||||
GATE input 0.00-0.00
|
||||
GCLK output
|
||||
M0 internal
|
||||
|
||||
Timing arcs
|
||||
CLK -> CLK
|
||||
width
|
||||
v -> ^
|
||||
CLK -> GATE
|
||||
setup
|
||||
^ -> ^
|
||||
^ -> v
|
||||
CLK -> GATE
|
||||
hold
|
||||
^ -> ^
|
||||
^ -> v
|
||||
CLK -> GCLK
|
||||
combinational
|
||||
^ -> ^
|
||||
v -> v
|
||||
sky130_fd_sc_hd__dlclkp_4 area=21.270399
|
||||
Cell sky130_fd_sc_hd__dlclkp_4
|
||||
Library sky130_fd_sc_hd__tt_025C_1v80
|
||||
File ../../test/sky130hd/sky130hd_tt.lib
|
||||
VGND ground
|
||||
VNB bias
|
||||
VPB bias
|
||||
VPWR power
|
||||
CLK input 0.00-0.01
|
||||
GATE input 0.00-0.00
|
||||
GCLK output
|
||||
M0 internal
|
||||
|
||||
Timing arcs
|
||||
CLK -> CLK
|
||||
width
|
||||
v -> ^
|
||||
CLK -> GATE
|
||||
setup
|
||||
^ -> ^
|
||||
^ -> v
|
||||
CLK -> GATE
|
||||
hold
|
||||
^ -> ^
|
||||
^ -> v
|
||||
CLK -> GCLK
|
||||
combinational
|
||||
^ -> ^
|
||||
v -> v
|
||||
sky130_fd_sc_hd__sdlclkp_1 area=18.768000
|
||||
VGND dir=ground func=
|
||||
VNB dir=bias func=
|
||||
VPB dir=bias func=
|
||||
VPWR dir=power func=
|
||||
CLK dir=input func=
|
||||
GATE dir=input func=
|
||||
GCLK dir=output func=
|
||||
M0 dir=internal func=
|
||||
SCE dir=input func=
|
||||
sky130_fd_sc_hd__sdlclkp_2 area=20.019199
|
||||
VGND dir=ground func=
|
||||
VNB dir=bias func=
|
||||
VPB dir=bias func=
|
||||
VPWR dir=power func=
|
||||
CLK dir=input func=
|
||||
GATE dir=input func=
|
||||
GCLK dir=output func=
|
||||
M0 dir=internal func=
|
||||
SCE dir=input func=
|
||||
sky130_fd_sc_hd__sdlclkp_4 area=22.521601
|
||||
VGND dir=ground func=
|
||||
VNB dir=bias func=
|
||||
VPB dir=bias func=
|
||||
VPWR dir=power func=
|
||||
CLK dir=input func=
|
||||
GATE dir=input func=
|
||||
GCLK dir=output func=
|
||||
M0 dir=internal func=
|
||||
SCE dir=input func=
|
||||
--- level shifter cell queries ---
|
||||
sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_1 area=35.033600
|
||||
A dir=input
|
||||
X dir=output
|
||||
sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_2 area=35.033600
|
||||
A dir=input
|
||||
X dir=output
|
||||
sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_4 area=40.038399
|
||||
A dir=input
|
||||
X dir=output
|
||||
sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_4 area=40.038399
|
||||
A dir=input
|
||||
X dir=output
|
||||
sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_1 area=35.033600
|
||||
A dir=input
|
||||
X dir=output
|
||||
sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_2 area=35.033600
|
||||
A dir=input
|
||||
X dir=output
|
||||
sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_4 area=40.038399
|
||||
A dir=input
|
||||
X dir=output
|
||||
--- pg_pin queries ---
|
||||
sky130_fd_sc_hd__inv_1: pwr_pins=4 signal_pins=2
|
||||
sky130_fd_sc_hd__buf_1: pwr_pins=4 signal_pins=2
|
||||
sky130_fd_sc_hd__nand2_1: pwr_pins=4 signal_pins=3
|
||||
sky130_fd_sc_hd__dfxtp_1: pwr_pins=4 signal_pins=5
|
||||
sky130_fd_sc_hd__dlclkp_1: pwr_pins=4 signal_pins=4
|
||||
sky130_fd_sc_hd__sdfxtp_1: pwr_pins=4 signal_pins=7
|
||||
--- clock gate timing arcs ---
|
||||
dlclkp_1 arc_sets = 4
|
||||
CLK -> CLK role=width
|
||||
CLK -> GATE role=setup
|
||||
CLK -> GATE role=hold
|
||||
CLK -> GCLK role=combinational
|
||||
sdlclkp_1 arc_sets = 6
|
||||
CLK -> CLK role=width
|
||||
CLK -> GATE role=setup
|
||||
CLK -> GATE role=hold
|
||||
CLK -> GCLK role=combinational
|
||||
CLK -> SCE role=setup
|
||||
CLK -> SCE role=hold
|
||||
--- level shifter timing arcs ---
|
||||
lsbuf_lh_hl_isowell_tap_1 arcs = 1
|
||||
A -> X role=combinational
|
||||
--- cell classification ---
|
||||
sky130_fd_sc_hd__inv_1: is_buffer=0 is_inverter=1 is_leaf=1
|
||||
sky130_fd_sc_hd__inv_2: is_buffer=0 is_inverter=1 is_leaf=1
|
||||
sky130_fd_sc_hd__buf_1: is_buffer=1 is_inverter=0 is_leaf=1
|
||||
sky130_fd_sc_hd__buf_2: is_buffer=1 is_inverter=0 is_leaf=1
|
||||
sky130_fd_sc_hd__clkinv_1: is_buffer=0 is_inverter=1 is_leaf=1
|
||||
sky130_fd_sc_hd__clkbuf_1: is_buffer=1 is_inverter=0 is_leaf=1
|
||||
sky130_fd_sc_hd__nand2_1: is_buffer=0 is_inverter=0 is_leaf=1
|
||||
sky130_fd_sc_hd__nor2_1: is_buffer=0 is_inverter=0 is_leaf=1
|
||||
sky130_fd_sc_hd__dfxtp_1: is_buffer=0 is_inverter=0 is_leaf=1
|
||||
sky130_fd_sc_hd__dlclkp_1: is_buffer=0 is_inverter=0 is_leaf=1
|
||||
IHP VDD exists: 0
|
||||
IHP sg13g2_inv_1: area=5.443200 buf=0 inv=1
|
||||
IHP sg13g2_buf_1: area=7.257600 buf=1 inv=0
|
||||
IHP sg13g2_nand2_1: area=7.257600 buf=0 inv=0
|
||||
IHP sg13g2_nor2_1: area=7.257600 buf=0 inv=0
|
||||
|
|
@ -0,0 +1,236 @@
|
|||
# Test clock gating cells, level shifter cells, pg_pin attributes,
|
||||
# voltage_map/supply_voltage queries, and related cell classification.
|
||||
source ../../test/helpers.tcl
|
||||
|
||||
############################################################
|
||||
# Read Sky130 library (has clock gate cells, level shifters, pg_pins)
|
||||
############################################################
|
||||
read_liberty ../../test/sky130hd/sky130hd_tt.lib
|
||||
|
||||
set lib [sta::find_liberty sky130_fd_sc_hd__tt_025C_1v80]
|
||||
|
||||
############################################################
|
||||
# Voltage map / supply voltage queries
|
||||
# Exercises: addSupplyVoltage, supplyVoltage, supplyExists
|
||||
############################################################
|
||||
puts "--- voltage_map / supply queries ---"
|
||||
|
||||
set vpwr_exists [sta::liberty_supply_exists VPWR]
|
||||
puts "VPWR exists: $vpwr_exists"
|
||||
|
||||
set vgnd_exists [sta::liberty_supply_exists VGND]
|
||||
puts "VGND exists: $vgnd_exists"
|
||||
|
||||
set vpb_exists [sta::liberty_supply_exists VPB]
|
||||
puts "VPB exists: $vpb_exists"
|
||||
|
||||
set vnb_exists [sta::liberty_supply_exists VNB]
|
||||
puts "VNB exists: $vnb_exists"
|
||||
|
||||
set kapwr_exists [sta::liberty_supply_exists KAPWR]
|
||||
puts "KAPWR exists: $kapwr_exists"
|
||||
|
||||
set lowlv_exists [sta::liberty_supply_exists LOWLVPWR]
|
||||
puts "LOWLVPWR exists: $lowlv_exists"
|
||||
|
||||
set vpwrin_exists [sta::liberty_supply_exists VPWRIN]
|
||||
puts "VPWRIN exists: $vpwrin_exists"
|
||||
|
||||
set vss_exists [sta::liberty_supply_exists VSS]
|
||||
puts "VSS exists: $vss_exists"
|
||||
|
||||
# Non-existent supply
|
||||
set fake_exists [sta::liberty_supply_exists FAKE_SUPPLY]
|
||||
puts "FAKE_SUPPLY exists: $fake_exists"
|
||||
|
||||
############################################################
|
||||
# Clock gate cell queries (exercises clock_gating_integrated_cell)
|
||||
# dlclkp cells have latch_posedge type
|
||||
############################################################
|
||||
puts "--- clock gate cell queries ---"
|
||||
|
||||
foreach cell_name {sky130_fd_sc_hd__dlclkp_1 sky130_fd_sc_hd__dlclkp_2
|
||||
sky130_fd_sc_hd__dlclkp_4} {
|
||||
set cell [get_lib_cell sky130_fd_sc_hd__tt_025C_1v80/$cell_name]
|
||||
if {$cell != "NULL" && $cell ne ""} {
|
||||
set area [get_property $cell area]
|
||||
puts "$cell_name area=$area"
|
||||
|
||||
# Report the cell to exercise arc enumeration
|
||||
report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/$cell_name
|
||||
}
|
||||
}
|
||||
|
||||
# sdlclkp cells have latch_posedge_precontrol type
|
||||
foreach cell_name {sky130_fd_sc_hd__sdlclkp_1 sky130_fd_sc_hd__sdlclkp_2
|
||||
sky130_fd_sc_hd__sdlclkp_4} {
|
||||
set cell [get_lib_cell sky130_fd_sc_hd__tt_025C_1v80/$cell_name]
|
||||
if {$cell != "NULL" && $cell ne ""} {
|
||||
set area [get_property $cell area]
|
||||
puts "$cell_name area=$area"
|
||||
|
||||
# Iterate ports to check clock_gate_* pin attributes
|
||||
set port_iter [$cell liberty_port_iterator]
|
||||
while {[$port_iter has_next]} {
|
||||
set port [$port_iter next]
|
||||
set dir [sta::liberty_port_direction $port]
|
||||
set func [$port function]
|
||||
puts " [get_name $port] dir=$dir func=$func"
|
||||
}
|
||||
$port_iter finish
|
||||
}
|
||||
}
|
||||
|
||||
############################################################
|
||||
# Level shifter cell queries
|
||||
# Exercises: visitIsLevelShifter, visitLevelShifterType
|
||||
############################################################
|
||||
puts "--- level shifter cell queries ---"
|
||||
|
||||
foreach cell_name {sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_1
|
||||
sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_2
|
||||
sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_4
|
||||
sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_4
|
||||
sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_1
|
||||
sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_2
|
||||
sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_4} {
|
||||
set cell [get_lib_cell sky130_fd_sc_hd__tt_025C_1v80/$cell_name]
|
||||
if {$cell != "NULL" && $cell ne ""} {
|
||||
set area [get_property $cell area]
|
||||
puts "$cell_name area=$area"
|
||||
|
||||
# Iterate ports
|
||||
set port_iter [$cell liberty_port_iterator]
|
||||
while {[$port_iter has_next]} {
|
||||
set port [$port_iter next]
|
||||
set dir [sta::liberty_port_direction $port]
|
||||
set is_pwr [$port is_pwr_gnd]
|
||||
if {!$is_pwr} {
|
||||
puts " [get_name $port] dir=$dir"
|
||||
}
|
||||
}
|
||||
$port_iter finish
|
||||
}
|
||||
}
|
||||
|
||||
############################################################
|
||||
# PG pin queries on various cells
|
||||
# Exercises: pg_pin parsing, isPwrGnd, voltage_name
|
||||
############################################################
|
||||
puts "--- pg_pin queries ---"
|
||||
|
||||
foreach cell_name {sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__buf_1
|
||||
sky130_fd_sc_hd__nand2_1 sky130_fd_sc_hd__dfxtp_1
|
||||
sky130_fd_sc_hd__dlclkp_1 sky130_fd_sc_hd__sdfxtp_1} {
|
||||
set cell [get_lib_cell sky130_fd_sc_hd__tt_025C_1v80/$cell_name]
|
||||
if {$cell != "NULL" && $cell ne ""} {
|
||||
set pwr_count 0
|
||||
set sig_count 0
|
||||
set port_iter [$cell liberty_port_iterator]
|
||||
while {[$port_iter has_next]} {
|
||||
set port [$port_iter next]
|
||||
set is_pwr [$port is_pwr_gnd]
|
||||
if {$is_pwr} {
|
||||
incr pwr_count
|
||||
} else {
|
||||
incr sig_count
|
||||
}
|
||||
}
|
||||
$port_iter finish
|
||||
puts "$cell_name: pwr_pins=$pwr_count signal_pins=$sig_count"
|
||||
}
|
||||
}
|
||||
|
||||
############################################################
|
||||
# Timing arc queries on clock gate cells
|
||||
# Exercises: timing_type for clock gate arcs
|
||||
############################################################
|
||||
puts "--- clock gate timing arcs ---"
|
||||
|
||||
set cell [get_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlclkp_1]
|
||||
if {$cell != "NULL" && $cell ne ""} {
|
||||
set arcs [$cell timing_arc_sets]
|
||||
set arc_count [llength $arcs]
|
||||
puts "dlclkp_1 arc_sets = $arc_count"
|
||||
foreach arc $arcs {
|
||||
set from_port [$arc from]
|
||||
set to_port [$arc to]
|
||||
set role [$arc role]
|
||||
puts " [$from_port bus_name] -> [$to_port bus_name] role=$role"
|
||||
}
|
||||
}
|
||||
|
||||
set cell [get_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdlclkp_1]
|
||||
if {$cell != "NULL" && $cell ne ""} {
|
||||
set arcs [$cell timing_arc_sets]
|
||||
set arc_count [llength $arcs]
|
||||
puts "sdlclkp_1 arc_sets = $arc_count"
|
||||
foreach arc $arcs {
|
||||
set from_port [$arc from]
|
||||
set to_port [$arc to]
|
||||
set role [$arc role]
|
||||
puts " [$from_port bus_name] -> [$to_port bus_name] role=$role"
|
||||
}
|
||||
}
|
||||
|
||||
############################################################
|
||||
# Timing arc queries on level shifter cells
|
||||
############################################################
|
||||
puts "--- level shifter timing arcs ---"
|
||||
|
||||
set cell [get_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_1]
|
||||
if {$cell != "NULL" && $cell ne ""} {
|
||||
set arcs [$cell timing_arc_sets]
|
||||
puts "lsbuf_lh_hl_isowell_tap_1 arcs = [llength $arcs]"
|
||||
foreach arc $arcs {
|
||||
set from_port [$arc from]
|
||||
set to_port [$arc to]
|
||||
set role [$arc role]
|
||||
puts " [$from_port bus_name] -> [$to_port bus_name] role=$role"
|
||||
}
|
||||
}
|
||||
|
||||
############################################################
|
||||
# Buffer/inverter classification on Sky130 cells
|
||||
############################################################
|
||||
puts "--- cell classification ---"
|
||||
|
||||
foreach cell_name {sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_2
|
||||
sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_2
|
||||
sky130_fd_sc_hd__clkinv_1 sky130_fd_sc_hd__clkbuf_1
|
||||
sky130_fd_sc_hd__nand2_1 sky130_fd_sc_hd__nor2_1
|
||||
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dlclkp_1} {
|
||||
set cell [get_lib_cell sky130_fd_sc_hd__tt_025C_1v80/$cell_name]
|
||||
if {$cell != "NULL" && $cell ne ""} {
|
||||
set is_buf [$cell is_buffer]
|
||||
set is_inv [$cell is_inverter]
|
||||
set is_leaf [$cell is_leaf]
|
||||
puts "$cell_name: is_buffer=$is_buf is_inverter=$is_inv is_leaf=$is_leaf"
|
||||
}
|
||||
}
|
||||
|
||||
############################################################
|
||||
# Write liberty for sky130 (exercises writer for pg_pin, level_shifter)
|
||||
############################################################
|
||||
set outfile [make_result_file liberty_clkgate_lvlshift_write.lib]
|
||||
sta::write_liberty sky130_fd_sc_hd__tt_025C_1v80 $outfile
|
||||
|
||||
############################################################
|
||||
# Read IHP library for more voltage_map / pg_pin coverage
|
||||
############################################################
|
||||
read_liberty ../../test/ihp-sg13g2/sg13g2_stdcell_typ_1p20V_25C.lib
|
||||
|
||||
# Check supply exists after IHP
|
||||
set ihp_vdd_exists [sta::liberty_supply_exists VDD]
|
||||
puts "IHP VDD exists: $ihp_vdd_exists"
|
||||
|
||||
# Query IHP cells
|
||||
foreach cell_name {sg13g2_inv_1 sg13g2_buf_1 sg13g2_nand2_1 sg13g2_nor2_1} {
|
||||
set cell [get_lib_cell sg13g2_stdcell_typ_1p20V_25C/$cell_name]
|
||||
if {$cell != "NULL" && $cell ne ""} {
|
||||
set area [get_property $cell area]
|
||||
set is_buf [$cell is_buffer]
|
||||
set is_inv [$cell is_inverter]
|
||||
puts "IHP $cell_name: area=$area buf=$is_buf inv=$is_inv"
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,59 @@
|
|||
library(test_ecsm_lib) {
|
||||
delay_model : table_lookup ;
|
||||
time_unit : "1ns" ;
|
||||
voltage_unit : "1V" ;
|
||||
current_unit : "1mA" ;
|
||||
capacitive_load_unit(1, ff) ;
|
||||
input_threshold_pct_rise : 50 ;
|
||||
output_threshold_pct_rise : 50 ;
|
||||
slew_lower_threshold_pct_rise : 20 ;
|
||||
slew_upper_threshold_pct_rise : 80 ;
|
||||
input_threshold_pct_fall : 50 ;
|
||||
output_threshold_pct_fall : 50 ;
|
||||
slew_lower_threshold_pct_fall : 20 ;
|
||||
slew_upper_threshold_pct_fall : 80 ;
|
||||
|
||||
lu_table_template(delay_template_2x2) {
|
||||
variable_1 : input_net_transition ;
|
||||
variable_2 : total_output_net_capacitance ;
|
||||
index_1("0.01, 0.1") ;
|
||||
index_2("0.001, 0.01") ;
|
||||
}
|
||||
|
||||
cell(ECSM1) {
|
||||
area : 2.0 ;
|
||||
pin(A) { direction : input ; capacitance : 0.01 ; }
|
||||
pin(Z) {
|
||||
direction : output ;
|
||||
function : "A" ;
|
||||
timing() {
|
||||
related_pin : "A" ;
|
||||
timing_sense : positive_unate ;
|
||||
cell_rise(delay_template_2x2) { values("0.01, 0.02", "0.03, 0.04") ; }
|
||||
cell_fall(delay_template_2x2) { values("0.01, 0.02", "0.03, 0.04") ; }
|
||||
rise_transition(delay_template_2x2) { values("0.01, 0.02", "0.03, 0.04") ; }
|
||||
fall_transition(delay_template_2x2) { values("0.01, 0.02", "0.03, 0.04") ; }
|
||||
ecsm_waveform() {}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
cell(ECSM2) {
|
||||
area : 2.0 ;
|
||||
pin(A) { direction : input ; capacitance : 0.01 ; }
|
||||
pin(Z) {
|
||||
direction : output ;
|
||||
function : "A" ;
|
||||
timing() {
|
||||
related_pin : "A" ;
|
||||
timing_sense : positive_unate ;
|
||||
cell_rise(delay_template_2x2) { values("0.01, 0.02", "0.03, 0.04") ; }
|
||||
cell_fall(delay_template_2x2) { values("0.01, 0.02", "0.03, 0.04") ; }
|
||||
rise_transition(delay_template_2x2) { values("0.01, 0.02", "0.03, 0.04") ; }
|
||||
fall_transition(delay_template_2x2) { values("0.01, 0.02", "0.03, 0.04") ; }
|
||||
ecsm_waveform_set() {}
|
||||
ecsm_capacitance() {}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
ecsm cell count: 2
|
||||
ecsm cell: ECSM1
|
||||
ecsm cell: ECSM2
|
||||
ecsm timing max: ok
|
||||
ecsm timing min: ok
|
||||
|
|
@ -0,0 +1,74 @@
|
|||
source ../../test/helpers.tcl
|
||||
|
||||
read_liberty liberty_ecsm.lib
|
||||
|
||||
set ecsm_src [open liberty_ecsm.lib r]
|
||||
set ecsm_text [read $ecsm_src]
|
||||
close $ecsm_src
|
||||
foreach token {ecsm_waveform ecsm_waveform_set ecsm_capacitance} {
|
||||
if {[string first $token $ecsm_text] < 0} {
|
||||
error "liberty_ecsm.lib is missing expected ECSM token '$token'"
|
||||
}
|
||||
}
|
||||
|
||||
set cell_names {}
|
||||
foreach cell [get_lib_cells test_ecsm_lib/*] {
|
||||
lappend cell_names [get_name $cell]
|
||||
}
|
||||
set cell_names [lsort $cell_names]
|
||||
puts "ecsm cell count: [llength $cell_names]"
|
||||
foreach cell_name $cell_names {
|
||||
puts "ecsm cell: $cell_name"
|
||||
}
|
||||
|
||||
if {$cell_names ne [list ECSM1 ECSM2]} {
|
||||
error "unexpected ECSM cell list: $cell_names"
|
||||
}
|
||||
|
||||
foreach cell_name $cell_names {
|
||||
set cell [get_lib_cell test_ecsm_lib/$cell_name]
|
||||
set arc_sets [$cell timing_arc_sets]
|
||||
if {[llength $arc_sets] == 0} {
|
||||
error "$cell_name has no timing arc sets"
|
||||
}
|
||||
|
||||
set arc_count 0
|
||||
foreach arc_set $arc_sets {
|
||||
incr arc_count [llength [$arc_set timing_arcs]]
|
||||
}
|
||||
if {$arc_count == 0} {
|
||||
error "$cell_name has no timing arcs"
|
||||
}
|
||||
}
|
||||
|
||||
# Verify ECSM-tagged library also participates in actual timing paths.
|
||||
read_verilog liberty_ecsm_test.v
|
||||
link_design liberty_ecsm_test
|
||||
|
||||
create_clock -name clk -period 10 [get_ports clk]
|
||||
set_input_delay -clock clk 1.0 [get_ports in1]
|
||||
set_output_delay -clock clk 1.0 [get_ports out1]
|
||||
|
||||
with_output_to_variable max_rep {
|
||||
report_checks -path_delay max -from [get_ports in1] -to [get_ports out1]
|
||||
}
|
||||
if {![regexp {Startpoint:\s+in1} $max_rep]
|
||||
|| ![regexp {Endpoint:\s+out1} $max_rep]
|
||||
|| ![regexp {u1/} $max_rep]
|
||||
|| ![regexp {u2/} $max_rep]
|
||||
|| ![regexp {slack} $max_rep]} {
|
||||
error "ECSM max timing report missing expected path content"
|
||||
}
|
||||
puts "ecsm timing max: ok"
|
||||
|
||||
with_output_to_variable min_rep {
|
||||
report_checks -path_delay min -from [get_ports in1] -to [get_ports out1]
|
||||
}
|
||||
if {![regexp {Startpoint:\s+in1} $min_rep]
|
||||
|| ![regexp {Endpoint:\s+out1} $min_rep]
|
||||
|| ![regexp {u1/} $min_rep]
|
||||
|| ![regexp {u2/} $min_rep]
|
||||
|| ![regexp {slack} $min_rep]} {
|
||||
error "ECSM min timing report missing expected path content"
|
||||
}
|
||||
puts "ecsm timing min: ok"
|
||||
|
|
@ -0,0 +1,19 @@
|
|||
module liberty_ecsm_test (
|
||||
input clk,
|
||||
input in1,
|
||||
output out1
|
||||
);
|
||||
|
||||
wire n1;
|
||||
|
||||
ECSM1 u1 (
|
||||
.A(in1),
|
||||
.Z(n1)
|
||||
);
|
||||
|
||||
ECSM2 u2 (
|
||||
.A(n1),
|
||||
.Z(out1)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,39 @@
|
|||
INV equiv count: 6
|
||||
BUF equiv count: 9
|
||||
NAND2 equiv count: 3
|
||||
NOR2 equiv count: 3
|
||||
AND2 equiv count: 3
|
||||
OR2 equiv count: 3
|
||||
DFF equiv count: 2
|
||||
DFFR equiv count: 2
|
||||
DFFS equiv count: 2
|
||||
AOI21 equiv count: 3
|
||||
OAI21 equiv count: 3
|
||||
MUX2 equiv count: 2
|
||||
SDFF equiv count: 2
|
||||
INV_X1 equiv INV_X2: 1
|
||||
BUF_X1 equiv BUF_X2: 1
|
||||
INV_X1 equiv BUF_X1: 0
|
||||
NAND2 equiv NOR2: 0
|
||||
DFF_X1 equiv DFF_X2: 1
|
||||
DFF_X1 equiv DFFR_X1: 0
|
||||
NAND2 equiv NAND3: 0
|
||||
INV_X4 equiv INV_X8: 1
|
||||
equiv_cell_ports INV_X1 INV_X2: 1
|
||||
equiv_cell_ports INV_X1 BUF_X1: 0
|
||||
equiv_cell_ports NAND2_X1 NAND2_X2: 1
|
||||
equiv_cell_ports NAND2_X1 NAND3_X1: 0
|
||||
equiv_cell_timing_arcs INV_X1 INV_X2: 1
|
||||
equiv_cell_timing_arcs BUF_X1 BUF_X2: 1
|
||||
equiv_cell_timing_arcs INV_X1 BUF_X1: 0
|
||||
library buffers count: 9
|
||||
find_liberty: NangateOpenCellLibrary
|
||||
supply VDD exists: 1
|
||||
supply VSS exists: 1
|
||||
supply NONEXISTENT exists: 0
|
||||
INV_X1/A direction: input
|
||||
INV_X1/ZN direction: output
|
||||
DFF_X1/CK direction: input
|
||||
DFF_X1/Q direction: output
|
||||
fast INV equiv count: 6
|
||||
INV_X1 (typ) equiv INV_X1 (fast): 1
|
||||
|
|
@ -0,0 +1,204 @@
|
|||
# Test equivalent cell finding for EquivCells.cc code coverage
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
|
||||
############################################################
|
||||
# make_equiv_cells / find_equiv_cells / equiv_cells
|
||||
############################################################
|
||||
|
||||
# Make equivalent cells for the Nangate library
|
||||
set lib [lindex [get_libs NangateOpenCellLibrary] 0]
|
||||
sta::make_equiv_cells $lib
|
||||
|
||||
# Find equiv cells for various cell types
|
||||
# INV_X1 should have equivalents (INV_X2, INV_X4, etc.)
|
||||
set inv_cell [get_lib_cell NangateOpenCellLibrary/INV_X1]
|
||||
set inv_equivs [sta::find_equiv_cells $inv_cell]
|
||||
puts "INV equiv count: [llength $inv_equivs]"
|
||||
|
||||
set buf_cell [get_lib_cell NangateOpenCellLibrary/BUF_X1]
|
||||
set buf_equivs [sta::find_equiv_cells $buf_cell]
|
||||
puts "BUF equiv count: [llength $buf_equivs]"
|
||||
|
||||
set nand_cell [get_lib_cell NangateOpenCellLibrary/NAND2_X1]
|
||||
set nand_equivs [sta::find_equiv_cells $nand_cell]
|
||||
puts "NAND2 equiv count: [llength $nand_equivs]"
|
||||
|
||||
set nor_cell [get_lib_cell NangateOpenCellLibrary/NOR2_X1]
|
||||
set nor_equivs [sta::find_equiv_cells $nor_cell]
|
||||
puts "NOR2 equiv count: [llength $nor_equivs]"
|
||||
|
||||
set and_cell [get_lib_cell NangateOpenCellLibrary/AND2_X1]
|
||||
set and_equivs [sta::find_equiv_cells $and_cell]
|
||||
puts "AND2 equiv count: [llength $and_equivs]"
|
||||
|
||||
set or_cell [get_lib_cell NangateOpenCellLibrary/OR2_X1]
|
||||
set or_equivs [sta::find_equiv_cells $or_cell]
|
||||
puts "OR2 equiv count: [llength $or_equivs]"
|
||||
|
||||
# DFF cells
|
||||
set dff_cell [get_lib_cell NangateOpenCellLibrary/DFF_X1]
|
||||
set dff_equivs [sta::find_equiv_cells $dff_cell]
|
||||
puts "DFF equiv count: [llength $dff_equivs]"
|
||||
|
||||
set dffr_cell [get_lib_cell NangateOpenCellLibrary/DFFR_X1]
|
||||
set dffr_equivs [sta::find_equiv_cells $dffr_cell]
|
||||
puts "DFFR equiv count: [llength $dffr_equivs]"
|
||||
|
||||
set dffs_cell [get_lib_cell NangateOpenCellLibrary/DFFS_X1]
|
||||
set dffs_equivs [sta::find_equiv_cells $dffs_cell]
|
||||
puts "DFFS equiv count: [llength $dffs_equivs]"
|
||||
|
||||
# AOI cells
|
||||
set aoi_cell [get_lib_cell NangateOpenCellLibrary/AOI21_X1]
|
||||
set aoi_equivs [sta::find_equiv_cells $aoi_cell]
|
||||
puts "AOI21 equiv count: [llength $aoi_equivs]"
|
||||
|
||||
# OAI cells
|
||||
set oai_cell [get_lib_cell NangateOpenCellLibrary/OAI21_X1]
|
||||
set oai_equivs [sta::find_equiv_cells $oai_cell]
|
||||
puts "OAI21 equiv count: [llength $oai_equivs]"
|
||||
|
||||
# MUX cells
|
||||
set mux_cell [get_lib_cell NangateOpenCellLibrary/MUX2_X1]
|
||||
set mux_equivs [sta::find_equiv_cells $mux_cell]
|
||||
puts "MUX2 equiv count: [llength $mux_equivs]"
|
||||
|
||||
# SDFF cells
|
||||
set sdff_cell [get_lib_cell NangateOpenCellLibrary/SDFF_X1]
|
||||
set sdff_equivs [sta::find_equiv_cells $sdff_cell]
|
||||
puts "SDFF equiv count: [llength $sdff_equivs]"
|
||||
|
||||
############################################################
|
||||
# equiv_cells comparison
|
||||
############################################################
|
||||
|
||||
# Same-function cells should be equivalent
|
||||
set inv_x1 [get_lib_cell NangateOpenCellLibrary/INV_X1]
|
||||
set inv_x2 [get_lib_cell NangateOpenCellLibrary/INV_X2]
|
||||
set result [sta::equiv_cells $inv_x1 $inv_x2]
|
||||
puts "INV_X1 equiv INV_X2: $result"
|
||||
|
||||
set buf_x1 [get_lib_cell NangateOpenCellLibrary/BUF_X1]
|
||||
set buf_x2 [get_lib_cell NangateOpenCellLibrary/BUF_X2]
|
||||
set result [sta::equiv_cells $buf_x1 $buf_x2]
|
||||
puts "BUF_X1 equiv BUF_X2: $result"
|
||||
|
||||
# Different-function cells should NOT be equivalent
|
||||
set result [sta::equiv_cells $inv_x1 $buf_x1]
|
||||
puts "INV_X1 equiv BUF_X1: $result"
|
||||
|
||||
set result [sta::equiv_cells $nand_cell $nor_cell]
|
||||
puts "NAND2 equiv NOR2: $result"
|
||||
|
||||
# DFF equivalence
|
||||
set dff_x1 [get_lib_cell NangateOpenCellLibrary/DFF_X1]
|
||||
set dff_x2 [get_lib_cell NangateOpenCellLibrary/DFF_X2]
|
||||
set result [sta::equiv_cells $dff_x1 $dff_x2]
|
||||
puts "DFF_X1 equiv DFF_X2: $result"
|
||||
|
||||
# DFF vs DFFR (different function - has reset)
|
||||
set result [sta::equiv_cells $dff_x1 $dffr_cell]
|
||||
puts "DFF_X1 equiv DFFR_X1: $result"
|
||||
|
||||
# NAND2 vs NAND3 (different port count)
|
||||
set nand3_cell [get_lib_cell NangateOpenCellLibrary/NAND3_X1]
|
||||
set result [sta::equiv_cells $nand_cell $nand3_cell]
|
||||
puts "NAND2 equiv NAND3: $result"
|
||||
|
||||
# Larger drive strengths
|
||||
set inv_x4 [get_lib_cell NangateOpenCellLibrary/INV_X4]
|
||||
set inv_x8 [get_lib_cell NangateOpenCellLibrary/INV_X8]
|
||||
set result [sta::equiv_cells $inv_x4 $inv_x8]
|
||||
puts "INV_X4 equiv INV_X8: $result"
|
||||
|
||||
############################################################
|
||||
# equiv_cell_ports comparison
|
||||
############################################################
|
||||
|
||||
set result [sta::equiv_cell_ports $inv_x1 $inv_x2]
|
||||
puts "equiv_cell_ports INV_X1 INV_X2: $result"
|
||||
|
||||
set result [sta::equiv_cell_ports $inv_x1 $buf_x1]
|
||||
puts "equiv_cell_ports INV_X1 BUF_X1: $result"
|
||||
|
||||
set nand2_x1 [get_lib_cell NangateOpenCellLibrary/NAND2_X1]
|
||||
set nand2_x2 [get_lib_cell NangateOpenCellLibrary/NAND2_X2]
|
||||
set result [sta::equiv_cell_ports $nand2_x1 $nand2_x2]
|
||||
puts "equiv_cell_ports NAND2_X1 NAND2_X2: $result"
|
||||
|
||||
# Different port count cells
|
||||
set nand3_x1 [get_lib_cell NangateOpenCellLibrary/NAND3_X1]
|
||||
set result [sta::equiv_cell_ports $nand2_x1 $nand3_x1]
|
||||
puts "equiv_cell_ports NAND2_X1 NAND3_X1: $result"
|
||||
|
||||
############################################################
|
||||
# equiv_cell_timing_arcs comparison
|
||||
############################################################
|
||||
|
||||
set result [sta::equiv_cell_timing_arcs $inv_x1 $inv_x2]
|
||||
puts "equiv_cell_timing_arcs INV_X1 INV_X2: $result"
|
||||
|
||||
set result [sta::equiv_cell_timing_arcs $buf_x1 $buf_x2]
|
||||
puts "equiv_cell_timing_arcs BUF_X1 BUF_X2: $result"
|
||||
|
||||
set result [sta::equiv_cell_timing_arcs $inv_x1 $buf_x1]
|
||||
puts "equiv_cell_timing_arcs INV_X1 BUF_X1: $result"
|
||||
|
||||
############################################################
|
||||
# find_library_buffers
|
||||
############################################################
|
||||
|
||||
set buffers [sta::find_library_buffers $lib]
|
||||
puts "library buffers count: [llength $buffers]"
|
||||
|
||||
############################################################
|
||||
# Additional library queries
|
||||
############################################################
|
||||
|
||||
set found_lib [sta::find_liberty NangateOpenCellLibrary]
|
||||
puts "find_liberty: [get_name $found_lib]"
|
||||
|
||||
set lib_iter [sta::liberty_library_iterator]
|
||||
|
||||
# liberty_supply_exists
|
||||
set result [sta::liberty_supply_exists VDD]
|
||||
puts "supply VDD exists: $result"
|
||||
|
||||
set result [sta::liberty_supply_exists VSS]
|
||||
puts "supply VSS exists: $result"
|
||||
|
||||
set result [sta::liberty_supply_exists NONEXISTENT]
|
||||
puts "supply NONEXISTENT exists: $result"
|
||||
|
||||
# liberty_port_direction on various pins
|
||||
set pin [get_lib_pin NangateOpenCellLibrary/INV_X1/A]
|
||||
set dir [sta::liberty_port_direction $pin]
|
||||
puts "INV_X1/A direction: $dir"
|
||||
|
||||
set pin [get_lib_pin NangateOpenCellLibrary/INV_X1/ZN]
|
||||
set dir [sta::liberty_port_direction $pin]
|
||||
puts "INV_X1/ZN direction: $dir"
|
||||
|
||||
set pin [get_lib_pin NangateOpenCellLibrary/DFF_X1/CK]
|
||||
set dir [sta::liberty_port_direction $pin]
|
||||
puts "DFF_X1/CK direction: $dir"
|
||||
|
||||
set pin [get_lib_pin NangateOpenCellLibrary/DFF_X1/Q]
|
||||
set dir [sta::liberty_port_direction $pin]
|
||||
puts "DFF_X1/Q direction: $dir"
|
||||
|
||||
############################################################
|
||||
# EquivCells across fast library
|
||||
############################################################
|
||||
|
||||
read_liberty ../../test/nangate45/Nangate45_fast.lib
|
||||
set fast_lib [lindex [get_libs NangateOpenCellLibrary_fast] 0]
|
||||
sta::make_equiv_cells $fast_lib
|
||||
|
||||
set fast_inv [get_lib_cell NangateOpenCellLibrary_fast/INV_X1]
|
||||
set fast_inv_equivs [sta::find_equiv_cells $fast_inv]
|
||||
puts "fast INV equiv count: [llength $fast_inv_equivs]"
|
||||
|
||||
# Cross-library equiv check
|
||||
set result [sta::equiv_cells $inv_x1 $fast_inv]
|
||||
puts "INV_X1 (typ) equiv INV_X1 (fast): $result"
|
||||
|
|
@ -0,0 +1,60 @@
|
|||
INVx1_ASAP7_75t_R equiv count = 21
|
||||
INVx2_ASAP7_75t_R equiv count = 21
|
||||
INVx3_ASAP7_75t_R equiv count = 21
|
||||
INVx4_ASAP7_75t_R equiv count = 21
|
||||
INVx5_ASAP7_75t_R equiv count = 21
|
||||
INVx8_ASAP7_75t_R equiv count = 21
|
||||
INVx11_ASAP7_75t_R equiv count = 21
|
||||
INVx13_ASAP7_75t_R equiv count = 21
|
||||
Warning 354: liberty_equiv_cross_lib.tcl line 1, cell 'INVx16_ASAP7_75t_R' not found.
|
||||
Warning 354: liberty_equiv_cross_lib.tcl line 1, cell 'BUFx1_ASAP7_75t_R' not found.
|
||||
BUFx2_ASAP7_75t_R equiv count = 16
|
||||
BUFx3_ASAP7_75t_R equiv count = 16
|
||||
BUFx4_ASAP7_75t_R equiv count = 16
|
||||
BUFx5_ASAP7_75t_R equiv count = 16
|
||||
BUFx8_ASAP7_75t_R equiv count = 16
|
||||
Warning 354: liberty_equiv_cross_lib.tcl line 1, cell 'BUFx11_ASAP7_75t_R' not found.
|
||||
Warning 354: liberty_equiv_cross_lib.tcl line 1, cell 'BUFx13_ASAP7_75t_R' not found.
|
||||
Warning 354: liberty_equiv_cross_lib.tcl line 1, cell 'BUFx16_ASAP7_75t_R' not found.
|
||||
LVT INVx1_ASAP7_75t_L equiv count = 21
|
||||
LVT INVx2_ASAP7_75t_L equiv count = 21
|
||||
LVT INVx4_ASAP7_75t_L equiv count = 21
|
||||
LVT INVx8_ASAP7_75t_L equiv count = 21
|
||||
Warning 354: liberty_equiv_cross_lib.tcl line 1, cell 'BUFx1_ASAP7_75t_L' not found.
|
||||
LVT BUFx2_ASAP7_75t_L equiv count = 16
|
||||
LVT BUFx4_ASAP7_75t_L equiv count = 16
|
||||
LVT BUFx8_ASAP7_75t_L equiv count = 16
|
||||
--- cross-Vt equiv comparisons ---
|
||||
equiv RVT/LVT INVx1 = 1
|
||||
port_equiv RVT/LVT INVx1 = 1
|
||||
arc_equiv RVT/LVT INVx1 = 1
|
||||
SEQ RVT DFFHQNx1 equiv count = 3
|
||||
equiv: DFFHQNx1_ASAP7_75t_R
|
||||
equiv: DFFHQNx2_ASAP7_75t_R
|
||||
equiv: DFFHQNx3_ASAP7_75t_R
|
||||
SEQ RVT ICGx1 equiv count = 10
|
||||
SEQ RVT DLLx1 equiv count = 3
|
||||
Warning 354: liberty_equiv_cross_lib.tcl line 1, cell 'SDFHQNx1_ASAP7_75t_R' not found.
|
||||
equiv SEQ RVT/LVT DFFHQNx1 = 1
|
||||
port_equiv SEQ RVT/LVT DFFHQNx1 = 1
|
||||
Sky130 inv_1 equiv count = 16
|
||||
equiv: sky130_fd_sc_hd__clkinvlp_2
|
||||
equiv: sky130_fd_sc_hd__inv_1
|
||||
equiv: sky130_fd_sc_hd__clkinv_1
|
||||
equiv: sky130_fd_sc_hd__clkinvlp_4
|
||||
equiv: sky130_fd_sc_hd__inv_2
|
||||
equiv: sky130_fd_sc_hd__clkinv_2
|
||||
equiv: sky130_fd_sc_hd__inv_4
|
||||
equiv: sky130_fd_sc_hd__inv_6
|
||||
equiv: sky130_fd_sc_hd__clkinv_4
|
||||
equiv: sky130_fd_sc_hd__bufinv_8
|
||||
equiv: sky130_fd_sc_hd__inv_8
|
||||
equiv: sky130_fd_sc_hd__clkinv_8
|
||||
equiv: sky130_fd_sc_hd__inv_12
|
||||
equiv: sky130_fd_sc_hd__bufinv_16
|
||||
equiv: sky130_fd_sc_hd__inv_16
|
||||
equiv: sky130_fd_sc_hd__clkinv_16
|
||||
Sky130 dfxtp_1 equiv count = 3
|
||||
equiv: sky130_fd_sc_hd__dfxtp_1
|
||||
equiv: sky130_fd_sc_hd__dfxtp_2
|
||||
equiv: sky130_fd_sc_hd__dfxtp_4
|
||||
|
|
@ -0,0 +1,187 @@
|
|||
# Test equivalent cells across multiple libraries from different PDKs,
|
||||
# exercising mapEquivCells and cross-library equivalence hashing.
|
||||
source ../../test/helpers.tcl
|
||||
|
||||
############################################################
|
||||
# Read multiple ASAP7 Vt flavors for cross-library equiv
|
||||
############################################################
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_INVBUF_RVT_FF_nldm_220122.lib.gz
|
||||
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_INVBUF_LVT_FF_nldm_220122.lib.gz
|
||||
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_INVBUF_SLVT_FF_nldm_220122.lib.gz
|
||||
|
||||
############################################################
|
||||
# Make equiv cells for RVT library
|
||||
############################################################
|
||||
set rvt_lib [lindex [get_libs asap7sc7p5t_INVBUF_RVT_FF_nldm_211120] 0]
|
||||
sta::make_equiv_cells $rvt_lib
|
||||
|
||||
# Find equiv cells in ASAP7 RVT
|
||||
foreach cell_prefix {INVx BUFx} {
|
||||
foreach size {1 2 3 4 5 8 11 13 16} {
|
||||
set cell_name "${cell_prefix}${size}_ASAP7_75t_R"
|
||||
set cell [get_lib_cell asap7sc7p5t_INVBUF_RVT_FF_nldm_211120/$cell_name]
|
||||
if {$cell != "NULL" && $cell ne ""} {
|
||||
set equivs [sta::find_equiv_cells $cell]
|
||||
if {$equivs != ""} {
|
||||
puts "$cell_name equiv count = [llength $equivs]"
|
||||
} else {
|
||||
puts "$cell_name equiv count = 0"
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
# Find library buffers
|
||||
set rvt_buffers [sta::find_library_buffers $rvt_lib]
|
||||
|
||||
############################################################
|
||||
# Make equiv cells for LVT library
|
||||
############################################################
|
||||
set lvt_lib [lindex [get_libs asap7sc7p5t_INVBUF_LVT_FF_nldm_211120] 0]
|
||||
sta::make_equiv_cells $lvt_lib
|
||||
|
||||
foreach cell_prefix {INVx BUFx} {
|
||||
foreach size {1 2 4 8} {
|
||||
set cell_name "${cell_prefix}${size}_ASAP7_75t_L"
|
||||
set cell [get_lib_cell asap7sc7p5t_INVBUF_LVT_FF_nldm_211120/$cell_name]
|
||||
if {$cell != "NULL" && $cell ne ""} {
|
||||
set equivs [sta::find_equiv_cells $cell]
|
||||
if {$equivs != ""} {
|
||||
puts "LVT $cell_name equiv count = [llength $equivs]"
|
||||
} else {
|
||||
puts "LVT $cell_name equiv count = 0"
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
set lvt_buffers [sta::find_library_buffers $lvt_lib]
|
||||
|
||||
############################################################
|
||||
# Make equiv cells for SLVT library
|
||||
############################################################
|
||||
set slvt_lib [lindex [get_libs asap7sc7p5t_INVBUF_SLVT_FF_nldm_211120] 0]
|
||||
sta::make_equiv_cells $slvt_lib
|
||||
|
||||
set slvt_buffers [sta::find_library_buffers $slvt_lib]
|
||||
|
||||
############################################################
|
||||
# Cross-Vt equiv_cells comparisons
|
||||
############################################################
|
||||
puts "--- cross-Vt equiv comparisons ---"
|
||||
|
||||
# RVT vs LVT (different cell name suffix -> not equiv)
|
||||
set rvt_inv [get_lib_cell asap7sc7p5t_INVBUF_RVT_FF_nldm_211120/INVx1_ASAP7_75t_R]
|
||||
set lvt_inv [get_lib_cell asap7sc7p5t_INVBUF_LVT_FF_nldm_211120/INVx1_ASAP7_75t_L]
|
||||
set result [sta::equiv_cells $rvt_inv $lvt_inv]
|
||||
puts "equiv RVT/LVT INVx1 = $result"
|
||||
set result [sta::equiv_cell_ports $rvt_inv $lvt_inv]
|
||||
puts "port_equiv RVT/LVT INVx1 = $result"
|
||||
set result [sta::equiv_cell_timing_arcs $rvt_inv $lvt_inv]
|
||||
puts "arc_equiv RVT/LVT INVx1 = $result"
|
||||
|
||||
############################################################
|
||||
# Read ASAP7 SEQ libraries for sequential equiv
|
||||
############################################################
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_SEQ_RVT_FF_nldm_220123.lib
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_SEQ_LVT_FF_nldm_220123.lib
|
||||
|
||||
set seq_rvt_lib [lindex [get_libs asap7sc7p5t_SEQ_RVT_FF_nldm_220123] 0]
|
||||
sta::make_equiv_cells $seq_rvt_lib
|
||||
|
||||
# Find equiv cells for DFF cells
|
||||
set dff [get_lib_cell asap7sc7p5t_SEQ_RVT_FF_nldm_220123/DFFHQNx1_ASAP7_75t_R]
|
||||
if {$dff != "NULL" && $dff ne ""} {
|
||||
set equivs [sta::find_equiv_cells $dff]
|
||||
if {$equivs != ""} {
|
||||
puts "SEQ RVT DFFHQNx1 equiv count = [llength $equivs]"
|
||||
foreach eq $equivs {
|
||||
puts " equiv: [$eq name]"
|
||||
}
|
||||
} else {
|
||||
puts "SEQ RVT DFFHQNx1 equiv count = 0"
|
||||
}
|
||||
}
|
||||
|
||||
# ICG equiv cells
|
||||
set icg [get_lib_cell asap7sc7p5t_SEQ_RVT_FF_nldm_220123/ICGx1_ASAP7_75t_R]
|
||||
if {$icg != "NULL" && $icg ne ""} {
|
||||
set equivs [sta::find_equiv_cells $icg]
|
||||
if {$equivs != ""} {
|
||||
puts "SEQ RVT ICGx1 equiv count = [llength $equivs]"
|
||||
} else {
|
||||
puts "SEQ RVT ICGx1 equiv count = 0"
|
||||
}
|
||||
}
|
||||
|
||||
# Latch equiv cells
|
||||
set dll [get_lib_cell asap7sc7p5t_SEQ_RVT_FF_nldm_220123/DLLx1_ASAP7_75t_R]
|
||||
if {$dll != "NULL" && $dll ne ""} {
|
||||
set equivs [sta::find_equiv_cells $dll]
|
||||
if {$equivs != ""} {
|
||||
puts "SEQ RVT DLLx1 equiv count = [llength $equivs]"
|
||||
} else {
|
||||
puts "SEQ RVT DLLx1 equiv count = 0"
|
||||
}
|
||||
}
|
||||
|
||||
# SDFF equiv cells
|
||||
set sdff [get_lib_cell asap7sc7p5t_SEQ_RVT_FF_nldm_220123/SDFHQNx1_ASAP7_75t_R]
|
||||
if {$sdff != "NULL" && $sdff ne ""} {
|
||||
set equivs [sta::find_equiv_cells $sdff]
|
||||
if {$equivs != ""} {
|
||||
puts "SEQ RVT SDFHQNx1 equiv count = [llength $equivs]"
|
||||
} else {
|
||||
puts "SEQ RVT SDFHQNx1 equiv count = 0"
|
||||
}
|
||||
}
|
||||
|
||||
############################################################
|
||||
# Cross-library comparisons of DFF cells
|
||||
############################################################
|
||||
set rvt_dff [get_lib_cell asap7sc7p5t_SEQ_RVT_FF_nldm_220123/DFFHQNx1_ASAP7_75t_R]
|
||||
set lvt_dff [get_lib_cell asap7sc7p5t_SEQ_LVT_FF_nldm_220123/DFFHQNx1_ASAP7_75t_L]
|
||||
set result [sta::equiv_cells $rvt_dff $lvt_dff]
|
||||
puts "equiv SEQ RVT/LVT DFFHQNx1 = $result"
|
||||
set result [sta::equiv_cell_ports $rvt_dff $lvt_dff]
|
||||
puts "port_equiv SEQ RVT/LVT DFFHQNx1 = $result"
|
||||
|
||||
############################################################
|
||||
# Read Sky130 and make equiv cells for a very different PDK
|
||||
############################################################
|
||||
read_liberty ../../test/sky130hd/sky130hd_tt.lib
|
||||
|
||||
set sky_lib [lindex [get_libs sky130_fd_sc_hd__tt_025C_1v80] 0]
|
||||
sta::make_equiv_cells $sky_lib
|
||||
|
||||
# Find equiv cells for Sky130 inverters
|
||||
set sky_inv [get_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__inv_1]
|
||||
if {$sky_inv != "NULL" && $sky_inv ne ""} {
|
||||
set equivs [sta::find_equiv_cells $sky_inv]
|
||||
if {$equivs != ""} {
|
||||
puts "Sky130 inv_1 equiv count = [llength $equivs]"
|
||||
foreach eq $equivs {
|
||||
puts " equiv: [$eq name]"
|
||||
}
|
||||
} else {
|
||||
puts "Sky130 inv_1 equiv count = 0"
|
||||
}
|
||||
}
|
||||
|
||||
# Find equiv for Sky130 DFF
|
||||
set sky_dff [get_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfxtp_1]
|
||||
if {$sky_dff != "NULL" && $sky_dff ne ""} {
|
||||
set equivs [sta::find_equiv_cells $sky_dff]
|
||||
if {$equivs != ""} {
|
||||
puts "Sky130 dfxtp_1 equiv count = [llength $equivs]"
|
||||
foreach eq $equivs {
|
||||
puts " equiv: [$eq name]"
|
||||
}
|
||||
} else {
|
||||
puts "Sky130 dfxtp_1 equiv count = 0"
|
||||
}
|
||||
}
|
||||
|
||||
set sky_buffers [sta::find_library_buffers $sky_lib]
|
||||
|
|
@ -0,0 +1,70 @@
|
|||
INV_X1 equiv count = 6
|
||||
equiv: INV_X1
|
||||
equiv: INV_X2
|
||||
equiv: INV_X4
|
||||
equiv: INV_X8
|
||||
equiv: INV_X16
|
||||
equiv: INV_X32
|
||||
BUF_X1 equiv count = 9
|
||||
equiv: BUF_X1
|
||||
equiv: CLKBUF_X1
|
||||
equiv: BUF_X2
|
||||
equiv: CLKBUF_X2
|
||||
equiv: CLKBUF_X3
|
||||
equiv: BUF_X4
|
||||
equiv: BUF_X8
|
||||
equiv: BUF_X16
|
||||
equiv: BUF_X32
|
||||
NAND2_X1 equiv count = 3
|
||||
NOR2_X1 equiv count = 3
|
||||
AND2_X1 equiv count = 3
|
||||
OR2_X1 equiv count = 3
|
||||
XOR2_X1 equiv count = 2
|
||||
XNOR2_X1 equiv count = 2
|
||||
NAND3_X1 equiv count = 3
|
||||
NOR3_X1 equiv count = 3
|
||||
AND3_X1 equiv count = 3
|
||||
OR3_X1 equiv count = 3
|
||||
NAND4_X1 equiv count = 3
|
||||
NOR4_X1 equiv count = 3
|
||||
AND4_X1 equiv count = 3
|
||||
OR4_X1 equiv count = 3
|
||||
AOI21_X1 equiv count = 3
|
||||
OAI21_X1 equiv count = 3
|
||||
AOI22_X1 equiv count = 3
|
||||
OAI22_X1 equiv count = 3
|
||||
AOI211_X1 equiv count = 2
|
||||
OAI211_X1 equiv count = 3
|
||||
MUX2_X1 equiv count = 2
|
||||
DFF_X1 equiv count = 2
|
||||
equiv: DFF_X1
|
||||
equiv: DFF_X2
|
||||
DFFR_X1 equiv count = 2
|
||||
DFFS_X1 equiv count = 2
|
||||
SDFF_X1 equiv count = 2
|
||||
equiv INV BUF = 0
|
||||
equiv INV NAND = 0
|
||||
equiv NAND NOR = 0
|
||||
equiv INV DFF = 0
|
||||
port_equiv INV_X1 INV_X2 = 1
|
||||
port_equiv INV_X1 BUF_X1 = 0
|
||||
port_equiv NAND2_X1 NAND2_X2 = 1
|
||||
arc_equiv INV_X1 INV_X2 = 1
|
||||
arc_equiv INV_X1 BUF_X1 = 0
|
||||
arc_equiv DFF_X1 DFF_X2 = 1
|
||||
arc_equiv DFF_X1 DFFR_X1 = 0
|
||||
equiv typ_INV fast_INV = 1
|
||||
equiv typ_INV fast_BUF = 0
|
||||
port_equiv typ_INV fast_INV = 1
|
||||
arc_equiv typ_INV fast_INV = 1
|
||||
fast INV_X1 equiv count = 6
|
||||
Library buffers count = 9
|
||||
buffer: BUF_X1
|
||||
buffer: BUF_X16
|
||||
buffer: BUF_X2
|
||||
buffer: BUF_X32
|
||||
buffer: BUF_X4
|
||||
buffer: BUF_X8
|
||||
buffer: CLKBUF_X1
|
||||
buffer: CLKBUF_X2
|
||||
buffer: CLKBUF_X3
|
||||
|
|
@ -0,0 +1,156 @@
|
|||
# Deep equivalent cell testing for EquivCells.cc code coverage.
|
||||
# Targets:
|
||||
# EquivCells.cc: findEquivCells, mapEquivCells,
|
||||
# hashCell, hashCellPorts, hashCellSequentials, hashSequential,
|
||||
# hashFuncExpr, hashPort, hashStatetable, hashStatetableRow,
|
||||
# equivCells, equivCellPorts, equivCellFuncs, equivCellSequentials,
|
||||
# equivCellStatetables, equivCellTimingArcSets, equivCellsArcs,
|
||||
# cellHasFuncs, cellDriveResistance, CellDriveResistanceGreater
|
||||
# Liberty.cc: Sequential related, Statetable related,
|
||||
# LibertyPort::equiv, FuncExpr::equiv
|
||||
source ../../test/helpers.tcl
|
||||
|
||||
############################################################
|
||||
# Read Nangate library
|
||||
############################################################
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
|
||||
set lib [lindex [get_libs NangateOpenCellLibrary] 0]
|
||||
|
||||
############################################################
|
||||
# Make equiv cells
|
||||
############################################################
|
||||
sta::make_equiv_cells $lib
|
||||
|
||||
############################################################
|
||||
# Test equiv cells for all major gate families
|
||||
############################################################
|
||||
|
||||
# Inverters (should find INV_X1/X2/X4/X8/X16/X32 as equivalent)
|
||||
set inv_x1 [get_lib_cell NangateOpenCellLibrary/INV_X1]
|
||||
set equivs [sta::find_equiv_cells $inv_x1]
|
||||
puts "INV_X1 equiv count = [llength $equivs]"
|
||||
foreach eq $equivs {
|
||||
puts " equiv: [$eq name]"
|
||||
}
|
||||
|
||||
# Buffers
|
||||
set buf_x1 [get_lib_cell NangateOpenCellLibrary/BUF_X1]
|
||||
set equivs [sta::find_equiv_cells $buf_x1]
|
||||
puts "BUF_X1 equiv count = [llength $equivs]"
|
||||
foreach eq $equivs {
|
||||
puts " equiv: [$eq name]"
|
||||
}
|
||||
|
||||
# 2-input gates
|
||||
foreach gate {NAND2 NOR2 AND2 OR2 XOR2 XNOR2} {
|
||||
set cell [get_lib_cell NangateOpenCellLibrary/${gate}_X1]
|
||||
set equivs [sta::find_equiv_cells $cell]
|
||||
puts "${gate}_X1 equiv count = [llength $equivs]"
|
||||
}
|
||||
|
||||
# 3-input gates
|
||||
foreach gate {NAND3 NOR3 AND3 OR3} {
|
||||
set cell [get_lib_cell NangateOpenCellLibrary/${gate}_X1]
|
||||
set equivs [sta::find_equiv_cells $cell]
|
||||
puts "${gate}_X1 equiv count = [llength $equivs]"
|
||||
}
|
||||
|
||||
# 4-input gates
|
||||
foreach gate {NAND4 NOR4 AND4 OR4} {
|
||||
set cell [get_lib_cell NangateOpenCellLibrary/${gate}_X1]
|
||||
set equivs [sta::find_equiv_cells $cell]
|
||||
puts "${gate}_X1 equiv count = [llength $equivs]"
|
||||
}
|
||||
|
||||
# AOI/OAI gates
|
||||
foreach gate {AOI21 OAI21 AOI22 OAI22 AOI211 OAI211} {
|
||||
set cell [get_lib_cell NangateOpenCellLibrary/${gate}_X1]
|
||||
set equivs [sta::find_equiv_cells $cell]
|
||||
puts "${gate}_X1 equiv count = [llength $equivs]"
|
||||
}
|
||||
|
||||
# MUX cells
|
||||
set mux_cell [get_lib_cell NangateOpenCellLibrary/MUX2_X1]
|
||||
set equivs [sta::find_equiv_cells $mux_cell]
|
||||
puts "MUX2_X1 equiv count = [llength $equivs]"
|
||||
|
||||
# DFF cells (sequential equivalence)
|
||||
set dff_x1 [get_lib_cell NangateOpenCellLibrary/DFF_X1]
|
||||
set dff_equivs [sta::find_equiv_cells $dff_x1]
|
||||
puts "DFF_X1 equiv count = [llength $dff_equivs]"
|
||||
foreach eq $dff_equivs {
|
||||
puts " equiv: [$eq name]"
|
||||
}
|
||||
|
||||
# DFFR cells (reset flip-flop)
|
||||
set dffr_x1 [get_lib_cell NangateOpenCellLibrary/DFFR_X1]
|
||||
set dffr_equivs [sta::find_equiv_cells $dffr_x1]
|
||||
puts "DFFR_X1 equiv count = [llength $dffr_equivs]"
|
||||
|
||||
# DFFS cells (set flip-flop)
|
||||
set dffs_x1 [get_lib_cell NangateOpenCellLibrary/DFFS_X1]
|
||||
set dffs_equivs [sta::find_equiv_cells $dffs_x1]
|
||||
puts "DFFS_X1 equiv count = [llength $dffs_equivs]"
|
||||
|
||||
# SDFF cells (scan DFF)
|
||||
set sdff_x1 [get_lib_cell NangateOpenCellLibrary/SDFF_X1]
|
||||
set sdff_equivs [sta::find_equiv_cells $sdff_x1]
|
||||
puts "SDFF_X1 equiv count = [llength $sdff_equivs]"
|
||||
|
||||
############################################################
|
||||
# Cross-cell type equiv comparisons (should be false)
|
||||
############################################################
|
||||
set inv_x1 [get_lib_cell NangateOpenCellLibrary/INV_X1]
|
||||
set buf_x1 [get_lib_cell NangateOpenCellLibrary/BUF_X1]
|
||||
set nand2_x1 [get_lib_cell NangateOpenCellLibrary/NAND2_X1]
|
||||
set nor2_x1 [get_lib_cell NangateOpenCellLibrary/NOR2_X1]
|
||||
set dff_x1 [get_lib_cell NangateOpenCellLibrary/DFF_X1]
|
||||
|
||||
# Pairwise comparisons that should be false
|
||||
puts "equiv INV BUF = [sta::equiv_cells $inv_x1 $buf_x1]"
|
||||
puts "equiv INV NAND = [sta::equiv_cells $inv_x1 $nand2_x1]"
|
||||
puts "equiv NAND NOR = [sta::equiv_cells $nand2_x1 $nor2_x1]"
|
||||
puts "equiv INV DFF = [sta::equiv_cells $inv_x1 $dff_x1]"
|
||||
|
||||
# Port equivalence detailed
|
||||
puts "port_equiv INV_X1 INV_X2 = [sta::equiv_cell_ports $inv_x1 [get_lib_cell NangateOpenCellLibrary/INV_X2]]"
|
||||
puts "port_equiv INV_X1 BUF_X1 = [sta::equiv_cell_ports $inv_x1 $buf_x1]"
|
||||
puts "port_equiv NAND2_X1 NAND2_X2 = [sta::equiv_cell_ports $nand2_x1 [get_lib_cell NangateOpenCellLibrary/NAND2_X2]]"
|
||||
|
||||
# Timing arc equivalence
|
||||
puts "arc_equiv INV_X1 INV_X2 = [sta::equiv_cell_timing_arcs $inv_x1 [get_lib_cell NangateOpenCellLibrary/INV_X2]]"
|
||||
puts "arc_equiv INV_X1 BUF_X1 = [sta::equiv_cell_timing_arcs $inv_x1 $buf_x1]"
|
||||
puts "arc_equiv DFF_X1 DFF_X2 = [sta::equiv_cell_timing_arcs $dff_x1 [get_lib_cell NangateOpenCellLibrary/DFF_X2]]"
|
||||
puts "arc_equiv DFF_X1 DFFR_X1 = [sta::equiv_cell_timing_arcs $dff_x1 $dffr_x1]"
|
||||
|
||||
############################################################
|
||||
# Multi-library equivalence (exercises mapEquivCells)
|
||||
############################################################
|
||||
read_liberty ../../test/nangate45/Nangate45_fast.lib
|
||||
|
||||
set fast_lib [lindex [get_libs NangateOpenCellLibrary_fast] 0]
|
||||
sta::make_equiv_cells $fast_lib
|
||||
|
||||
# Cross-library comparisons
|
||||
set fast_inv [get_lib_cell NangateOpenCellLibrary_fast/INV_X1]
|
||||
set fast_buf [get_lib_cell NangateOpenCellLibrary_fast/BUF_X1]
|
||||
|
||||
puts "equiv typ_INV fast_INV = [sta::equiv_cells $inv_x1 $fast_inv]"
|
||||
puts "equiv typ_INV fast_BUF = [sta::equiv_cells $inv_x1 $fast_buf]"
|
||||
puts "port_equiv typ_INV fast_INV = [sta::equiv_cell_ports $inv_x1 $fast_inv]"
|
||||
puts "arc_equiv typ_INV fast_INV = [sta::equiv_cell_timing_arcs $inv_x1 $fast_inv]"
|
||||
|
||||
# Find equiv cells in the fast library
|
||||
set fast_equivs [sta::find_equiv_cells $fast_inv]
|
||||
puts "fast INV_X1 equiv count = [llength $fast_equivs]"
|
||||
|
||||
############################################################
|
||||
# Find library buffers
|
||||
############################################################
|
||||
set lib [lindex [get_libs NangateOpenCellLibrary] 0]
|
||||
set buffers [sta::find_library_buffers $lib]
|
||||
puts "Library buffers count = [llength $buffers]"
|
||||
foreach buf $buffers {
|
||||
puts " buffer: [$buf name]"
|
||||
}
|
||||
|
|
@ -0,0 +1,168 @@
|
|||
INV_X1 equiv=6
|
||||
INV_X2 equiv=6
|
||||
INV_X4 equiv=6
|
||||
INV_X8 equiv=6
|
||||
INV_X16 equiv=6
|
||||
INV_X32 equiv=6
|
||||
BUF_X1 equiv=9
|
||||
BUF_X2 equiv=9
|
||||
BUF_X4 equiv=9
|
||||
BUF_X8 equiv=9
|
||||
BUF_X16 equiv=9
|
||||
BUF_X32 equiv=9
|
||||
NAND2_X1 equiv=3
|
||||
NAND2_X2 equiv=3
|
||||
NAND2_X4 equiv=3
|
||||
NOR2_X1 equiv=3
|
||||
NOR2_X2 equiv=3
|
||||
NOR2_X4 equiv=3
|
||||
AND2_X1 equiv=3
|
||||
AND2_X2 equiv=3
|
||||
AND2_X4 equiv=3
|
||||
OR2_X1 equiv=3
|
||||
OR2_X2 equiv=3
|
||||
OR2_X4 equiv=3
|
||||
NAND3_X1 equiv=3
|
||||
NAND3_X2 equiv=3
|
||||
NAND3_X4 equiv=3
|
||||
NOR3_X1 equiv=3
|
||||
NOR3_X2 equiv=3
|
||||
NOR3_X4 equiv=3
|
||||
AND3_X1 equiv=3
|
||||
AND3_X2 equiv=3
|
||||
AND3_X4 equiv=3
|
||||
OR3_X1 equiv=3
|
||||
OR3_X2 equiv=3
|
||||
OR3_X4 equiv=3
|
||||
NAND4_X1 equiv=3
|
||||
NAND4_X2 equiv=3
|
||||
NAND4_X4 equiv=3
|
||||
NOR4_X1 equiv=3
|
||||
NOR4_X2 equiv=3
|
||||
NOR4_X4 equiv=3
|
||||
AND4_X1 equiv=3
|
||||
AND4_X2 equiv=3
|
||||
AND4_X4 equiv=3
|
||||
OR4_X1 equiv=3
|
||||
OR4_X2 equiv=3
|
||||
OR4_X4 equiv=3
|
||||
XOR2_X1 equiv=2
|
||||
XOR2_X2 equiv=2
|
||||
XNOR2_X1 equiv=2
|
||||
XNOR2_X2 equiv=2
|
||||
AOI21_X1 equiv=3
|
||||
AOI21_X2 equiv=3
|
||||
AOI21_X4 equiv=3
|
||||
OAI21_X1 equiv=3
|
||||
OAI21_X2 equiv=3
|
||||
OAI21_X4 equiv=3
|
||||
AOI22_X1 equiv=3
|
||||
AOI22_X2 equiv=3
|
||||
AOI22_X4 equiv=3
|
||||
OAI22_X1 equiv=3
|
||||
OAI22_X2 equiv=3
|
||||
OAI22_X4 equiv=3
|
||||
AOI211_X1 equiv=2
|
||||
AOI211_X2 equiv=2
|
||||
OAI211_X1 equiv=3
|
||||
OAI211_X2 equiv=3
|
||||
OAI211_X4 equiv=3
|
||||
MUX2_X1 equiv=2
|
||||
MUX2_X2 equiv=2
|
||||
DFF_X1 equiv=2
|
||||
DFF_X2 equiv=2
|
||||
DFFR_X1 equiv=2
|
||||
DFFR_X2 equiv=2
|
||||
DFFS_X1 equiv=2
|
||||
DFFS_X2 equiv=2
|
||||
DFFRS_X1 equiv=2
|
||||
DFFRS_X2 equiv=2
|
||||
SDFF_X1 equiv=2
|
||||
SDFF_X2 equiv=2
|
||||
SDFFR_X1 equiv=2
|
||||
SDFFR_X2 equiv=2
|
||||
SDFFS_X1 equiv=2
|
||||
SDFFS_X2 equiv=2
|
||||
SDFFRS_X1 equiv=2
|
||||
SDFFRS_X2 equiv=2
|
||||
CLKBUF_X1 equiv=9
|
||||
CLKBUF_X2 equiv=9
|
||||
CLKBUF_X3 equiv=9
|
||||
CLKGATETST_X1 equiv=4
|
||||
CLKGATETST_X2 equiv=4
|
||||
CLKGATETST_X4 equiv=4
|
||||
CLKGATETST_X8 equiv=4
|
||||
equiv INV_X1 INV_X2 = 1
|
||||
equiv BUF_X1 BUF_X2 = 1
|
||||
equiv NAND2_X1 NAND2_X2 = 1
|
||||
equiv NOR2_X1 NOR2_X2 = 1
|
||||
equiv DFF_X1 DFF_X2 = 1
|
||||
equiv CLKGATE_X1 CLKGATE_X2 = 1
|
||||
equiv INV BUF = 0
|
||||
equiv NAND2 NOR2 = 0
|
||||
equiv NAND2 NAND3 = 0
|
||||
equiv AND2 OR2 = 0
|
||||
equiv DFF DFFR = 0
|
||||
equiv DFF SDFF = 0
|
||||
equiv INV DFF = 0
|
||||
equiv INV CLKGATE = 0
|
||||
ports INV_X1 INV_X2 = 1
|
||||
ports INV BUF = 0
|
||||
ports NAND2_X1 NAND2_X2 = 1
|
||||
ports NAND2 NAND3 = 0
|
||||
ports DFF_X1 DFF_X2 = 1
|
||||
ports DFF DFFR = 0
|
||||
arcs INV_X1 INV_X2 = 1
|
||||
arcs INV BUF = 0
|
||||
arcs DFF_X1 DFF_X2 = 1
|
||||
arcs DFF DFFR = 0
|
||||
arcs NAND2_X1 NAND2_X2 = 1
|
||||
arcs NAND2 NOR2 = 1
|
||||
Nangate45 buffers = 9
|
||||
SKY sky130_fd_sc_hd__inv_1 equiv=16
|
||||
SKY sky130_fd_sc_hd__inv_2 equiv=16
|
||||
SKY sky130_fd_sc_hd__inv_4 equiv=16
|
||||
SKY sky130_fd_sc_hd__inv_8 equiv=16
|
||||
SKY sky130_fd_sc_hd__buf_1 equiv=30
|
||||
SKY sky130_fd_sc_hd__buf_2 equiv=30
|
||||
SKY sky130_fd_sc_hd__buf_4 equiv=30
|
||||
SKY sky130_fd_sc_hd__buf_8 equiv=30
|
||||
SKY sky130_fd_sc_hd__nand2_1 equiv=4
|
||||
SKY sky130_fd_sc_hd__nand2_2 equiv=4
|
||||
SKY sky130_fd_sc_hd__nand2_4 equiv=4
|
||||
SKY sky130_fd_sc_hd__nor2_1 equiv=4
|
||||
SKY sky130_fd_sc_hd__nor2_2 equiv=4
|
||||
SKY sky130_fd_sc_hd__nor2_4 equiv=4
|
||||
SKY sky130_fd_sc_hd__and2_1 equiv=4
|
||||
SKY sky130_fd_sc_hd__and2_2 equiv=4
|
||||
SKY sky130_fd_sc_hd__and2_4 equiv=4
|
||||
SKY sky130_fd_sc_hd__or2_1 equiv=4
|
||||
SKY sky130_fd_sc_hd__or2_2 equiv=4
|
||||
SKY sky130_fd_sc_hd__or2_4 equiv=4
|
||||
SKY sky130_fd_sc_hd__dfxtp_1 equiv=3
|
||||
SKY sky130_fd_sc_hd__dfxtp_2 equiv=3
|
||||
SKY sky130_fd_sc_hd__dfxtp_4 equiv=3
|
||||
SKY sky130_fd_sc_hd__dfrtp_1 equiv=3
|
||||
SKY sky130_fd_sc_hd__dfrtp_2 equiv=3
|
||||
SKY sky130_fd_sc_hd__dfrtp_4 equiv=3
|
||||
SKY sky130_fd_sc_hd__clkbuf_1 equiv=30
|
||||
SKY sky130_fd_sc_hd__clkbuf_2 equiv=30
|
||||
SKY sky130_fd_sc_hd__clkbuf_4 equiv=30
|
||||
Sky130 buffers = 35
|
||||
IHP sg13g2_inv_1 equiv=5
|
||||
IHP sg13g2_inv_2 equiv=5
|
||||
IHP sg13g2_inv_4 equiv=5
|
||||
IHP sg13g2_inv_8 equiv=5
|
||||
IHP sg13g2_buf_1 equiv=8
|
||||
IHP sg13g2_buf_2 equiv=8
|
||||
IHP sg13g2_buf_4 equiv=8
|
||||
IHP sg13g2_buf_8 equiv=8
|
||||
IHP sg13g2_nand2_1 equiv=2
|
||||
IHP sg13g2_nand2_2 equiv=2
|
||||
IHP sg13g2_nor2_1 equiv=2
|
||||
IHP sg13g2_nor2_2 equiv=2
|
||||
IHP sg13g2_and2_1 equiv=2
|
||||
IHP sg13g2_and2_2 equiv=2
|
||||
IHP sg13g2_or2_1 equiv=2
|
||||
IHP sg13g2_or2_2 equiv=2
|
||||
IHP buffers = 8
|
||||
|
|
@ -0,0 +1,182 @@
|
|||
# Test EquivCells pairwise comparisons across multiple PDKs.
|
||||
# Exercises all comparison functions and drive-strength sorting.
|
||||
# Targets:
|
||||
# EquivCells.cc: EquivCells constructor, findEquivCells,
|
||||
# hashCell, hashCellPorts, hashCellSequentials, hashSequential,
|
||||
# hashFuncExpr, hashPort, equivCells, equivCellPorts, equivCellFuncs,
|
||||
# equivCellSequentials, equivCellTimingArcSets, equivCellsArcs,
|
||||
# cellHasFuncs, cellDriveResistance, CellDriveResistanceGreater
|
||||
source ../../test/helpers.tcl
|
||||
|
||||
############################################################
|
||||
# Test 1: Nangate45 pairwise
|
||||
############################################################
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
|
||||
set ng_lib [lindex [get_libs NangateOpenCellLibrary] 0]
|
||||
sta::make_equiv_cells $ng_lib
|
||||
|
||||
# Known-working families for find_equiv_cells
|
||||
foreach cell_name {INV_X1 INV_X2 INV_X4 INV_X8 INV_X16 INV_X32
|
||||
BUF_X1 BUF_X2 BUF_X4 BUF_X8 BUF_X16 BUF_X32
|
||||
NAND2_X1 NAND2_X2 NAND2_X4
|
||||
NOR2_X1 NOR2_X2 NOR2_X4
|
||||
AND2_X1 AND2_X2 AND2_X4
|
||||
OR2_X1 OR2_X2 OR2_X4
|
||||
NAND3_X1 NAND3_X2 NAND3_X4
|
||||
NOR3_X1 NOR3_X2 NOR3_X4
|
||||
AND3_X1 AND3_X2 AND3_X4
|
||||
OR3_X1 OR3_X2 OR3_X4
|
||||
NAND4_X1 NAND4_X2 NAND4_X4
|
||||
NOR4_X1 NOR4_X2 NOR4_X4
|
||||
AND4_X1 AND4_X2 AND4_X4
|
||||
OR4_X1 OR4_X2 OR4_X4
|
||||
XOR2_X1 XOR2_X2
|
||||
XNOR2_X1 XNOR2_X2
|
||||
AOI21_X1 AOI21_X2 AOI21_X4
|
||||
OAI21_X1 OAI21_X2 OAI21_X4
|
||||
AOI22_X1 AOI22_X2 AOI22_X4
|
||||
OAI22_X1 OAI22_X2 OAI22_X4
|
||||
AOI211_X1 AOI211_X2
|
||||
OAI211_X1 OAI211_X2 OAI211_X4
|
||||
MUX2_X1 MUX2_X2
|
||||
DFF_X1 DFF_X2
|
||||
DFFR_X1 DFFR_X2
|
||||
DFFS_X1 DFFS_X2
|
||||
DFFRS_X1 DFFRS_X2
|
||||
SDFF_X1 SDFF_X2
|
||||
SDFFR_X1 SDFFR_X2
|
||||
SDFFS_X1 SDFFS_X2
|
||||
SDFFRS_X1 SDFFRS_X2
|
||||
CLKBUF_X1 CLKBUF_X2 CLKBUF_X3
|
||||
CLKGATETST_X1 CLKGATETST_X2 CLKGATETST_X4 CLKGATETST_X8} {
|
||||
set cell [get_lib_cell -quiet NangateOpenCellLibrary/$cell_name]
|
||||
if {$cell != ""} {
|
||||
set equivs [sta::find_equiv_cells $cell]
|
||||
if {$equivs != "" && $equivs != "NULL"} {
|
||||
puts "$cell_name equiv=[llength $equivs]"
|
||||
} else {
|
||||
puts "$cell_name equiv=0"
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
# Extensive pairwise comparisons
|
||||
set inv_x1 [get_lib_cell NangateOpenCellLibrary/INV_X1]
|
||||
set inv_x2 [get_lib_cell NangateOpenCellLibrary/INV_X2]
|
||||
set buf_x1 [get_lib_cell NangateOpenCellLibrary/BUF_X1]
|
||||
set buf_x2 [get_lib_cell NangateOpenCellLibrary/BUF_X2]
|
||||
set nand2_x1 [get_lib_cell NangateOpenCellLibrary/NAND2_X1]
|
||||
set nand2_x2 [get_lib_cell NangateOpenCellLibrary/NAND2_X2]
|
||||
set nand3_x1 [get_lib_cell NangateOpenCellLibrary/NAND3_X1]
|
||||
set nor2_x1 [get_lib_cell NangateOpenCellLibrary/NOR2_X1]
|
||||
set nor2_x2 [get_lib_cell NangateOpenCellLibrary/NOR2_X2]
|
||||
set and2_x1 [get_lib_cell NangateOpenCellLibrary/AND2_X1]
|
||||
set or2_x1 [get_lib_cell NangateOpenCellLibrary/OR2_X1]
|
||||
set xor2_x1 [get_lib_cell NangateOpenCellLibrary/XOR2_X1]
|
||||
set dff_x1 [get_lib_cell NangateOpenCellLibrary/DFF_X1]
|
||||
set dff_x2 [get_lib_cell NangateOpenCellLibrary/DFF_X2]
|
||||
set dffr_x1 [get_lib_cell NangateOpenCellLibrary/DFFR_X1]
|
||||
set sdff_x1 [get_lib_cell NangateOpenCellLibrary/SDFF_X1]
|
||||
set clkgate_x1 [get_lib_cell NangateOpenCellLibrary/CLKGATETST_X1]
|
||||
set clkgate_x2 [get_lib_cell NangateOpenCellLibrary/CLKGATETST_X2]
|
||||
|
||||
# Same-function equivalence (should be true)
|
||||
puts "equiv INV_X1 INV_X2 = [sta::equiv_cells $inv_x1 $inv_x2]"
|
||||
puts "equiv BUF_X1 BUF_X2 = [sta::equiv_cells $buf_x1 $buf_x2]"
|
||||
puts "equiv NAND2_X1 NAND2_X2 = [sta::equiv_cells $nand2_x1 $nand2_x2]"
|
||||
puts "equiv NOR2_X1 NOR2_X2 = [sta::equiv_cells $nor2_x1 $nor2_x2]"
|
||||
puts "equiv DFF_X1 DFF_X2 = [sta::equiv_cells $dff_x1 $dff_x2]"
|
||||
puts "equiv CLKGATE_X1 CLKGATE_X2 = [sta::equiv_cells $clkgate_x1 $clkgate_x2]"
|
||||
|
||||
# Different-function comparisons (should be false)
|
||||
puts "equiv INV BUF = [sta::equiv_cells $inv_x1 $buf_x1]"
|
||||
puts "equiv NAND2 NOR2 = [sta::equiv_cells $nand2_x1 $nor2_x1]"
|
||||
puts "equiv NAND2 NAND3 = [sta::equiv_cells $nand2_x1 $nand3_x1]"
|
||||
puts "equiv AND2 OR2 = [sta::equiv_cells $and2_x1 $or2_x1]"
|
||||
puts "equiv DFF DFFR = [sta::equiv_cells $dff_x1 $dffr_x1]"
|
||||
puts "equiv DFF SDFF = [sta::equiv_cells $dff_x1 $sdff_x1]"
|
||||
puts "equiv INV DFF = [sta::equiv_cells $inv_x1 $dff_x1]"
|
||||
puts "equiv INV CLKGATE = [sta::equiv_cells $inv_x1 $clkgate_x1]"
|
||||
|
||||
# Port equivalence
|
||||
puts "ports INV_X1 INV_X2 = [sta::equiv_cell_ports $inv_x1 $inv_x2]"
|
||||
puts "ports INV BUF = [sta::equiv_cell_ports $inv_x1 $buf_x1]"
|
||||
puts "ports NAND2_X1 NAND2_X2 = [sta::equiv_cell_ports $nand2_x1 $nand2_x2]"
|
||||
puts "ports NAND2 NAND3 = [sta::equiv_cell_ports $nand2_x1 $nand3_x1]"
|
||||
puts "ports DFF_X1 DFF_X2 = [sta::equiv_cell_ports $dff_x1 $dff_x2]"
|
||||
puts "ports DFF DFFR = [sta::equiv_cell_ports $dff_x1 $dffr_x1]"
|
||||
|
||||
# Timing arc equivalence
|
||||
puts "arcs INV_X1 INV_X2 = [sta::equiv_cell_timing_arcs $inv_x1 $inv_x2]"
|
||||
puts "arcs INV BUF = [sta::equiv_cell_timing_arcs $inv_x1 $buf_x1]"
|
||||
puts "arcs DFF_X1 DFF_X2 = [sta::equiv_cell_timing_arcs $dff_x1 $dff_x2]"
|
||||
puts "arcs DFF DFFR = [sta::equiv_cell_timing_arcs $dff_x1 $dffr_x1]"
|
||||
puts "arcs NAND2_X1 NAND2_X2 = [sta::equiv_cell_timing_arcs $nand2_x1 $nand2_x2]"
|
||||
puts "arcs NAND2 NOR2 = [sta::equiv_cell_timing_arcs $nand2_x1 $nor2_x1]"
|
||||
|
||||
set ng_bufs [sta::find_library_buffers $ng_lib]
|
||||
puts "Nangate45 buffers = [llength $ng_bufs]"
|
||||
|
||||
############################################################
|
||||
# Test 2: Sky130 families
|
||||
############################################################
|
||||
read_liberty ../../test/sky130hd/sky130hd_tt.lib
|
||||
|
||||
set sky_lib [lindex [get_libs sky130_fd_sc_hd__tt_025C_1v80] 0]
|
||||
sta::make_equiv_cells $sky_lib
|
||||
|
||||
foreach cell_name {
|
||||
sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_2 sky130_fd_sc_hd__inv_4 sky130_fd_sc_hd__inv_8
|
||||
sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_8
|
||||
sky130_fd_sc_hd__nand2_1 sky130_fd_sc_hd__nand2_2 sky130_fd_sc_hd__nand2_4
|
||||
sky130_fd_sc_hd__nor2_1 sky130_fd_sc_hd__nor2_2 sky130_fd_sc_hd__nor2_4
|
||||
sky130_fd_sc_hd__and2_1 sky130_fd_sc_hd__and2_2 sky130_fd_sc_hd__and2_4
|
||||
sky130_fd_sc_hd__or2_1 sky130_fd_sc_hd__or2_2 sky130_fd_sc_hd__or2_4
|
||||
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_2 sky130_fd_sc_hd__dfxtp_4
|
||||
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_2 sky130_fd_sc_hd__dfrtp_4
|
||||
sky130_fd_sc_hd__clkbuf_1 sky130_fd_sc_hd__clkbuf_2 sky130_fd_sc_hd__clkbuf_4
|
||||
} {
|
||||
set cell [get_lib_cell -quiet sky130_fd_sc_hd__tt_025C_1v80/$cell_name]
|
||||
if {$cell != ""} {
|
||||
set equivs [sta::find_equiv_cells $cell]
|
||||
if {$equivs != "" && $equivs != "NULL"} {
|
||||
puts "SKY $cell_name equiv=[llength $equivs]"
|
||||
} else {
|
||||
puts "SKY $cell_name equiv=0"
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
set sky_bufs [sta::find_library_buffers $sky_lib]
|
||||
puts "Sky130 buffers = [llength $sky_bufs]"
|
||||
|
||||
############################################################
|
||||
# Test 3: IHP cell families
|
||||
############################################################
|
||||
read_liberty ../../test/ihp-sg13g2/sg13g2_stdcell_typ_1p20V_25C.lib
|
||||
|
||||
set ihp_lib [lindex [get_libs sg13g2_stdcell_typ_1p20V_25C] 0]
|
||||
sta::make_equiv_cells $ihp_lib
|
||||
|
||||
foreach cell_name {
|
||||
sg13g2_inv_1 sg13g2_inv_2 sg13g2_inv_4 sg13g2_inv_8
|
||||
sg13g2_buf_1 sg13g2_buf_2 sg13g2_buf_4 sg13g2_buf_8
|
||||
sg13g2_nand2_1 sg13g2_nand2_2
|
||||
sg13g2_nor2_1 sg13g2_nor2_2
|
||||
sg13g2_and2_1 sg13g2_and2_2
|
||||
sg13g2_or2_1 sg13g2_or2_2
|
||||
} {
|
||||
set cell [get_lib_cell -quiet sg13g2_stdcell_typ_1p20V_25C/$cell_name]
|
||||
if {$cell != ""} {
|
||||
set equivs [sta::find_equiv_cells $cell]
|
||||
if {$equivs != "" && $equivs != "NULL"} {
|
||||
puts "IHP $cell_name equiv=[llength $equivs]"
|
||||
} else {
|
||||
puts "IHP $cell_name equiv=0"
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
set ihp_bufs [sta::find_library_buffers $ihp_lib]
|
||||
puts "IHP buffers = [llength $ihp_bufs]"
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,200 @@
|
|||
# Test complex boolean function expressions and cell type classification
|
||||
# Targets: FuncExpr.cc (to_string, port matching, op types),
|
||||
# Liberty.cc (cell property queries, function expression evaluation),
|
||||
# LibertyReader.cc (function expression parsing),
|
||||
# TimingArc.cc (arc queries on cells with complex functions)
|
||||
source ../../test/helpers.tcl
|
||||
|
||||
############################################################
|
||||
# Read Nangate45 - has AOI, OAI, MUX, XOR, XNOR etc.
|
||||
############################################################
|
||||
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
|
||||
# Link a design to enable timing queries
|
||||
read_verilog ../../sdc/test/sdc_test2.v
|
||||
link_design sdc_test2
|
||||
|
||||
create_clock -name clk1 -period 10 [get_ports clk1]
|
||||
create_clock -name clk2 -period 20 [get_ports clk2]
|
||||
set_input_delay -clock clk1 2.0 [all_inputs]
|
||||
set_output_delay -clock clk1 3.0 [all_outputs]
|
||||
|
||||
############################################################
|
||||
# XOR/XNOR cells (FuncExpr op_xor)
|
||||
############################################################
|
||||
|
||||
report_lib_cell NangateOpenCellLibrary/XOR2_X1
|
||||
|
||||
report_lib_cell NangateOpenCellLibrary/XOR2_X2
|
||||
|
||||
report_lib_cell NangateOpenCellLibrary/XNOR2_X1
|
||||
|
||||
report_lib_cell NangateOpenCellLibrary/XNOR2_X2
|
||||
|
||||
############################################################
|
||||
# AOI cells (complex AND-OR-INVERT functions)
|
||||
############################################################
|
||||
|
||||
# AOI21: !(A1&A2 | B)
|
||||
report_lib_cell NangateOpenCellLibrary/AOI21_X1
|
||||
report_lib_cell NangateOpenCellLibrary/AOI21_X2
|
||||
report_lib_cell NangateOpenCellLibrary/AOI21_X4
|
||||
|
||||
# AOI22: !(A1&A2 | B1&B2)
|
||||
report_lib_cell NangateOpenCellLibrary/AOI22_X1
|
||||
report_lib_cell NangateOpenCellLibrary/AOI22_X2
|
||||
report_lib_cell NangateOpenCellLibrary/AOI22_X4
|
||||
|
||||
# AOI211: !(A1&A2 | B | C)
|
||||
report_lib_cell NangateOpenCellLibrary/AOI211_X1
|
||||
report_lib_cell NangateOpenCellLibrary/AOI211_X2
|
||||
report_lib_cell NangateOpenCellLibrary/AOI211_X4
|
||||
|
||||
############################################################
|
||||
# OAI cells (complex OR-AND-INVERT functions)
|
||||
############################################################
|
||||
|
||||
# OAI21: !((A1|A2) & B)
|
||||
report_lib_cell NangateOpenCellLibrary/OAI21_X1
|
||||
report_lib_cell NangateOpenCellLibrary/OAI21_X2
|
||||
report_lib_cell NangateOpenCellLibrary/OAI21_X4
|
||||
|
||||
# OAI22: !((A1|A2) & (B1|B2))
|
||||
report_lib_cell NangateOpenCellLibrary/OAI22_X1
|
||||
report_lib_cell NangateOpenCellLibrary/OAI22_X2
|
||||
report_lib_cell NangateOpenCellLibrary/OAI22_X4
|
||||
|
||||
# OAI211: !((A1|A2) & B & C)
|
||||
report_lib_cell NangateOpenCellLibrary/OAI211_X1
|
||||
report_lib_cell NangateOpenCellLibrary/OAI211_X2
|
||||
report_lib_cell NangateOpenCellLibrary/OAI211_X4
|
||||
|
||||
# OAI33: !((A1|A2|A3) & (B1|B2|B3))
|
||||
report_lib_cell NangateOpenCellLibrary/OAI33_X1
|
||||
|
||||
############################################################
|
||||
# MUX cells (complex function: S?B:A)
|
||||
############################################################
|
||||
|
||||
report_lib_cell NangateOpenCellLibrary/MUX2_X1
|
||||
report_lib_cell NangateOpenCellLibrary/MUX2_X2
|
||||
|
||||
############################################################
|
||||
# Full/half adder (complex multi-output functions)
|
||||
############################################################
|
||||
|
||||
report_lib_cell NangateOpenCellLibrary/FA_X1
|
||||
|
||||
report_lib_cell NangateOpenCellLibrary/HA_X1
|
||||
|
||||
############################################################
|
||||
# Tristate cells (three_state enable)
|
||||
############################################################
|
||||
|
||||
report_lib_cell NangateOpenCellLibrary/TINV_X1
|
||||
|
||||
report_lib_cell NangateOpenCellLibrary/TBUF_X1
|
||||
report_lib_cell NangateOpenCellLibrary/TBUF_X2
|
||||
|
||||
############################################################
|
||||
# Special cells: antenna, filler, tie, clock gate
|
||||
############################################################
|
||||
|
||||
report_lib_cell NangateOpenCellLibrary/ANTENNA_X1
|
||||
|
||||
report_lib_cell NangateOpenCellLibrary/FILLCELL_X1
|
||||
report_lib_cell NangateOpenCellLibrary/FILLCELL_X2
|
||||
report_lib_cell NangateOpenCellLibrary/FILLCELL_X4
|
||||
report_lib_cell NangateOpenCellLibrary/FILLCELL_X8
|
||||
report_lib_cell NangateOpenCellLibrary/FILLCELL_X16
|
||||
report_lib_cell NangateOpenCellLibrary/FILLCELL_X32
|
||||
|
||||
report_lib_cell NangateOpenCellLibrary/LOGIC0_X1
|
||||
report_lib_cell NangateOpenCellLibrary/LOGIC1_X1
|
||||
|
||||
report_lib_cell NangateOpenCellLibrary/CLKGATETST_X1
|
||||
report_lib_cell NangateOpenCellLibrary/CLKGATETST_X2
|
||||
report_lib_cell NangateOpenCellLibrary/CLKGATETST_X4
|
||||
report_lib_cell NangateOpenCellLibrary/CLKGATETST_X8
|
||||
|
||||
############################################################
|
||||
# Scan DFF cells (complex function with scan mux)
|
||||
############################################################
|
||||
|
||||
report_lib_cell NangateOpenCellLibrary/SDFF_X1
|
||||
report_lib_cell NangateOpenCellLibrary/SDFF_X2
|
||||
report_lib_cell NangateOpenCellLibrary/SDFFR_X1
|
||||
report_lib_cell NangateOpenCellLibrary/SDFFR_X2
|
||||
report_lib_cell NangateOpenCellLibrary/SDFFS_X1
|
||||
report_lib_cell NangateOpenCellLibrary/SDFFS_X2
|
||||
report_lib_cell NangateOpenCellLibrary/SDFFRS_X1
|
||||
report_lib_cell NangateOpenCellLibrary/SDFFRS_X2
|
||||
|
||||
############################################################
|
||||
# Write liberty to exercise FuncExpr::to_string for all types
|
||||
############################################################
|
||||
|
||||
set outfile1 [make_result_file liberty_func_expr_write.lib]
|
||||
sta::write_liberty NangateOpenCellLibrary $outfile1
|
||||
|
||||
############################################################
|
||||
# Read IHP library (different function syntax/features)
|
||||
############################################################
|
||||
|
||||
read_liberty ../../test/ihp-sg13g2/sg13g2_stdcell_typ_1p20V_25C.lib
|
||||
|
||||
# IHP has different cell naming and function formats
|
||||
report_lib_cell sg13g2_stdcell_typ_1p20V_25C/sg13g2_inv_1
|
||||
report_lib_cell sg13g2_stdcell_typ_1p20V_25C/sg13g2_buf_1
|
||||
report_lib_cell sg13g2_stdcell_typ_1p20V_25C/sg13g2_nand2_1
|
||||
report_lib_cell sg13g2_stdcell_typ_1p20V_25C/sg13g2_nor2_1
|
||||
report_lib_cell sg13g2_stdcell_typ_1p20V_25C/sg13g2_xor2_1
|
||||
report_lib_cell sg13g2_stdcell_typ_1p20V_25C/sg13g2_xnor2_1
|
||||
report_lib_cell sg13g2_stdcell_typ_1p20V_25C/sg13g2_mux2_1
|
||||
report_lib_cell sg13g2_stdcell_typ_1p20V_25C/sg13g2_dfrbp_1
|
||||
report_lib_cell sg13g2_stdcell_typ_1p20V_25C/sg13g2_ebufn_2
|
||||
report_lib_cell sg13g2_stdcell_typ_1p20V_25C/sg13g2_antn
|
||||
report_lib_cell sg13g2_stdcell_typ_1p20V_25C/sg13g2_tiehi
|
||||
report_lib_cell sg13g2_stdcell_typ_1p20V_25C/sg13g2_tielo
|
||||
|
||||
set outfile2 [make_result_file liberty_func_expr_write_ihp.lib]
|
||||
sta::write_liberty sg13g2_stdcell_typ_1p20V_25C $outfile2
|
||||
|
||||
############################################################
|
||||
# Read Sky130 library (yet another function expression style)
|
||||
############################################################
|
||||
|
||||
read_liberty ../../test/sky130hd/sky130hd_tt.lib
|
||||
|
||||
# Sky130 has complex cells with different function expression styles
|
||||
report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__a21o_1
|
||||
report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__a21oi_1
|
||||
report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__a22o_1
|
||||
report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__a22oi_1
|
||||
report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__a31o_1
|
||||
report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__a32o_1
|
||||
report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__o21a_1
|
||||
report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__o21ai_0
|
||||
report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__o22a_1
|
||||
report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__mux2_1
|
||||
report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__mux4_1
|
||||
report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__xor2_1
|
||||
report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__xnor2_1
|
||||
report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__fa_1
|
||||
report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__ha_1
|
||||
report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__maj3_1
|
||||
report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxtp_1
|
||||
report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfxtp_1
|
||||
report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__ebufn_1
|
||||
|
||||
set outfile3 [make_result_file liberty_func_expr_write_sky130.lib]
|
||||
sta::write_liberty sky130_fd_sc_hd__tt_025C_1v80 $outfile3
|
||||
|
||||
############################################################
|
||||
# Timing path reports through complex cells
|
||||
############################################################
|
||||
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
|
||||
report_checks -from [get_ports in1] -to [get_ports out1] -path_delay min
|
||||
|
|
@ -0,0 +1,126 @@
|
|||
--- leakage power queries ---
|
||||
--- detailed cell reports ---
|
||||
Cell sky130_fd_sc_hd__inv_1
|
||||
Library sky130_fd_sc_hd__tt_025C_1v80
|
||||
File ../../test/sky130hd/sky130hd_tt.lib
|
||||
VGND ground
|
||||
VNB bias
|
||||
VPB bias
|
||||
VPWR power
|
||||
A input 0.00-0.00
|
||||
Y output function=!A
|
||||
|
||||
Timing arcs
|
||||
A -> Y
|
||||
combinational
|
||||
^ -> v
|
||||
v -> ^
|
||||
Cell sky130_fd_sc_hd__nand2_1
|
||||
Library sky130_fd_sc_hd__tt_025C_1v80
|
||||
File ../../test/sky130hd/sky130hd_tt.lib
|
||||
VGND ground
|
||||
VNB bias
|
||||
VPB bias
|
||||
VPWR power
|
||||
A input 0.00-0.00
|
||||
B input 0.00-0.00
|
||||
Y output function=!A+!B
|
||||
|
||||
Timing arcs
|
||||
A -> Y
|
||||
combinational
|
||||
^ -> v
|
||||
v -> ^
|
||||
B -> Y
|
||||
combinational
|
||||
^ -> v
|
||||
v -> ^
|
||||
Cell sky130_fd_sc_hd__dfxtp_1
|
||||
Library sky130_fd_sc_hd__tt_025C_1v80
|
||||
File ../../test/sky130hd/sky130hd_tt.lib
|
||||
VGND ground
|
||||
VNB bias
|
||||
VPB bias
|
||||
VPWR power
|
||||
CLK input 0.00-0.00
|
||||
D input 0.00-0.00
|
||||
Q output function=IQ
|
||||
IQ internal
|
||||
IQ_N internal
|
||||
|
||||
Timing arcs
|
||||
CLK -> CLK
|
||||
width
|
||||
^ -> v
|
||||
v -> ^
|
||||
CLK -> D
|
||||
setup
|
||||
^ -> ^
|
||||
^ -> v
|
||||
CLK -> D
|
||||
hold
|
||||
^ -> ^
|
||||
^ -> v
|
||||
CLK -> Q
|
||||
Reg Clk to Q
|
||||
^ -> ^
|
||||
^ -> v
|
||||
Warning 441: liberty_leakage_power_deep.tcl line 1, set_input_delay relative to a clock defined on the same port/pin not allowed.
|
||||
Group Internal Switching Leakage Total
|
||||
Power Power Power Power (Watts)
|
||||
----------------------------------------------------------------
|
||||
Sequential 1.76e-06 6.90e-09 2.36e-07 2.01e-06 86.3%
|
||||
Combinational 1.22e-07 7.11e-08 1.25e-07 3.18e-07 13.7%
|
||||
Clock 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
|
||||
Macro 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
|
||||
Pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
|
||||
----------------------------------------------------------------
|
||||
Total 1.88e-06 7.80e-08 3.61e-07 2.32e-06 100.0%
|
||||
81.1% 3.4% 15.5%
|
||||
Group Internal Switching Leakage Total
|
||||
Power Power Power Power (Watts)
|
||||
--------------------------------------------------------------------------------
|
||||
Sequential 1.76263279e-06 6.89875490e-09 2.35681341e-07 2.00521299e-06 86.3%
|
||||
Combinational 1.22147213e-07 7.10827521e-08 1.25075346e-07 3.18305297e-07 13.7%
|
||||
Clock 0.00000000e+00 0.00000000e+00 0.00000000e+00 0.00000000e+00 0.0%
|
||||
Macro 0.00000000e+00 0.00000000e+00 0.00000000e+00 0.00000000e+00 0.0%
|
||||
Pad 0.00000000e+00 0.00000000e+00 0.00000000e+00 0.00000000e+00 0.0%
|
||||
--------------------------------------------------------------------------------
|
||||
Total 1.88477998e-06 7.79815039e-08 3.60756701e-07 2.32351817e-06 100.0%
|
||||
81.1% 3.4% 15.5%
|
||||
Internal Switching Leakage Total
|
||||
Power Power Power Power (Watts)
|
||||
--------------------------------------------
|
||||
2.69e-08 1.13e-08 2.14e-08 5.96e-08 buf1
|
||||
Internal Switching Leakage Total
|
||||
Power Power Power Power (Watts)
|
||||
--------------------------------------------
|
||||
1.68e-08 5.90e-09 1.44e-08 3.71e-08 inv1
|
||||
Internal Switching Leakage Total
|
||||
Power Power Power Power (Watts)
|
||||
--------------------------------------------
|
||||
2.56e-08 2.00e-08 2.51e-08 7.07e-08 and1
|
||||
Internal Switching Leakage Total
|
||||
Power Power Power Power (Watts)
|
||||
--------------------------------------------
|
||||
2.59e-08 2.01e-08 2.27e-08 6.87e-08 or1
|
||||
Internal Switching Leakage Total
|
||||
Power Power Power Power (Watts)
|
||||
--------------------------------------------
|
||||
1.24e-08 6.90e-09 2.18e-08 4.11e-08 nand1
|
||||
Internal Switching Leakage Total
|
||||
Power Power Power Power (Watts)
|
||||
--------------------------------------------
|
||||
1.46e-08 6.90e-09 1.97e-08 4.11e-08 nor1
|
||||
Internal Switching Leakage Total
|
||||
Power Power Power Power (Watts)
|
||||
--------------------------------------------
|
||||
5.87e-07 6.90e-09 7.86e-08 6.73e-07 reg1
|
||||
Internal Switching Leakage Total
|
||||
Power Power Power Power (Watts)
|
||||
--------------------------------------------
|
||||
5.89e-07 0.00e+00 7.84e-08 6.67e-07 reg2
|
||||
Internal Switching Leakage Total
|
||||
Power Power Power Power (Watts)
|
||||
--------------------------------------------
|
||||
5.87e-07 0.00e+00 7.86e-08 6.65e-07 reg3
|
||||
|
|
@ -0,0 +1,66 @@
|
|||
# Test deep leakage power groups with when conditions, internal power
|
||||
# with related_pg_pin, and power attribute parsing across PDKs.
|
||||
source ../../test/helpers.tcl
|
||||
|
||||
############################################################
|
||||
# Read Sky130 library (has leakage_power groups with when conditions)
|
||||
############################################################
|
||||
read_liberty ../../test/sky130hd/sky130hd_tt.lib
|
||||
|
||||
############################################################
|
||||
# Query leakage power on various cell types
|
||||
# Sky130 has per-state leakage_power groups with when conditions
|
||||
############################################################
|
||||
puts "--- leakage power queries ---"
|
||||
|
||||
# Note: cell_leakage_power is not a supported get_property property.
|
||||
# Leakage power is exercised through report_power and report_lib_cell below.
|
||||
|
||||
############################################################
|
||||
# Report lib cells to exercise detailed leakage/power info
|
||||
############################################################
|
||||
puts "--- detailed cell reports ---"
|
||||
|
||||
report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__inv_1
|
||||
|
||||
report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__nand2_1
|
||||
|
||||
report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfxtp_1
|
||||
|
||||
############################################################
|
||||
# Read Nangate library for internal power with when conditions
|
||||
############################################################
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
|
||||
############################################################
|
||||
# Link design and run power analysis to exercise internal power
|
||||
############################################################
|
||||
read_verilog ../../sdc/test/sdc_test2.v
|
||||
link_design sdc_test2
|
||||
|
||||
create_clock -name clk1 -period 10 [get_ports clk1]
|
||||
create_clock -name clk2 -period 20 [get_ports clk2]
|
||||
set_input_delay -clock clk1 2.0 [all_inputs]
|
||||
set_output_delay -clock clk1 3.0 [all_outputs]
|
||||
set_input_transition 0.1 [all_inputs]
|
||||
|
||||
# Power reports exercise internal power evaluation
|
||||
report_power
|
||||
|
||||
report_power -digits 8
|
||||
|
||||
# Per-instance power
|
||||
foreach inst_name {buf1 inv1 and1 or1 nand1 nor1 reg1 reg2 reg3} {
|
||||
report_power -instances [get_cells $inst_name]
|
||||
}
|
||||
|
||||
############################################################
|
||||
# Read IHP library for different power model format
|
||||
############################################################
|
||||
read_liberty ../../test/ihp-sg13g2/sg13g2_stdcell_typ_1p20V_25C.lib
|
||||
|
||||
############################################################
|
||||
# Write liberty roundtrip for Sky130 (exercises power writer)
|
||||
############################################################
|
||||
set outfile [make_result_file liberty_leakage_power_deep_write.lib]
|
||||
sta::write_liberty sky130_fd_sc_hd__tt_025C_1v80 $outfile
|
||||
|
|
@ -0,0 +1,205 @@
|
|||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: out1 (output port clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
Corner: fast
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg1/CK (DFF_X1)
|
||||
0.05 0.05 v reg1/Q (DFF_X1)
|
||||
0.00 0.05 v out1 (out)
|
||||
0.05 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
-3.00 7.00 output external delay
|
||||
7.00 data required time
|
||||
---------------------------------------------------------
|
||||
7.00 data required time
|
||||
-0.05 data arrival time
|
||||
---------------------------------------------------------
|
||||
6.95 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: out1 (output port clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
Corner: slow
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg1/CK (DFF_X1)
|
||||
0.29 0.29 ^ reg1/Q (DFF_X1)
|
||||
0.00 0.29 ^ out1 (out)
|
||||
0.29 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
-3.00 7.00 output external delay
|
||||
7.00 data required time
|
||||
---------------------------------------------------------
|
||||
7.00 data required time
|
||||
-0.29 data arrival time
|
||||
---------------------------------------------------------
|
||||
6.71 slack (MET)
|
||||
|
||||
|
||||
Clock Period Waveform
|
||||
----------------------------------------------------
|
||||
clk 10.00 0.00 5.00
|
||||
Startpoint: in1 (input port clocked by clk)
|
||||
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: min
|
||||
Corner: fast
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
2.00 2.00 ^ input external delay
|
||||
0.00 2.00 ^ in1 (in)
|
||||
0.01 2.01 ^ buf1/Z (BUF_X1)
|
||||
0.00 2.01 ^ reg1/D (DFF_X1)
|
||||
2.01 data arrival time
|
||||
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 clock reconvergence pessimism
|
||||
0.00 ^ reg1/CK (DFF_X1)
|
||||
0.00 0.00 library hold time
|
||||
0.00 data required time
|
||||
---------------------------------------------------------
|
||||
0.00 data required time
|
||||
-2.01 data arrival time
|
||||
---------------------------------------------------------
|
||||
2.01 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: out1 (output port clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
Corner: slow
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg1/CK (DFF_X1)
|
||||
0.29 0.29 ^ reg1/Q (DFF_X1)
|
||||
0.00 0.29 ^ out1 (out)
|
||||
0.29 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
-3.00 7.00 output external delay
|
||||
7.00 data required time
|
||||
---------------------------------------------------------
|
||||
7.00 data required time
|
||||
-0.29 data arrival time
|
||||
---------------------------------------------------------
|
||||
6.71 slack (MET)
|
||||
|
||||
|
||||
Cell BUF_X1
|
||||
Library NangateOpenCellLibrary_fast
|
||||
File ../../test/nangate45/Nangate45_fast.lib
|
||||
VDD power
|
||||
VSS ground
|
||||
A input 0.91-0.98
|
||||
Z output function=A
|
||||
|
||||
Timing arcs
|
||||
A -> Z
|
||||
combinational
|
||||
^ -> ^
|
||||
v -> v
|
||||
Cell BUF_X1
|
||||
Library NangateOpenCellLibrary_slow
|
||||
File ../../test/nangate45/Nangate45_slow.lib
|
||||
VDD power
|
||||
VSS ground
|
||||
A input 0.84-0.93
|
||||
Z output function=A
|
||||
|
||||
Timing arcs
|
||||
A -> Z
|
||||
combinational
|
||||
^ -> ^
|
||||
v -> v
|
||||
Cell DFF_X1
|
||||
Library NangateOpenCellLibrary_fast
|
||||
File ../../test/nangate45/Nangate45_fast.lib
|
||||
VDD power
|
||||
VSS ground
|
||||
D input 1.10-1.16
|
||||
CK input 0.89-0.97
|
||||
Q output function=IQ
|
||||
QN output function=IQN
|
||||
IQ internal
|
||||
IQN internal
|
||||
|
||||
Timing arcs
|
||||
CK -> D
|
||||
hold
|
||||
^ -> ^
|
||||
^ -> v
|
||||
CK -> D
|
||||
setup
|
||||
^ -> ^
|
||||
^ -> v
|
||||
CK -> CK
|
||||
width
|
||||
^ -> v
|
||||
v -> ^
|
||||
CK -> Q
|
||||
Reg Clk to Q
|
||||
^ -> ^
|
||||
^ -> v
|
||||
CK -> QN
|
||||
Reg Clk to Q
|
||||
^ -> ^
|
||||
^ -> v
|
||||
Cell DFF_X1
|
||||
Library NangateOpenCellLibrary_slow
|
||||
File ../../test/nangate45/Nangate45_slow.lib
|
||||
VDD power
|
||||
VSS ground
|
||||
D input 1.03-1.11
|
||||
CK input 0.82-0.91
|
||||
Q output function=IQ
|
||||
QN output function=IQN
|
||||
IQ internal
|
||||
IQN internal
|
||||
|
||||
Timing arcs
|
||||
CK -> D
|
||||
hold
|
||||
^ -> ^
|
||||
^ -> v
|
||||
CK -> D
|
||||
setup
|
||||
^ -> ^
|
||||
^ -> v
|
||||
CK -> CK
|
||||
width
|
||||
^ -> v
|
||||
v -> ^
|
||||
CK -> Q
|
||||
Reg Clk to Q
|
||||
^ -> ^
|
||||
^ -> v
|
||||
CK -> QN
|
||||
Reg Clk to Q
|
||||
^ -> ^
|
||||
^ -> v
|
||||
|
|
@ -0,0 +1,67 @@
|
|||
# Test multi-corner liberty reading for code coverage
|
||||
define_corners fast slow
|
||||
|
||||
read_liberty -corner fast ../../test/nangate45/Nangate45_fast.lib
|
||||
read_liberty -corner slow ../../test/nangate45/Nangate45_slow.lib
|
||||
|
||||
# Verify both corners loaded
|
||||
set fast_lib [get_libs NangateOpenCellLibrary_fast]
|
||||
if { $fast_lib == "" } {
|
||||
puts "FAIL: fast library not found"
|
||||
exit 1
|
||||
}
|
||||
|
||||
set slow_lib [get_libs NangateOpenCellLibrary_slow]
|
||||
if { $slow_lib == "" } {
|
||||
puts "FAIL: slow library not found"
|
||||
exit 1
|
||||
}
|
||||
|
||||
# Query cells in each corner
|
||||
set fast_inv [get_lib_cells NangateOpenCellLibrary_fast/INV_X1]
|
||||
if { $fast_inv == "" } {
|
||||
puts "FAIL: fast INV_X1 not found"
|
||||
exit 1
|
||||
}
|
||||
|
||||
set slow_inv [get_lib_cells NangateOpenCellLibrary_slow/INV_X1]
|
||||
if { $slow_inv == "" } {
|
||||
puts "FAIL: slow INV_X1 not found"
|
||||
exit 1
|
||||
}
|
||||
|
||||
# Read verilog and link
|
||||
read_verilog ../../sdc/test/sdc_test1.v
|
||||
link_design sdc_test1
|
||||
|
||||
# Setup constraints
|
||||
create_clock -name clk -period 10 [get_ports clk]
|
||||
set_input_delay -clock clk 2.0 [get_ports in1]
|
||||
set_output_delay -clock clk 3.0 [get_ports out1]
|
||||
|
||||
# Report for each corner
|
||||
report_checks -corner fast
|
||||
|
||||
report_checks -corner slow
|
||||
|
||||
# Report clock properties
|
||||
report_clock_properties
|
||||
|
||||
# Report with path details
|
||||
report_checks -corner fast -path_delay min
|
||||
|
||||
report_checks -corner slow -path_delay max
|
||||
|
||||
# Query lib cells from both corners
|
||||
report_lib_cell NangateOpenCellLibrary_fast/BUF_X1
|
||||
|
||||
report_lib_cell NangateOpenCellLibrary_slow/BUF_X1
|
||||
|
||||
report_lib_cell NangateOpenCellLibrary_fast/DFF_X1
|
||||
|
||||
report_lib_cell NangateOpenCellLibrary_slow/DFF_X1
|
||||
|
||||
# Get lib pins from both corners
|
||||
set fast_buf_pins [get_lib_pins NangateOpenCellLibrary_fast/BUF_X1/*]
|
||||
|
||||
set slow_buf_pins [get_lib_pins NangateOpenCellLibrary_slow/BUF_X1/*]
|
||||
|
|
@ -0,0 +1,47 @@
|
|||
INV equiv count: 6
|
||||
BUF equiv count: 9
|
||||
NAND2 equiv count: 3
|
||||
NAND3 equiv count: 3
|
||||
NAND4 equiv count: 3
|
||||
NOR2 equiv count: 3
|
||||
NOR3 equiv count: 3
|
||||
NOR4 equiv count: 3
|
||||
AND2 equiv count: 3
|
||||
OR2 equiv count: 3
|
||||
AOI21 equiv count: 3
|
||||
OAI21 equiv count: 3
|
||||
DFF equiv count: 2
|
||||
SDFF equiv count: 2
|
||||
CLKBUF equiv count: 9
|
||||
XOR2 equiv count: 2
|
||||
INV_X1 typ equiv fast: 1
|
||||
INV_X1 typ equiv slow: 1
|
||||
INV_X1 fast equiv slow: 1
|
||||
BUF_X1 typ equiv fast: 1
|
||||
NAND2_X1 typ equiv fast: 1
|
||||
DFF_X1 typ equiv fast: 1
|
||||
equiv_cell_ports INV typ/fast: 1
|
||||
equiv_cell_ports BUF typ/fast: 1
|
||||
equiv_cell_ports INV/BUF: 0
|
||||
equiv_cell_ports NAND2/NAND3: 0
|
||||
equiv_cell_timing_arcs INV typ/fast: 1
|
||||
equiv_cell_timing_arcs BUF typ/fast: 1
|
||||
equiv_cell_timing_arcs INV/BUF: 0
|
||||
typ library buffers: 9
|
||||
fast library buffers: 9
|
||||
slow library buffers: 9
|
||||
INV_X1 equiv INV_X2: 1
|
||||
INV_X1 equiv INV_X4: 1
|
||||
INV_X1 equiv INV_X8: 1
|
||||
INV_X1 equiv INV_X16: 1
|
||||
INV_X1 equiv INV_X32: 1
|
||||
NAND2 equiv NOR2: 0
|
||||
AND2 equiv OR2: 0
|
||||
AOI21 equiv OAI21: 0
|
||||
DFF equiv DFFR: 0
|
||||
DFF equiv DFFS: 0
|
||||
DFFR equiv DFFRS: 0
|
||||
LVT INV equiv count: 6
|
||||
LVT library buffers: 9
|
||||
INV_X1 equiv LVT INV_X1_L: 1
|
||||
equiv_cell_ports INV/LVT_INV: 1
|
||||
|
|
@ -0,0 +1,254 @@
|
|||
# Test multi-library equivalent cell analysis for code coverage
|
||||
# Targets: EquivCells.cc (hashCell, hashCellPorts, equivCellPorts, equivCellTimingArcSets,
|
||||
# CellDriveResistanceGreater, cross-library matching),
|
||||
# Liberty.cc (cell comparison, port iteration),
|
||||
# LibertyReader.cc (multiple library reading)
|
||||
source ../../test/helpers.tcl
|
||||
|
||||
############################################################
|
||||
# Read multiple Nangate45 corners for cross-library equiv
|
||||
############################################################
|
||||
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
|
||||
read_liberty ../../test/nangate45/Nangate45_fast.lib
|
||||
|
||||
read_liberty ../../test/nangate45/Nangate45_slow.lib
|
||||
|
||||
############################################################
|
||||
# Make equiv cells for typ library
|
||||
############################################################
|
||||
|
||||
set typ_lib [lindex [get_libs NangateOpenCellLibrary] 0]
|
||||
sta::make_equiv_cells $typ_lib
|
||||
|
||||
############################################################
|
||||
# Find equiv cells in typ library (various cell families)
|
||||
############################################################
|
||||
|
||||
# INV family
|
||||
set inv_x1 [get_lib_cell NangateOpenCellLibrary/INV_X1]
|
||||
set inv_equivs [sta::find_equiv_cells $inv_x1]
|
||||
puts "INV equiv count: [llength $inv_equivs]"
|
||||
|
||||
# BUF family
|
||||
set buf_x1 [get_lib_cell NangateOpenCellLibrary/BUF_X1]
|
||||
set buf_equivs [sta::find_equiv_cells $buf_x1]
|
||||
puts "BUF equiv count: [llength $buf_equivs]"
|
||||
|
||||
# NAND2 family
|
||||
set nand2_x1 [get_lib_cell NangateOpenCellLibrary/NAND2_X1]
|
||||
set nand2_equivs [sta::find_equiv_cells $nand2_x1]
|
||||
puts "NAND2 equiv count: [llength $nand2_equivs]"
|
||||
|
||||
# NAND3 family
|
||||
set nand3_x1 [get_lib_cell NangateOpenCellLibrary/NAND3_X1]
|
||||
set nand3_equivs [sta::find_equiv_cells $nand3_x1]
|
||||
puts "NAND3 equiv count: [llength $nand3_equivs]"
|
||||
|
||||
# NAND4 family
|
||||
set nand4_x1 [get_lib_cell NangateOpenCellLibrary/NAND4_X1]
|
||||
set nand4_equivs [sta::find_equiv_cells $nand4_x1]
|
||||
puts "NAND4 equiv count: [llength $nand4_equivs]"
|
||||
|
||||
# NOR2 family
|
||||
set nor2_x1 [get_lib_cell NangateOpenCellLibrary/NOR2_X1]
|
||||
set nor2_equivs [sta::find_equiv_cells $nor2_x1]
|
||||
puts "NOR2 equiv count: [llength $nor2_equivs]"
|
||||
|
||||
# NOR3 family
|
||||
set nor3_x1 [get_lib_cell NangateOpenCellLibrary/NOR3_X1]
|
||||
set nor3_equivs [sta::find_equiv_cells $nor3_x1]
|
||||
puts "NOR3 equiv count: [llength $nor3_equivs]"
|
||||
|
||||
# NOR4 family
|
||||
set nor4_x1 [get_lib_cell NangateOpenCellLibrary/NOR4_X1]
|
||||
set nor4_equivs [sta::find_equiv_cells $nor4_x1]
|
||||
puts "NOR4 equiv count: [llength $nor4_equivs]"
|
||||
|
||||
# AND2 family
|
||||
set and2_x1 [get_lib_cell NangateOpenCellLibrary/AND2_X1]
|
||||
set and2_equivs [sta::find_equiv_cells $and2_x1]
|
||||
puts "AND2 equiv count: [llength $and2_equivs]"
|
||||
|
||||
# OR2 family
|
||||
set or2_x1 [get_lib_cell NangateOpenCellLibrary/OR2_X1]
|
||||
set or2_equivs [sta::find_equiv_cells $or2_x1]
|
||||
puts "OR2 equiv count: [llength $or2_equivs]"
|
||||
|
||||
# AOI21 family
|
||||
set aoi21_x1 [get_lib_cell NangateOpenCellLibrary/AOI21_X1]
|
||||
set aoi21_equivs [sta::find_equiv_cells $aoi21_x1]
|
||||
puts "AOI21 equiv count: [llength $aoi21_equivs]"
|
||||
|
||||
# OAI21 family
|
||||
set oai21_x1 [get_lib_cell NangateOpenCellLibrary/OAI21_X1]
|
||||
set oai21_equivs [sta::find_equiv_cells $oai21_x1]
|
||||
puts "OAI21 equiv count: [llength $oai21_equivs]"
|
||||
|
||||
# DFF family
|
||||
set dff_x1 [get_lib_cell NangateOpenCellLibrary/DFF_X1]
|
||||
set dff_equivs [sta::find_equiv_cells $dff_x1]
|
||||
puts "DFF equiv count: [llength $dff_equivs]"
|
||||
|
||||
# SDFF family
|
||||
set sdff_x1 [get_lib_cell NangateOpenCellLibrary/SDFF_X1]
|
||||
set sdff_equivs [sta::find_equiv_cells $sdff_x1]
|
||||
puts "SDFF equiv count: [llength $sdff_equivs]"
|
||||
|
||||
# CLKBUF family
|
||||
set clkbuf_x1 [get_lib_cell NangateOpenCellLibrary/CLKBUF_X1]
|
||||
set clkbuf_equivs [sta::find_equiv_cells $clkbuf_x1]
|
||||
puts "CLKBUF equiv count: [llength $clkbuf_equivs]"
|
||||
|
||||
# XOR2 family
|
||||
set xor2_x1 [get_lib_cell NangateOpenCellLibrary/XOR2_X1]
|
||||
set xor2_equivs [sta::find_equiv_cells $xor2_x1]
|
||||
puts "XOR2 equiv count: [llength $xor2_equivs]"
|
||||
|
||||
############################################################
|
||||
# Cross-library equiv_cells comparisons
|
||||
############################################################
|
||||
|
||||
set fast_inv_x1 [get_lib_cell NangateOpenCellLibrary_fast/INV_X1]
|
||||
set slow_inv_x1 [get_lib_cell NangateOpenCellLibrary_slow/INV_X1]
|
||||
|
||||
set result [sta::equiv_cells $inv_x1 $fast_inv_x1]
|
||||
puts "INV_X1 typ equiv fast: $result"
|
||||
|
||||
set result [sta::equiv_cells $inv_x1 $slow_inv_x1]
|
||||
puts "INV_X1 typ equiv slow: $result"
|
||||
|
||||
set result [sta::equiv_cells $fast_inv_x1 $slow_inv_x1]
|
||||
puts "INV_X1 fast equiv slow: $result"
|
||||
|
||||
# Cross-library BUF
|
||||
set fast_buf_x1 [get_lib_cell NangateOpenCellLibrary_fast/BUF_X1]
|
||||
set result [sta::equiv_cells $buf_x1 $fast_buf_x1]
|
||||
puts "BUF_X1 typ equiv fast: $result"
|
||||
|
||||
# Cross-library NAND2
|
||||
set fast_nand2_x1 [get_lib_cell NangateOpenCellLibrary_fast/NAND2_X1]
|
||||
set result [sta::equiv_cells $nand2_x1 $fast_nand2_x1]
|
||||
puts "NAND2_X1 typ equiv fast: $result"
|
||||
|
||||
# Cross-library DFF
|
||||
set fast_dff_x1 [get_lib_cell NangateOpenCellLibrary_fast/DFF_X1]
|
||||
set result [sta::equiv_cells $dff_x1 $fast_dff_x1]
|
||||
puts "DFF_X1 typ equiv fast: $result"
|
||||
|
||||
############################################################
|
||||
# equiv_cell_ports cross-library
|
||||
############################################################
|
||||
|
||||
set result [sta::equiv_cell_ports $inv_x1 $fast_inv_x1]
|
||||
puts "equiv_cell_ports INV typ/fast: $result"
|
||||
|
||||
set result [sta::equiv_cell_ports $buf_x1 $fast_buf_x1]
|
||||
puts "equiv_cell_ports BUF typ/fast: $result"
|
||||
|
||||
# Different function should NOT match
|
||||
set result [sta::equiv_cell_ports $inv_x1 $buf_x1]
|
||||
puts "equiv_cell_ports INV/BUF: $result"
|
||||
|
||||
set result [sta::equiv_cell_ports $nand2_x1 $nand3_x1]
|
||||
puts "equiv_cell_ports NAND2/NAND3: $result"
|
||||
|
||||
############################################################
|
||||
# equiv_cell_timing_arcs cross-library
|
||||
############################################################
|
||||
|
||||
set result [sta::equiv_cell_timing_arcs $inv_x1 $fast_inv_x1]
|
||||
puts "equiv_cell_timing_arcs INV typ/fast: $result"
|
||||
|
||||
set result [sta::equiv_cell_timing_arcs $buf_x1 $fast_buf_x1]
|
||||
puts "equiv_cell_timing_arcs BUF typ/fast: $result"
|
||||
|
||||
set result [sta::equiv_cell_timing_arcs $inv_x1 $buf_x1]
|
||||
puts "equiv_cell_timing_arcs INV/BUF: $result"
|
||||
|
||||
############################################################
|
||||
# Find library buffers for each library
|
||||
############################################################
|
||||
|
||||
set typ_buffers [sta::find_library_buffers $typ_lib]
|
||||
puts "typ library buffers: [llength $typ_buffers]"
|
||||
|
||||
set fast_lib [lindex [get_libs NangateOpenCellLibrary_fast] 0]
|
||||
set fast_buffers [sta::find_library_buffers $fast_lib]
|
||||
puts "fast library buffers: [llength $fast_buffers]"
|
||||
|
||||
set slow_lib [lindex [get_libs NangateOpenCellLibrary_slow] 0]
|
||||
set slow_buffers [sta::find_library_buffers $slow_lib]
|
||||
puts "slow library buffers: [llength $slow_buffers]"
|
||||
|
||||
############################################################
|
||||
# Additional equiv cells in typ library - within family
|
||||
############################################################
|
||||
|
||||
# Same family - different sizes
|
||||
set inv_x2 [get_lib_cell NangateOpenCellLibrary/INV_X2]
|
||||
set inv_x4 [get_lib_cell NangateOpenCellLibrary/INV_X4]
|
||||
set inv_x8 [get_lib_cell NangateOpenCellLibrary/INV_X8]
|
||||
set inv_x16 [get_lib_cell NangateOpenCellLibrary/INV_X16]
|
||||
set inv_x32 [get_lib_cell NangateOpenCellLibrary/INV_X32]
|
||||
|
||||
set result [sta::equiv_cells $inv_x1 $inv_x2]
|
||||
puts "INV_X1 equiv INV_X2: $result"
|
||||
|
||||
set result [sta::equiv_cells $inv_x1 $inv_x4]
|
||||
puts "INV_X1 equiv INV_X4: $result"
|
||||
|
||||
set result [sta::equiv_cells $inv_x1 $inv_x8]
|
||||
puts "INV_X1 equiv INV_X8: $result"
|
||||
|
||||
set result [sta::equiv_cells $inv_x1 $inv_x16]
|
||||
puts "INV_X1 equiv INV_X16: $result"
|
||||
|
||||
set result [sta::equiv_cells $inv_x1 $inv_x32]
|
||||
puts "INV_X1 equiv INV_X32: $result"
|
||||
|
||||
# Different family comparisons
|
||||
set result [sta::equiv_cells $nand2_x1 $nor2_x1]
|
||||
puts "NAND2 equiv NOR2: $result"
|
||||
|
||||
set result [sta::equiv_cells $and2_x1 $or2_x1]
|
||||
puts "AND2 equiv OR2: $result"
|
||||
|
||||
set result [sta::equiv_cells $aoi21_x1 $oai21_x1]
|
||||
puts "AOI21 equiv OAI21: $result"
|
||||
|
||||
set dffr_x1 [get_lib_cell NangateOpenCellLibrary/DFFR_X1]
|
||||
set result [sta::equiv_cells $dff_x1 $dffr_x1]
|
||||
puts "DFF equiv DFFR: $result"
|
||||
|
||||
set dffs_x1 [get_lib_cell NangateOpenCellLibrary/DFFS_X1]
|
||||
set result [sta::equiv_cells $dff_x1 $dffs_x1]
|
||||
puts "DFF equiv DFFS: $result"
|
||||
|
||||
set dffrs_x1 [get_lib_cell NangateOpenCellLibrary/DFFRS_X1]
|
||||
set result [sta::equiv_cells $dffr_x1 $dffrs_x1]
|
||||
puts "DFFR equiv DFFRS: $result"
|
||||
|
||||
############################################################
|
||||
# Read LVT library and make equiv cells
|
||||
############################################################
|
||||
|
||||
read_liberty ../../test/nangate45/Nangate45_lvt.lib
|
||||
|
||||
set lvt_lib [lindex [get_libs NangateOpenCellLibrary_lvt] 0]
|
||||
sta::make_equiv_cells $lvt_lib
|
||||
|
||||
set lvt_inv_x1 [get_lib_cell NangateOpenCellLibrary_lvt/INV_X1_L]
|
||||
set lvt_inv_equivs [sta::find_equiv_cells $lvt_inv_x1]
|
||||
puts "LVT INV equiv count: [llength $lvt_inv_equivs]"
|
||||
|
||||
set lvt_buffers [sta::find_library_buffers $lvt_lib]
|
||||
puts "LVT library buffers: [llength $lvt_buffers]"
|
||||
|
||||
# Cross library with LVT (different cell naming so not equiv)
|
||||
set result [sta::equiv_cells $inv_x1 $lvt_inv_x1]
|
||||
puts "INV_X1 equiv LVT INV_X1_L: $result"
|
||||
|
||||
set result [sta::equiv_cell_ports $inv_x1 $lvt_inv_x1]
|
||||
puts "equiv_cell_ports INV/LVT_INV: $result"
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
Warning 441: liberty_opcond_scale.tcl line 1, set_input_delay relative to a clock defined on the same port/pin not allowed.
|
||||
No paths found.
|
||||
INFO: wireload selection not found
|
||||
No paths found.
|
||||
No paths found.
|
||||
max slew
|
||||
|
||||
Pin inv1/ZN ^
|
||||
max slew 0.15
|
||||
slew 0.02
|
||||
----------------
|
||||
Slack 0.13 (MET)
|
||||
|
||||
max capacitance
|
||||
|
||||
Pin nor1/ZN ^
|
||||
max capacitance 26.70
|
||||
capacitance 1.16
|
||||
-----------------------
|
||||
Slack 25.55 (MET)
|
||||
|
||||
|
|
@ -0,0 +1,230 @@
|
|||
# Test operating conditions, scale factors, and multi-corner features.
|
||||
# Targets:
|
||||
# Liberty.cc: findOperatingConditions, defaultOperatingConditions,
|
||||
# scaleFactor (all overloads), addScaleFactors, findScaleFactors,
|
||||
# inverters(), buffers(), makeCornerMap, setDelayModelType,
|
||||
# findLibertyCellsMatching, findLibertyPortsMatching,
|
||||
# ocvArcDepth, defaultOcvDerate, supplyVoltage, supplyExists,
|
||||
# slewDerateFromLibrary, input/output/slewThresholds,
|
||||
# defaultMaxFanout/Slew/Capacitance, defaultFanoutLoad,
|
||||
# defaultIntrinsic, defaultPinResistance, footprint
|
||||
# LibertyReader.cc: operating_conditions, scale_factors visitor paths
|
||||
# EquivCells.cc: EquivCells constructor with map_libs path
|
||||
source ../../test/helpers.tcl
|
||||
|
||||
############################################################
|
||||
# Read Nangate45 library - has operating conditions
|
||||
############################################################
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
|
||||
set lib [sta::find_liberty NangateOpenCellLibrary]
|
||||
|
||||
############################################################
|
||||
# Operating conditions queries
|
||||
############################################################
|
||||
set op_cond [$lib find_operating_conditions typical]
|
||||
if { $op_cond == "NULL" } {
|
||||
puts "INFO: no operating_conditions named typical"
|
||||
}
|
||||
|
||||
set def_op [$lib default_operating_conditions]
|
||||
if { $def_op == "NULL" } {
|
||||
puts "INFO: no default operating conditions"
|
||||
}
|
||||
|
||||
############################################################
|
||||
# Set operating conditions and run timing
|
||||
############################################################
|
||||
read_verilog ../../sdc/test/sdc_test2.v
|
||||
link_design sdc_test2
|
||||
|
||||
create_clock -name clk1 -period 10 [get_ports clk1]
|
||||
create_clock -name clk2 -period 20 [get_ports clk2]
|
||||
set_input_delay -clock clk1 2.0 [all_inputs]
|
||||
set_output_delay -clock clk1 3.0 [all_outputs]
|
||||
set_input_transition 0.1 [all_inputs]
|
||||
|
||||
set_operating_conditions typical
|
||||
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
|
||||
############################################################
|
||||
# Library cell classification queries
|
||||
# Exercises: inverters(), buffers(), isBuffer(), isInverter()
|
||||
############################################################
|
||||
set inv_cell [sta::find_liberty_cell INV_X1]
|
||||
|
||||
set buf_cell [sta::find_liberty_cell BUF_X1]
|
||||
|
||||
set inv_is_inv [$inv_cell is_inverter]
|
||||
|
||||
set inv_is_buf [$inv_cell is_buffer]
|
||||
|
||||
set buf_is_buf [$buf_cell is_buffer]
|
||||
|
||||
set buf_is_inv [$buf_cell is_inverter]
|
||||
|
||||
# Test is_leaf on various cells
|
||||
set dff_cell [sta::find_liberty_cell DFF_X1]
|
||||
set dff_leaf [$dff_cell is_leaf]
|
||||
|
||||
# Liberty library accessor on cell
|
||||
set cell_lib [$inv_cell liberty_library]
|
||||
|
||||
############################################################
|
||||
# Pattern matching on liberty cells
|
||||
# Exercises: findLibertyCellsMatching, findLibertyPortsMatching
|
||||
############################################################
|
||||
set inv_matches [$lib find_liberty_cells_matching "INV*" 0 0]
|
||||
|
||||
set buf_matches [$lib find_liberty_cells_matching "BUF*" 0 0]
|
||||
|
||||
set dff_matches [$lib find_liberty_cells_matching "DFF*" 0 0]
|
||||
|
||||
set sdff_matches [$lib find_liberty_cells_matching "SDFF*" 0 0]
|
||||
|
||||
set all_matches [$lib find_liberty_cells_matching "*" 0 0]
|
||||
|
||||
# Port pattern matching
|
||||
set inv_port_matches [$inv_cell find_liberty_ports_matching "*" 0 0]
|
||||
|
||||
set dff_port_matches [$dff_cell find_liberty_ports_matching "*" 0 0]
|
||||
|
||||
############################################################
|
||||
# Timing arc queries on cells
|
||||
# Exercises: timingArcSets, timingArcSetCount, hasTimingArcs
|
||||
############################################################
|
||||
set inv_arc_sets [$inv_cell timing_arc_sets]
|
||||
|
||||
set dff_arc_sets [$dff_cell timing_arc_sets]
|
||||
|
||||
# Check timing arc set ports
|
||||
set clkgate_cell [sta::find_liberty_cell CLKGATETST_X1]
|
||||
set clkgate_arcs [$clkgate_cell timing_arc_sets]
|
||||
|
||||
############################################################
|
||||
# Find port on liberty cell
|
||||
# Exercises: findLibertyPort
|
||||
############################################################
|
||||
set inv_a [$inv_cell find_liberty_port A]
|
||||
|
||||
set inv_zn [$inv_cell find_liberty_port ZN]
|
||||
|
||||
set dff_ck [$dff_cell find_liberty_port CK]
|
||||
|
||||
set dff_d [$dff_cell find_liberty_port D]
|
||||
|
||||
set dff_q [$dff_cell find_liberty_port Q]
|
||||
|
||||
############################################################
|
||||
# Liberty port iterator on cell
|
||||
# Exercises: LibertyCellPortIterator
|
||||
############################################################
|
||||
set port_iter [$inv_cell liberty_port_iterator]
|
||||
set count 0
|
||||
while { [$port_iter has_next] } {
|
||||
set port [$port_iter next]
|
||||
incr count
|
||||
}
|
||||
$port_iter finish
|
||||
|
||||
set port_iter2 [$dff_cell liberty_port_iterator]
|
||||
set count2 0
|
||||
while { [$port_iter2 has_next] } {
|
||||
set port [$port_iter2 next]
|
||||
incr count2
|
||||
}
|
||||
$port_iter2 finish
|
||||
|
||||
############################################################
|
||||
# Wireload queries
|
||||
# Exercises: findWireload, findWireloadSelection
|
||||
############################################################
|
||||
set wl [$lib find_wireload "1K_hvratio_1_1"]
|
||||
if { $wl == "NULL" } {
|
||||
puts "INFO: wireload not found"
|
||||
}
|
||||
|
||||
set wls [$lib find_wireload_selection "WireloadSelection"]
|
||||
if { $wls == "NULL" } {
|
||||
puts "INFO: wireload selection not found"
|
||||
}
|
||||
|
||||
############################################################
|
||||
# Read Sky130 library - has different features
|
||||
############################################################
|
||||
read_liberty ../../test/sky130hd/sky130hd_tt.lib
|
||||
|
||||
set sky_lib [sta::find_liberty sky130_fd_sc_hd__tt_025C_1v80]
|
||||
|
||||
set sky_op [$sky_lib find_operating_conditions "tt_025C_1v80"]
|
||||
if { $sky_op == "NULL" } {
|
||||
puts "INFO: sky130 no named operating conditions"
|
||||
}
|
||||
|
||||
set sky_def_op [$sky_lib default_operating_conditions]
|
||||
if { $sky_def_op == "NULL" } {
|
||||
puts "INFO: sky130 no default operating conditions"
|
||||
}
|
||||
|
||||
############################################################
|
||||
# Read fast/slow libraries for multi-corner analysis
|
||||
# Exercises: makeCornerMap path, setCornerCell, scaleFactor
|
||||
############################################################
|
||||
read_liberty ../../test/nangate45/Nangate45_fast.lib
|
||||
|
||||
# Read slow too - exercises more corner mapping paths
|
||||
read_liberty ../../test/sky130hd/sky130_fd_sc_hd__ff_n40C_1v95.lib
|
||||
|
||||
read_liberty ../../test/sky130hd/sky130_fd_sc_hd__ss_n40C_1v40.lib
|
||||
|
||||
# Report checks exercises multi-library corner paths
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
|
||||
############################################################
|
||||
# set_timing_derate - exercises OCV paths
|
||||
############################################################
|
||||
set_timing_derate -early 0.95
|
||||
set_timing_derate -late 1.05
|
||||
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
|
||||
############################################################
|
||||
# Write liberty for Nangate to exercise all writer paths
|
||||
############################################################
|
||||
set outfile [make_result_file liberty_opcond_scale_write.lib]
|
||||
sta::write_liberty NangateOpenCellLibrary $outfile
|
||||
|
||||
set outfile2 [make_result_file liberty_opcond_scale_sky130.lib]
|
||||
sta::write_liberty sky130_fd_sc_hd__tt_025C_1v80 $outfile2
|
||||
|
||||
############################################################
|
||||
# EquivCells with multiple libraries
|
||||
# Exercises: EquivCells constructor with map_libs
|
||||
############################################################
|
||||
set lib1 [lindex [get_libs NangateOpenCellLibrary] 0]
|
||||
set lib2 [lindex [get_libs NangateOpenCellLibrary_fast] 0]
|
||||
|
||||
sta::make_equiv_cells $lib1
|
||||
|
||||
sta::make_equiv_cells $lib2
|
||||
|
||||
# Cross-library equiv
|
||||
set inv_typ [get_lib_cell NangateOpenCellLibrary/INV_X1]
|
||||
set inv_fast [get_lib_cell NangateOpenCellLibrary_fast/INV_X1]
|
||||
set result [sta::equiv_cells $inv_typ $inv_fast]
|
||||
|
||||
set buf_typ [get_lib_cell NangateOpenCellLibrary/BUF_X1]
|
||||
set buf_fast [get_lib_cell NangateOpenCellLibrary_fast/BUF_X1]
|
||||
set result [sta::equiv_cells $buf_typ $buf_fast]
|
||||
|
||||
# equiv_cell_ports across libraries
|
||||
set result [sta::equiv_cell_ports $inv_typ $inv_fast]
|
||||
|
||||
# equiv_cell_timing_arcs across libraries
|
||||
set result [sta::equiv_cell_timing_arcs $inv_typ $inv_fast]
|
||||
|
||||
############################################################
|
||||
# Report check types for max_cap, max_slew, max_fanout
|
||||
############################################################
|
||||
report_check_types -max_slew -max_capacitance -max_fanout -verbose
|
||||
|
|
@ -0,0 +1,713 @@
|
|||
--- supply voltage queries ---
|
||||
VPWR exists = 1
|
||||
VGND exists = 1
|
||||
VPB exists = 1
|
||||
VNB exists = 1
|
||||
BOGUS_SUPPLY exists = 0
|
||||
--- pg pin port queries ---
|
||||
inv_1/VGND dir=ground is_pg=1
|
||||
inv_1/VNB dir=bias is_pg=1
|
||||
inv_1/VPB dir=bias is_pg=1
|
||||
inv_1/VPWR dir=power is_pg=1
|
||||
sky130_fd_sc_hd__buf_1 pg_pin_count=4
|
||||
sky130_fd_sc_hd__nand2_1 pg_pin_count=4
|
||||
sky130_fd_sc_hd__dfxtp_1 pg_pin_count=4
|
||||
sky130_fd_sc_hd__dfrtp_1 pg_pin_count=4
|
||||
sky130_fd_sc_hd__ebufn_1 pg_pin_count=4
|
||||
sky130_fd_sc_hd__dlclkp_1 pg_pin_count=4
|
||||
sky130_fd_sc_hd__mux2_1 pg_pin_count=4
|
||||
sky130_fd_sc_hd__sdfxtp_1 pg_pin_count=4
|
||||
--- leakage power per-state queries ---
|
||||
sky130_fd_sc_hd__inv_1 area=3.753600
|
||||
sky130_fd_sc_hd__inv_2 area=3.753600
|
||||
sky130_fd_sc_hd__inv_4 area=6.256000
|
||||
sky130_fd_sc_hd__inv_8 area=11.260800
|
||||
sky130_fd_sc_hd__buf_1 area=3.753600
|
||||
sky130_fd_sc_hd__buf_2 area=5.004800
|
||||
sky130_fd_sc_hd__nand2_1 area=3.753600
|
||||
sky130_fd_sc_hd__nand3_1 area=5.004800
|
||||
sky130_fd_sc_hd__nor2_1 area=3.753600
|
||||
sky130_fd_sc_hd__nor3_1 area=5.004800
|
||||
sky130_fd_sc_hd__and2_1 area=6.256000
|
||||
sky130_fd_sc_hd__and3_1 area=6.256000
|
||||
sky130_fd_sc_hd__or2_1 area=6.256000
|
||||
sky130_fd_sc_hd__or3_1 area=6.256000
|
||||
sky130_fd_sc_hd__xor2_1 area=8.758400
|
||||
sky130_fd_sc_hd__xnor2_1 area=8.758400
|
||||
sky130_fd_sc_hd__a21o_1 area=7.507200
|
||||
sky130_fd_sc_hd__a21oi_1 area=5.004800
|
||||
sky130_fd_sc_hd__a22o_1 area=8.758400
|
||||
sky130_fd_sc_hd__a22oi_1 area=7.507200
|
||||
sky130_fd_sc_hd__o21a_1 area=7.507200
|
||||
sky130_fd_sc_hd__o21ai_0 area=5.004800
|
||||
sky130_fd_sc_hd__o22a_1 area=8.758400
|
||||
sky130_fd_sc_hd__o22ai_1 area=6.256000
|
||||
sky130_fd_sc_hd__mux2_1 area=11.260800
|
||||
sky130_fd_sc_hd__mux2i_1 area=10.009600
|
||||
sky130_fd_sc_hd__mux4_1 area=26.275200
|
||||
sky130_fd_sc_hd__ha_1 area=12.512000
|
||||
sky130_fd_sc_hd__fa_1 area=20.019199
|
||||
sky130_fd_sc_hd__dfxtp_1 area=20.019199
|
||||
sky130_fd_sc_hd__dfxtp_2 area=21.270399
|
||||
sky130_fd_sc_hd__dfxtp_4 area=23.772800
|
||||
sky130_fd_sc_hd__dfrtp_1 area=25.024000
|
||||
sky130_fd_sc_hd__dfrtp_2 area=26.275200
|
||||
sky130_fd_sc_hd__dfrtp_4 area=28.777599
|
||||
sky130_fd_sc_hd__dfstp_1 area=26.275200
|
||||
sky130_fd_sc_hd__dfstp_2 area=26.275200
|
||||
sky130_fd_sc_hd__dfstp_4 area=30.028799
|
||||
sky130_fd_sc_hd__dfbbp_1 area=32.531200
|
||||
Warning 354: liberty_pgpin_voltage.tcl line 1, cell 'sky130_fd_sc_hd__dfbbp_2' not found.
|
||||
sky130_fd_sc_hd__dlxtp_1 area=15.014400
|
||||
sky130_fd_sc_hd__dlxtn_1 area=15.014400
|
||||
sky130_fd_sc_hd__dlxbn_1 area=18.768000
|
||||
sky130_fd_sc_hd__sdfxtp_1 area=26.275200
|
||||
sky130_fd_sc_hd__sdfxtp_2 area=27.526400
|
||||
sky130_fd_sc_hd__sdfrtp_1 area=31.280001
|
||||
sky130_fd_sc_hd__sdfstp_1 area=33.782398
|
||||
sky130_fd_sc_hd__sdlclkp_1 area=18.768000
|
||||
sky130_fd_sc_hd__dlclkp_1 area=17.516800
|
||||
--- detailed cell reports with pg_pin ---
|
||||
Cell sky130_fd_sc_hd__inv_1
|
||||
Library sky130_fd_sc_hd__tt_025C_1v80
|
||||
File ../../test/sky130hd/sky130hd_tt.lib
|
||||
VGND ground
|
||||
VNB bias
|
||||
VPB bias
|
||||
VPWR power
|
||||
A input 0.00-0.00
|
||||
Y output function=!A
|
||||
|
||||
Timing arcs
|
||||
A -> Y
|
||||
combinational
|
||||
^ -> v
|
||||
v -> ^
|
||||
Cell sky130_fd_sc_hd__dfxtp_1
|
||||
Library sky130_fd_sc_hd__tt_025C_1v80
|
||||
File ../../test/sky130hd/sky130hd_tt.lib
|
||||
VGND ground
|
||||
VNB bias
|
||||
VPB bias
|
||||
VPWR power
|
||||
CLK input 0.00-0.00
|
||||
D input 0.00-0.00
|
||||
Q output function=IQ
|
||||
IQ internal
|
||||
IQ_N internal
|
||||
|
||||
Timing arcs
|
||||
CLK -> CLK
|
||||
width
|
||||
^ -> v
|
||||
v -> ^
|
||||
CLK -> D
|
||||
setup
|
||||
^ -> ^
|
||||
^ -> v
|
||||
CLK -> D
|
||||
hold
|
||||
^ -> ^
|
||||
^ -> v
|
||||
CLK -> Q
|
||||
Reg Clk to Q
|
||||
^ -> ^
|
||||
^ -> v
|
||||
Cell sky130_fd_sc_hd__dfrtp_1
|
||||
Library sky130_fd_sc_hd__tt_025C_1v80
|
||||
File ../../test/sky130hd/sky130hd_tt.lib
|
||||
VGND ground
|
||||
VNB bias
|
||||
VPB bias
|
||||
VPWR power
|
||||
CLK input 0.00-0.00
|
||||
D input 0.00-0.00
|
||||
Q output function=IQ
|
||||
RESET_B input 0.00-0.00
|
||||
IQ internal
|
||||
IQ_N internal
|
||||
|
||||
Timing arcs
|
||||
CLK -> CLK
|
||||
width
|
||||
^ -> v
|
||||
v -> ^
|
||||
CLK -> D
|
||||
setup
|
||||
^ -> ^
|
||||
^ -> v
|
||||
CLK -> D
|
||||
hold
|
||||
^ -> ^
|
||||
^ -> v
|
||||
CLK -> Q
|
||||
Reg Clk to Q
|
||||
^ -> ^
|
||||
^ -> v
|
||||
RESET_B -> Q
|
||||
Reg Set/Clr
|
||||
v -> v
|
||||
CLK -> RESET_B
|
||||
recovery
|
||||
^ -> ^
|
||||
CLK -> RESET_B
|
||||
removal
|
||||
^ -> ^
|
||||
RESET_B -> RESET_B
|
||||
width
|
||||
v -> ^
|
||||
Cell sky130_fd_sc_hd__ebufn_1
|
||||
Library sky130_fd_sc_hd__tt_025C_1v80
|
||||
File ../../test/sky130hd/sky130hd_tt.lib
|
||||
VGND ground
|
||||
VNB bias
|
||||
VPB bias
|
||||
VPWR power
|
||||
A input 0.00-0.00
|
||||
TE_B input 0.00-0.00
|
||||
Z tristate enable=!TE_B function=A 0.00
|
||||
|
||||
Timing arcs
|
||||
A -> Z
|
||||
combinational
|
||||
^ -> ^
|
||||
v -> v
|
||||
TE_B -> Z
|
||||
tristate enable
|
||||
v -> Z1
|
||||
v -> Z0
|
||||
TE_B -> Z
|
||||
tristate disable
|
||||
^ -> 0Z
|
||||
^ -> 1Z
|
||||
Cell sky130_fd_sc_hd__dlclkp_1
|
||||
Library sky130_fd_sc_hd__tt_025C_1v80
|
||||
File ../../test/sky130hd/sky130hd_tt.lib
|
||||
VGND ground
|
||||
VNB bias
|
||||
VPB bias
|
||||
VPWR power
|
||||
CLK input 0.00-0.00
|
||||
GATE input 0.00-0.00
|
||||
GCLK output
|
||||
M0 internal
|
||||
|
||||
Timing arcs
|
||||
CLK -> CLK
|
||||
width
|
||||
v -> ^
|
||||
CLK -> GATE
|
||||
setup
|
||||
^ -> ^
|
||||
^ -> v
|
||||
CLK -> GATE
|
||||
hold
|
||||
^ -> ^
|
||||
^ -> v
|
||||
CLK -> GCLK
|
||||
combinational
|
||||
^ -> ^
|
||||
v -> v
|
||||
IHP sg13g2_inv_1 area=5.443200
|
||||
IHP sg13g2_inv_1 pg_pins=0
|
||||
IHP sg13g2_buf_1 area=7.257600
|
||||
IHP sg13g2_buf_1 pg_pins=0
|
||||
IHP sg13g2_nand2_1 area=7.257600
|
||||
IHP sg13g2_nand2_1 pg_pins=0
|
||||
IHP sg13g2_nor2_1 area=7.257600
|
||||
IHP sg13g2_nor2_1 pg_pins=0
|
||||
IHP sg13g2_and2_1 area=9.072000
|
||||
IHP sg13g2_and2_1 pg_pins=0
|
||||
IHP sg13g2_or2_1 area=9.072000
|
||||
IHP sg13g2_or2_1 pg_pins=0
|
||||
IHP sg13g2_dfrbp_1 area=47.174400
|
||||
IHP sg13g2_dfrbp_1 pg_pins=0
|
||||
IHP sg13g2_dlhq_1 area=30.844801
|
||||
IHP sg13g2_dlhq_1 pg_pins=0
|
||||
Warning 441: liberty_pgpin_voltage.tcl line 1, set_input_delay relative to a clock defined on the same port/pin not allowed.
|
||||
Group Internal Switching Leakage Total
|
||||
Power Power Power Power (Watts)
|
||||
----------------------------------------------------------------
|
||||
Sequential 1.76e-06 6.90e-09 2.36e-07 2.01e-06 86.3%
|
||||
Combinational 1.22e-07 7.11e-08 1.25e-07 3.18e-07 13.7%
|
||||
Clock 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
|
||||
Macro 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
|
||||
Pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
|
||||
----------------------------------------------------------------
|
||||
Total 1.88e-06 7.80e-08 3.61e-07 2.32e-06 100.0%
|
||||
81.1% 3.4% 15.5%
|
||||
Group Internal Switching Leakage Total
|
||||
Power Power Power Power (Watts)
|
||||
------------------------------------------------------------------------
|
||||
Sequential 1.762633e-06 6.898755e-09 2.356813e-07 2.005213e-06 86.3%
|
||||
Combinational 1.221472e-07 7.108275e-08 1.250753e-07 3.183053e-07 13.7%
|
||||
Clock 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.0%
|
||||
Macro 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.0%
|
||||
Pad 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.0%
|
||||
------------------------------------------------------------------------
|
||||
Total 1.884780e-06 7.798150e-08 3.607567e-07 2.323518e-06 100.0%
|
||||
81.1% 3.4% 15.5%
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfbbn_1 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfbbn_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfbbn_1 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfbbn_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfbbn_2 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfbbn_2.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfbbn_2 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfbbn_2.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfbbp_1 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfbbp_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfbbp_1 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfbbp_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfrbp_1 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfrbp_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfrbp_1 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfrbp_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfrbp_2 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfrbp_2.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfrbp_2 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfrbp_2.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfrtn_1 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfrtn_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfrtn_1 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfrtn_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfrtp_1 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfrtp_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfrtp_1 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfrtp_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfrtp_2 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfrtp_2.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfrtp_2 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfrtp_2.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfrtp_4 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfrtp_4.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfrtp_4 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfrtp_4.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfsbp_1 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfsbp_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfsbp_1 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfsbp_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfsbp_2 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfsbp_2.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfsbp_2 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfsbp_2.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfstp_1 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfstp_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfstp_1 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfstp_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfstp_2 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfstp_2.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfstp_2 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfstp_2.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfstp_4 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfstp_4.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfstp_4 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfstp_4.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfxbp_1 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfxbp_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfxbp_1 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfxbp_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfxbp_2 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfxbp_2.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfxbp_2 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfxbp_2.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfxtp_1 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfxtp_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfxtp_1 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfxtp_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfxtp_2 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfxtp_2.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfxtp_2 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfxtp_2.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfxtp_4 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfxtp_4.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfxtp_4 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfxtp_4.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlclkp_1 port M0 not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlclkp_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlclkp_2 port M0 not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlclkp_2.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlclkp_4 port M0 not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlclkp_4.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbn_1 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbn_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbn_1 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbn_1.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbn_1 D -> Q timing group Latch D to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbn_1.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbn_1 GATE_N -> Q timing group Latch En to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbn_1.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbn_1 D -> Q_N timing group Latch D to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbn_1.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbn_1 GATE_N -> Q_N timing group Latch En to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbn_1.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbn_1 D -> Q timing group combinational not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbn_1.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbn_1 GATE_N -> Q timing group Reg Clk to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbn_1.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbn_1 D -> Q_N timing group combinational not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbn_1.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbn_1 GATE_N -> Q_N timing group Reg Clk to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbn_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbn_2 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbn_2.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbn_2 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbn_2.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbn_2 D -> Q timing group Latch D to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbn_2.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbn_2 GATE_N -> Q timing group Latch En to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbn_2.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbn_2 D -> Q_N timing group Latch D to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbn_2.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbn_2 GATE_N -> Q_N timing group Latch En to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbn_2.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbn_2 D -> Q timing group combinational not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbn_2.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbn_2 GATE_N -> Q timing group Reg Clk to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbn_2.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbn_2 D -> Q_N timing group combinational not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbn_2.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbn_2 GATE_N -> Q_N timing group Reg Clk to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbn_2.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbp_1 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbp_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbp_1 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbp_1.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbp_1 D -> Q timing group Latch D to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbp_1.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbp_1 GATE -> Q timing group Latch En to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbp_1.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbp_1 D -> Q_N timing group Latch D to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbp_1.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbp_1 GATE -> Q_N timing group Latch En to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbp_1.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbp_1 D -> Q timing group combinational not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbp_1.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbp_1 GATE -> Q timing group Reg Clk to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbp_1.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbp_1 D -> Q_N timing group combinational not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbp_1.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbp_1 GATE -> Q_N timing group Reg Clk to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbp_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbp_2 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbp_2.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbp_2 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbp_2.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbp_2 D -> Q timing group Latch D to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbp_2.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbp_2 GATE -> Q timing group Latch En to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbp_2.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbp_2 D -> Q_N timing group Latch D to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbp_2.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbp_2 GATE -> Q_N timing group Latch En to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbp_2.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbp_2 D -> Q timing group combinational not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbp_2.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbp_2 GATE -> Q timing group Reg Clk to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbp_2.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbp_2 D -> Q_N timing group combinational not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbp_2.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbp_2 GATE -> Q_N timing group Reg Clk to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbp_2.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtn_1 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtn_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtn_1 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtn_1.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtn_1 D -> Q timing group Latch D to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtn_1.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtn_1 GATE_N -> Q timing group Latch En to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtn_1.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtn_1 D -> Q timing group combinational not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtn_1.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtn_1 GATE_N -> Q timing group Reg Clk to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtn_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtn_2 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtn_2.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtn_2 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtn_2.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtn_2 D -> Q timing group Latch D to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtn_2.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtn_2 GATE_N -> Q timing group Latch En to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtn_2.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtn_2 D -> Q timing group combinational not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtn_2.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtn_2 GATE_N -> Q timing group Reg Clk to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtn_2.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtn_4 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtn_4.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtn_4 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtn_4.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtn_4 D -> Q timing group Latch D to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtn_4.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtn_4 GATE_N -> Q timing group Latch En to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtn_4.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtn_4 D -> Q timing group combinational not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtn_4.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtn_4 GATE_N -> Q timing group Reg Clk to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtn_4.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtp_1 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtp_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtp_1 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtp_1.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtp_1 D -> Q timing group Latch D to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtp_1.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtp_1 GATE -> Q timing group Latch En to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtp_1.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtp_1 D -> Q timing group combinational not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtp_1.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtp_1 GATE -> Q timing group Reg Clk to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtp_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtp_2 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtp_2.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtp_2 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtp_2.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtp_2 D -> Q timing group Latch D to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtp_2.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtp_2 GATE -> Q timing group Latch En to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtp_2.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtp_2 D -> Q timing group combinational not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtp_2.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtp_2 GATE -> Q timing group Reg Clk to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtp_2.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtp_4 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtp_4.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtp_4 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtp_4.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtp_4 D -> Q timing group Latch D to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtp_4.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtp_4 GATE -> Q timing group Latch En to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtp_4.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtp_4 D -> Q timing group combinational not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtp_4.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtp_4 GATE -> Q timing group Reg Clk to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtp_4.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbn_1 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbn_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbn_1 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbn_1.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbn_1 D -> Q timing group Latch D to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbn_1.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbn_1 GATE_N -> Q timing group Latch En to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbn_1.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbn_1 D -> Q_N timing group Latch D to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbn_1.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbn_1 GATE_N -> Q_N timing group Latch En to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbn_1.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbn_1 D -> Q timing group combinational not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbn_1.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbn_1 GATE_N -> Q timing group Reg Clk to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbn_1.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbn_1 D -> Q_N timing group combinational not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbn_1.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbn_1 GATE_N -> Q_N timing group Reg Clk to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbn_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbn_2 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbn_2.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbn_2 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbn_2.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbn_2 D -> Q timing group Latch D to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbn_2.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbn_2 GATE_N -> Q timing group Latch En to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbn_2.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbn_2 D -> Q_N timing group Latch D to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbn_2.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbn_2 GATE_N -> Q_N timing group Latch En to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbn_2.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbn_2 D -> Q timing group combinational not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbn_2.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbn_2 GATE_N -> Q timing group Reg Clk to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbn_2.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbn_2 D -> Q_N timing group combinational not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbn_2.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbn_2 GATE_N -> Q_N timing group Reg Clk to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbn_2.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbp_1 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbp_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbp_1 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbp_1.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbp_1 D -> Q timing group Latch D to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbp_1.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbp_1 GATE -> Q timing group Latch En to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbp_1.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbp_1 D -> Q_N timing group Latch D to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbp_1.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbp_1 GATE -> Q_N timing group Latch En to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbp_1.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbp_1 D -> Q timing group combinational not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbp_1.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbp_1 GATE -> Q timing group Reg Clk to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbp_1.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbp_1 D -> Q_N timing group combinational not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbp_1.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbp_1 GATE -> Q_N timing group Reg Clk to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbp_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxtn_1 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxtn_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxtn_1 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxtn_1.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxtn_1 D -> Q timing group Latch D to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxtn_1.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxtn_1 GATE_N -> Q timing group Latch En to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxtn_1.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxtn_1 D -> Q timing group combinational not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxtn_1.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxtn_1 GATE_N -> Q timing group Reg Clk to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxtn_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxtn_2 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxtn_2.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxtn_2 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxtn_2.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxtn_2 D -> Q timing group Latch D to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxtn_2.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxtn_2 GATE_N -> Q timing group Latch En to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxtn_2.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxtn_2 D -> Q timing group combinational not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxtn_2.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxtn_2 GATE_N -> Q timing group Reg Clk to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxtn_2.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxtn_4 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxtn_4.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxtn_4 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxtn_4.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxtn_4 D -> Q timing group Latch D to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxtn_4.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxtn_4 GATE_N -> Q timing group Latch En to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxtn_4.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxtn_4 D -> Q timing group combinational not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxtn_4.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxtn_4 GATE_N -> Q timing group Reg Clk to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxtn_4.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxtp_1 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxtp_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxtp_1 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxtp_1.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxtp_1 D -> Q timing group Latch D to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxtp_1.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxtp_1 GATE -> Q timing group Latch En to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxtp_1.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxtp_1 D -> Q timing group combinational not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxtp_1.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxtp_1 GATE -> Q timing group Reg Clk to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxtp_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__edfxbp_1 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__edfxbp_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__edfxbp_1 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__edfxbp_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__edfxtp_1 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__edfxtp_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__edfxtp_1 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__edfxtp_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__lpflow_inputisolatch_1 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__lpflow_inputisolatch_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__lpflow_inputisolatch_1 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__lpflow_inputisolatch_1.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__lpflow_inputisolatch_1 D -> Q timing group Latch D to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__lpflow_inputisolatch_1.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__lpflow_inputisolatch_1 SLEEP_B -> Q timing group Latch En to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__lpflow_inputisolatch_1.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__lpflow_inputisolatch_1 D -> Q timing group combinational not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__lpflow_inputisolatch_1.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__lpflow_inputisolatch_1 SLEEP_B -> Q timing group Reg Clk to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__lpflow_inputisolatch_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfbbn_1 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfbbn_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfbbn_1 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfbbn_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfbbn_2 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfbbn_2.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfbbn_2 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfbbn_2.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfbbp_1 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfbbp_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfbbp_1 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfbbp_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfrbp_1 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfrbp_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfrbp_1 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfrbp_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfrbp_2 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfrbp_2.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfrbp_2 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfrbp_2.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfrtn_1 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfrtn_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfrtn_1 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfrtn_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfrtp_1 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfrtp_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfrtp_1 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfrtp_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfrtp_2 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfrtp_2.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfrtp_2 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfrtp_2.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfrtp_4 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfrtp_4.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfrtp_4 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfrtp_4.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfsbp_1 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfsbp_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfsbp_1 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfsbp_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfsbp_2 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfsbp_2.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfsbp_2 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfsbp_2.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfstp_1 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfstp_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfstp_1 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfstp_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfstp_2 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfstp_2.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfstp_2 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfstp_2.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfstp_4 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfstp_4.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfstp_4 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfstp_4.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfxbp_1 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfxbp_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfxbp_1 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfxbp_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfxbp_2 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfxbp_2.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfxbp_2 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfxbp_2.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfxtp_1 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfxtp_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfxtp_1 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfxtp_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfxtp_2 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfxtp_2.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfxtp_2 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfxtp_2.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfxtp_4 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfxtp_4.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfxtp_4 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfxtp_4.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdlclkp_1 port M0 not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdlclkp_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdlclkp_2 port M0 not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdlclkp_2.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdlclkp_4 port M0 not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdlclkp_4.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sedfxbp_1 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sedfxbp_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sedfxbp_1 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sedfxbp_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sedfxbp_2 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sedfxbp_2.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sedfxbp_2 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sedfxbp_2.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sedfxtp_1 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sedfxtp_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sedfxtp_1 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sedfxtp_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sedfxtp_2 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sedfxtp_2.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sedfxtp_2 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sedfxtp_2.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sedfxtp_4 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sedfxtp_4.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sedfxtp_4 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sedfxtp_4.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfbbn_1 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfbbn_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfbbn_1 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfbbn_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfbbn_2 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfbbn_2.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfbbn_2 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfbbn_2.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfbbp_1 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfbbp_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfbbp_1 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfbbp_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfrbp_1 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfrbp_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfrbp_1 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfrbp_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfrbp_2 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfrbp_2.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfrbp_2 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfrbp_2.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfrtn_1 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfrtn_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfrtn_1 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfrtn_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfrtp_1 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfrtp_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfrtp_1 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfrtp_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfrtp_2 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfrtp_2.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfrtp_2 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfrtp_2.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfrtp_4 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfrtp_4.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfrtp_4 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfrtp_4.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfsbp_1 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfsbp_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfsbp_1 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfsbp_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfsbp_2 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfsbp_2.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfsbp_2 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfsbp_2.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfstp_1 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfstp_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfstp_1 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfstp_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfstp_2 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfstp_2.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfstp_2 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfstp_2.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfstp_4 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfstp_4.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfstp_4 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfstp_4.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfxbp_1 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfxbp_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfxbp_1 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfxbp_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfxbp_2 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfxbp_2.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfxbp_2 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfxbp_2.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfxtp_1 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfxtp_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfxtp_1 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfxtp_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfxtp_2 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfxtp_2.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfxtp_2 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfxtp_2.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfxtp_4 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfxtp_4.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfxtp_4 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfxtp_4.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlclkp_1 port M0 not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlclkp_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlclkp_2 port M0 not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlclkp_2.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlclkp_4 port M0 not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlclkp_4.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbn_1 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbn_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbn_1 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbn_1.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbn_1 D -> Q timing group Latch D to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbn_1.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbn_1 GATE_N -> Q timing group Latch En to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbn_1.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbn_1 D -> Q_N timing group Latch D to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbn_1.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbn_1 GATE_N -> Q_N timing group Latch En to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbn_1.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbn_1 D -> Q timing group combinational not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbn_1.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbn_1 GATE_N -> Q timing group Reg Clk to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbn_1.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbn_1 D -> Q_N timing group combinational not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbn_1.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbn_1 GATE_N -> Q_N timing group Reg Clk to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbn_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbn_2 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbn_2.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbn_2 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbn_2.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbn_2 D -> Q timing group Latch D to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbn_2.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbn_2 GATE_N -> Q timing group Latch En to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbn_2.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbn_2 D -> Q_N timing group Latch D to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbn_2.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbn_2 GATE_N -> Q_N timing group Latch En to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbn_2.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbn_2 D -> Q timing group combinational not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbn_2.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbn_2 GATE_N -> Q timing group Reg Clk to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbn_2.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbn_2 D -> Q_N timing group combinational not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbn_2.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbn_2 GATE_N -> Q_N timing group Reg Clk to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbn_2.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbp_1 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbp_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbp_1 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbp_1.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbp_1 D -> Q timing group Latch D to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbp_1.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbp_1 GATE -> Q timing group Latch En to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbp_1.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbp_1 D -> Q_N timing group Latch D to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbp_1.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbp_1 GATE -> Q_N timing group Latch En to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbp_1.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbp_1 D -> Q timing group combinational not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbp_1.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbp_1 GATE -> Q timing group Reg Clk to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbp_1.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbp_1 D -> Q_N timing group combinational not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbp_1.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbp_1 GATE -> Q_N timing group Reg Clk to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbp_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbp_2 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbp_2.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbp_2 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbp_2.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbp_2 D -> Q timing group Latch D to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbp_2.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbp_2 GATE -> Q timing group Latch En to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbp_2.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbp_2 D -> Q_N timing group Latch D to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbp_2.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbp_2 GATE -> Q_N timing group Latch En to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbp_2.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbp_2 D -> Q timing group combinational not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbp_2.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbp_2 GATE -> Q timing group Reg Clk to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbp_2.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbp_2 D -> Q_N timing group combinational not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbp_2.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbp_2 GATE -> Q_N timing group Reg Clk to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrbp_2.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtn_1 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtn_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtn_1 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtn_1.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtn_1 D -> Q timing group Latch D to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtn_1.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtn_1 GATE_N -> Q timing group Latch En to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtn_1.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtn_1 D -> Q timing group combinational not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtn_1.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtn_1 GATE_N -> Q timing group Reg Clk to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtn_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtn_2 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtn_2.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtn_2 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtn_2.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtn_2 D -> Q timing group Latch D to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtn_2.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtn_2 GATE_N -> Q timing group Latch En to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtn_2.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtn_2 D -> Q timing group combinational not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtn_2.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtn_2 GATE_N -> Q timing group Reg Clk to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtn_2.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtn_4 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtn_4.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtn_4 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtn_4.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtn_4 D -> Q timing group Latch D to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtn_4.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtn_4 GATE_N -> Q timing group Latch En to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtn_4.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtn_4 D -> Q timing group combinational not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtn_4.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtn_4 GATE_N -> Q timing group Reg Clk to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtn_4.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtp_1 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtp_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtp_1 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtp_1.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtp_1 D -> Q timing group Latch D to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtp_1.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtp_1 GATE -> Q timing group Latch En to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtp_1.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtp_1 D -> Q timing group combinational not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtp_1.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtp_1 GATE -> Q timing group Reg Clk to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtp_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtp_2 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtp_2.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtp_2 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtp_2.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtp_2 D -> Q timing group Latch D to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtp_2.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtp_2 GATE -> Q timing group Latch En to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtp_2.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtp_2 D -> Q timing group combinational not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtp_2.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtp_2 GATE -> Q timing group Reg Clk to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtp_2.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtp_4 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtp_4.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtp_4 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtp_4.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtp_4 D -> Q timing group Latch D to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtp_4.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtp_4 GATE -> Q timing group Latch En to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtp_4.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtp_4 D -> Q timing group combinational not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtp_4.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtp_4 GATE -> Q timing group Reg Clk to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlrtp_4.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbn_1 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbn_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbn_1 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbn_1.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbn_1 D -> Q timing group Latch D to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbn_1.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbn_1 GATE_N -> Q timing group Latch En to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbn_1.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbn_1 D -> Q_N timing group Latch D to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbn_1.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbn_1 GATE_N -> Q_N timing group Latch En to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbn_1.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbn_1 D -> Q timing group combinational not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbn_1.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbn_1 GATE_N -> Q timing group Reg Clk to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbn_1.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbn_1 D -> Q_N timing group combinational not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbn_1.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbn_1 GATE_N -> Q_N timing group Reg Clk to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbn_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbn_2 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbn_2.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbn_2 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbn_2.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbn_2 D -> Q timing group Latch D to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbn_2.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbn_2 GATE_N -> Q timing group Latch En to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbn_2.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbn_2 D -> Q_N timing group Latch D to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbn_2.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbn_2 GATE_N -> Q_N timing group Latch En to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbn_2.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbn_2 D -> Q timing group combinational not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbn_2.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbn_2 GATE_N -> Q timing group Reg Clk to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbn_2.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbn_2 D -> Q_N timing group combinational not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbn_2.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbn_2 GATE_N -> Q_N timing group Reg Clk to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbn_2.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbp_1 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbp_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbp_1 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbp_1.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbp_1 D -> Q timing group Latch D to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbp_1.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbp_1 GATE -> Q timing group Latch En to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbp_1.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbp_1 D -> Q_N timing group Latch D to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbp_1.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbp_1 GATE -> Q_N timing group Latch En to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbp_1.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbp_1 D -> Q timing group combinational not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbp_1.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbp_1 GATE -> Q timing group Reg Clk to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbp_1.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbp_1 D -> Q_N timing group combinational not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbp_1.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbp_1 GATE -> Q_N timing group Reg Clk to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxbp_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxtn_1 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxtn_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxtn_1 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxtn_1.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxtn_1 D -> Q timing group Latch D to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxtn_1.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxtn_1 GATE_N -> Q timing group Latch En to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxtn_1.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxtn_1 D -> Q timing group combinational not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxtn_1.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxtn_1 GATE_N -> Q timing group Reg Clk to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxtn_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxtn_2 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxtn_2.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxtn_2 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxtn_2.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxtn_2 D -> Q timing group Latch D to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxtn_2.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxtn_2 GATE_N -> Q timing group Latch En to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxtn_2.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxtn_2 D -> Q timing group combinational not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxtn_2.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxtn_2 GATE_N -> Q timing group Reg Clk to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxtn_2.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxtn_4 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxtn_4.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxtn_4 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxtn_4.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxtn_4 D -> Q timing group Latch D to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxtn_4.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxtn_4 GATE_N -> Q timing group Latch En to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxtn_4.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxtn_4 D -> Q timing group combinational not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxtn_4.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxtn_4 GATE_N -> Q timing group Reg Clk to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxtn_4.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxtp_1 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxtp_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxtp_1 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxtp_1.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxtp_1 D -> Q timing group Latch D to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxtp_1.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxtp_1 GATE -> Q timing group Latch En to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxtp_1.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxtp_1 D -> Q timing group combinational not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxtp_1.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxtp_1 GATE -> Q timing group Reg Clk to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxtp_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__edfxbp_1 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__edfxbp_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__edfxbp_1 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__edfxbp_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__edfxtp_1 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__edfxtp_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__edfxtp_1 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__edfxtp_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__lpflow_inputisolatch_1 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__lpflow_inputisolatch_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__lpflow_inputisolatch_1 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__lpflow_inputisolatch_1.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__lpflow_inputisolatch_1 D -> Q timing group Latch D to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__lpflow_inputisolatch_1.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__lpflow_inputisolatch_1 SLEEP_B -> Q timing group Latch En to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__lpflow_inputisolatch_1.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__lpflow_inputisolatch_1 D -> Q timing group combinational not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__lpflow_inputisolatch_1.
|
||||
Warning 1111: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__lpflow_inputisolatch_1 SLEEP_B -> Q timing group Reg Clk to Q not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__lpflow_inputisolatch_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfbbn_1 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfbbn_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfbbn_1 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfbbn_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfbbn_2 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfbbn_2.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfbbn_2 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfbbn_2.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfbbp_1 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfbbp_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfbbp_1 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfbbp_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfrbp_1 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfrbp_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfrbp_1 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfrbp_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfrbp_2 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfrbp_2.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfrbp_2 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfrbp_2.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfrtn_1 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfrtn_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfrtn_1 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfrtn_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfrtp_1 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfrtp_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfrtp_1 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfrtp_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfrtp_2 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfrtp_2.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfrtp_2 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfrtp_2.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfrtp_4 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfrtp_4.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfrtp_4 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfrtp_4.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfsbp_1 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfsbp_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfsbp_1 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfsbp_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfsbp_2 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfsbp_2.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfsbp_2 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfsbp_2.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfstp_1 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfstp_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfstp_1 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfstp_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfstp_2 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfstp_2.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfstp_2 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfstp_2.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfstp_4 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfstp_4.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfstp_4 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfstp_4.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfxbp_1 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfxbp_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfxbp_1 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfxbp_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfxbp_2 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfxbp_2.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfxbp_2 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfxbp_2.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfxtp_1 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfxtp_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfxtp_1 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfxtp_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfxtp_2 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfxtp_2.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfxtp_2 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfxtp_2.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfxtp_4 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfxtp_4.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfxtp_4 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfxtp_4.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdlclkp_1 port M0 not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdlclkp_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdlclkp_2 port M0 not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdlclkp_2.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdlclkp_4 port M0 not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdlclkp_4.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sedfxbp_1 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sedfxbp_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sedfxbp_1 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sedfxbp_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sedfxbp_2 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sedfxbp_2.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sedfxbp_2 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sedfxbp_2.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sedfxtp_1 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sedfxtp_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sedfxtp_1 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sedfxtp_1.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sedfxtp_2 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sedfxtp_2.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sedfxtp_2 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sedfxtp_2.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sedfxtp_4 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sedfxtp_4.
|
||||
Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sedfxtp_4 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sedfxtp_4.
|
||||
|
|
@ -0,0 +1,184 @@
|
|||
# Test pg_pin, voltage_map, supply voltage, and power group parsing.
|
||||
source ../../test/helpers.tcl
|
||||
suppress_msg 1140
|
||||
|
||||
############################################################
|
||||
# Read Sky130 library (has pg_pin, voltage_map extensively)
|
||||
############################################################
|
||||
read_liberty ../../test/sky130hd/sky130hd_tt.lib
|
||||
|
||||
set sky_lib [sta::find_liberty sky130_fd_sc_hd__tt_025C_1v80]
|
||||
|
||||
############################################################
|
||||
# Check supply voltage existence
|
||||
############################################################
|
||||
puts "--- supply voltage queries ---"
|
||||
|
||||
# sky130hd has VPWR and VGND supply names
|
||||
set vpwr_exists [sta::liberty_supply_exists "VPWR"]
|
||||
puts "VPWR exists = $vpwr_exists"
|
||||
|
||||
set vgnd_exists [sta::liberty_supply_exists "VGND"]
|
||||
puts "VGND exists = $vgnd_exists"
|
||||
|
||||
set vbp_exists [sta::liberty_supply_exists "VPB"]
|
||||
puts "VPB exists = $vbp_exists"
|
||||
|
||||
set vbn_exists [sta::liberty_supply_exists "VNB"]
|
||||
puts "VNB exists = $vbn_exists"
|
||||
|
||||
set nonexist [sta::liberty_supply_exists "BOGUS_SUPPLY"]
|
||||
puts "BOGUS_SUPPLY exists = $nonexist"
|
||||
|
||||
############################################################
|
||||
# Query PG pin ports (power/ground pins)
|
||||
############################################################
|
||||
puts "--- pg pin port queries ---"
|
||||
|
||||
# Inverter has VPWR, VGND, VPB, VNB pg_pins
|
||||
set inv_cell [get_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__inv_1]
|
||||
set port_iter [$inv_cell liberty_port_iterator]
|
||||
while {[$port_iter has_next]} {
|
||||
set port [$port_iter next]
|
||||
set is_pg [$port is_pwr_gnd]
|
||||
set dir [sta::liberty_port_direction $port]
|
||||
set name [get_name $port]
|
||||
if {$is_pg} {
|
||||
puts "inv_1/$name dir=$dir is_pg=$is_pg"
|
||||
}
|
||||
}
|
||||
$port_iter finish
|
||||
|
||||
# Query PG pins on various cell types
|
||||
foreach cell_name {sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__nand2_1
|
||||
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfrtp_1
|
||||
sky130_fd_sc_hd__ebufn_1 sky130_fd_sc_hd__dlclkp_1
|
||||
sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__sdfxtp_1} {
|
||||
set cell [get_lib_cell sky130_fd_sc_hd__tt_025C_1v80/$cell_name]
|
||||
if {$cell != "NULL" && $cell ne ""} {
|
||||
set pg_count 0
|
||||
set port_iter [$cell liberty_port_iterator]
|
||||
while {[$port_iter has_next]} {
|
||||
set port [$port_iter next]
|
||||
if {[$port is_pwr_gnd]} {
|
||||
incr pg_count
|
||||
}
|
||||
}
|
||||
$port_iter finish
|
||||
puts "$cell_name pg_pin_count=$pg_count"
|
||||
}
|
||||
}
|
||||
|
||||
############################################################
|
||||
# Leakage power with when conditions per state
|
||||
# Sky130 has per-state leakage_power groups
|
||||
############################################################
|
||||
puts "--- leakage power per-state queries ---"
|
||||
|
||||
foreach cell_name {sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_2
|
||||
sky130_fd_sc_hd__inv_4 sky130_fd_sc_hd__inv_8
|
||||
sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_2
|
||||
sky130_fd_sc_hd__nand2_1 sky130_fd_sc_hd__nand3_1
|
||||
sky130_fd_sc_hd__nor2_1 sky130_fd_sc_hd__nor3_1
|
||||
sky130_fd_sc_hd__and2_1 sky130_fd_sc_hd__and3_1
|
||||
sky130_fd_sc_hd__or2_1 sky130_fd_sc_hd__or3_1
|
||||
sky130_fd_sc_hd__xor2_1 sky130_fd_sc_hd__xnor2_1
|
||||
sky130_fd_sc_hd__a21o_1 sky130_fd_sc_hd__a21oi_1
|
||||
sky130_fd_sc_hd__a22o_1 sky130_fd_sc_hd__a22oi_1
|
||||
sky130_fd_sc_hd__o21a_1 sky130_fd_sc_hd__o21ai_0
|
||||
sky130_fd_sc_hd__o22a_1 sky130_fd_sc_hd__o22ai_1
|
||||
sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2i_1
|
||||
sky130_fd_sc_hd__mux4_1 sky130_fd_sc_hd__ha_1
|
||||
sky130_fd_sc_hd__fa_1} {
|
||||
set cell [get_lib_cell sky130_fd_sc_hd__tt_025C_1v80/$cell_name]
|
||||
if {$cell != "NULL" && $cell ne ""} {
|
||||
set area [get_property $cell area]
|
||||
puts "$cell_name area=$area"
|
||||
}
|
||||
}
|
||||
|
||||
# Sequential cells
|
||||
foreach cell_name {sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_2
|
||||
sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfrtp_1
|
||||
sky130_fd_sc_hd__dfrtp_2 sky130_fd_sc_hd__dfrtp_4
|
||||
sky130_fd_sc_hd__dfstp_1 sky130_fd_sc_hd__dfstp_2
|
||||
sky130_fd_sc_hd__dfstp_4 sky130_fd_sc_hd__dfbbp_1
|
||||
sky130_fd_sc_hd__dfbbp_2 sky130_fd_sc_hd__dlxtp_1
|
||||
sky130_fd_sc_hd__dlxtn_1 sky130_fd_sc_hd__dlxbn_1
|
||||
sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_2
|
||||
sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfstp_1
|
||||
sky130_fd_sc_hd__sdlclkp_1 sky130_fd_sc_hd__dlclkp_1} {
|
||||
set cell [get_lib_cell sky130_fd_sc_hd__tt_025C_1v80/$cell_name]
|
||||
if {$cell != "NULL" && $cell ne ""} {
|
||||
set area [get_property $cell area]
|
||||
puts "$cell_name area=$area"
|
||||
}
|
||||
}
|
||||
|
||||
############################################################
|
||||
# Report cells to exercise detailed pg_pin/power writer paths
|
||||
############################################################
|
||||
puts "--- detailed cell reports with pg_pin ---"
|
||||
|
||||
report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__inv_1
|
||||
report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfxtp_1
|
||||
report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfrtp_1
|
||||
report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__ebufn_1
|
||||
report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlclkp_1
|
||||
|
||||
############################################################
|
||||
# Read IHP library (different voltage/supply naming)
|
||||
############################################################
|
||||
read_liberty ../../test/ihp-sg13g2/sg13g2_stdcell_typ_1p20V_25C.lib
|
||||
|
||||
foreach cell_name {sg13g2_inv_1 sg13g2_buf_1 sg13g2_nand2_1
|
||||
sg13g2_nor2_1 sg13g2_and2_1 sg13g2_or2_1
|
||||
sg13g2_dfrbp_1 sg13g2_dlhq_1} {
|
||||
set cell [get_lib_cell sg13g2_stdcell_typ_1p20V_25C/$cell_name]
|
||||
if {$cell != "NULL" && $cell ne ""} {
|
||||
set area [get_property $cell area]
|
||||
puts "IHP $cell_name area=$area"
|
||||
# Query pg pins
|
||||
set pg_count 0
|
||||
set port_iter [$cell liberty_port_iterator]
|
||||
while {[$port_iter has_next]} {
|
||||
set port [$port_iter next]
|
||||
if {[$port is_pwr_gnd]} {
|
||||
incr pg_count
|
||||
}
|
||||
}
|
||||
$port_iter finish
|
||||
puts "IHP $cell_name pg_pins=$pg_count"
|
||||
}
|
||||
}
|
||||
|
||||
############################################################
|
||||
# Read IHP second corner
|
||||
############################################################
|
||||
read_liberty ../../test/ihp-sg13g2/sg13g2_stdcell_typ_1p50V_25C.lib
|
||||
|
||||
############################################################
|
||||
# Link design and run power analysis
|
||||
############################################################
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
read_verilog ../../sdc/test/sdc_test2.v
|
||||
link_design sdc_test2
|
||||
|
||||
create_clock -name clk1 -period 10 [get_ports clk1]
|
||||
create_clock -name clk2 -period 20 [get_ports clk2]
|
||||
set_input_delay -clock clk1 2.0 [all_inputs]
|
||||
set_output_delay -clock clk1 3.0 [all_outputs]
|
||||
set_input_transition 0.1 [all_inputs]
|
||||
|
||||
report_power
|
||||
|
||||
report_power -digits 6
|
||||
|
||||
############################################################
|
||||
# Write liberty roundtrip for Sky130 (with pg_pin groups)
|
||||
############################################################
|
||||
set outfile [make_result_file liberty_pgpin_voltage_write.lib]
|
||||
sta::write_liberty sky130_fd_sc_hd__tt_025C_1v80 $outfile
|
||||
|
||||
# Read back the written library to verify
|
||||
read_liberty $outfile
|
||||
|
|
@ -0,0 +1,69 @@
|
|||
Group Internal Switching Leakage Total
|
||||
Power Power Power Power (Watts)
|
||||
----------------------------------------------------------------
|
||||
Sequential 1.52e-06 6.90e-09 2.36e-07 1.76e-06 84.2%
|
||||
Combinational 1.33e-07 7.11e-08 1.25e-07 3.29e-07 15.8%
|
||||
Clock 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
|
||||
Macro 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
|
||||
Pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
|
||||
----------------------------------------------------------------
|
||||
Total 1.65e-06 7.80e-08 3.61e-07 2.09e-06 100.0%
|
||||
79.0% 3.7% 17.3%
|
||||
Group Internal Switching Leakage Total
|
||||
Power Power Power Power (Watts)
|
||||
------------------------------------------------------------------------
|
||||
Sequential 1.517312e-06 6.898755e-09 2.356813e-07 1.759892e-06 84.2%
|
||||
Combinational 1.332258e-07 7.108275e-08 1.250753e-07 3.293839e-07 15.8%
|
||||
Clock 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.0%
|
||||
Macro 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.0%
|
||||
Pad 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.0%
|
||||
------------------------------------------------------------------------
|
||||
Total 1.650538e-06 7.798150e-08 3.607567e-07 2.089276e-06 100.0%
|
||||
79.0% 3.7% 17.3%
|
||||
Internal Switching Leakage Total
|
||||
Power Power Power Power (Watts)
|
||||
--------------------------------------------
|
||||
3.04e-08 1.13e-08 2.14e-08 6.31e-08 buf1
|
||||
Internal Switching Leakage Total
|
||||
Power Power Power Power (Watts)
|
||||
--------------------------------------------
|
||||
2.33e-08 5.90e-09 1.44e-08 4.35e-08 inv1
|
||||
Internal Switching Leakage Total
|
||||
Power Power Power Power (Watts)
|
||||
--------------------------------------------
|
||||
2.56e-08 2.00e-08 2.51e-08 7.07e-08 and1
|
||||
Internal Switching Leakage Total
|
||||
Power Power Power Power (Watts)
|
||||
--------------------------------------------
|
||||
5.87e-07 6.90e-09 7.86e-08 6.73e-07 reg1
|
||||
Internal Switching Leakage Total
|
||||
Power Power Power Power (Watts)
|
||||
--------------------------------------------
|
||||
5.89e-07 0.00e+00 7.84e-08 6.67e-07 reg2
|
||||
Internal Switching Leakage Total
|
||||
Power Power Power Power (Watts)
|
||||
--------------------------------------------
|
||||
3.41e-07 0.00e+00 7.86e-08 4.20e-07 reg3
|
||||
Internal Switching Leakage Total
|
||||
Power Power Power Power (Watts)
|
||||
--------------------------------------------
|
||||
5.87e-07 6.90e-09 7.86e-08 6.73e-07 reg1
|
||||
5.89e-07 0.00e+00 7.84e-08 6.67e-07 reg2
|
||||
3.41e-07 0.00e+00 7.86e-08 4.20e-07 reg3
|
||||
2.56e-08 2.00e-08 2.51e-08 7.07e-08 and1
|
||||
2.70e-08 2.01e-08 2.27e-08 6.98e-08 or1
|
||||
3.04e-08 1.13e-08 2.14e-08 6.31e-08 buf1
|
||||
2.33e-08 5.90e-09 1.44e-08 4.35e-08 inv1
|
||||
1.46e-08 6.90e-09 1.97e-08 4.11e-08 nor1
|
||||
1.24e-08 6.90e-09 2.18e-08 4.11e-08 nand1
|
||||
INV_X1 area: 0.532000
|
||||
BUF_X1 area: 0.798000
|
||||
DFF_X1 area: 4.522000
|
||||
INV_X1 is_inverter: 1
|
||||
INV_X1 is_buffer: 0
|
||||
BUF_X1 is_buffer: 1
|
||||
BUF_X1 is_inverter: 0
|
||||
DFF_X1 is_buffer: 0
|
||||
sky130 inv area: 3.753600
|
||||
IHP inv area: 5.443200
|
||||
ASAP7 DFF area: 0.291600
|
||||
|
|
@ -0,0 +1,121 @@
|
|||
# Test internal power, leakage power, and power reporting for code coverage
|
||||
source ../../test/helpers.tcl
|
||||
|
||||
############################################################
|
||||
# Read libraries with power models
|
||||
############################################################
|
||||
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
|
||||
# Read a design to enable power reporting
|
||||
read_verilog ../../sdc/test/sdc_test2.v
|
||||
link_design sdc_test2
|
||||
|
||||
# Setup constraints for power analysis
|
||||
create_clock -name clk1 -period 10 [get_ports clk1]
|
||||
create_clock -name clk2 -period 20 [get_ports clk2]
|
||||
set_input_delay -clock clk1 2.0 [get_ports in1]
|
||||
set_input_delay -clock clk1 2.0 [get_ports in2]
|
||||
set_input_delay -clock clk1 2.0 [get_ports in3]
|
||||
set_output_delay -clock clk1 3.0 [get_ports out1]
|
||||
set_output_delay -clock clk2 3.0 [get_ports out2]
|
||||
set_input_transition 0.1 [get_ports in1]
|
||||
set_input_transition 0.1 [get_ports in2]
|
||||
set_input_transition 0.1 [get_ports in3]
|
||||
|
||||
############################################################
|
||||
# Report power (exercises internal power computation)
|
||||
############################################################
|
||||
|
||||
report_power
|
||||
|
||||
report_power -digits 6
|
||||
|
||||
# Report power for specific instances
|
||||
report_power -instances [get_cells buf1]
|
||||
|
||||
report_power -instances [get_cells inv1]
|
||||
|
||||
report_power -instances [get_cells and1]
|
||||
|
||||
report_power -instances [get_cells reg1]
|
||||
|
||||
report_power -instances [get_cells reg2]
|
||||
|
||||
report_power -instances [get_cells reg3]
|
||||
|
||||
report_power -instances [get_cells {buf1 inv1 and1 or1 nand1 nor1 reg1 reg2 reg3}]
|
||||
|
||||
############################################################
|
||||
# Cell leakage power property (exercises LeakagePower.cc)
|
||||
############################################################
|
||||
|
||||
set inv_cell [get_lib_cell NangateOpenCellLibrary/INV_X1]
|
||||
set buf_cell [get_lib_cell NangateOpenCellLibrary/BUF_X1]
|
||||
|
||||
set dff_cell [get_lib_cell NangateOpenCellLibrary/DFF_X1]
|
||||
|
||||
set nand_cell [get_lib_cell NangateOpenCellLibrary/NAND2_X1]
|
||||
|
||||
# Area property
|
||||
puts "INV_X1 area: [get_property $inv_cell area]"
|
||||
puts "BUF_X1 area: [get_property $buf_cell area]"
|
||||
puts "DFF_X1 area: [get_property $dff_cell area]"
|
||||
|
||||
############################################################
|
||||
# Cell properties - is_buffer, is_inverter, etc.
|
||||
############################################################
|
||||
|
||||
puts "INV_X1 is_inverter: [get_property $inv_cell is_inverter]"
|
||||
puts "INV_X1 is_buffer: [get_property $inv_cell is_buffer]"
|
||||
puts "BUF_X1 is_buffer: [get_property $buf_cell is_buffer]"
|
||||
puts "BUF_X1 is_inverter: [get_property $buf_cell is_inverter]"
|
||||
puts "DFF_X1 is_buffer: [get_property $dff_cell is_buffer]"
|
||||
|
||||
############################################################
|
||||
# Write liberty and re-read (exercises writer power paths)
|
||||
############################################################
|
||||
|
||||
set outfile [make_result_file liberty_power_write.lib]
|
||||
sta::write_liberty NangateOpenCellLibrary $outfile
|
||||
|
||||
############################################################
|
||||
# Read more libraries with power data
|
||||
############################################################
|
||||
|
||||
read_liberty ../../test/sky130hd/sky130hd_tt.lib
|
||||
|
||||
# Query sky130 cell leakage powers
|
||||
set sky_inv [get_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__inv_1]
|
||||
puts "sky130 inv area: [get_property $sky_inv area]"
|
||||
|
||||
# Write sky130 liberty
|
||||
set outfile2 [make_result_file liberty_power_write_sky130.lib]
|
||||
sta::write_liberty sky130_fd_sc_hd__tt_025C_1v80 $outfile2
|
||||
|
||||
############################################################
|
||||
# Read IHP library and query power
|
||||
############################################################
|
||||
|
||||
read_liberty ../../test/ihp-sg13g2/sg13g2_stdcell_typ_1p20V_25C.lib
|
||||
|
||||
set ihp_inv [get_lib_cell sg13g2_stdcell_typ_1p20V_25C/sg13g2_inv_1]
|
||||
puts "IHP inv area: [get_property $ihp_inv area]"
|
||||
|
||||
############################################################
|
||||
# Read ASAP7 CCSN library (CCS timing + power models)
|
||||
############################################################
|
||||
|
||||
read_liberty ../../test/asap7_ccsn.lib.gz
|
||||
|
||||
set outfile3 [make_result_file liberty_power_write_ccsn.lib]
|
||||
sta::write_liberty asap7sc7p5t_AO_LVT_FF_ccsn_211120 $outfile3
|
||||
|
||||
############################################################
|
||||
# Read ASAP7 SEQ for power on sequential cells
|
||||
############################################################
|
||||
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_SEQ_RVT_FF_nldm_220123.lib
|
||||
|
||||
set asap7_dff [get_lib_cell asap7sc7p5t_SEQ_RVT_FF_nldm_220123/DFFHQNx1_ASAP7_75t_R]
|
||||
puts "ASAP7 DFF area: [get_property $asap7_dff area]"
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,167 @@
|
|||
# Test liberty cell/pin/arc property queries for code coverage
|
||||
# Targets: Liberty.cc, TimingArc.cc, InternalPower.cc, FuncExpr.cc, TableModel.cc
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
|
||||
############################################################
|
||||
# Library-level properties
|
||||
############################################################
|
||||
|
||||
set lib [get_libs NangateOpenCellLibrary]
|
||||
|
||||
# Library iterator
|
||||
set lib_iter [sta::liberty_library_iterator]
|
||||
|
||||
# find_liberty
|
||||
set found_lib [sta::find_liberty NangateOpenCellLibrary]
|
||||
|
||||
############################################################
|
||||
# Cell property queries on various cell types
|
||||
############################################################
|
||||
|
||||
# Query cell properties using get_property / report_lib_cell
|
||||
# Inverter
|
||||
set inv [get_lib_cell NangateOpenCellLibrary/INV_X1]
|
||||
report_lib_cell NangateOpenCellLibrary/INV_X1
|
||||
|
||||
# Buffer
|
||||
set buf [get_lib_cell NangateOpenCellLibrary/BUF_X1]
|
||||
report_lib_cell NangateOpenCellLibrary/BUF_X1
|
||||
|
||||
# Sequential cells - DFF
|
||||
set dff [get_lib_cell NangateOpenCellLibrary/DFF_X1]
|
||||
report_lib_cell NangateOpenCellLibrary/DFF_X1
|
||||
|
||||
# DFF with reset
|
||||
set dffr [get_lib_cell NangateOpenCellLibrary/DFFR_X1]
|
||||
report_lib_cell NangateOpenCellLibrary/DFFR_X1
|
||||
|
||||
# DFF with set
|
||||
set dffs [get_lib_cell NangateOpenCellLibrary/DFFS_X1]
|
||||
report_lib_cell NangateOpenCellLibrary/DFFS_X1
|
||||
|
||||
# DFF with set and reset
|
||||
set dffrs [get_lib_cell NangateOpenCellLibrary/DFFRS_X1]
|
||||
report_lib_cell NangateOpenCellLibrary/DFFRS_X1
|
||||
|
||||
# Latch
|
||||
set latch [get_lib_cell NangateOpenCellLibrary/TLAT_X1]
|
||||
report_lib_cell NangateOpenCellLibrary/TLAT_X1
|
||||
|
||||
# Complex cells
|
||||
foreach cell_name {AOI21_X1 AOI22_X1 OAI21_X1 OAI22_X1 AOI211_X1 OAI211_X1 \
|
||||
HA_X1 FA_X1 XNOR2_X1 XOR2_X1 MUX2_X1 \
|
||||
CLKBUF_X1 CLKBUF_X2 CLKBUF_X3 TINV_X1 \
|
||||
NAND2_X1 NAND3_X1 NAND4_X1 NOR2_X1 NOR3_X1 NOR4_X1 \
|
||||
AND2_X1 AND3_X1 AND4_X1 OR2_X1 OR3_X1 OR4_X1 \
|
||||
ANTENNA_X1 FILLCELL_X1 LOGIC0_X1 LOGIC1_X1 \
|
||||
CLKGATETST_X1 CLKGATETST_X2 SDFF_X1 SDFFR_X1 SDFFS_X1 SDFFRS_X1} {
|
||||
report_lib_cell NangateOpenCellLibrary/$cell_name
|
||||
}
|
||||
|
||||
############################################################
|
||||
# Pin direction queries
|
||||
############################################################
|
||||
|
||||
# Test liberty_port_direction on various pin types
|
||||
foreach {cell_name pin_name} {
|
||||
INV_X1 A INV_X1 ZN
|
||||
BUF_X1 A BUF_X1 Z
|
||||
DFF_X1 D DFF_X1 CK DFF_X1 Q DFF_X1 QN
|
||||
NAND2_X1 A1 NAND2_X1 A2 NAND2_X1 ZN
|
||||
DFFR_X1 RN
|
||||
DFFS_X1 SN
|
||||
CLKGATETST_X1 CK CLKGATETST_X1 E CLKGATETST_X1 SE CLKGATETST_X1 GCK
|
||||
} {
|
||||
set pin [get_lib_pin NangateOpenCellLibrary/$cell_name/$pin_name]
|
||||
if { $pin != "" } {
|
||||
set dir [sta::liberty_port_direction $pin]
|
||||
}
|
||||
}
|
||||
|
||||
############################################################
|
||||
# get_lib_pins and get_lib_cells with various patterns
|
||||
############################################################
|
||||
|
||||
# Wildcard patterns
|
||||
set all_cells [get_lib_cells NangateOpenCellLibrary/*]
|
||||
|
||||
set inv_cells [get_lib_cells NangateOpenCellLibrary/INV_*]
|
||||
|
||||
set dff_cells [get_lib_cells NangateOpenCellLibrary/DFF*]
|
||||
|
||||
set sdff_cells [get_lib_cells NangateOpenCellLibrary/SDFF*]
|
||||
|
||||
# All pins of a cell
|
||||
set inv_pins [get_lib_pins NangateOpenCellLibrary/INV_X1/*]
|
||||
|
||||
set dff_pins [get_lib_pins NangateOpenCellLibrary/DFF_X1/*]
|
||||
|
||||
set dffr_pins [get_lib_pins NangateOpenCellLibrary/DFFR_X1/*]
|
||||
|
||||
set aoi_pins [get_lib_pins NangateOpenCellLibrary/AOI21_X1/*]
|
||||
|
||||
set fa_pins [get_lib_pins NangateOpenCellLibrary/FA_X1/*]
|
||||
|
||||
set clkgate_pins [get_lib_pins NangateOpenCellLibrary/CLKGATETST_X1/*]
|
||||
|
||||
############################################################
|
||||
# liberty_supply_exists
|
||||
############################################################
|
||||
|
||||
set result [sta::liberty_supply_exists VDD]
|
||||
|
||||
set result [sta::liberty_supply_exists VSS]
|
||||
|
||||
set result [sta::liberty_supply_exists NONEXISTENT]
|
||||
|
||||
############################################################
|
||||
# Read ASAP7 SEQ library (exercises different liberty features)
|
||||
############################################################
|
||||
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_SEQ_RVT_FF_nldm_220123.lib
|
||||
|
||||
# Query ASAP7 sequential cells
|
||||
set asap7_dff [get_lib_cell asap7sc7p5t_SEQ_RVT_FF_nldm_220123/DFFHQNx1_ASAP7_75t_R]
|
||||
report_lib_cell asap7sc7p5t_SEQ_RVT_FF_nldm_220123/DFFHQNx1_ASAP7_75t_R
|
||||
|
||||
set asap7_dff_pins [get_lib_pins asap7sc7p5t_SEQ_RVT_FF_nldm_220123/DFFHQNx1_ASAP7_75t_R/*]
|
||||
|
||||
# ICG cell (clock gating)
|
||||
set icg [get_lib_cell asap7sc7p5t_SEQ_RVT_FF_nldm_220123/ICGx1_ASAP7_75t_R]
|
||||
report_lib_cell asap7sc7p5t_SEQ_RVT_FF_nldm_220123/ICGx1_ASAP7_75t_R
|
||||
|
||||
############################################################
|
||||
# Read IHP library (different vendor, different features)
|
||||
############################################################
|
||||
|
||||
read_liberty ../../test/ihp-sg13g2/sg13g2_stdcell_typ_1p20V_25C.lib
|
||||
|
||||
# Tristate buffer
|
||||
set ebufn [get_lib_cell sg13g2_stdcell_typ_1p20V_25C/sg13g2_ebufn_2]
|
||||
report_lib_cell sg13g2_stdcell_typ_1p20V_25C/sg13g2_ebufn_2
|
||||
|
||||
# Scan DFF
|
||||
set sdff [get_lib_cell sg13g2_stdcell_typ_1p20V_25C/sg13g2_sdfbbp_1]
|
||||
if { $sdff != "" } {
|
||||
report_lib_cell sg13g2_stdcell_typ_1p20V_25C/sg13g2_sdfbbp_1
|
||||
}
|
||||
|
||||
############################################################
|
||||
# Read Sky130 library
|
||||
############################################################
|
||||
|
||||
read_liberty ../../test/sky130hd/sky130hd_tt.lib
|
||||
|
||||
# Query sky130 cells
|
||||
report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__inv_1
|
||||
|
||||
# Query all sky130 cells
|
||||
set sky_cells [get_lib_cells sky130_fd_sc_hd__tt_025C_1v80/*]
|
||||
|
||||
############################################################
|
||||
# Write liberty
|
||||
############################################################
|
||||
|
||||
source ../../test/helpers.tcl
|
||||
set outfile [make_result_file liberty_properties_write.lib]
|
||||
sta::write_liberty NangateOpenCellLibrary $outfile
|
||||
|
|
@ -0,0 +1,160 @@
|
|||
Cell DFFHQNx1_ASAP7_75t_R
|
||||
Library asap7sc7p5t_SEQ_RVT_FF_nldm_220123
|
||||
File ../../test/asap7/asap7sc7p5t_SEQ_RVT_FF_nldm_220123.lib
|
||||
VDD power
|
||||
VSS ground
|
||||
QN output function=IQN
|
||||
CLK input 0.40-0.52
|
||||
D input 0.55-0.62
|
||||
IQN internal
|
||||
IQNN internal
|
||||
|
||||
Timing arcs
|
||||
CLK -> QN
|
||||
Reg Clk to Q
|
||||
^ -> ^
|
||||
^ -> v
|
||||
CLK -> CLK
|
||||
width
|
||||
when D
|
||||
^ -> v
|
||||
v -> ^
|
||||
CLK -> CLK
|
||||
width
|
||||
when !D
|
||||
^ -> v
|
||||
v -> ^
|
||||
CLK -> D
|
||||
hold
|
||||
^ -> ^
|
||||
^ -> v
|
||||
CLK -> D
|
||||
setup
|
||||
^ -> ^
|
||||
^ -> v
|
||||
Cell DLLx1_ASAP7_75t_R
|
||||
Library asap7sc7p5t_SEQ_RVT_FF_nldm_220123
|
||||
File ../../test/asap7/asap7sc7p5t_SEQ_RVT_FF_nldm_220123.lib
|
||||
VDD power
|
||||
VSS ground
|
||||
Q output function=IQ
|
||||
CLK input 0.41-0.53
|
||||
D input 0.50-0.63
|
||||
IQ internal
|
||||
IQN internal
|
||||
|
||||
Timing arcs
|
||||
CLK -> Q
|
||||
Latch En to Q
|
||||
v -> ^
|
||||
v -> v
|
||||
D -> Q
|
||||
Latch D to Q
|
||||
^ -> ^
|
||||
v -> v
|
||||
CLK -> CLK
|
||||
width
|
||||
when D
|
||||
v -> ^
|
||||
CLK -> CLK
|
||||
width
|
||||
when !D
|
||||
v -> ^
|
||||
CLK -> D
|
||||
hold
|
||||
^ -> ^
|
||||
^ -> v
|
||||
CLK -> D
|
||||
setup
|
||||
^ -> ^
|
||||
^ -> v
|
||||
Cell ICGx1_ASAP7_75t_R
|
||||
Library asap7sc7p5t_SEQ_RVT_FF_nldm_220123
|
||||
File ../../test/asap7/asap7sc7p5t_SEQ_RVT_FF_nldm_220123.lib
|
||||
VDD power
|
||||
VSS ground
|
||||
IQ internal
|
||||
GCLK output
|
||||
CLK input 1.63-2.39
|
||||
ENA input 0.33-0.47
|
||||
SE input 0.39-0.47
|
||||
|
||||
Timing arcs
|
||||
CLK -> GCLK
|
||||
combinational
|
||||
when ENA+(!ENA*SE)
|
||||
v -> v
|
||||
CLK -> GCLK
|
||||
combinational
|
||||
when !ENA*!SE
|
||||
v -> v
|
||||
CLK -> GCLK
|
||||
combinational
|
||||
^ -> ^
|
||||
v -> v
|
||||
CLK -> CLK
|
||||
width
|
||||
when ENA+(!ENA*SE)
|
||||
^ -> v
|
||||
v -> ^
|
||||
CLK -> CLK
|
||||
width
|
||||
when !ENA*!SE
|
||||
v -> ^
|
||||
CLK -> ENA
|
||||
hold
|
||||
when !SE
|
||||
^ -> ^
|
||||
^ -> v
|
||||
CLK -> ENA
|
||||
hold
|
||||
^ -> ^
|
||||
^ -> v
|
||||
CLK -> ENA
|
||||
setup
|
||||
when !SE
|
||||
^ -> ^
|
||||
^ -> v
|
||||
CLK -> ENA
|
||||
setup
|
||||
^ -> ^
|
||||
^ -> v
|
||||
CLK -> SE
|
||||
hold
|
||||
when !ENA
|
||||
^ -> ^
|
||||
^ -> v
|
||||
CLK -> SE
|
||||
hold
|
||||
^ -> ^
|
||||
^ -> v
|
||||
CLK -> SE
|
||||
setup
|
||||
when !ENA
|
||||
^ -> ^
|
||||
^ -> v
|
||||
CLK -> SE
|
||||
setup
|
||||
^ -> ^
|
||||
^ -> v
|
||||
Warning 1212: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13178, timing group from output port.
|
||||
Warning 1212: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13211, timing group from output port.
|
||||
Warning 1212: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13244, timing group from output port.
|
||||
Warning 1212: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13277, timing group from output port.
|
||||
Warning 1212: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13310, timing group from output port.
|
||||
Warning 1212: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13343, timing group from output port.
|
||||
Warning 1212: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13376, timing group from output port.
|
||||
Warning 1212: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 14772, timing group from output port.
|
||||
Warning 1212: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 14805, timing group from output port.
|
||||
Warning 1212: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 14838, timing group from output port.
|
||||
Warning 1212: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_SS_nldm_211120.lib.gz line 13156, timing group from output port.
|
||||
Warning 1212: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_SS_nldm_211120.lib.gz line 13189, timing group from output port.
|
||||
Warning 1212: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_SS_nldm_211120.lib.gz line 13222, timing group from output port.
|
||||
Warning 1212: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_SS_nldm_211120.lib.gz line 13255, timing group from output port.
|
||||
Warning 1212: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_SS_nldm_211120.lib.gz line 13288, timing group from output port.
|
||||
Warning 1212: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_SS_nldm_211120.lib.gz line 13321, timing group from output port.
|
||||
Warning 1212: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_SS_nldm_211120.lib.gz line 13354, timing group from output port.
|
||||
Warning 1212: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_SS_nldm_211120.lib.gz line 14748, timing group from output port.
|
||||
Warning 1212: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_SS_nldm_211120.lib.gz line 14781, timing group from output port.
|
||||
Warning 1212: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_SS_nldm_211120.lib.gz line 14814, timing group from output port.
|
||||
Warning 1171: ../../test/nangate45/fake_macros.lib line 32, default_max_transition is 0.0.
|
||||
|
|
@ -0,0 +1,174 @@
|
|||
# Test ASAP7 library reading for code coverage
|
||||
# Tests multiple lib reading including compressed (.lib.gz) files
|
||||
|
||||
############################################################
|
||||
# Read uncompressed ASAP7 SEQ library
|
||||
############################################################
|
||||
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_SEQ_RVT_FF_nldm_220123.lib
|
||||
|
||||
set seq_lib [get_libs asap7sc7p5t_SEQ_RVT_FF_nldm_220123]
|
||||
if { $seq_lib == "" } {
|
||||
puts "FAIL: SEQ RVT FF library not found"
|
||||
exit 1
|
||||
}
|
||||
|
||||
# Query DFF cells
|
||||
set dff [get_lib_cells asap7sc7p5t_SEQ_RVT_FF_nldm_220123/DFFHQNx1_ASAP7_75t_R]
|
||||
if { $dff == "" } {
|
||||
puts "FAIL: DFFHQNx1 not found"
|
||||
exit 1
|
||||
}
|
||||
|
||||
report_lib_cell asap7sc7p5t_SEQ_RVT_FF_nldm_220123/DFFHQNx1_ASAP7_75t_R
|
||||
|
||||
# Query latch cells
|
||||
set latch [get_lib_cells asap7sc7p5t_SEQ_RVT_FF_nldm_220123/DLLx1_ASAP7_75t_R]
|
||||
if { $latch == "" } {
|
||||
puts "FAIL: DLLx1 not found"
|
||||
exit 1
|
||||
}
|
||||
|
||||
report_lib_cell asap7sc7p5t_SEQ_RVT_FF_nldm_220123/DLLx1_ASAP7_75t_R
|
||||
|
||||
# Query ICG (integrated clock gate) cells
|
||||
set icg [get_lib_cells asap7sc7p5t_SEQ_RVT_FF_nldm_220123/ICGx1_ASAP7_75t_R]
|
||||
if { $icg == "" } {
|
||||
puts "FAIL: ICGx1 not found"
|
||||
exit 1
|
||||
}
|
||||
|
||||
report_lib_cell asap7sc7p5t_SEQ_RVT_FF_nldm_220123/ICGx1_ASAP7_75t_R
|
||||
|
||||
# Query all cells in SEQ library
|
||||
set all_seq_cells [get_lib_cells asap7sc7p5t_SEQ_RVT_FF_nldm_220123/*]
|
||||
if { [llength $all_seq_cells] == 0 } {
|
||||
error "expected cells in asap7 SEQ FF library"
|
||||
}
|
||||
|
||||
# Get pins of DFF
|
||||
set dff_pins [get_lib_pins asap7sc7p5t_SEQ_RVT_FF_nldm_220123/DFFHQNx1_ASAP7_75t_R/*]
|
||||
if { [llength $dff_pins] < 3 } {
|
||||
error "expected DFFHQNx1 pins in asap7 SEQ FF library"
|
||||
}
|
||||
|
||||
############################################################
|
||||
# Read compressed ASAP7 SIMPLE library (.lib.gz)
|
||||
############################################################
|
||||
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz
|
||||
|
||||
set simple_lib [get_libs asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120]
|
||||
if { $simple_lib == "" } {
|
||||
puts "FAIL: SIMPLE RVT FF library not found"
|
||||
exit 1
|
||||
}
|
||||
|
||||
# Query cells in SIMPLE library
|
||||
set all_simple_cells [get_lib_cells asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120/*]
|
||||
if { [llength $all_simple_cells] == 0 } {
|
||||
error "expected cells in asap7 SIMPLE FF library"
|
||||
}
|
||||
|
||||
############################################################
|
||||
# Read compressed ASAP7 INVBUF library (.lib.gz)
|
||||
############################################################
|
||||
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_INVBUF_RVT_FF_nldm_220122.lib.gz
|
||||
|
||||
set invbuf_lib [get_libs asap7sc7p5t_INVBUF_RVT_FF_nldm_211120]
|
||||
if { $invbuf_lib == "" } {
|
||||
puts "FAIL: INVBUF RVT FF library not found"
|
||||
exit 1
|
||||
}
|
||||
|
||||
set all_invbuf_cells [get_lib_cells asap7sc7p5t_INVBUF_RVT_FF_nldm_211120/*]
|
||||
if { [llength $all_invbuf_cells] == 0 } {
|
||||
error "expected cells in asap7 INVBUF FF library"
|
||||
}
|
||||
|
||||
############################################################
|
||||
# Read compressed ASAP7 OA library (.lib.gz)
|
||||
############################################################
|
||||
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_OA_RVT_FF_nldm_211120.lib.gz
|
||||
|
||||
set oa_lib [get_libs asap7sc7p5t_OA_RVT_FF_nldm_211120]
|
||||
if { $oa_lib == "" } {
|
||||
puts "FAIL: OA RVT FF library not found"
|
||||
exit 1
|
||||
}
|
||||
|
||||
set all_oa_cells [get_lib_cells asap7sc7p5t_OA_RVT_FF_nldm_211120/*]
|
||||
if { [llength $all_oa_cells] == 0 } {
|
||||
error "expected cells in asap7 OA FF library"
|
||||
}
|
||||
|
||||
############################################################
|
||||
# Read compressed ASAP7 AO library (.lib.gz)
|
||||
############################################################
|
||||
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_AO_RVT_FF_nldm_211120.lib.gz
|
||||
|
||||
set ao_lib [get_libs asap7sc7p5t_AO_RVT_FF_nldm_211120]
|
||||
if { $ao_lib == "" } {
|
||||
puts "FAIL: AO RVT FF library not found"
|
||||
exit 1
|
||||
}
|
||||
|
||||
set all_ao_cells [get_lib_cells asap7sc7p5t_AO_RVT_FF_nldm_211120/*]
|
||||
if { [llength $all_ao_cells] == 0 } {
|
||||
error "expected cells in asap7 AO FF library"
|
||||
}
|
||||
|
||||
############################################################
|
||||
# Read SS corner for different timing
|
||||
############################################################
|
||||
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_SEQ_RVT_SS_nldm_220123.lib
|
||||
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_SS_nldm_211120.lib.gz
|
||||
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_INVBUF_RVT_SS_nldm_220122.lib.gz
|
||||
|
||||
if { [llength [get_lib_cells asap7sc7p5t_SEQ_RVT_SS_nldm_220123/*]] == 0 } {
|
||||
error "expected cells in asap7 SEQ SS library"
|
||||
}
|
||||
if { [llength [get_lib_cells asap7sc7p5t_SIMPLE_RVT_SS_nldm_211120/*]] == 0 } {
|
||||
error "expected cells in asap7 SIMPLE SS library"
|
||||
}
|
||||
if { [llength [get_lib_cells asap7sc7p5t_INVBUF_RVT_SS_nldm_211120/*]] == 0 } {
|
||||
error "expected cells in asap7 INVBUF SS library"
|
||||
}
|
||||
|
||||
############################################################
|
||||
# Read CCSN library (compressed, exercises LibertyReader CCSN)
|
||||
############################################################
|
||||
|
||||
read_liberty ../../test/asap7_ccsn.lib.gz
|
||||
if { [llength [get_lib_cells asap7sc7p5t_AO_LVT_FF_ccsn_211120/*]] == 0 } {
|
||||
error "expected cells in asap7 CCSN library"
|
||||
}
|
||||
|
||||
############################################################
|
||||
# Read latch library (exercises latch-specific parsing)
|
||||
############################################################
|
||||
|
||||
read_liberty ../../test/liberty_latch3.lib
|
||||
if { [llength [get_lib_cells asap7sc7p5t_lvt_ff/*]] == 0 } {
|
||||
error "expected cells in latch3 library"
|
||||
}
|
||||
|
||||
############################################################
|
||||
# Read fakeram (macro library)
|
||||
############################################################
|
||||
|
||||
read_liberty ../../test/nangate45/fake_macros.lib
|
||||
|
||||
read_liberty ../../test/nangate45/fakeram45_256x16.lib
|
||||
if { [llength [get_lib_cells fake_macros/*]] == 0 } {
|
||||
error "expected cells in fake_macros library"
|
||||
}
|
||||
if { [llength [get_lib_cells fakeram45_256x16/*]] == 0 } {
|
||||
error "expected cells in fakeram45_256x16 library"
|
||||
}
|
||||
|
|
@ -0,0 +1,369 @@
|
|||
Cell sg13g2_inv_1
|
||||
Library sg13g2_stdcell_typ_1p20V_25C
|
||||
File ../../test/ihp-sg13g2/sg13g2_stdcell_typ_1p20V_25C.lib
|
||||
Y output function=!A
|
||||
A input 0.00-0.00
|
||||
|
||||
Timing arcs
|
||||
A -> Y
|
||||
combinational
|
||||
^ -> v
|
||||
v -> ^
|
||||
Cell sg13g2_buf_1
|
||||
Library sg13g2_stdcell_typ_1p20V_25C
|
||||
File ../../test/ihp-sg13g2/sg13g2_stdcell_typ_1p20V_25C.lib
|
||||
X output function=A
|
||||
A input 0.00-0.00
|
||||
|
||||
Timing arcs
|
||||
A -> X
|
||||
combinational
|
||||
^ -> ^
|
||||
v -> v
|
||||
Cell sg13g2_nand2_1
|
||||
Library sg13g2_stdcell_typ_1p20V_25C
|
||||
File ../../test/ihp-sg13g2/sg13g2_stdcell_typ_1p20V_25C.lib
|
||||
Y output function=!(A*B)
|
||||
A input 0.00-0.00
|
||||
B input 0.00-0.00
|
||||
|
||||
Timing arcs
|
||||
A -> Y
|
||||
combinational
|
||||
^ -> v
|
||||
v -> ^
|
||||
B -> Y
|
||||
combinational
|
||||
^ -> v
|
||||
v -> ^
|
||||
Cell sg13g2_nor2_1
|
||||
Library sg13g2_stdcell_typ_1p20V_25C
|
||||
File ../../test/ihp-sg13g2/sg13g2_stdcell_typ_1p20V_25C.lib
|
||||
Y output function=!(A+B)
|
||||
A input 0.00-0.00
|
||||
B input 0.00-0.00
|
||||
|
||||
Timing arcs
|
||||
A -> Y
|
||||
combinational
|
||||
^ -> v
|
||||
v -> ^
|
||||
B -> Y
|
||||
combinational
|
||||
^ -> v
|
||||
v -> ^
|
||||
Cell sg13g2_and2_1
|
||||
Library sg13g2_stdcell_typ_1p20V_25C
|
||||
File ../../test/ihp-sg13g2/sg13g2_stdcell_typ_1p20V_25C.lib
|
||||
X output function=A*B
|
||||
A input 0.00-0.00
|
||||
B input 0.00-0.00
|
||||
|
||||
Timing arcs
|
||||
A -> X
|
||||
combinational
|
||||
^ -> ^
|
||||
v -> v
|
||||
B -> X
|
||||
combinational
|
||||
^ -> ^
|
||||
v -> v
|
||||
Cell sg13g2_mux2_1
|
||||
Library sg13g2_stdcell_typ_1p20V_25C
|
||||
File ../../test/ihp-sg13g2/sg13g2_stdcell_typ_1p20V_25C.lib
|
||||
X output function=(!S*A0)+(S*A1)
|
||||
A0 input 0.00-0.00
|
||||
A1 input 0.00-0.00
|
||||
S input 0.01-0.01
|
||||
|
||||
Timing arcs
|
||||
A0 -> X
|
||||
combinational
|
||||
^ -> ^
|
||||
v -> v
|
||||
A1 -> X
|
||||
combinational
|
||||
^ -> ^
|
||||
v -> v
|
||||
S -> X
|
||||
combinational
|
||||
when !A0*A1
|
||||
^ -> ^
|
||||
v -> v
|
||||
S -> X
|
||||
combinational
|
||||
v -> v
|
||||
^ -> v
|
||||
^ -> ^
|
||||
v -> ^
|
||||
S -> X
|
||||
combinational
|
||||
when A0*!A1
|
||||
^ -> v
|
||||
v -> ^
|
||||
Cell sg13g2_mux4_1
|
||||
Library sg13g2_stdcell_typ_1p20V_25C
|
||||
File ../../test/ihp-sg13g2/sg13g2_stdcell_typ_1p20V_25C.lib
|
||||
X output function=(((A0*(!S0*!S1))+(A1*(S0*!S1)))+(A2*(!S0*S1)))+(A3*(S0*S1))
|
||||
A0 input 0.00-0.00
|
||||
A1 input 0.00-0.00
|
||||
A2 input 0.00-0.00
|
||||
A3 input 0.00-0.00
|
||||
S0 input 0.01-0.01
|
||||
S1 input 0.00-0.01
|
||||
|
||||
Timing arcs
|
||||
A0 -> X
|
||||
combinational
|
||||
^ -> ^
|
||||
v -> v
|
||||
A1 -> X
|
||||
combinational
|
||||
^ -> ^
|
||||
v -> v
|
||||
A2 -> X
|
||||
combinational
|
||||
^ -> ^
|
||||
v -> v
|
||||
A3 -> X
|
||||
combinational
|
||||
^ -> ^
|
||||
v -> v
|
||||
S0 -> X
|
||||
combinational
|
||||
when (!A2*A3)*S1
|
||||
^ -> ^
|
||||
v -> v
|
||||
S0 -> X
|
||||
combinational
|
||||
when (!A0*A1)*!S1
|
||||
^ -> ^
|
||||
v -> v
|
||||
S0 -> X
|
||||
combinational
|
||||
v -> v
|
||||
^ -> v
|
||||
^ -> ^
|
||||
v -> ^
|
||||
S0 -> X
|
||||
combinational
|
||||
when (A2*!A3)*S1
|
||||
^ -> v
|
||||
v -> ^
|
||||
S0 -> X
|
||||
combinational
|
||||
when (A0*!A1)*!S1
|
||||
^ -> v
|
||||
v -> ^
|
||||
S1 -> X
|
||||
combinational
|
||||
when (!A1*A3)*S0
|
||||
^ -> ^
|
||||
v -> v
|
||||
S1 -> X
|
||||
combinational
|
||||
when (!A0*A2)*!S0
|
||||
^ -> ^
|
||||
v -> v
|
||||
S1 -> X
|
||||
combinational
|
||||
v -> v
|
||||
^ -> v
|
||||
^ -> ^
|
||||
v -> ^
|
||||
S1 -> X
|
||||
combinational
|
||||
when (A1*!A3)*S0
|
||||
^ -> v
|
||||
v -> ^
|
||||
S1 -> X
|
||||
combinational
|
||||
when (A0*!A2)*!S0
|
||||
^ -> v
|
||||
v -> ^
|
||||
Cell sg13g2_dfrbp_1
|
||||
Library sg13g2_stdcell_typ_1p20V_25C
|
||||
File ../../test/ihp-sg13g2/sg13g2_stdcell_typ_1p20V_25C.lib
|
||||
Q output function=IQ
|
||||
Q_N output function=IQN
|
||||
CLK input 0.00-0.00
|
||||
D input 0.00-0.00
|
||||
RESET_B input 0.01-0.01
|
||||
IQ internal
|
||||
IQN internal
|
||||
|
||||
Timing arcs
|
||||
CLK -> Q
|
||||
Reg Clk to Q
|
||||
^ -> ^
|
||||
^ -> v
|
||||
RESET_B -> Q
|
||||
Reg Set/Clr
|
||||
v -> v
|
||||
CLK -> Q_N
|
||||
Reg Clk to Q
|
||||
^ -> ^
|
||||
^ -> v
|
||||
RESET_B -> Q_N
|
||||
Reg Set/Clr
|
||||
v -> ^
|
||||
CLK -> CLK
|
||||
width
|
||||
^ -> v
|
||||
v -> ^
|
||||
CLK -> D
|
||||
hold
|
||||
^ -> ^
|
||||
^ -> v
|
||||
CLK -> D
|
||||
setup
|
||||
^ -> ^
|
||||
^ -> v
|
||||
CLK -> RESET_B
|
||||
recovery
|
||||
^ -> ^
|
||||
CLK -> RESET_B
|
||||
removal
|
||||
^ -> ^
|
||||
RESET_B -> RESET_B
|
||||
width
|
||||
v -> ^
|
||||
Cell sg13g2_dlhq_1
|
||||
Library sg13g2_stdcell_typ_1p20V_25C
|
||||
File ../../test/ihp-sg13g2/sg13g2_stdcell_typ_1p20V_25C.lib
|
||||
Q output function=IQ
|
||||
D input 0.00-0.00
|
||||
GATE input 0.00-0.00
|
||||
IQ internal
|
||||
IQN internal
|
||||
|
||||
Timing arcs
|
||||
D -> Q
|
||||
Latch D to Q
|
||||
^ -> ^
|
||||
v -> v
|
||||
GATE -> Q
|
||||
Latch En to Q
|
||||
^ -> ^
|
||||
^ -> v
|
||||
GATE -> D
|
||||
hold
|
||||
v -> ^
|
||||
v -> v
|
||||
GATE -> D
|
||||
setup
|
||||
v -> ^
|
||||
v -> v
|
||||
GATE -> GATE
|
||||
width
|
||||
^ -> v
|
||||
Cell sg13g2_a21o_1
|
||||
Library sg13g2_stdcell_typ_1p20V_25C
|
||||
File ../../test/ihp-sg13g2/sg13g2_stdcell_typ_1p20V_25C.lib
|
||||
X output function=(A1*A2)+B1
|
||||
A1 input 0.00-0.00
|
||||
A2 input 0.00-0.00
|
||||
B1 input 0.00-0.00
|
||||
|
||||
Timing arcs
|
||||
A1 -> X
|
||||
combinational
|
||||
^ -> ^
|
||||
v -> v
|
||||
A2 -> X
|
||||
combinational
|
||||
^ -> ^
|
||||
v -> v
|
||||
B1 -> X
|
||||
combinational
|
||||
when A1*!A2
|
||||
^ -> ^
|
||||
v -> v
|
||||
B1 -> X
|
||||
combinational
|
||||
when !A1*A2
|
||||
^ -> ^
|
||||
v -> v
|
||||
B1 -> X
|
||||
combinational
|
||||
^ -> ^
|
||||
v -> v
|
||||
Cell sg13g2_xor2_1
|
||||
Library sg13g2_stdcell_typ_1p20V_25C
|
||||
File ../../test/ihp-sg13g2/sg13g2_stdcell_typ_1p20V_25C.lib
|
||||
X output function=A^B
|
||||
A input 0.01-0.01
|
||||
B input 0.01-0.01
|
||||
|
||||
Timing arcs
|
||||
A -> X
|
||||
combinational
|
||||
^ -> ^
|
||||
v -> v
|
||||
A -> X
|
||||
combinational
|
||||
^ -> v
|
||||
v -> ^
|
||||
B -> X
|
||||
combinational
|
||||
^ -> ^
|
||||
v -> v
|
||||
B -> X
|
||||
combinational
|
||||
^ -> v
|
||||
v -> ^
|
||||
Cell sg13g2_xnor2_1
|
||||
Library sg13g2_stdcell_typ_1p20V_25C
|
||||
File ../../test/ihp-sg13g2/sg13g2_stdcell_typ_1p20V_25C.lib
|
||||
Y output function=!(A^B)
|
||||
A input 0.01-0.01
|
||||
B input 0.01-0.01
|
||||
|
||||
Timing arcs
|
||||
A -> Y
|
||||
combinational
|
||||
^ -> ^
|
||||
v -> v
|
||||
A -> Y
|
||||
combinational
|
||||
^ -> v
|
||||
v -> ^
|
||||
B -> Y
|
||||
combinational
|
||||
^ -> ^
|
||||
v -> v
|
||||
B -> Y
|
||||
combinational
|
||||
^ -> v
|
||||
v -> ^
|
||||
Cell sg13g2_ebufn_2
|
||||
Library sg13g2_stdcell_typ_1p20V_25C
|
||||
File ../../test/ihp-sg13g2/sg13g2_stdcell_typ_1p20V_25C.lib
|
||||
Z tristate enable=!TE_B function=A 0.00-0.01
|
||||
A input 0.00-0.00
|
||||
TE_B input 0.01-0.01
|
||||
|
||||
Timing arcs
|
||||
A -> Z
|
||||
combinational
|
||||
^ -> ^
|
||||
v -> v
|
||||
TE_B -> Z
|
||||
tristate disable
|
||||
^ -> 0Z
|
||||
^ -> 1Z
|
||||
TE_B -> Z
|
||||
tristate enable
|
||||
v -> Z1
|
||||
v -> Z0
|
||||
Cell sg13g2_dlygate4sd1_1
|
||||
Library sg13g2_stdcell_typ_1p20V_25C
|
||||
File ../../test/ihp-sg13g2/sg13g2_stdcell_typ_1p20V_25C.lib
|
||||
X output function=A
|
||||
A input 0.00-0.00
|
||||
|
||||
Timing arcs
|
||||
A -> X
|
||||
combinational
|
||||
^ -> ^
|
||||
v -> v
|
||||
|
|
@ -0,0 +1,218 @@
|
|||
# Test IHP SG13G2 library reading for code coverage
|
||||
read_liberty ../../test/ihp-sg13g2/sg13g2_stdcell_typ_1p20V_25C.lib
|
||||
|
||||
############################################################
|
||||
# Library queries
|
||||
############################################################
|
||||
|
||||
set lib [get_libs sg13g2_stdcell_typ_1p20V_25C]
|
||||
if { $lib == "" } {
|
||||
puts "FAIL: IHP library not found"
|
||||
exit 1
|
||||
}
|
||||
|
||||
############################################################
|
||||
# Query various cell types
|
||||
############################################################
|
||||
|
||||
# Inverters
|
||||
set inv [get_lib_cells sg13g2_stdcell_typ_1p20V_25C/sg13g2_inv_1]
|
||||
if { $inv == "" } {
|
||||
puts "FAIL: sg13g2_inv_1 not found"
|
||||
exit 1
|
||||
}
|
||||
|
||||
report_lib_cell sg13g2_stdcell_typ_1p20V_25C/sg13g2_inv_1
|
||||
|
||||
set inv_pins [get_lib_pins sg13g2_stdcell_typ_1p20V_25C/sg13g2_inv_1/*]
|
||||
if { [llength $inv_pins] != 2 } {
|
||||
error "expected 2 pins on sg13g2_inv_1, found [llength $inv_pins]"
|
||||
}
|
||||
|
||||
foreach sz {2 4 8 16} {
|
||||
set cell [get_lib_cells sg13g2_stdcell_typ_1p20V_25C/sg13g2_inv_$sz]
|
||||
if { $cell == "" } {
|
||||
puts "FAIL: sg13g2_inv_$sz not found"
|
||||
exit 1
|
||||
}
|
||||
}
|
||||
|
||||
# Buffers
|
||||
set buf [get_lib_cells sg13g2_stdcell_typ_1p20V_25C/sg13g2_buf_1]
|
||||
if { $buf == "" } {
|
||||
puts "FAIL: sg13g2_buf_1 not found"
|
||||
exit 1
|
||||
}
|
||||
|
||||
report_lib_cell sg13g2_stdcell_typ_1p20V_25C/sg13g2_buf_1
|
||||
|
||||
# NAND gates
|
||||
set nand2 [get_lib_cells sg13g2_stdcell_typ_1p20V_25C/sg13g2_nand2_1]
|
||||
if { $nand2 == "" } {
|
||||
puts "FAIL: sg13g2_nand2_1 not found"
|
||||
exit 1
|
||||
}
|
||||
|
||||
report_lib_cell sg13g2_stdcell_typ_1p20V_25C/sg13g2_nand2_1
|
||||
|
||||
foreach cell_name {sg13g2_nand2_2 sg13g2_nand3_1 sg13g2_nand4_1} {
|
||||
set cell [get_lib_cells sg13g2_stdcell_typ_1p20V_25C/$cell_name]
|
||||
if { $cell == "" } {
|
||||
puts "FAIL: $cell_name not found"
|
||||
exit 1
|
||||
}
|
||||
}
|
||||
|
||||
# NOR gates
|
||||
set nor2 [get_lib_cells sg13g2_stdcell_typ_1p20V_25C/sg13g2_nor2_1]
|
||||
if { $nor2 == "" } {
|
||||
puts "FAIL: sg13g2_nor2_1 not found"
|
||||
exit 1
|
||||
}
|
||||
|
||||
report_lib_cell sg13g2_stdcell_typ_1p20V_25C/sg13g2_nor2_1
|
||||
|
||||
foreach cell_name {sg13g2_nor2_2 sg13g2_nor3_1 sg13g2_nor4_1} {
|
||||
set cell [get_lib_cells sg13g2_stdcell_typ_1p20V_25C/$cell_name]
|
||||
if { $cell == "" } {
|
||||
puts "FAIL: $cell_name not found"
|
||||
exit 1
|
||||
}
|
||||
}
|
||||
|
||||
# AND gates
|
||||
set and2 [get_lib_cells sg13g2_stdcell_typ_1p20V_25C/sg13g2_and2_1]
|
||||
if { $and2 == "" } {
|
||||
puts "FAIL: sg13g2_and2_1 not found"
|
||||
exit 1
|
||||
}
|
||||
|
||||
report_lib_cell sg13g2_stdcell_typ_1p20V_25C/sg13g2_and2_1
|
||||
|
||||
foreach cell_name {sg13g2_and2_2 sg13g2_and3_1 sg13g2_and4_1} {
|
||||
set cell [get_lib_cells sg13g2_stdcell_typ_1p20V_25C/$cell_name]
|
||||
if { $cell == "" } {
|
||||
puts "FAIL: $cell_name not found"
|
||||
exit 1
|
||||
}
|
||||
}
|
||||
|
||||
# MUX cells
|
||||
set mux2 [get_lib_cells sg13g2_stdcell_typ_1p20V_25C/sg13g2_mux2_1]
|
||||
if { $mux2 == "" } {
|
||||
puts "FAIL: sg13g2_mux2_1 not found"
|
||||
exit 1
|
||||
}
|
||||
|
||||
report_lib_cell sg13g2_stdcell_typ_1p20V_25C/sg13g2_mux2_1
|
||||
|
||||
set mux4 [get_lib_cells sg13g2_stdcell_typ_1p20V_25C/sg13g2_mux4_1]
|
||||
if { $mux4 == "" } {
|
||||
puts "FAIL: sg13g2_mux4_1 not found"
|
||||
exit 1
|
||||
}
|
||||
|
||||
report_lib_cell sg13g2_stdcell_typ_1p20V_25C/sg13g2_mux4_1
|
||||
|
||||
# Flip-flop cells
|
||||
set dfrbp [get_lib_cells sg13g2_stdcell_typ_1p20V_25C/sg13g2_dfrbp_1]
|
||||
if { $dfrbp == "" } {
|
||||
puts "FAIL: sg13g2_dfrbp_1 not found"
|
||||
exit 1
|
||||
}
|
||||
|
||||
report_lib_cell sg13g2_stdcell_typ_1p20V_25C/sg13g2_dfrbp_1
|
||||
|
||||
set dfrbp_pins [get_lib_pins sg13g2_stdcell_typ_1p20V_25C/sg13g2_dfrbp_1/*]
|
||||
if { [llength $dfrbp_pins] < 4 } {
|
||||
error "expected dfrbp_1 to have at least 4 pins, found [llength $dfrbp_pins]"
|
||||
}
|
||||
|
||||
# Latch cells
|
||||
set dlhq [get_lib_cells sg13g2_stdcell_typ_1p20V_25C/sg13g2_dlhq_1]
|
||||
if { $dlhq == "" } {
|
||||
puts "FAIL: sg13g2_dlhq_1 not found"
|
||||
exit 1
|
||||
}
|
||||
|
||||
report_lib_cell sg13g2_stdcell_typ_1p20V_25C/sg13g2_dlhq_1
|
||||
|
||||
# Complex cells (AOI)
|
||||
set a21o [get_lib_cells sg13g2_stdcell_typ_1p20V_25C/sg13g2_a21o_1]
|
||||
if { $a21o == "" } {
|
||||
puts "FAIL: sg13g2_a21o_1 not found"
|
||||
exit 1
|
||||
}
|
||||
|
||||
report_lib_cell sg13g2_stdcell_typ_1p20V_25C/sg13g2_a21o_1
|
||||
|
||||
# XOR/XNOR
|
||||
set xor [get_lib_cells sg13g2_stdcell_typ_1p20V_25C/sg13g2_xor2_1]
|
||||
if { $xor == "" } {
|
||||
puts "FAIL: sg13g2_xor2_1 not found"
|
||||
exit 1
|
||||
}
|
||||
|
||||
report_lib_cell sg13g2_stdcell_typ_1p20V_25C/sg13g2_xor2_1
|
||||
|
||||
set xnor [get_lib_cells sg13g2_stdcell_typ_1p20V_25C/sg13g2_xnor2_1]
|
||||
if { $xnor == "" } {
|
||||
puts "FAIL: sg13g2_xnor2_1 not found"
|
||||
exit 1
|
||||
}
|
||||
|
||||
report_lib_cell sg13g2_stdcell_typ_1p20V_25C/sg13g2_xnor2_1
|
||||
|
||||
# Tri-state / enable buffers
|
||||
set ebufn [get_lib_cells sg13g2_stdcell_typ_1p20V_25C/sg13g2_ebufn_2]
|
||||
if { $ebufn == "" } {
|
||||
puts "FAIL: sg13g2_ebufn_2 not found"
|
||||
exit 1
|
||||
}
|
||||
|
||||
report_lib_cell sg13g2_stdcell_typ_1p20V_25C/sg13g2_ebufn_2
|
||||
|
||||
# Delay cells
|
||||
set dlygate [get_lib_cells sg13g2_stdcell_typ_1p20V_25C/sg13g2_dlygate4sd1_1]
|
||||
if { $dlygate == "" } {
|
||||
puts "FAIL: sg13g2_dlygate4sd1_1 not found"
|
||||
exit 1
|
||||
}
|
||||
|
||||
report_lib_cell sg13g2_stdcell_typ_1p20V_25C/sg13g2_dlygate4sd1_1
|
||||
|
||||
############################################################
|
||||
# Pattern matching across library
|
||||
############################################################
|
||||
|
||||
set all_cells [get_lib_cells sg13g2_stdcell_typ_1p20V_25C/*]
|
||||
if { [llength $all_cells] < 70 } {
|
||||
error "expected broad sg13g2 1p20V cell set, found [llength $all_cells]"
|
||||
}
|
||||
|
||||
set all_inv [get_lib_cells sg13g2_stdcell_typ_1p20V_25C/sg13g2_inv_*]
|
||||
if { [llength $all_inv] < 4 } {
|
||||
error "expected sg13g2 inverter variants, found [llength $all_inv]"
|
||||
}
|
||||
|
||||
set all_nand [get_lib_cells sg13g2_stdcell_typ_1p20V_25C/sg13g2_nand*]
|
||||
if { [llength $all_nand] < 3 } {
|
||||
error "expected sg13g2 nand variants, found [llength $all_nand]"
|
||||
}
|
||||
|
||||
############################################################
|
||||
# Also read the 1.50V variant
|
||||
############################################################
|
||||
|
||||
read_liberty ../../test/ihp-sg13g2/sg13g2_stdcell_typ_1p50V_25C.lib
|
||||
|
||||
set lib_1p5 [get_libs sg13g2_stdcell_typ_1p50V_25C]
|
||||
if { $lib_1p5 == "" } {
|
||||
puts "FAIL: IHP 1p50V library not found"
|
||||
exit 1
|
||||
}
|
||||
|
||||
set cells_1p5 [get_lib_cells sg13g2_stdcell_typ_1p50V_25C/*]
|
||||
if { [llength $cells_1p5] < 70 } {
|
||||
error "expected broad sg13g2 1p50V cell set, found [llength $cells_1p5]"
|
||||
}
|
||||
|
|
@ -0,0 +1,48 @@
|
|||
# Read sky130hd liberty and query cells/pins
|
||||
read_liberty ../../test/sky130hd/sky130_fd_sc_hd__tt_025C_1v80.lib
|
||||
|
||||
set lib [get_libs sky130_fd_sc_hd__tt_025C_1v80]
|
||||
if { $lib == "" } {
|
||||
puts "FAIL: library not found"
|
||||
exit 1
|
||||
}
|
||||
|
||||
# Query a common cell
|
||||
set cell [get_lib_cells sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__inv_1]
|
||||
if { $cell == "" } {
|
||||
puts "FAIL: inv_1 cell not found"
|
||||
exit 1
|
||||
}
|
||||
|
||||
# Query pins
|
||||
set pins [get_lib_pins sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__inv_1/*]
|
||||
if { [llength $pins] == 0 } {
|
||||
puts "FAIL: no pins found"
|
||||
exit 1
|
||||
}
|
||||
if { [llength $pins] != 2 } {
|
||||
error "expected exactly 2 pins on sky130 inv_1, found [llength $pins]"
|
||||
}
|
||||
|
||||
set inv_area [get_property $cell area]
|
||||
if { $inv_area <= 0.0 } {
|
||||
error "expected positive area for sky130 inv_1, got $inv_area"
|
||||
}
|
||||
|
||||
set inv_a [get_lib_pins sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__inv_1/A]
|
||||
set inv_y [get_lib_pins sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__inv_1/Y]
|
||||
if { $inv_a == "" || $inv_y == "" } {
|
||||
error "expected both A and Y pins on sky130 inv_1"
|
||||
}
|
||||
|
||||
# Query a 2-input gate
|
||||
set nand [get_lib_cells sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__nand2_1]
|
||||
if { $nand == "" } {
|
||||
puts "FAIL: nand2_1 not found"
|
||||
exit 1
|
||||
}
|
||||
|
||||
set nand_pins [get_lib_pins sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__nand2_1/*]
|
||||
if { [llength $nand_pins] != 3 } {
|
||||
error "expected 3 pins on sky130 nand2_1, found [llength $nand_pins]"
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,238 @@
|
|||
--- scan DFF cell queries ---
|
||||
sky130_fd_sc_hd__sdfxtp_1 area=26.275200
|
||||
has test_cell: yes
|
||||
CLK dir=input scan_type=none func=
|
||||
D dir=input scan_type=none func=
|
||||
Q dir=output scan_type=none func=IQ
|
||||
SCD dir=input scan_type=none func=
|
||||
SCE dir=input scan_type=none func=
|
||||
IQ dir=internal scan_type=none func=
|
||||
IQ_N dir=internal scan_type=none func=
|
||||
sky130_fd_sc_hd__sdfxtp_2 area=27.526400
|
||||
has test_cell: yes
|
||||
CLK dir=input scan_type=none func=
|
||||
D dir=input scan_type=none func=
|
||||
Q dir=output scan_type=none func=IQ
|
||||
SCD dir=input scan_type=none func=
|
||||
SCE dir=input scan_type=none func=
|
||||
IQ dir=internal scan_type=none func=
|
||||
IQ_N dir=internal scan_type=none func=
|
||||
sky130_fd_sc_hd__sdfxtp_4 area=30.028799
|
||||
has test_cell: yes
|
||||
CLK dir=input scan_type=none func=
|
||||
D dir=input scan_type=none func=
|
||||
Q dir=output scan_type=none func=IQ
|
||||
SCD dir=input scan_type=none func=
|
||||
SCE dir=input scan_type=none func=
|
||||
IQ dir=internal scan_type=none func=
|
||||
IQ_N dir=internal scan_type=none func=
|
||||
sky130_fd_sc_hd__sdfxbp_1 area=30.028799
|
||||
has test_cell: yes
|
||||
CLK dir=input scan_type=none
|
||||
D dir=input scan_type=none
|
||||
Q dir=output scan_type=none
|
||||
Q_N dir=output scan_type=none
|
||||
SCD dir=input scan_type=none
|
||||
SCE dir=input scan_type=none
|
||||
IQ dir=internal scan_type=none
|
||||
IQ_N dir=internal scan_type=none
|
||||
sky130_fd_sc_hd__sdfxbp_2 area=32.531200
|
||||
has test_cell: yes
|
||||
CLK dir=input scan_type=none
|
||||
D dir=input scan_type=none
|
||||
Q dir=output scan_type=none
|
||||
Q_N dir=output scan_type=none
|
||||
SCD dir=input scan_type=none
|
||||
SCE dir=input scan_type=none
|
||||
IQ dir=internal scan_type=none
|
||||
IQ_N dir=internal scan_type=none
|
||||
sky130_fd_sc_hd__sdfrtp_1 area=31.280001
|
||||
has test_cell: yes
|
||||
CLK dir=input scan_type=none
|
||||
D dir=input scan_type=none
|
||||
Q dir=output scan_type=none
|
||||
RESET_B dir=input scan_type=none
|
||||
SCD dir=input scan_type=none
|
||||
SCE dir=input scan_type=none
|
||||
IQ dir=internal scan_type=none
|
||||
IQ_N dir=internal scan_type=none
|
||||
sky130_fd_sc_hd__sdfrtp_2 area=32.531200
|
||||
has test_cell: yes
|
||||
CLK dir=input scan_type=none
|
||||
D dir=input scan_type=none
|
||||
Q dir=output scan_type=none
|
||||
RESET_B dir=input scan_type=none
|
||||
SCD dir=input scan_type=none
|
||||
SCE dir=input scan_type=none
|
||||
IQ dir=internal scan_type=none
|
||||
IQ_N dir=internal scan_type=none
|
||||
sky130_fd_sc_hd__sdfrtp_4 area=35.033600
|
||||
has test_cell: yes
|
||||
CLK dir=input scan_type=none
|
||||
D dir=input scan_type=none
|
||||
Q dir=output scan_type=none
|
||||
RESET_B dir=input scan_type=none
|
||||
SCD dir=input scan_type=none
|
||||
SCE dir=input scan_type=none
|
||||
IQ dir=internal scan_type=none
|
||||
IQ_N dir=internal scan_type=none
|
||||
sky130_fd_sc_hd__sdfstp_1 area=33.782398
|
||||
CLK dir=input scan_type=none
|
||||
D dir=input scan_type=none
|
||||
Q dir=output scan_type=none
|
||||
SCD dir=input scan_type=none
|
||||
SCE dir=input scan_type=none
|
||||
SET_B dir=input scan_type=none
|
||||
IQ dir=internal scan_type=none
|
||||
IQ_N dir=internal scan_type=none
|
||||
sky130_fd_sc_hd__sdfstp_2 area=35.033600
|
||||
CLK dir=input scan_type=none
|
||||
D dir=input scan_type=none
|
||||
Q dir=output scan_type=none
|
||||
SCD dir=input scan_type=none
|
||||
SCE dir=input scan_type=none
|
||||
SET_B dir=input scan_type=none
|
||||
IQ dir=internal scan_type=none
|
||||
IQ_N dir=internal scan_type=none
|
||||
sky130_fd_sc_hd__sdfstp_4 area=37.535999
|
||||
CLK dir=input scan_type=none
|
||||
D dir=input scan_type=none
|
||||
Q dir=output scan_type=none
|
||||
SCD dir=input scan_type=none
|
||||
SCE dir=input scan_type=none
|
||||
SET_B dir=input scan_type=none
|
||||
IQ dir=internal scan_type=none
|
||||
IQ_N dir=internal scan_type=none
|
||||
--- scan DFF timing arcs ---
|
||||
sky130_fd_sc_hd__sdfxtp_1 arc_sets = 8
|
||||
sky130_fd_sc_hd__sdfxtp_1 CLK -> CLK role=width
|
||||
sky130_fd_sc_hd__sdfxtp_1 CLK -> D role=setup
|
||||
sky130_fd_sc_hd__sdfxtp_1 CLK -> D role=hold
|
||||
sky130_fd_sc_hd__sdfxtp_1 CLK -> Q role=Reg Clk to Q
|
||||
sky130_fd_sc_hd__sdfxtp_1 CLK -> SCD role=setup
|
||||
sky130_fd_sc_hd__sdfxtp_1 CLK -> SCD role=hold
|
||||
sky130_fd_sc_hd__sdfxtp_1 CLK -> SCE role=setup
|
||||
sky130_fd_sc_hd__sdfxtp_1 CLK -> SCE role=hold
|
||||
sky130_fd_sc_hd__sdfrtp_1 arc_sets = 12
|
||||
sky130_fd_sc_hd__sdfrtp_1 CLK -> CLK role=width
|
||||
sky130_fd_sc_hd__sdfrtp_1 CLK -> D role=setup
|
||||
sky130_fd_sc_hd__sdfrtp_1 CLK -> D role=hold
|
||||
sky130_fd_sc_hd__sdfrtp_1 CLK -> Q role=Reg Clk to Q
|
||||
sky130_fd_sc_hd__sdfrtp_1 RESET_B -> Q role=Reg Set/Clr
|
||||
sky130_fd_sc_hd__sdfrtp_1 CLK -> RESET_B role=recovery
|
||||
sky130_fd_sc_hd__sdfrtp_1 CLK -> RESET_B role=removal
|
||||
sky130_fd_sc_hd__sdfrtp_1 RESET_B -> RESET_B role=width
|
||||
sky130_fd_sc_hd__sdfrtp_1 CLK -> SCD role=setup
|
||||
sky130_fd_sc_hd__sdfrtp_1 CLK -> SCD role=hold
|
||||
sky130_fd_sc_hd__sdfrtp_1 CLK -> SCE role=setup
|
||||
sky130_fd_sc_hd__sdfrtp_1 CLK -> SCE role=hold
|
||||
sky130_fd_sc_hd__sdfstp_1 arc_sets = 12
|
||||
sky130_fd_sc_hd__sdfstp_1 CLK -> CLK role=width
|
||||
sky130_fd_sc_hd__sdfstp_1 CLK -> D role=setup
|
||||
sky130_fd_sc_hd__sdfstp_1 CLK -> D role=hold
|
||||
sky130_fd_sc_hd__sdfstp_1 CLK -> Q role=Reg Clk to Q
|
||||
sky130_fd_sc_hd__sdfstp_1 SET_B -> Q role=Reg Set/Clr
|
||||
sky130_fd_sc_hd__sdfstp_1 CLK -> SCD role=setup
|
||||
sky130_fd_sc_hd__sdfstp_1 CLK -> SCD role=hold
|
||||
sky130_fd_sc_hd__sdfstp_1 CLK -> SCE role=setup
|
||||
sky130_fd_sc_hd__sdfstp_1 CLK -> SCE role=hold
|
||||
sky130_fd_sc_hd__sdfstp_1 CLK -> SET_B role=recovery
|
||||
sky130_fd_sc_hd__sdfstp_1 CLK -> SET_B role=removal
|
||||
sky130_fd_sc_hd__sdfstp_1 SET_B -> SET_B role=width
|
||||
SDFF_X1 test_cell=no
|
||||
SDFF_X2 test_cell=no
|
||||
SDFFR_X1 test_cell=no
|
||||
SDFFS_X1 test_cell=no
|
||||
SDFFRS_X1 test_cell=no
|
||||
CLKGATETST_X1 area=3.990000 test_cell=no
|
||||
CLKGATETST_X1 CK -> CK role=width
|
||||
CLKGATETST_X1 CK -> E role=hold
|
||||
CLKGATETST_X1 CK -> E role=setup
|
||||
CLKGATETST_X1 CK -> SE role=hold
|
||||
CLKGATETST_X1 CK -> SE role=setup
|
||||
CLKGATETST_X1 CK -> GCK role=combinational
|
||||
CLKGATETST_X1 CK -> GCK role=combinational
|
||||
CLKGATETST_X1 CK -> GCK role=combinational
|
||||
CLKGATETST_X1 CK -> GCK role=combinational
|
||||
ASAP7 ICGx1 arc_sets = 13
|
||||
ICGx1_ASAP7_75t_R CLK -> GCLK role=combinational
|
||||
ICGx1_ASAP7_75t_R CLK -> GCLK role=combinational
|
||||
ICGx1_ASAP7_75t_R CLK -> GCLK role=combinational
|
||||
ICGx1_ASAP7_75t_R CLK -> CLK role=width
|
||||
ICGx1_ASAP7_75t_R CLK -> CLK role=width
|
||||
ICGx1_ASAP7_75t_R CLK -> ENA role=hold
|
||||
ICGx1_ASAP7_75t_R CLK -> ENA role=hold
|
||||
ICGx1_ASAP7_75t_R CLK -> ENA role=setup
|
||||
ICGx1_ASAP7_75t_R CLK -> ENA role=setup
|
||||
ICGx1_ASAP7_75t_R CLK -> SE role=hold
|
||||
ICGx1_ASAP7_75t_R CLK -> SE role=hold
|
||||
ICGx1_ASAP7_75t_R CLK -> SE role=setup
|
||||
ICGx1_ASAP7_75t_R CLK -> SE role=setup
|
||||
DFFHQNx1_ASAP7_75t_R arcs=5
|
||||
DFFHQNx1_ASAP7_75t_R CLK -> QN role=Reg Clk to Q
|
||||
DFFHQNx1_ASAP7_75t_R CLK -> CLK role=width
|
||||
DFFHQNx1_ASAP7_75t_R CLK -> CLK role=width
|
||||
DFFHQNx1_ASAP7_75t_R CLK -> D role=hold
|
||||
DFFHQNx1_ASAP7_75t_R CLK -> D role=setup
|
||||
Warning 354: liberty_scan_signal_types.tcl line 1, cell 'DFFHQx1_ASAP7_75t_R' not found.
|
||||
DFFHQNx2_ASAP7_75t_R arcs=5
|
||||
DFFHQNx2_ASAP7_75t_R CLK -> QN role=Reg Clk to Q
|
||||
DFFHQNx2_ASAP7_75t_R CLK -> CLK role=width
|
||||
DFFHQNx2_ASAP7_75t_R CLK -> CLK role=width
|
||||
DFFHQNx2_ASAP7_75t_R CLK -> D role=hold
|
||||
DFFHQNx2_ASAP7_75t_R CLK -> D role=setup
|
||||
Warning 354: liberty_scan_signal_types.tcl line 1, cell 'DFFHQx2_ASAP7_75t_R' not found.
|
||||
Warning 441: liberty_scan_signal_types.tcl line 1, set_input_delay relative to a clock defined on the same port/pin not allowed.
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: out1 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk1 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg2/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg2/Q (DFF_X1)
|
||||
0.00 0.08 ^ out1 (out)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
-3.00 7.00 output external delay
|
||||
7.00 data required time
|
||||
---------------------------------------------------------
|
||||
7.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
6.92 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
|
||||
Path Group: clk2
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 ^ reg1/CK (DFF_X1)
|
||||
0.08 10.08 v reg1/Q (DFF_X1)
|
||||
0.00 10.08 v reg3/D (DFF_X1)
|
||||
10.08 data arrival time
|
||||
|
||||
20.00 20.00 clock clk2 (rise edge)
|
||||
0.00 20.00 clock network delay (ideal)
|
||||
0.00 20.00 clock reconvergence pessimism
|
||||
20.00 ^ reg3/CK (DFF_X1)
|
||||
-0.04 19.96 library setup time
|
||||
19.96 data required time
|
||||
---------------------------------------------------------
|
||||
19.96 data required time
|
||||
-10.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.88 slack (MET)
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,226 @@
|
|||
# Test scan signal_type parsing, test_cell construction, and
|
||||
# scan-related port attributes across multiple PDKs.
|
||||
source ../../test/helpers.tcl
|
||||
|
||||
############################################################
|
||||
# Read Sky130 library (has scan flip-flop cells with test_cell groups)
|
||||
############################################################
|
||||
read_liberty ../../test/sky130hd/sky130hd_tt.lib
|
||||
|
||||
############################################################
|
||||
# Query scan DFF cells - these have test_cell groups with signal_type
|
||||
############################################################
|
||||
puts "--- scan DFF cell queries ---"
|
||||
|
||||
# sdfxtp cells are scan DFFs
|
||||
foreach cell_name {sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_2
|
||||
sky130_fd_sc_hd__sdfxtp_4} {
|
||||
set cell [get_lib_cell sky130_fd_sc_hd__tt_025C_1v80/$cell_name]
|
||||
if {$cell != "NULL" && $cell ne ""} {
|
||||
set area [get_property $cell area]
|
||||
puts "$cell_name area=$area"
|
||||
|
||||
# Check test_cell
|
||||
set tc [$cell test_cell]
|
||||
if {$tc != "NULL" && $tc ne ""} {
|
||||
puts " has test_cell: yes"
|
||||
} else {
|
||||
puts " has test_cell: no"
|
||||
}
|
||||
|
||||
# Iterate ports and check scan_signal_type
|
||||
set port_iter [$cell liberty_port_iterator]
|
||||
while {[$port_iter has_next]} {
|
||||
set port [$port_iter next]
|
||||
set dir [sta::liberty_port_direction $port]
|
||||
set is_pwr [$port is_pwr_gnd]
|
||||
if {!$is_pwr} {
|
||||
set sst [$port scan_signal_type]
|
||||
set func [$port function]
|
||||
puts " [get_name $port] dir=$dir scan_type=$sst func=$func"
|
||||
}
|
||||
}
|
||||
$port_iter finish
|
||||
}
|
||||
}
|
||||
|
||||
# sdfxbp cells are scan DFFs with complementary outputs
|
||||
foreach cell_name {sky130_fd_sc_hd__sdfxbp_1 sky130_fd_sc_hd__sdfxbp_2} {
|
||||
set cell [get_lib_cell sky130_fd_sc_hd__tt_025C_1v80/$cell_name]
|
||||
if {$cell != "NULL" && $cell ne ""} {
|
||||
set area [get_property $cell area]
|
||||
puts "$cell_name area=$area"
|
||||
|
||||
set tc [$cell test_cell]
|
||||
if {$tc != "NULL" && $tc ne ""} {
|
||||
puts " has test_cell: yes"
|
||||
} else {
|
||||
puts " has test_cell: no"
|
||||
}
|
||||
|
||||
set port_iter [$cell liberty_port_iterator]
|
||||
while {[$port_iter has_next]} {
|
||||
set port [$port_iter next]
|
||||
set is_pwr [$port is_pwr_gnd]
|
||||
if {!$is_pwr} {
|
||||
set dir [sta::liberty_port_direction $port]
|
||||
set sst [$port scan_signal_type]
|
||||
puts " [get_name $port] dir=$dir scan_type=$sst"
|
||||
}
|
||||
}
|
||||
$port_iter finish
|
||||
}
|
||||
}
|
||||
|
||||
# sdfrtp cells are scan DFFs with async reset
|
||||
foreach cell_name {sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_2
|
||||
sky130_fd_sc_hd__sdfrtp_4} {
|
||||
set cell [get_lib_cell sky130_fd_sc_hd__tt_025C_1v80/$cell_name]
|
||||
if {$cell != "NULL" && $cell ne ""} {
|
||||
set area [get_property $cell area]
|
||||
puts "$cell_name area=$area"
|
||||
|
||||
set tc [$cell test_cell]
|
||||
if {$tc != "NULL" && $tc ne ""} {
|
||||
puts " has test_cell: yes"
|
||||
} else {
|
||||
puts " has test_cell: no"
|
||||
}
|
||||
|
||||
set port_iter [$cell liberty_port_iterator]
|
||||
while {[$port_iter has_next]} {
|
||||
set port [$port_iter next]
|
||||
set is_pwr [$port is_pwr_gnd]
|
||||
if {!$is_pwr} {
|
||||
set dir [sta::liberty_port_direction $port]
|
||||
set sst [$port scan_signal_type]
|
||||
puts " [get_name $port] dir=$dir scan_type=$sst"
|
||||
}
|
||||
}
|
||||
$port_iter finish
|
||||
}
|
||||
}
|
||||
|
||||
# sdfstp cells are scan DFFs with async set
|
||||
foreach cell_name {sky130_fd_sc_hd__sdfstp_1 sky130_fd_sc_hd__sdfstp_2
|
||||
sky130_fd_sc_hd__sdfstp_4} {
|
||||
set cell [get_lib_cell sky130_fd_sc_hd__tt_025C_1v80/$cell_name]
|
||||
if {$cell != "NULL" && $cell ne ""} {
|
||||
set area [get_property $cell area]
|
||||
puts "$cell_name area=$area"
|
||||
|
||||
set port_iter [$cell liberty_port_iterator]
|
||||
while {[$port_iter has_next]} {
|
||||
set port [$port_iter next]
|
||||
set is_pwr [$port is_pwr_gnd]
|
||||
if {!$is_pwr} {
|
||||
set dir [sta::liberty_port_direction $port]
|
||||
set sst [$port scan_signal_type]
|
||||
puts " [get_name $port] dir=$dir scan_type=$sst"
|
||||
}
|
||||
}
|
||||
$port_iter finish
|
||||
}
|
||||
}
|
||||
|
||||
############################################################
|
||||
# Timing arcs on scan DFFs (exercises recovery/removal arcs)
|
||||
############################################################
|
||||
puts "--- scan DFF timing arcs ---"
|
||||
|
||||
foreach cell_name {sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfrtp_1
|
||||
sky130_fd_sc_hd__sdfstp_1} {
|
||||
set cell [get_lib_cell sky130_fd_sc_hd__tt_025C_1v80/$cell_name]
|
||||
if {$cell != "NULL" && $cell ne ""} {
|
||||
set arcs [$cell timing_arc_sets]
|
||||
set arc_count [llength $arcs]
|
||||
puts "$cell_name arc_sets = $arc_count"
|
||||
foreach arc $arcs {
|
||||
set role [$arc role]
|
||||
puts " [$arc full_name] role=$role"
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
############################################################
|
||||
# Read Nangate library and query scan cells there too
|
||||
############################################################
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
|
||||
# Nangate SDFF cells
|
||||
foreach cell_name {SDFF_X1 SDFF_X2 SDFFR_X1 SDFFS_X1 SDFFRS_X1} {
|
||||
set cell [get_lib_cell NangateOpenCellLibrary/$cell_name]
|
||||
if {$cell != "NULL" && $cell ne ""} {
|
||||
set tc [$cell test_cell]
|
||||
puts "$cell_name test_cell=[expr {$tc != "NULL" ? "yes" : "no"}]"
|
||||
|
||||
set port_iter [$cell liberty_port_iterator]
|
||||
while {[$port_iter has_next]} {
|
||||
set port [$port_iter next]
|
||||
set dir [sta::liberty_port_direction $port]
|
||||
set sst [$port scan_signal_type]
|
||||
if {$sst != "none"} {
|
||||
puts " [get_name $port] dir=$dir scan_type=$sst"
|
||||
}
|
||||
}
|
||||
$port_iter finish
|
||||
}
|
||||
}
|
||||
|
||||
# Nangate CLKGATETST cell (clock gate test)
|
||||
set cell [get_lib_cell NangateOpenCellLibrary/CLKGATETST_X1]
|
||||
if {$cell != "NULL" && $cell ne ""} {
|
||||
set tc [$cell test_cell]
|
||||
set area [get_property $cell area]
|
||||
puts "CLKGATETST_X1 area=$area test_cell=[expr {$tc != "NULL" ? "yes" : "no"}]"
|
||||
|
||||
set arcs [$cell timing_arc_sets]
|
||||
foreach arc $arcs {
|
||||
puts " [$arc full_name] role=[$arc role]"
|
||||
}
|
||||
}
|
||||
|
||||
############################################################
|
||||
# Read ASAP7 SEQ for ICG (integrated clock gate) scan coverage
|
||||
############################################################
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_SEQ_RVT_FF_nldm_220123.lib
|
||||
|
||||
# ASAP7 ICG cell has statetable (exercises clock gate paths)
|
||||
set cell [get_lib_cell asap7sc7p5t_SEQ_RVT_FF_nldm_220123/ICGx1_ASAP7_75t_R]
|
||||
if {$cell != "NULL" && $cell ne ""} {
|
||||
set arcs [$cell timing_arc_sets]
|
||||
puts "ASAP7 ICGx1 arc_sets = [llength $arcs]"
|
||||
foreach arc $arcs {
|
||||
puts " [$arc full_name] role=[$arc role]"
|
||||
}
|
||||
}
|
||||
|
||||
# ASAP7 DFFs with scan
|
||||
foreach cell_name {DFFHQNx1_ASAP7_75t_R DFFHQx1_ASAP7_75t_R
|
||||
DFFHQNx2_ASAP7_75t_R DFFHQx2_ASAP7_75t_R} {
|
||||
set cell [get_lib_cell asap7sc7p5t_SEQ_RVT_FF_nldm_220123/$cell_name]
|
||||
if {$cell != "NULL" && $cell ne ""} {
|
||||
set arcs [$cell timing_arc_sets]
|
||||
puts "$cell_name arcs=[llength $arcs]"
|
||||
foreach arc $arcs {
|
||||
set role [$arc role]
|
||||
if {$role != "combinational"} {
|
||||
puts " [$arc full_name] role=$role"
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
############################################################
|
||||
# Link design with Nangate and report checks to exercise
|
||||
# scan cell timing through a design
|
||||
############################################################
|
||||
read_verilog ../../sdc/test/sdc_test2.v
|
||||
link_design sdc_test2
|
||||
create_clock -name clk1 -period 10 [get_ports clk1]
|
||||
create_clock -name clk2 -period 20 [get_ports clk2]
|
||||
set_input_delay -clock clk1 2.0 [all_inputs]
|
||||
set_output_delay -clock clk1 3.0 [all_outputs]
|
||||
set_input_transition 0.1 [all_inputs]
|
||||
|
||||
report_checks
|
||||
|
|
@ -0,0 +1,216 @@
|
|||
sdfxtp_1 area = 26.275200
|
||||
sdfxtp_1/SCD dir=input
|
||||
sdfxtp_1/SCE dir=input
|
||||
sdfxtp_1/CLK dir=input
|
||||
sdfxtp_1/D dir=input
|
||||
sdfxtp_1/Q dir=output
|
||||
sdfxbp_1 area = 30.028799
|
||||
sky130_fd_sc_hd__ebufn_1 area = 10.009600
|
||||
sky130_fd_sc_hd__ebufn_1 Z tristate_enable = !TE_B
|
||||
sky130_fd_sc_hd__ebufn_2 area = 11.260800
|
||||
sky130_fd_sc_hd__ebufn_2 Z tristate_enable = !TE_B
|
||||
sky130_fd_sc_hd__ebufn_4 area = 16.265600
|
||||
sky130_fd_sc_hd__ebufn_4 Z tristate_enable = !TE_B
|
||||
sky130_fd_sc_hd__ebufn_8 area = 26.275200
|
||||
sky130_fd_sc_hd__ebufn_8 Z tristate_enable = !TE_B
|
||||
sky130_fd_sc_hd__dlxtp_1 area = 15.014400
|
||||
sky130_fd_sc_hd__dlxtn_1 area = 15.014400
|
||||
sky130_fd_sc_hd__dlxbn_1 area = 18.768000
|
||||
sky130_fd_sc_hd__dlxbp_1 area = 18.768000
|
||||
sky130_fd_sc_hd__dfrtp_1 area=25.024000 is_buf=0 is_inv=0
|
||||
sky130_fd_sc_hd__dfstp_1 area=26.275200 is_buf=0 is_inv=0
|
||||
sky130_fd_sc_hd__dfxtp_1 area=20.019199 is_buf=0 is_inv=0
|
||||
sky130_fd_sc_hd__dfbbp_1 area=32.531200 is_buf=0 is_inv=0
|
||||
sky130_fd_sc_hd__and2_1/X dir=output func=A*B
|
||||
sky130_fd_sc_hd__or2_1/X dir=output func=A+B
|
||||
sky130_fd_sc_hd__xor2_1/X dir=output func=(A*!B)+(!A*B)
|
||||
sky130_fd_sc_hd__xnor2_1/Y dir=output func=(!A*!B)+(A*B)
|
||||
sky130_fd_sc_hd__mux2_1/X dir=output func=(A0*!S)+(A1*S)
|
||||
INV_X1/A cap=0.001700
|
||||
INV_X2/A cap=0.003251
|
||||
INV_X4/A cap=0.006258
|
||||
BUF_X1/A cap=0.000975
|
||||
BUF_X2/A cap=0.001779
|
||||
BUF_X4/A cap=0.003402
|
||||
NAND2_X1/A1 cap=0.001599
|
||||
NAND2_X1/A2 cap=0.001664
|
||||
NOR2_X1/A1 cap=0.001714
|
||||
NOR2_X1/A2 cap=0.001651
|
||||
AOI21_X1/A cap=0.001626
|
||||
AOI21_X1/B1 cap=0.001647
|
||||
AOI21_X1/B2 cap=0.001677
|
||||
OAI21_X1/A cap=0.001671
|
||||
OAI21_X1/B1 cap=0.001662
|
||||
OAI21_X1/B2 cap=0.001572
|
||||
DFF_X1 arc_sets = 5
|
||||
DFF_X1 CK -> D role=hold
|
||||
DFF_X1 CK -> D role=setup
|
||||
DFF_X1 CK -> CK role=width
|
||||
DFF_X1 CK -> Q role=Reg Clk to Q
|
||||
DFF_X1 CK -> QN role=Reg Clk to Q
|
||||
DFFR_X1 arc_sets = 16
|
||||
DFFR_X1 CK -> D role=hold
|
||||
DFFR_X1 CK -> D role=setup
|
||||
DFFR_X1 CK -> RN role=recovery
|
||||
DFFR_X1 CK -> RN role=removal
|
||||
DFFR_X1 RN -> RN role=width
|
||||
DFFR_X1 CK -> CK role=width
|
||||
DFFR_X1 CK -> Q role=Reg Clk to Q
|
||||
DFFR_X1 RN -> Q role=Reg Set/Clr
|
||||
DFFR_X1 RN -> Q role=Reg Set/Clr
|
||||
DFFR_X1 RN -> Q role=Reg Set/Clr
|
||||
DFFR_X1 RN -> Q role=Reg Set/Clr
|
||||
DFFR_X1 CK -> QN role=Reg Clk to Q
|
||||
DFFR_X1 RN -> QN role=Reg Set/Clr
|
||||
DFFR_X1 RN -> QN role=Reg Set/Clr
|
||||
DFFR_X1 RN -> QN role=Reg Set/Clr
|
||||
DFFR_X1 RN -> QN role=Reg Set/Clr
|
||||
DFFS_X1 arc_sets = 16
|
||||
DFFS_X1 CK -> D role=hold
|
||||
DFFS_X1 CK -> D role=setup
|
||||
DFFS_X1 CK -> SN role=recovery
|
||||
DFFS_X1 CK -> SN role=removal
|
||||
DFFS_X1 SN -> SN role=width
|
||||
DFFS_X1 CK -> CK role=width
|
||||
DFFS_X1 CK -> Q role=Reg Clk to Q
|
||||
DFFS_X1 SN -> Q role=Reg Set/Clr
|
||||
DFFS_X1 SN -> Q role=Reg Set/Clr
|
||||
DFFS_X1 SN -> Q role=Reg Set/Clr
|
||||
DFFS_X1 SN -> Q role=Reg Set/Clr
|
||||
DFFS_X1 CK -> QN role=Reg Clk to Q
|
||||
DFFS_X1 SN -> QN role=Reg Set/Clr
|
||||
DFFS_X1 SN -> QN role=Reg Set/Clr
|
||||
DFFS_X1 SN -> QN role=Reg Set/Clr
|
||||
DFFS_X1 SN -> QN role=Reg Set/Clr
|
||||
DFFRS_X1 arc_sets = 35
|
||||
DFFRS_X1 CK -> D role=hold
|
||||
DFFRS_X1 CK -> D role=setup
|
||||
DFFRS_X1 CK -> RN role=recovery
|
||||
DFFRS_X1 CK -> RN role=removal
|
||||
DFFRS_X1 RN -> RN role=width
|
||||
DFFRS_X1 CK -> SN role=recovery
|
||||
DFFRS_X1 CK -> SN role=removal
|
||||
DFFRS_X1 SN -> SN role=width
|
||||
DFFRS_X1 CK -> CK role=width
|
||||
DFFRS_X1 CK -> Q role=Reg Clk to Q
|
||||
DFFRS_X1 RN -> Q role=Reg Set/Clr
|
||||
DFFRS_X1 RN -> Q role=Reg Set/Clr
|
||||
DFFRS_X1 RN -> Q role=Reg Set/Clr
|
||||
DFFRS_X1 RN -> Q role=Reg Set/Clr
|
||||
DFFRS_X1 RN -> Q role=Reg Set/Clr
|
||||
DFFRS_X1 RN -> Q role=Reg Set/Clr
|
||||
DFFRS_X1 RN -> Q role=Reg Set/Clr
|
||||
DFFRS_X1 RN -> Q role=Reg Set/Clr
|
||||
DFFRS_X1 SN -> Q role=Reg Set/Clr
|
||||
DFFRS_X1 SN -> Q role=Reg Set/Clr
|
||||
DFFRS_X1 SN -> Q role=Reg Set/Clr
|
||||
DFFRS_X1 SN -> Q role=Reg Set/Clr
|
||||
DFFRS_X1 CK -> QN role=Reg Clk to Q
|
||||
DFFRS_X1 RN -> QN role=Reg Set/Clr
|
||||
DFFRS_X1 RN -> QN role=Reg Set/Clr
|
||||
DFFRS_X1 RN -> QN role=Reg Set/Clr
|
||||
DFFRS_X1 RN -> QN role=Reg Set/Clr
|
||||
DFFRS_X1 SN -> QN role=Reg Set/Clr
|
||||
DFFRS_X1 SN -> QN role=Reg Set/Clr
|
||||
DFFRS_X1 SN -> QN role=Reg Set/Clr
|
||||
DFFRS_X1 SN -> QN role=Reg Set/Clr
|
||||
DFFRS_X1 SN -> QN role=Reg Set/Clr
|
||||
DFFRS_X1 SN -> QN role=Reg Set/Clr
|
||||
DFFRS_X1 SN -> QN role=Reg Set/Clr
|
||||
DFFRS_X1 SN -> QN role=Reg Set/Clr
|
||||
fakeram/clk dir=input bus=0 bundle=0 has_members=0
|
||||
fakeram/rd_out dir=output bus=1 bundle=0 has_members=1
|
||||
member_count = 7
|
||||
fakeram/we_in dir=input bus=0 bundle=0 has_members=0
|
||||
fakeram/ce_in dir=input bus=0 bundle=0 has_members=0
|
||||
fakeram/addr_in dir=input bus=1 bundle=0 has_members=1
|
||||
member_count = 6
|
||||
fakeram/wd_in dir=input bus=1 bundle=0 has_members=1
|
||||
member_count = 7
|
||||
fakeram/w_mask_in dir=input bus=1 bundle=0 has_members=1
|
||||
member_count = 7
|
||||
DLLx1 arc_sets = 6
|
||||
DLLx1_ASAP7_75t_R CLK -> Q role=Latch En to Q
|
||||
DLLx1_ASAP7_75t_R D -> Q role=Latch D to Q
|
||||
DLLx1_ASAP7_75t_R CLK -> CLK role=width
|
||||
DLLx1_ASAP7_75t_R CLK -> CLK role=width
|
||||
DLLx1_ASAP7_75t_R CLK -> D role=hold
|
||||
DLLx1_ASAP7_75t_R CLK -> D role=setup
|
||||
ICGx1 arc_sets = 13
|
||||
ICGx1_ASAP7_75t_R CLK -> GCLK role=combinational
|
||||
ICGx1_ASAP7_75t_R CLK -> GCLK role=combinational
|
||||
ICGx1_ASAP7_75t_R CLK -> GCLK role=combinational
|
||||
ICGx1_ASAP7_75t_R CLK -> CLK role=width
|
||||
ICGx1_ASAP7_75t_R CLK -> CLK role=width
|
||||
ICGx1_ASAP7_75t_R CLK -> ENA role=hold
|
||||
ICGx1_ASAP7_75t_R CLK -> ENA role=hold
|
||||
ICGx1_ASAP7_75t_R CLK -> ENA role=setup
|
||||
ICGx1_ASAP7_75t_R CLK -> ENA role=setup
|
||||
ICGx1_ASAP7_75t_R CLK -> SE role=hold
|
||||
ICGx1_ASAP7_75t_R CLK -> SE role=hold
|
||||
ICGx1_ASAP7_75t_R CLK -> SE role=setup
|
||||
ICGx1_ASAP7_75t_R CLK -> SE role=setup
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: out1 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk1 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg2/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg2/Q (DFF_X1)
|
||||
0.00 0.08 ^ out1 (out)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
-3.00 7.00 output external delay
|
||||
7.00 data required time
|
||||
---------------------------------------------------------
|
||||
7.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
6.92 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
|
||||
Path Group: clk2
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 ^ reg1/CK (DFF_X1)
|
||||
0.08 10.08 v reg1/Q (DFF_X1)
|
||||
0.00 10.08 v reg3/D (DFF_X1)
|
||||
10.08 data arrival time
|
||||
|
||||
20.00 20.00 clock clk2 (rise edge)
|
||||
0.00 20.00 clock network delay (ideal)
|
||||
0.00 20.00 clock reconvergence pessimism
|
||||
20.00 ^ reg3/CK (DFF_X1)
|
||||
-0.04 19.96 library setup time
|
||||
19.96 data required time
|
||||
---------------------------------------------------------
|
||||
19.96 data required time
|
||||
-10.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.88 slack (MET)
|
||||
|
||||
|
||||
Group Internal Switching Leakage Total
|
||||
Power Power Power Power (Watts)
|
||||
----------------------------------------------------------------
|
||||
Sequential 1.52e-06 6.90e-09 2.36e-07 1.76e-06 84.7%
|
||||
Combinational 1.22e-07 7.11e-08 1.25e-07 3.18e-07 15.3%
|
||||
Clock 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
|
||||
Macro 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
|
||||
Pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
|
||||
----------------------------------------------------------------
|
||||
Total 1.64e-06 7.80e-08 3.61e-07 2.08e-06 100.0%
|
||||
78.9% 3.8% 17.4%
|
||||
|
|
@ -0,0 +1,223 @@
|
|||
# Test liberty reading and querying of sequential cells (latch, ff, statetable),
|
||||
# test_cell/scan definitions, bus/bundle ports, tristate outputs,
|
||||
# internal power, and scaled cells through multi-corner.
|
||||
source ../../test/helpers.tcl
|
||||
|
||||
############################################################
|
||||
# Read Sky130 library (has test_cell, scan, tristate, latch cells)
|
||||
############################################################
|
||||
read_liberty ../../test/sky130hd/sky130hd_tt.lib
|
||||
|
||||
############################################################
|
||||
# Query scan flip-flop cells (exercises test_cell path in reader)
|
||||
############################################################
|
||||
# sdfxtp has a test_cell group with scan ports
|
||||
set sdf_cell [get_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfxtp_1]
|
||||
set sdf_area [get_property $sdf_cell area]
|
||||
puts "sdfxtp_1 area = $sdf_area"
|
||||
|
||||
# Check test_cell exists
|
||||
set tc [$sdf_cell test_cell]
|
||||
|
||||
# Query scan ports
|
||||
foreach port_name {SCD SCE CLK D Q} {
|
||||
set port [$sdf_cell find_liberty_port $port_name]
|
||||
if {$port != "NULL" && $port ne ""} {
|
||||
set dir [sta::liberty_port_direction $port]
|
||||
puts "sdfxtp_1/$port_name dir=$dir"
|
||||
}
|
||||
}
|
||||
|
||||
# Another scan cell
|
||||
set sdf_cell2 [get_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfxbp_1]
|
||||
set area2 [get_property $sdf_cell2 area]
|
||||
puts "sdfxbp_1 area = $area2"
|
||||
|
||||
############################################################
|
||||
# Query tristate buffer cells (exercises three_state parsing)
|
||||
############################################################
|
||||
foreach cell_name {sky130_fd_sc_hd__ebufn_1 sky130_fd_sc_hd__ebufn_2
|
||||
sky130_fd_sc_hd__ebufn_4 sky130_fd_sc_hd__ebufn_8} {
|
||||
set cell [get_lib_cell sky130_fd_sc_hd__tt_025C_1v80/$cell_name]
|
||||
if {$cell ne ""} {
|
||||
set area [get_property $cell area]
|
||||
puts "$cell_name area = $area"
|
||||
# Query tristate enable function
|
||||
set z_port [$cell find_liberty_port "Z"]
|
||||
if {$z_port != "NULL" && $z_port ne ""} {
|
||||
set tri_en [$z_port tristate_enable]
|
||||
puts "$cell_name Z tristate_enable = $tri_en"
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
############################################################
|
||||
# Query latch cells (exercises latch sequential parsing)
|
||||
############################################################
|
||||
foreach cell_name {sky130_fd_sc_hd__dlxtp_1 sky130_fd_sc_hd__dlxtn_1
|
||||
sky130_fd_sc_hd__dlxbn_1 sky130_fd_sc_hd__dlxbp_1} {
|
||||
set cell [get_lib_cell sky130_fd_sc_hd__tt_025C_1v80/$cell_name]
|
||||
if {$cell != "NULL" && $cell ne ""} {
|
||||
set area [get_property $cell area]
|
||||
puts "$cell_name area = $area"
|
||||
}
|
||||
}
|
||||
|
||||
############################################################
|
||||
# Query DFF cells with async set/clear (exercises recovery/removal arcs)
|
||||
############################################################
|
||||
foreach cell_name {sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfstp_1
|
||||
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfbbp_1} {
|
||||
set cell [get_lib_cell sky130_fd_sc_hd__tt_025C_1v80/$cell_name]
|
||||
if {$cell != "NULL" && $cell ne ""} {
|
||||
set area [get_property $cell area]
|
||||
set is_buf [$cell is_buffer]
|
||||
set is_inv [$cell is_inverter]
|
||||
puts "$cell_name area=$area is_buf=$is_buf is_inv=$is_inv"
|
||||
}
|
||||
}
|
||||
|
||||
############################################################
|
||||
# Port function and direction queries (exercises setFunction)
|
||||
############################################################
|
||||
foreach cell_name {sky130_fd_sc_hd__and2_1 sky130_fd_sc_hd__or2_1
|
||||
sky130_fd_sc_hd__xor2_1 sky130_fd_sc_hd__xnor2_1
|
||||
sky130_fd_sc_hd__mux2_1} {
|
||||
set cell [get_lib_cell sky130_fd_sc_hd__tt_025C_1v80/$cell_name]
|
||||
if {$cell != "NULL" && $cell ne ""} {
|
||||
set port_iter [$cell liberty_port_iterator]
|
||||
while {[$port_iter has_next]} {
|
||||
set port [$port_iter next]
|
||||
set dir [sta::liberty_port_direction $port]
|
||||
set func [$port function]
|
||||
if {$func != ""} {
|
||||
puts "$cell_name/[get_name $port] dir=$dir func=$func"
|
||||
}
|
||||
}
|
||||
$port_iter finish
|
||||
}
|
||||
}
|
||||
|
||||
############################################################
|
||||
# Read Nangate library for more queries
|
||||
############################################################
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
|
||||
############################################################
|
||||
# Port capacitance and drive resistance
|
||||
############################################################
|
||||
foreach cell_name {INV_X1 INV_X2 INV_X4 BUF_X1 BUF_X2 BUF_X4
|
||||
NAND2_X1 NOR2_X1 AOI21_X1 OAI21_X1} {
|
||||
set cell [get_lib_cell NangateOpenCellLibrary/$cell_name]
|
||||
set port_iter [$cell liberty_port_iterator]
|
||||
while {[$port_iter has_next]} {
|
||||
set port [$port_iter next]
|
||||
set dir [sta::liberty_port_direction $port]
|
||||
if {$dir == "input"} {
|
||||
set cap [get_property $port capacitance]
|
||||
puts "$cell_name/[get_name $port] cap=$cap"
|
||||
}
|
||||
}
|
||||
$port_iter finish
|
||||
}
|
||||
|
||||
############################################################
|
||||
# Timing arc set queries (exercises makeTimingArcMap paths)
|
||||
############################################################
|
||||
foreach cell_name {DFF_X1 DFFR_X1 DFFS_X1 DFFRS_X1} {
|
||||
set cell [get_lib_cell NangateOpenCellLibrary/$cell_name]
|
||||
if {$cell != "NULL" && $cell ne ""} {
|
||||
set arcs [$cell timing_arc_sets]
|
||||
set arc_count [llength $arcs]
|
||||
puts "$cell_name arc_sets = $arc_count"
|
||||
foreach arc $arcs {
|
||||
set from_port [$arc from]
|
||||
set to_port [$arc to]
|
||||
set role [$arc role]
|
||||
puts " [$arc full_name] role=$role"
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
############################################################
|
||||
# Read bus-port library (exercises bus port parsing)
|
||||
############################################################
|
||||
read_liberty ../../test/nangate45/fakeram45_64x7.lib
|
||||
|
||||
# Query bus ports
|
||||
set cell [get_lib_cell fakeram45_64x7/fakeram45_64x7]
|
||||
if {$cell != "NULL" && $cell ne ""} {
|
||||
set port_iter [$cell liberty_port_iterator]
|
||||
while {[$port_iter has_next]} {
|
||||
set port [$port_iter next]
|
||||
set dir [sta::liberty_port_direction $port]
|
||||
set is_bus [$port is_bus]
|
||||
set is_bundle [$port is_bundle]
|
||||
set has_mem [$port has_members]
|
||||
puts "fakeram/[get_name $port] dir=$dir bus=$is_bus bundle=$is_bundle has_members=$has_mem"
|
||||
if {$is_bus || $has_mem} {
|
||||
# Iterate members
|
||||
set mem_iter [$port member_iterator]
|
||||
set mem_count 0
|
||||
while {[$mem_iter has_next]} {
|
||||
set mem [$mem_iter next]
|
||||
incr mem_count
|
||||
}
|
||||
$mem_iter finish
|
||||
puts " member_count = $mem_count"
|
||||
}
|
||||
}
|
||||
$port_iter finish
|
||||
}
|
||||
|
||||
############################################################
|
||||
# Read ASAP7 SEQ for statetable/latch coverage
|
||||
############################################################
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_SEQ_RVT_FF_nldm_220123.lib
|
||||
|
||||
# Query ASAP7 latch cells
|
||||
set cell [get_lib_cell asap7sc7p5t_SEQ_RVT_FF_nldm_220123/DLLx1_ASAP7_75t_R]
|
||||
if {$cell != "NULL" && $cell ne ""} {
|
||||
set arcs [$cell timing_arc_sets]
|
||||
set arc_count [llength $arcs]
|
||||
puts "DLLx1 arc_sets = $arc_count"
|
||||
foreach arc $arcs {
|
||||
puts " [$arc full_name] role=[$arc role]"
|
||||
}
|
||||
}
|
||||
|
||||
# Query ICG (Integrated Clock Gate) cell with statetable
|
||||
set cell [get_lib_cell asap7sc7p5t_SEQ_RVT_FF_nldm_220123/ICGx1_ASAP7_75t_R]
|
||||
if {$cell != "NULL" && $cell ne ""} {
|
||||
set arcs [$cell timing_arc_sets]
|
||||
set arc_count [llength $arcs]
|
||||
puts "ICGx1 arc_sets = $arc_count"
|
||||
foreach arc $arcs {
|
||||
puts " [$arc full_name] role=[$arc role]"
|
||||
}
|
||||
}
|
||||
|
||||
############################################################
|
||||
# Link a design and run timing to exercise more Liberty.cc paths
|
||||
############################################################
|
||||
read_verilog ../../sdc/test/sdc_test2.v
|
||||
link_design sdc_test2
|
||||
create_clock -name clk1 -period 10 [get_ports clk1]
|
||||
create_clock -name clk2 -period 20 [get_ports clk2]
|
||||
set_input_delay -clock clk1 2.0 [get_ports in1]
|
||||
set_input_delay -clock clk1 2.0 [get_ports in2]
|
||||
set_input_delay -clock clk2 2.0 [get_ports in3]
|
||||
set_output_delay -clock clk1 3.0 [get_ports out1]
|
||||
set_output_delay -clock clk2 3.0 [get_ports out2]
|
||||
set_input_transition 0.1 [all_inputs]
|
||||
|
||||
report_checks
|
||||
|
||||
# Report power to exercise internal power models
|
||||
report_power
|
||||
|
||||
############################################################
|
||||
# Write liberty roundtrip
|
||||
############################################################
|
||||
set outfile [make_result_file liberty_seq_scan_bus_write.lib]
|
||||
sta::write_liberty NangateOpenCellLibrary $outfile
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,139 @@
|
|||
# Test multi-corner library reading and timing analysis with Sky130HD.
|
||||
source ../../test/helpers.tcl
|
||||
suppress_msg 1140
|
||||
|
||||
############################################################
|
||||
# Define corners and read Sky130HD libraries with explicit -max/-min views
|
||||
############################################################
|
||||
define_corners fast slow
|
||||
|
||||
read_liberty -corner fast -max ../../test/sky130hd/sky130_fd_sc_hd__ff_n40C_1v95.lib
|
||||
read_liberty -corner fast -min ../../test/sky130hd/sky130_fd_sc_hd__ff_n40C_1v95.lib
|
||||
read_liberty -corner slow -min ../../test/sky130hd/sky130_fd_sc_hd__ss_n40C_1v40.lib
|
||||
read_liberty -corner slow -max ../../test/sky130hd/sky130_fd_sc_hd__ss_n40C_1v40.lib
|
||||
|
||||
############################################################
|
||||
# Read design and link
|
||||
############################################################
|
||||
read_verilog sky130_corners_test.v
|
||||
link_design sky130_corners_test
|
||||
|
||||
############################################################
|
||||
# Create constraints
|
||||
############################################################
|
||||
create_clock -name clk -period 10 [get_ports clk]
|
||||
set_input_delay -clock clk 2.0 [get_ports in1]
|
||||
set_input_delay -clock clk 2.0 [get_ports in2]
|
||||
set_output_delay -clock clk 3.0 [get_ports out1]
|
||||
set_output_delay -clock clk 3.0 [get_ports out2]
|
||||
|
||||
############################################################
|
||||
# Report timing per corner (shows different delays per corner)
|
||||
############################################################
|
||||
puts "--- Fast corner, max ---"
|
||||
report_checks -corner fast -path_delay max
|
||||
|
||||
puts "--- Slow corner, max ---"
|
||||
report_checks -corner slow -path_delay max
|
||||
|
||||
puts "--- Fast corner, min ---"
|
||||
report_checks -corner fast -path_delay min
|
||||
|
||||
puts "--- Slow corner, min ---"
|
||||
report_checks -corner slow -path_delay min
|
||||
|
||||
# Additional non-printing checks ensure report_checks emits corner-specific paths
|
||||
# for both max and min views loaded with -max/-min.
|
||||
with_output_to_variable fast_max_rep {
|
||||
report_checks -corner fast -path_delay max
|
||||
}
|
||||
if {![regexp {Corner:\s+fast} $fast_max_rep] || ![regexp {Path Type:\s+max} $fast_max_rep]} {
|
||||
error "fast corner max report did not include expected corner/path markers"
|
||||
}
|
||||
|
||||
with_output_to_variable slow_min_rep {
|
||||
report_checks -corner slow -path_delay min
|
||||
}
|
||||
if {![regexp {Corner:\s+slow} $slow_min_rep] || ![regexp {Path Type:\s+min} $slow_min_rep]} {
|
||||
error "slow corner min report did not include expected corner/path markers"
|
||||
}
|
||||
|
||||
############################################################
|
||||
# Comprehensive cell reports - fast corner library
|
||||
############################################################
|
||||
set sky130_cells_to_report {
|
||||
sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_2 sky130_fd_sc_hd__inv_4
|
||||
sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_4
|
||||
sky130_fd_sc_hd__nand2_1 sky130_fd_sc_hd__nand3_1 sky130_fd_sc_hd__nand4_1
|
||||
sky130_fd_sc_hd__nor2_1 sky130_fd_sc_hd__nor3_1 sky130_fd_sc_hd__nor4_1
|
||||
sky130_fd_sc_hd__and2_1 sky130_fd_sc_hd__and3_1 sky130_fd_sc_hd__and4_1
|
||||
sky130_fd_sc_hd__or2_1 sky130_fd_sc_hd__or3_1 sky130_fd_sc_hd__or4_1
|
||||
sky130_fd_sc_hd__xor2_1 sky130_fd_sc_hd__xnor2_1
|
||||
sky130_fd_sc_hd__a21o_1 sky130_fd_sc_hd__a21oi_1
|
||||
sky130_fd_sc_hd__a22o_1 sky130_fd_sc_hd__a22oi_1
|
||||
sky130_fd_sc_hd__o21a_1 sky130_fd_sc_hd__o21ai_0
|
||||
sky130_fd_sc_hd__o22a_1 sky130_fd_sc_hd__o22ai_1
|
||||
sky130_fd_sc_hd__a31o_1 sky130_fd_sc_hd__a32o_1
|
||||
sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux4_1
|
||||
sky130_fd_sc_hd__fa_1 sky130_fd_sc_hd__ha_1 sky130_fd_sc_hd__maj3_1
|
||||
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfrtp_1
|
||||
sky130_fd_sc_hd__dfstp_1 sky130_fd_sc_hd__dfbbp_1
|
||||
sky130_fd_sc_hd__dlxtp_1 sky130_fd_sc_hd__dlxtn_1
|
||||
sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxbp_1
|
||||
sky130_fd_sc_hd__ebufn_1 sky130_fd_sc_hd__ebufn_2
|
||||
sky130_fd_sc_hd__clkbuf_1 sky130_fd_sc_hd__clkbuf_2
|
||||
sky130_fd_sc_hd__clkinv_1 sky130_fd_sc_hd__clkinv_2
|
||||
sky130_fd_sc_hd__conb_1
|
||||
sky130_fd_sc_hd__diode_2
|
||||
}
|
||||
|
||||
foreach cell_name $sky130_cells_to_report {
|
||||
report_lib_cell sky130_fd_sc_hd__ff_n40C_1v95/$cell_name
|
||||
}
|
||||
|
||||
############################################################
|
||||
# Cell property queries - slow corner library
|
||||
############################################################
|
||||
foreach cell_name {sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__buf_1
|
||||
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dlxtp_1
|
||||
sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__ebufn_1
|
||||
sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__fa_1} {
|
||||
set cell [lindex [get_lib_cell sky130_fd_sc_hd__ss_n40C_1v40/$cell_name] 0]
|
||||
set area [get_property $cell area]
|
||||
set du [get_property $cell dont_use]
|
||||
puts "$cell_name: area=$area dont_use=$du"
|
||||
}
|
||||
|
||||
############################################################
|
||||
# Pin capacitance queries - fast corner library
|
||||
############################################################
|
||||
foreach {cell_name pin_name} {
|
||||
sky130_fd_sc_hd__inv_1 A
|
||||
sky130_fd_sc_hd__inv_1 Y
|
||||
sky130_fd_sc_hd__buf_1 A
|
||||
sky130_fd_sc_hd__buf_1 X
|
||||
sky130_fd_sc_hd__nand2_1 A
|
||||
sky130_fd_sc_hd__nand2_1 B
|
||||
sky130_fd_sc_hd__nand2_1 Y
|
||||
sky130_fd_sc_hd__dfxtp_1 CLK
|
||||
sky130_fd_sc_hd__dfxtp_1 D
|
||||
sky130_fd_sc_hd__dfxtp_1 Q
|
||||
sky130_fd_sc_hd__dfrtp_1 CLK
|
||||
sky130_fd_sc_hd__dfrtp_1 D
|
||||
sky130_fd_sc_hd__dfrtp_1 RESET_B
|
||||
sky130_fd_sc_hd__dfrtp_1 Q
|
||||
} {
|
||||
set pin [lindex [get_lib_pin sky130_fd_sc_hd__ff_n40C_1v95/$cell_name/$pin_name] 0]
|
||||
set cap [get_property $pin capacitance]
|
||||
set dir [sta::liberty_port_direction $pin]
|
||||
puts "$cell_name/$pin_name: cap=$cap dir=$dir"
|
||||
}
|
||||
|
||||
############################################################
|
||||
# Write libraries to exercise writer paths
|
||||
############################################################
|
||||
set outfile1 [make_result_file liberty_sky130_hd_ff.lib]
|
||||
sta::write_liberty sky130_fd_sc_hd__ff_n40C_1v95 $outfile1
|
||||
|
||||
set outfile2 [make_result_file liberty_sky130_hd_ss.lib]
|
||||
sta::write_liberty sky130_fd_sc_hd__ss_n40C_1v40 $outfile2
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,164 @@
|
|||
# Test timing arc/model queries and various cell types for code coverage
|
||||
# Targets: TimingArc.cc, TableModel.cc, Liberty.cc (deep model queries),
|
||||
# LibertyReader.cc (timing type parsing), Sequential.cc
|
||||
source ../../test/helpers.tcl
|
||||
|
||||
############################################################
|
||||
# Read libraries with different timing model types
|
||||
############################################################
|
||||
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
|
||||
read_verilog ../../sdc/test/sdc_test2.v
|
||||
link_design sdc_test2
|
||||
|
||||
create_clock -name clk1 -period 10 [get_ports clk1]
|
||||
create_clock -name clk2 -period 20 [get_ports clk2]
|
||||
set_input_delay -clock clk1 2.0 [get_ports in1]
|
||||
set_input_delay -clock clk1 2.0 [get_ports in2]
|
||||
set_input_delay -clock clk1 2.0 [get_ports in3]
|
||||
set_output_delay -clock clk1 3.0 [get_ports out1]
|
||||
set_output_delay -clock clk2 3.0 [get_ports out2]
|
||||
|
||||
############################################################
|
||||
# Query timing arcs on various cell types
|
||||
############################################################
|
||||
|
||||
# Combinational cells - report_lib_cell shows timing arcs
|
||||
report_lib_cell NangateOpenCellLibrary/INV_X1
|
||||
|
||||
report_lib_cell NangateOpenCellLibrary/BUF_X1
|
||||
|
||||
report_lib_cell NangateOpenCellLibrary/NAND2_X1
|
||||
|
||||
report_lib_cell NangateOpenCellLibrary/NOR2_X1
|
||||
|
||||
report_lib_cell NangateOpenCellLibrary/AOI21_X1
|
||||
|
||||
report_lib_cell NangateOpenCellLibrary/OAI21_X1
|
||||
|
||||
report_lib_cell NangateOpenCellLibrary/AND2_X1
|
||||
|
||||
report_lib_cell NangateOpenCellLibrary/OR2_X1
|
||||
|
||||
# XOR cells
|
||||
report_lib_cell NangateOpenCellLibrary/XOR2_X1
|
||||
|
||||
report_lib_cell NangateOpenCellLibrary/XNOR2_X1
|
||||
|
||||
# Full/Half adder
|
||||
report_lib_cell NangateOpenCellLibrary/FA_X1
|
||||
|
||||
report_lib_cell NangateOpenCellLibrary/HA_X1
|
||||
|
||||
# MUX
|
||||
report_lib_cell NangateOpenCellLibrary/MUX2_X1
|
||||
|
||||
# Tristate
|
||||
report_lib_cell NangateOpenCellLibrary/TINV_X1
|
||||
|
||||
############################################################
|
||||
# Sequential cells (timing arcs: setup, hold, clk-to-q)
|
||||
############################################################
|
||||
|
||||
report_lib_cell NangateOpenCellLibrary/DFF_X1
|
||||
|
||||
report_lib_cell NangateOpenCellLibrary/DFF_X2
|
||||
|
||||
report_lib_cell NangateOpenCellLibrary/DFFR_X1
|
||||
|
||||
report_lib_cell NangateOpenCellLibrary/DFFS_X1
|
||||
|
||||
report_lib_cell NangateOpenCellLibrary/DFFRS_X1
|
||||
|
||||
# Scan DFFs
|
||||
report_lib_cell NangateOpenCellLibrary/SDFF_X1
|
||||
|
||||
report_lib_cell NangateOpenCellLibrary/SDFFR_X1
|
||||
|
||||
report_lib_cell NangateOpenCellLibrary/SDFFS_X1
|
||||
|
||||
report_lib_cell NangateOpenCellLibrary/SDFFRS_X1
|
||||
|
||||
# Latch
|
||||
report_lib_cell NangateOpenCellLibrary/TLAT_X1
|
||||
|
||||
# Clock gate
|
||||
report_lib_cell NangateOpenCellLibrary/CLKGATETST_X1
|
||||
|
||||
report_lib_cell NangateOpenCellLibrary/CLKGATETST_X2
|
||||
|
||||
############################################################
|
||||
# Query timing paths (exercises timing arc evaluation)
|
||||
############################################################
|
||||
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
|
||||
report_checks -from [get_ports in2] -to [get_ports out1]
|
||||
|
||||
report_checks -from [get_ports in1] -to [get_ports out2]
|
||||
|
||||
# Min delay paths
|
||||
report_checks -path_delay min -from [get_ports in1] -to [get_ports out1]
|
||||
|
||||
# Rise/fall reports
|
||||
report_checks -from [get_ports in1] -rise_to [get_ports out1]
|
||||
|
||||
report_checks -from [get_ports in1] -fall_to [get_ports out1]
|
||||
|
||||
############################################################
|
||||
# Drive strength variations (larger cells with different tables)
|
||||
############################################################
|
||||
|
||||
foreach size {1 2 4 8 16 32} {
|
||||
report_lib_cell NangateOpenCellLibrary/INV_X${size}
|
||||
}
|
||||
|
||||
foreach size {1 2 4 8 16 32} {
|
||||
report_lib_cell NangateOpenCellLibrary/BUF_X${size}
|
||||
}
|
||||
|
||||
foreach size {1 2 4} {
|
||||
report_lib_cell NangateOpenCellLibrary/NAND2_X${size}
|
||||
report_lib_cell NangateOpenCellLibrary/NAND3_X${size}
|
||||
report_lib_cell NangateOpenCellLibrary/NAND4_X${size}
|
||||
report_lib_cell NangateOpenCellLibrary/NOR2_X${size}
|
||||
report_lib_cell NangateOpenCellLibrary/NOR3_X${size}
|
||||
report_lib_cell NangateOpenCellLibrary/NOR4_X${size}
|
||||
}
|
||||
|
||||
############################################################
|
||||
# Write liberty (exercises timing model writing)
|
||||
############################################################
|
||||
|
||||
set outfile [make_result_file liberty_timing_models_write.lib]
|
||||
sta::write_liberty NangateOpenCellLibrary $outfile
|
||||
|
||||
############################################################
|
||||
# Read ASAP7 CCSN (CCS noise models)
|
||||
############################################################
|
||||
|
||||
read_liberty ../../test/asap7_ccsn.lib.gz
|
||||
|
||||
############################################################
|
||||
# Read latch library (exercises latch-specific paths)
|
||||
############################################################
|
||||
|
||||
read_liberty ../../test/liberty_latch3.lib
|
||||
|
||||
############################################################
|
||||
# Report check types to exercise more report paths
|
||||
############################################################
|
||||
|
||||
report_check_types -max_slew -max_capacitance -max_fanout
|
||||
|
||||
############################################################
|
||||
# ASAP7 cells with different timing model variations
|
||||
############################################################
|
||||
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz
|
||||
|
||||
# Query AO/OA complex gates
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_AO_RVT_FF_nldm_211120.lib.gz
|
||||
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_OA_RVT_FF_nldm_211120.lib.gz
|
||||
|
|
@ -0,0 +1,335 @@
|
|||
--- async reset DFF cells ---
|
||||
dfrtp_1 arc_sets = 8
|
||||
sky130_fd_sc_hd__dfrtp_1 CLK -> CLK role=width
|
||||
sky130_fd_sc_hd__dfrtp_1 CLK -> D role=setup
|
||||
sky130_fd_sc_hd__dfrtp_1 CLK -> D role=hold
|
||||
sky130_fd_sc_hd__dfrtp_1 CLK -> Q role=Reg Clk to Q
|
||||
sky130_fd_sc_hd__dfrtp_1 RESET_B -> Q role=Reg Set/Clr
|
||||
sky130_fd_sc_hd__dfrtp_1 CLK -> RESET_B role=recovery
|
||||
sky130_fd_sc_hd__dfrtp_1 CLK -> RESET_B role=removal
|
||||
sky130_fd_sc_hd__dfrtp_1 RESET_B -> RESET_B role=width
|
||||
dfstp_1 arc_sets = 8
|
||||
sky130_fd_sc_hd__dfstp_1 CLK -> CLK role=width
|
||||
sky130_fd_sc_hd__dfstp_1 CLK -> D role=setup
|
||||
sky130_fd_sc_hd__dfstp_1 CLK -> D role=hold
|
||||
sky130_fd_sc_hd__dfstp_1 CLK -> Q role=Reg Clk to Q
|
||||
sky130_fd_sc_hd__dfstp_1 SET_B -> Q role=Reg Set/Clr
|
||||
sky130_fd_sc_hd__dfstp_1 CLK -> SET_B role=recovery
|
||||
sky130_fd_sc_hd__dfstp_1 CLK -> SET_B role=removal
|
||||
sky130_fd_sc_hd__dfstp_1 SET_B -> SET_B role=width
|
||||
dfbbp_1 arc_sets = 19
|
||||
sky130_fd_sc_hd__dfbbp_1 CLK -> CLK role=width
|
||||
sky130_fd_sc_hd__dfbbp_1 CLK -> D role=setup
|
||||
sky130_fd_sc_hd__dfbbp_1 CLK -> D role=hold
|
||||
sky130_fd_sc_hd__dfbbp_1 CLK -> Q role=Reg Clk to Q
|
||||
sky130_fd_sc_hd__dfbbp_1 RESET_B -> Q role=Reg Set/Clr
|
||||
sky130_fd_sc_hd__dfbbp_1 SET_B -> Q role=Reg Set/Clr
|
||||
sky130_fd_sc_hd__dfbbp_1 CLK -> Q_N role=Reg Clk to Q
|
||||
sky130_fd_sc_hd__dfbbp_1 RESET_B -> Q_N role=Reg Set/Clr
|
||||
sky130_fd_sc_hd__dfbbp_1 SET_B -> Q_N role=Reg Set/Clr
|
||||
sky130_fd_sc_hd__dfbbp_1 CLK -> RESET_B role=recovery
|
||||
sky130_fd_sc_hd__dfbbp_1 CLK -> RESET_B role=removal
|
||||
sky130_fd_sc_hd__dfbbp_1 RESET_B -> RESET_B role=width
|
||||
sky130_fd_sc_hd__dfbbp_1 SET_B -> RESET_B role=non-sequential setup
|
||||
sky130_fd_sc_hd__dfbbp_1 SET_B -> RESET_B role=non-sequential hold
|
||||
sky130_fd_sc_hd__dfbbp_1 CLK -> SET_B role=recovery
|
||||
sky130_fd_sc_hd__dfbbp_1 CLK -> SET_B role=removal
|
||||
sky130_fd_sc_hd__dfbbp_1 RESET_B -> SET_B role=non-sequential setup
|
||||
sky130_fd_sc_hd__dfbbp_1 SET_B -> SET_B role=width
|
||||
sky130_fd_sc_hd__dfbbp_1 RESET_B -> SET_B role=non-sequential hold
|
||||
sdfrtp_1 arc_sets = 12
|
||||
sky130_fd_sc_hd__sdfrtp_1 CLK -> CLK role=width
|
||||
sky130_fd_sc_hd__sdfrtp_1 CLK -> D role=setup
|
||||
sky130_fd_sc_hd__sdfrtp_1 CLK -> D role=hold
|
||||
sky130_fd_sc_hd__sdfrtp_1 CLK -> Q role=Reg Clk to Q
|
||||
sky130_fd_sc_hd__sdfrtp_1 RESET_B -> Q role=Reg Set/Clr
|
||||
sky130_fd_sc_hd__sdfrtp_1 CLK -> RESET_B role=recovery
|
||||
sky130_fd_sc_hd__sdfrtp_1 CLK -> RESET_B role=removal
|
||||
sky130_fd_sc_hd__sdfrtp_1 RESET_B -> RESET_B role=width
|
||||
sky130_fd_sc_hd__sdfrtp_1 CLK -> SCD role=setup
|
||||
sky130_fd_sc_hd__sdfrtp_1 CLK -> SCD role=hold
|
||||
sky130_fd_sc_hd__sdfrtp_1 CLK -> SCE role=setup
|
||||
sky130_fd_sc_hd__sdfrtp_1 CLK -> SCE role=hold
|
||||
sdfstp_1 arc_sets = 12
|
||||
sky130_fd_sc_hd__sdfstp_1 CLK -> CLK role=width
|
||||
sky130_fd_sc_hd__sdfstp_1 CLK -> D role=setup
|
||||
sky130_fd_sc_hd__sdfstp_1 CLK -> D role=hold
|
||||
sky130_fd_sc_hd__sdfstp_1 CLK -> Q role=Reg Clk to Q
|
||||
sky130_fd_sc_hd__sdfstp_1 SET_B -> Q role=Reg Set/Clr
|
||||
sky130_fd_sc_hd__sdfstp_1 CLK -> SCD role=setup
|
||||
sky130_fd_sc_hd__sdfstp_1 CLK -> SCD role=hold
|
||||
sky130_fd_sc_hd__sdfstp_1 CLK -> SCE role=setup
|
||||
sky130_fd_sc_hd__sdfstp_1 CLK -> SCE role=hold
|
||||
sky130_fd_sc_hd__sdfstp_1 CLK -> SET_B role=recovery
|
||||
sky130_fd_sc_hd__sdfstp_1 CLK -> SET_B role=removal
|
||||
sky130_fd_sc_hd__sdfstp_1 SET_B -> SET_B role=width
|
||||
--- tristate cell timing arcs ---
|
||||
sky130_fd_sc_hd__ebufn_1 arc_sets = 3
|
||||
sky130_fd_sc_hd__ebufn_1 A -> Z role=combinational
|
||||
sky130_fd_sc_hd__ebufn_1 TE_B -> Z role=tristate enable
|
||||
sky130_fd_sc_hd__ebufn_1 TE_B -> Z role=tristate disable
|
||||
sky130_fd_sc_hd__ebufn_2 arc_sets = 3
|
||||
sky130_fd_sc_hd__ebufn_2 A -> Z role=combinational
|
||||
sky130_fd_sc_hd__ebufn_2 TE_B -> Z role=tristate enable
|
||||
sky130_fd_sc_hd__ebufn_2 TE_B -> Z role=tristate disable
|
||||
sky130_fd_sc_hd__ebufn_4 arc_sets = 3
|
||||
sky130_fd_sc_hd__ebufn_4 A -> Z role=combinational
|
||||
sky130_fd_sc_hd__ebufn_4 TE_B -> Z role=tristate enable
|
||||
sky130_fd_sc_hd__ebufn_4 TE_B -> Z role=tristate disable
|
||||
sky130_fd_sc_hd__ebufn_8 arc_sets = 3
|
||||
sky130_fd_sc_hd__ebufn_8 A -> Z role=combinational
|
||||
sky130_fd_sc_hd__ebufn_8 TE_B -> Z role=tristate enable
|
||||
sky130_fd_sc_hd__ebufn_8 TE_B -> Z role=tristate disable
|
||||
--- clock gate cell timing arcs ---
|
||||
sky130_fd_sc_hd__dlclkp_1 arc_sets = 4
|
||||
sky130_fd_sc_hd__dlclkp_1 CLK -> CLK role=width
|
||||
sky130_fd_sc_hd__dlclkp_1 CLK -> GATE role=setup
|
||||
sky130_fd_sc_hd__dlclkp_1 CLK -> GATE role=hold
|
||||
sky130_fd_sc_hd__dlclkp_1 CLK -> GCLK role=combinational
|
||||
sky130_fd_sc_hd__dlclkp_2 arc_sets = 4
|
||||
sky130_fd_sc_hd__dlclkp_2 CLK -> CLK role=width
|
||||
sky130_fd_sc_hd__dlclkp_2 CLK -> GATE role=setup
|
||||
sky130_fd_sc_hd__dlclkp_2 CLK -> GATE role=hold
|
||||
sky130_fd_sc_hd__dlclkp_2 CLK -> GCLK role=combinational
|
||||
sky130_fd_sc_hd__sdlclkp_1 arc_sets = 6
|
||||
sky130_fd_sc_hd__sdlclkp_1 CLK -> CLK role=width
|
||||
sky130_fd_sc_hd__sdlclkp_1 CLK -> GATE role=setup
|
||||
sky130_fd_sc_hd__sdlclkp_1 CLK -> GATE role=hold
|
||||
sky130_fd_sc_hd__sdlclkp_1 CLK -> GCLK role=combinational
|
||||
sky130_fd_sc_hd__sdlclkp_1 CLK -> SCE role=setup
|
||||
sky130_fd_sc_hd__sdlclkp_1 CLK -> SCE role=hold
|
||||
sky130_fd_sc_hd__sdlclkp_2 arc_sets = 6
|
||||
sky130_fd_sc_hd__sdlclkp_2 CLK -> CLK role=width
|
||||
sky130_fd_sc_hd__sdlclkp_2 CLK -> GATE role=setup
|
||||
sky130_fd_sc_hd__sdlclkp_2 CLK -> GATE role=hold
|
||||
sky130_fd_sc_hd__sdlclkp_2 CLK -> GCLK role=combinational
|
||||
sky130_fd_sc_hd__sdlclkp_2 CLK -> SCE role=setup
|
||||
sky130_fd_sc_hd__sdlclkp_2 CLK -> SCE role=hold
|
||||
--- latch cell timing arcs ---
|
||||
sky130_fd_sc_hd__dlxtp_1 arc_sets = 5
|
||||
sky130_fd_sc_hd__dlxtp_1 GATE -> D role=setup
|
||||
sky130_fd_sc_hd__dlxtp_1 GATE -> D role=hold
|
||||
sky130_fd_sc_hd__dlxtp_1 GATE -> GATE role=width
|
||||
sky130_fd_sc_hd__dlxtp_1 D -> Q role=Latch D to Q
|
||||
sky130_fd_sc_hd__dlxtp_1 GATE -> Q role=Latch En to Q
|
||||
sky130_fd_sc_hd__dlxtn_1 arc_sets = 5
|
||||
sky130_fd_sc_hd__dlxtn_1 GATE_N -> D role=setup
|
||||
sky130_fd_sc_hd__dlxtn_1 GATE_N -> D role=hold
|
||||
sky130_fd_sc_hd__dlxtn_1 GATE_N -> GATE_N role=width
|
||||
sky130_fd_sc_hd__dlxtn_1 D -> Q role=Latch D to Q
|
||||
sky130_fd_sc_hd__dlxtn_1 GATE_N -> Q role=Latch En to Q
|
||||
sky130_fd_sc_hd__dlxbn_1 arc_sets = 7
|
||||
sky130_fd_sc_hd__dlxbn_1 GATE_N -> D role=setup
|
||||
sky130_fd_sc_hd__dlxbn_1 GATE_N -> D role=hold
|
||||
sky130_fd_sc_hd__dlxbn_1 GATE_N -> GATE_N role=width
|
||||
sky130_fd_sc_hd__dlxbn_1 D -> Q role=Latch D to Q
|
||||
sky130_fd_sc_hd__dlxbn_1 GATE_N -> Q role=Latch En to Q
|
||||
sky130_fd_sc_hd__dlxbn_1 D -> Q_N role=Latch D to Q
|
||||
sky130_fd_sc_hd__dlxbn_1 GATE_N -> Q_N role=Latch En to Q
|
||||
sky130_fd_sc_hd__dlxbp_1 arc_sets = 7
|
||||
sky130_fd_sc_hd__dlxbp_1 GATE -> D role=setup
|
||||
sky130_fd_sc_hd__dlxbp_1 GATE -> D role=hold
|
||||
sky130_fd_sc_hd__dlxbp_1 GATE -> GATE role=width
|
||||
sky130_fd_sc_hd__dlxbp_1 D -> Q role=Latch D to Q
|
||||
sky130_fd_sc_hd__dlxbp_1 GATE -> Q role=Latch En to Q
|
||||
sky130_fd_sc_hd__dlxbp_1 D -> Q_N role=Latch D to Q
|
||||
sky130_fd_sc_hd__dlxbp_1 GATE -> Q_N role=Latch En to Q
|
||||
DFFHQNx1 arc_sets = 5
|
||||
DFFHQNx1_ASAP7_75t_R CLK -> QN role=Reg Clk to Q
|
||||
DFFHQNx1_ASAP7_75t_R CLK -> CLK role=width
|
||||
DFFHQNx1_ASAP7_75t_R CLK -> CLK role=width
|
||||
DFFHQNx1_ASAP7_75t_R CLK -> D role=hold
|
||||
DFFHQNx1_ASAP7_75t_R CLK -> D role=setup
|
||||
DLLx1 arc_sets = 6
|
||||
DLLx1_ASAP7_75t_R CLK -> Q role=Latch En to Q
|
||||
DLLx1_ASAP7_75t_R D -> Q role=Latch D to Q
|
||||
DLLx1_ASAP7_75t_R CLK -> CLK role=width
|
||||
DLLx1_ASAP7_75t_R CLK -> CLK role=width
|
||||
DLLx1_ASAP7_75t_R CLK -> D role=hold
|
||||
DLLx1_ASAP7_75t_R CLK -> D role=setup
|
||||
ICGx1 arc_sets = 13
|
||||
ICGx1_ASAP7_75t_R CLK -> GCLK role=combinational
|
||||
ICGx1_ASAP7_75t_R CLK -> GCLK role=combinational
|
||||
ICGx1_ASAP7_75t_R CLK -> GCLK role=combinational
|
||||
ICGx1_ASAP7_75t_R CLK -> CLK role=width
|
||||
ICGx1_ASAP7_75t_R CLK -> CLK role=width
|
||||
ICGx1_ASAP7_75t_R CLK -> ENA role=hold
|
||||
ICGx1_ASAP7_75t_R CLK -> ENA role=hold
|
||||
ICGx1_ASAP7_75t_R CLK -> ENA role=setup
|
||||
ICGx1_ASAP7_75t_R CLK -> ENA role=setup
|
||||
ICGx1_ASAP7_75t_R CLK -> SE role=hold
|
||||
ICGx1_ASAP7_75t_R CLK -> SE role=hold
|
||||
ICGx1_ASAP7_75t_R CLK -> SE role=setup
|
||||
ICGx1_ASAP7_75t_R CLK -> SE role=setup
|
||||
sg13g2_dlhq_1 arc_sets = 5
|
||||
sg13g2_dlhq_1 D -> Q role=Latch D to Q
|
||||
sg13g2_dlhq_1 GATE -> Q role=Latch En to Q
|
||||
sg13g2_dlhq_1 GATE -> D role=hold
|
||||
sg13g2_dlhq_1 GATE -> D role=setup
|
||||
sg13g2_dlhq_1 GATE -> GATE role=width
|
||||
Warning 354: liberty_timing_types_deep.tcl line 1, cell 'sg13g2_dllq_1' not found.
|
||||
sg13g2_dfrbp_1 arc_sets = 10
|
||||
sg13g2_dfrbp_1 CLK -> Q role=Reg Clk to Q
|
||||
sg13g2_dfrbp_1 RESET_B -> Q role=Reg Set/Clr
|
||||
sg13g2_dfrbp_1 CLK -> Q_N role=Reg Clk to Q
|
||||
sg13g2_dfrbp_1 RESET_B -> Q_N role=Reg Set/Clr
|
||||
sg13g2_dfrbp_1 CLK -> CLK role=width
|
||||
sg13g2_dfrbp_1 CLK -> D role=hold
|
||||
sg13g2_dfrbp_1 CLK -> D role=setup
|
||||
sg13g2_dfrbp_1 CLK -> RESET_B role=recovery
|
||||
sg13g2_dfrbp_1 CLK -> RESET_B role=removal
|
||||
sg13g2_dfrbp_1 RESET_B -> RESET_B role=width
|
||||
sg13g2_dfrbp_2 arc_sets = 10
|
||||
sg13g2_dfrbp_2 CLK -> Q role=Reg Clk to Q
|
||||
sg13g2_dfrbp_2 RESET_B -> Q role=Reg Set/Clr
|
||||
sg13g2_dfrbp_2 CLK -> Q_N role=Reg Clk to Q
|
||||
sg13g2_dfrbp_2 RESET_B -> Q_N role=Reg Set/Clr
|
||||
sg13g2_dfrbp_2 CLK -> CLK role=width
|
||||
sg13g2_dfrbp_2 CLK -> D role=hold
|
||||
sg13g2_dfrbp_2 CLK -> D role=setup
|
||||
sg13g2_dfrbp_2 CLK -> RESET_B role=recovery
|
||||
sg13g2_dfrbp_2 CLK -> RESET_B role=removal
|
||||
sg13g2_dfrbp_2 RESET_B -> RESET_B role=width
|
||||
sg13g2_sdfbbp_1 arc_sets = 23
|
||||
sg13g2_sdfbbp_1 CLK -> Q role=Reg Clk to Q
|
||||
sg13g2_sdfbbp_1 CLK -> Q role=Reg Clk to Q
|
||||
sg13g2_sdfbbp_1 RESET_B -> Q role=Reg Set/Clr
|
||||
sg13g2_sdfbbp_1 SET_B -> Q role=Reg Set/Clr
|
||||
sg13g2_sdfbbp_1 CLK -> Q_N role=Reg Clk to Q
|
||||
sg13g2_sdfbbp_1 CLK -> Q_N role=Reg Clk to Q
|
||||
sg13g2_sdfbbp_1 RESET_B -> Q_N role=Reg Set/Clr
|
||||
sg13g2_sdfbbp_1 SET_B -> Q_N role=Reg Set/Clr
|
||||
sg13g2_sdfbbp_1 CLK -> CLK role=width
|
||||
sg13g2_sdfbbp_1 CLK -> D role=hold
|
||||
sg13g2_sdfbbp_1 CLK -> D role=setup
|
||||
sg13g2_sdfbbp_1 CLK -> RESET_B role=recovery
|
||||
sg13g2_sdfbbp_1 CLK -> RESET_B role=removal
|
||||
sg13g2_sdfbbp_1 RESET_B -> RESET_B role=width
|
||||
sg13g2_sdfbbp_1 CLK -> SCD role=hold
|
||||
sg13g2_sdfbbp_1 CLK -> SCD role=setup
|
||||
sg13g2_sdfbbp_1 CLK -> SCE role=hold
|
||||
sg13g2_sdfbbp_1 CLK -> SCE role=setup
|
||||
sg13g2_sdfbbp_1 CLK -> SET_B role=recovery
|
||||
sg13g2_sdfbbp_1 CLK -> SET_B role=removal
|
||||
sg13g2_sdfbbp_1 RESET_B -> SET_B role=non-sequential hold
|
||||
sg13g2_sdfbbp_1 RESET_B -> SET_B role=non-sequential setup
|
||||
sg13g2_sdfbbp_1 SET_B -> SET_B role=width
|
||||
Warning 441: liberty_timing_types_deep.tcl line 1, set_input_delay relative to a clock defined on the same port/pin not allowed.
|
||||
Group Slack
|
||||
--------------------------------------------
|
||||
clk1 2.05
|
||||
clk2 0.08
|
||||
clk1 6.92
|
||||
clk2 9.88
|
||||
|
||||
Group Slack
|
||||
--------------------------------------------
|
||||
No paths found.
|
||||
|
||||
Required Actual
|
||||
Pin Width Width Slack
|
||||
------------------------------------------------------------
|
||||
reg1/CK (high) 0.05 5.00 4.95 (MET)
|
||||
|
||||
Group Slack
|
||||
--------------------------------------------
|
||||
No paths found.
|
||||
|
||||
max slew
|
||||
|
||||
Pin Limit Slew Slack
|
||||
------------------------------------------------------------
|
||||
inv1/ZN 0.20 0.02 0.18 (MET)
|
||||
|
||||
max capacitance
|
||||
|
||||
Pin Limit Cap Slack
|
||||
------------------------------------------------------------
|
||||
nor1/ZN 0.03 0.00 0.03 (MET)
|
||||
|
||||
Cell sky130_fd_sc_hd__dfrtp_1
|
||||
Library sky130_fd_sc_hd__ff_n40C_1v95
|
||||
File ../../test/sky130hd/sky130_fd_sc_hd__ff_n40C_1v95.lib
|
||||
VGND ground
|
||||
VNB bias
|
||||
VPB bias
|
||||
VPWR power
|
||||
CLK input 0.00-0.00
|
||||
D input 0.00-0.00
|
||||
Q output function=IQ
|
||||
RESET_B input 0.00-0.00
|
||||
IQ internal
|
||||
IQ_N internal
|
||||
|
||||
Timing arcs
|
||||
CLK -> CLK
|
||||
width
|
||||
^ -> v
|
||||
v -> ^
|
||||
CLK -> D
|
||||
setup
|
||||
^ -> ^
|
||||
^ -> v
|
||||
CLK -> D
|
||||
hold
|
||||
^ -> ^
|
||||
^ -> v
|
||||
CLK -> Q
|
||||
Reg Clk to Q
|
||||
^ -> ^
|
||||
^ -> v
|
||||
RESET_B -> Q
|
||||
Reg Set/Clr
|
||||
v -> v
|
||||
CLK -> RESET_B
|
||||
recovery
|
||||
^ -> ^
|
||||
CLK -> RESET_B
|
||||
removal
|
||||
^ -> ^
|
||||
RESET_B -> RESET_B
|
||||
width
|
||||
v -> ^
|
||||
Cell sky130_fd_sc_hd__dfrtp_1
|
||||
Library sky130_fd_sc_hd__ss_n40C_1v40
|
||||
File ../../test/sky130hd/sky130_fd_sc_hd__ss_n40C_1v40.lib
|
||||
VGND ground
|
||||
VNB bias
|
||||
VPB bias
|
||||
VPWR power
|
||||
CLK input 0.00-0.00
|
||||
D input 0.00-0.00
|
||||
Q output function=IQ
|
||||
RESET_B input 0.00-0.00
|
||||
IQ internal
|
||||
IQ_N internal
|
||||
|
||||
Timing arcs
|
||||
CLK -> CLK
|
||||
width
|
||||
^ -> v
|
||||
v -> ^
|
||||
CLK -> D
|
||||
setup
|
||||
^ -> ^
|
||||
^ -> v
|
||||
CLK -> D
|
||||
hold
|
||||
^ -> ^
|
||||
^ -> v
|
||||
CLK -> Q
|
||||
Reg Clk to Q
|
||||
^ -> ^
|
||||
^ -> v
|
||||
RESET_B -> Q
|
||||
Reg Set/Clr
|
||||
v -> v
|
||||
CLK -> RESET_B
|
||||
recovery
|
||||
^ -> ^
|
||||
CLK -> RESET_B
|
||||
removal
|
||||
^ -> ^
|
||||
RESET_B -> RESET_B
|
||||
width
|
||||
v -> ^
|
||||
|
|
@ -0,0 +1,209 @@
|
|||
# Deep timing type and timing arc attribute testing across diverse PDKs.
|
||||
source ../../test/helpers.tcl
|
||||
|
||||
############################################################
|
||||
# Read Sky130 library - has pg_pin, voltage_map, DFF with
|
||||
# async clear/set (recovery/removal arcs), latches
|
||||
############################################################
|
||||
read_liberty ../../test/sky130hd/sky130hd_tt.lib
|
||||
|
||||
set sky_lib [sta::find_liberty sky130_fd_sc_hd__tt_025C_1v80]
|
||||
|
||||
############################################################
|
||||
# Query cells with async reset (DFRTP has RESET_B -> recovery/removal)
|
||||
# Uses full_name which returns "cell from -> to"
|
||||
############################################################
|
||||
puts "--- async reset DFF cells ---"
|
||||
|
||||
set cell [get_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfrtp_1]
|
||||
set arcs [$cell timing_arc_sets]
|
||||
puts "dfrtp_1 arc_sets = [llength $arcs]"
|
||||
foreach arc $arcs {
|
||||
set role [$arc role]
|
||||
puts " [$arc full_name] role=$role"
|
||||
}
|
||||
|
||||
set cell [get_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfstp_1]
|
||||
set arcs [$cell timing_arc_sets]
|
||||
puts "dfstp_1 arc_sets = [llength $arcs]"
|
||||
foreach arc $arcs {
|
||||
puts " [$arc full_name] role=[$arc role]"
|
||||
}
|
||||
|
||||
set cell [get_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfbbp_1]
|
||||
set arcs [$cell timing_arc_sets]
|
||||
puts "dfbbp_1 arc_sets = [llength $arcs]"
|
||||
foreach arc $arcs {
|
||||
puts " [$arc full_name] role=[$arc role]"
|
||||
}
|
||||
|
||||
# sdfrtp has scan + async reset
|
||||
set cell [get_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfrtp_1]
|
||||
set arcs [$cell timing_arc_sets]
|
||||
puts "sdfrtp_1 arc_sets = [llength $arcs]"
|
||||
foreach arc $arcs {
|
||||
puts " [$arc full_name] role=[$arc role]"
|
||||
}
|
||||
|
||||
# sdfstp has scan + async set
|
||||
set cell [get_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfstp_1]
|
||||
set arcs [$cell timing_arc_sets]
|
||||
puts "sdfstp_1 arc_sets = [llength $arcs]"
|
||||
foreach arc $arcs {
|
||||
puts " [$arc full_name] role=[$arc role]"
|
||||
}
|
||||
|
||||
############################################################
|
||||
# Query tristate cells (three_state_enable/disable timing types)
|
||||
############################################################
|
||||
puts "--- tristate cell timing arcs ---"
|
||||
|
||||
foreach cell_name {sky130_fd_sc_hd__ebufn_1 sky130_fd_sc_hd__ebufn_2
|
||||
sky130_fd_sc_hd__ebufn_4 sky130_fd_sc_hd__ebufn_8} {
|
||||
set cell [get_lib_cell sky130_fd_sc_hd__tt_025C_1v80/$cell_name]
|
||||
set arcs [$cell timing_arc_sets]
|
||||
puts "$cell_name arc_sets = [llength $arcs]"
|
||||
foreach arc $arcs {
|
||||
puts " [$arc full_name] role=[$arc role]"
|
||||
}
|
||||
}
|
||||
|
||||
############################################################
|
||||
# Query clock gate cells
|
||||
############################################################
|
||||
puts "--- clock gate cell timing arcs ---"
|
||||
|
||||
foreach cell_name {sky130_fd_sc_hd__dlclkp_1 sky130_fd_sc_hd__dlclkp_2
|
||||
sky130_fd_sc_hd__sdlclkp_1 sky130_fd_sc_hd__sdlclkp_2} {
|
||||
set cell [get_lib_cell sky130_fd_sc_hd__tt_025C_1v80/$cell_name]
|
||||
if {$cell != "NULL" && $cell ne ""} {
|
||||
set arcs [$cell timing_arc_sets]
|
||||
puts "$cell_name arc_sets = [llength $arcs]"
|
||||
foreach arc $arcs {
|
||||
puts " [$arc full_name] role=[$arc role]"
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
############################################################
|
||||
# Query latch cells
|
||||
############################################################
|
||||
puts "--- latch cell timing arcs ---"
|
||||
|
||||
foreach cell_name {sky130_fd_sc_hd__dlxtp_1 sky130_fd_sc_hd__dlxtn_1
|
||||
sky130_fd_sc_hd__dlxbn_1 sky130_fd_sc_hd__dlxbp_1} {
|
||||
set cell [get_lib_cell sky130_fd_sc_hd__tt_025C_1v80/$cell_name]
|
||||
if {$cell != "NULL" && $cell ne ""} {
|
||||
set arcs [$cell timing_arc_sets]
|
||||
puts "$cell_name arc_sets = [llength $arcs]"
|
||||
foreach arc $arcs {
|
||||
puts " [$arc full_name] role=[$arc role]"
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
############################################################
|
||||
# Read ASAP7 SEQ library
|
||||
############################################################
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_SEQ_RVT_FF_nldm_220123.lib
|
||||
|
||||
set cell [get_lib_cell asap7sc7p5t_SEQ_RVT_FF_nldm_220123/DFFHQNx1_ASAP7_75t_R]
|
||||
set arcs [$cell timing_arc_sets]
|
||||
puts "DFFHQNx1 arc_sets = [llength $arcs]"
|
||||
foreach arc $arcs {
|
||||
puts " [$arc full_name] role=[$arc role]"
|
||||
}
|
||||
|
||||
set cell [get_lib_cell asap7sc7p5t_SEQ_RVT_FF_nldm_220123/DLLx1_ASAP7_75t_R]
|
||||
set arcs [$cell timing_arc_sets]
|
||||
puts "DLLx1 arc_sets = [llength $arcs]"
|
||||
foreach arc $arcs {
|
||||
puts " [$arc full_name] role=[$arc role]"
|
||||
}
|
||||
|
||||
set cell [get_lib_cell asap7sc7p5t_SEQ_RVT_FF_nldm_220123/ICGx1_ASAP7_75t_R]
|
||||
set arcs [$cell timing_arc_sets]
|
||||
puts "ICGx1 arc_sets = [llength $arcs]"
|
||||
foreach arc $arcs {
|
||||
puts " [$arc full_name] role=[$arc role]"
|
||||
}
|
||||
|
||||
############################################################
|
||||
# Read IHP library
|
||||
############################################################
|
||||
read_liberty ../../test/ihp-sg13g2/sg13g2_stdcell_typ_1p20V_25C.lib
|
||||
|
||||
foreach cell_name {sg13g2_dlhq_1 sg13g2_dllq_1} {
|
||||
set cell [get_lib_cell sg13g2_stdcell_typ_1p20V_25C/$cell_name]
|
||||
if {$cell != "NULL" && $cell ne ""} {
|
||||
set arcs [$cell timing_arc_sets]
|
||||
puts "$cell_name arc_sets = [llength $arcs]"
|
||||
foreach arc $arcs {
|
||||
puts " [$arc full_name] role=[$arc role]"
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
foreach cell_name {sg13g2_dfrbp_1 sg13g2_dfrbp_2} {
|
||||
set cell [get_lib_cell sg13g2_stdcell_typ_1p20V_25C/$cell_name]
|
||||
if {$cell != "NULL" && $cell ne ""} {
|
||||
set arcs [$cell timing_arc_sets]
|
||||
puts "$cell_name arc_sets = [llength $arcs]"
|
||||
foreach arc $arcs {
|
||||
puts " [$arc full_name] role=[$arc role]"
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
foreach cell_name {sg13g2_sdfbbp_1} {
|
||||
set cell [get_lib_cell sg13g2_stdcell_typ_1p20V_25C/$cell_name]
|
||||
if {$cell != "NULL" && $cell ne ""} {
|
||||
set arcs [$cell timing_arc_sets]
|
||||
puts "$cell_name arc_sets = [llength $arcs]"
|
||||
foreach arc $arcs {
|
||||
puts " [$arc full_name] role=[$arc role]"
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
############################################################
|
||||
# Link design and exercise check timing types
|
||||
############################################################
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
read_verilog ../../sdc/test/sdc_test2.v
|
||||
link_design sdc_test2
|
||||
|
||||
create_clock -name clk1 -period 10 [get_ports clk1]
|
||||
create_clock -name clk2 -period 20 [get_ports clk2]
|
||||
set_input_delay -clock clk1 2.0 [all_inputs]
|
||||
set_output_delay -clock clk1 3.0 [all_outputs]
|
||||
set_input_transition 0.1 [all_inputs]
|
||||
|
||||
report_check_types -max_delay -min_delay
|
||||
|
||||
report_check_types -recovery -removal
|
||||
|
||||
report_check_types -min_pulse_width -min_period
|
||||
|
||||
report_check_types -clock_gating_setup -clock_gating_hold
|
||||
|
||||
report_check_types -max_slew -max_capacitance -max_fanout
|
||||
|
||||
report_check_types -max_skew
|
||||
|
||||
############################################################
|
||||
# Read Sky130 fast/slow corners
|
||||
############################################################
|
||||
read_liberty ../../test/sky130hd/sky130_fd_sc_hd__ff_n40C_1v95.lib
|
||||
|
||||
read_liberty ../../test/sky130hd/sky130_fd_sc_hd__ss_n40C_1v40.lib
|
||||
|
||||
report_lib_cell sky130_fd_sc_hd__ff_n40C_1v95/sky130_fd_sc_hd__dfrtp_1
|
||||
|
||||
report_lib_cell sky130_fd_sc_hd__ss_n40C_1v40/sky130_fd_sc_hd__dfrtp_1
|
||||
|
||||
############################################################
|
||||
# Write liberty
|
||||
############################################################
|
||||
set outfile [make_result_file liberty_timing_types_deep_write.lib]
|
||||
sta::write_liberty sky130_fd_sc_hd__tt_025C_1v80 $outfile
|
||||
|
|
@ -0,0 +1,390 @@
|
|||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: out1 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk1 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg2/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg2/Q (DFF_X1)
|
||||
0.00 0.08 ^ out1 (out)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
-3.00 7.00 output external delay
|
||||
7.00 data required time
|
||||
---------------------------------------------------------
|
||||
7.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
6.92 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: out1 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk1 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg2/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg2/Q (DFF_X1)
|
||||
0.00 0.08 ^ out1 (out)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
-3.00 7.00 output external delay
|
||||
7.00 data required time
|
||||
---------------------------------------------------------
|
||||
7.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
6.92 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: out1 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk1 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg2/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg2/Q (DFF_X1)
|
||||
0.00 0.08 ^ out1 (out)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
-3.00 7.00 output external delay
|
||||
7.00 data required time
|
||||
---------------------------------------------------------
|
||||
7.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
6.92 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: out1 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk1 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg2/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg2/Q (DFF_X1)
|
||||
0.00 0.08 ^ out1 (out)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
-3.00 7.00 output external delay
|
||||
7.00 data required time
|
||||
---------------------------------------------------------
|
||||
7.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
6.92 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: out1 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk1 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg2/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg2/Q (DFF_X1)
|
||||
0.00 0.08 ^ out1 (out)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
-3.00 7.00 output external delay
|
||||
7.00 data required time
|
||||
---------------------------------------------------------
|
||||
7.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
6.92 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: out1 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk1 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg2/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg2/Q (DFF_X1)
|
||||
0.00 0.08 ^ out1 (out)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
-3.00 7.00 output external delay
|
||||
7.00 data required time
|
||||
---------------------------------------------------------
|
||||
7.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
6.92 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: out1 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk1 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg2/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg2/Q (DFF_X1)
|
||||
0.00 0.08 ^ out1 (out)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
-3.00 7.00 output external delay
|
||||
7.00 data required time
|
||||
---------------------------------------------------------
|
||||
7.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
6.92 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: out1 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk1 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg2/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg2/Q (DFF_X1)
|
||||
0.00 0.08 ^ out1 (out)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
-3.00 7.00 output external delay
|
||||
7.00 data required time
|
||||
---------------------------------------------------------
|
||||
7.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
6.92 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: out1 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk1 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg2/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg2/Q (DFF_X1)
|
||||
0.00 0.08 ^ out1 (out)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
-3.00 7.00 output external delay
|
||||
7.00 data required time
|
||||
---------------------------------------------------------
|
||||
7.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
6.92 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: out1 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk1 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg2/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg2/Q (DFF_X1)
|
||||
0.00 0.08 ^ out1 (out)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
-3.00 7.00 output external delay
|
||||
7.00 data required time
|
||||
---------------------------------------------------------
|
||||
7.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
6.92 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: out1 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk1 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg2/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg2/Q (DFF_X1)
|
||||
0.00 0.08 ^ out1 (out)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
-3.00 7.00 output external delay
|
||||
7.00 data required time
|
||||
---------------------------------------------------------
|
||||
7.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
6.92 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: out1 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk1 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg2/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg2/Q (DFF_X1)
|
||||
0.00 0.08 ^ out1 (out)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
-3.00 7.00 output external delay
|
||||
7.00 data required time
|
||||
---------------------------------------------------------
|
||||
7.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
6.92 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: out1 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk1 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg2/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg2/Q (DFF_X1)
|
||||
0.00 0.08 ^ out1 (out)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
-3.00 7.00 output external delay
|
||||
7.00 data required time
|
||||
---------------------------------------------------------
|
||||
7.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
6.92 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: out1 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk1 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg2/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg2/Q (DFF_X1)
|
||||
0.00 0.08 ^ out1 (out)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
-3.00 7.00 output external delay
|
||||
7.00 data required time
|
||||
---------------------------------------------------------
|
||||
7.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
6.92 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: out1 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk1 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg2/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg2/Q (DFF_X1)
|
||||
0.00 0.08 ^ out1 (out)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
-3.00 7.00 output external delay
|
||||
7.00 data required time
|
||||
---------------------------------------------------------
|
||||
7.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
6.92 slack (MET)
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,117 @@
|
|||
# Test wire load model handling for code coverage
|
||||
source ../../test/helpers.tcl
|
||||
|
||||
############################################################
|
||||
# Read library with wire load models
|
||||
############################################################
|
||||
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
|
||||
# Read verilog and link design to enable wireload operations
|
||||
read_verilog ../../sdc/test/sdc_test2.v
|
||||
link_design sdc_test2
|
||||
|
||||
############################################################
|
||||
# Setup constraints (needed before report_checks)
|
||||
############################################################
|
||||
|
||||
create_clock -name clk1 -period 10 [get_ports clk1]
|
||||
set_input_delay -clock clk1 2.0 [get_ports in1]
|
||||
set_input_delay -clock clk1 2.0 [get_ports in2]
|
||||
set_input_delay -clock clk1 2.0 [get_ports in3]
|
||||
set_output_delay -clock clk1 3.0 [get_ports out1]
|
||||
set_output_delay -clock clk1 3.0 [get_ports out2]
|
||||
|
||||
############################################################
|
||||
# Wire load model queries - report_checks after each to show timing impact
|
||||
############################################################
|
||||
|
||||
set_wire_load_model -name "1K_hvratio_1_1"
|
||||
report_checks
|
||||
|
||||
set_wire_load_model -name "1K_hvratio_1_2"
|
||||
report_checks
|
||||
|
||||
set_wire_load_model -name "1K_hvratio_1_4"
|
||||
report_checks
|
||||
|
||||
set_wire_load_model -name "3K_hvratio_1_1"
|
||||
report_checks
|
||||
|
||||
set_wire_load_model -name "3K_hvratio_1_2"
|
||||
report_checks
|
||||
|
||||
set_wire_load_model -name "3K_hvratio_1_4"
|
||||
report_checks
|
||||
|
||||
set_wire_load_model -name "5K_hvratio_1_1"
|
||||
report_checks
|
||||
|
||||
set_wire_load_model -name "5K_hvratio_1_2"
|
||||
report_checks
|
||||
|
||||
set_wire_load_model -name "5K_hvratio_1_4"
|
||||
report_checks
|
||||
|
||||
############################################################
|
||||
# Wire load mode switching (exercises wireloadModeString)
|
||||
############################################################
|
||||
|
||||
set_wire_load_mode top
|
||||
report_checks
|
||||
|
||||
set_wire_load_mode enclosed
|
||||
report_checks
|
||||
|
||||
set_wire_load_mode segmented
|
||||
report_checks
|
||||
|
||||
############################################################
|
||||
# Write SDC with wireload info
|
||||
############################################################
|
||||
|
||||
set sdc_file [make_result_file liberty_wireload.sdc]
|
||||
write_sdc -no_timestamp $sdc_file
|
||||
|
||||
############################################################
|
||||
# Write liberty (exercises wireload writing in LibertyWriter)
|
||||
############################################################
|
||||
|
||||
set outfile [make_result_file liberty_wireload_write.lib]
|
||||
sta::write_liberty NangateOpenCellLibrary $outfile
|
||||
|
||||
############################################################
|
||||
# Read Sky130 library (different wireload models)
|
||||
############################################################
|
||||
|
||||
read_liberty ../../test/sky130hd/sky130hd_tt.lib
|
||||
|
||||
# Try Sky130 wire load models
|
||||
set_wire_load_model -name "Small"
|
||||
report_checks
|
||||
set_wire_load_model -name "Medium"
|
||||
report_checks
|
||||
|
||||
############################################################
|
||||
# Write liberty for sky130 (different wireload format)
|
||||
############################################################
|
||||
|
||||
set outfile2 [make_result_file liberty_wireload_write_sky130.lib]
|
||||
sta::write_liberty sky130_fd_sc_hd__tt_025C_1v80 $outfile2
|
||||
|
||||
############################################################
|
||||
# Read IHP library
|
||||
############################################################
|
||||
|
||||
read_liberty ../../test/ihp-sg13g2/sg13g2_stdcell_typ_1p20V_25C.lib
|
||||
|
||||
set outfile3 [make_result_file liberty_wireload_write_ihp.lib]
|
||||
sta::write_liberty sg13g2_stdcell_typ_1p20V_25C $outfile3
|
||||
|
||||
############################################################
|
||||
# Operating conditions + wireload interaction
|
||||
############################################################
|
||||
|
||||
set_operating_conditions typical
|
||||
|
||||
report_checks
|
||||
|
|
@ -0,0 +1,42 @@
|
|||
Differences found at line 107.
|
||||
cell_rise(Timing_7_7) {
|
||||
cell_rise(Timing_7_7) {
|
||||
Differences found at line 118.
|
||||
cell_rise(del_1_7_7) {
|
||||
cell_rise(del_1_7_7) {
|
||||
Differences found at line 70.
|
||||
cell_rise(TIMING_DELAY_7x7ds1) {
|
||||
cell_rise(TIMING_DELAY_7x7ds1) {
|
||||
Warning 1212: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13178, timing group from output port.
|
||||
Warning 1212: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13211, timing group from output port.
|
||||
Warning 1212: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13244, timing group from output port.
|
||||
Warning 1212: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13277, timing group from output port.
|
||||
Warning 1212: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13310, timing group from output port.
|
||||
Warning 1212: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13343, timing group from output port.
|
||||
Warning 1212: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13376, timing group from output port.
|
||||
Warning 1212: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 14772, timing group from output port.
|
||||
Warning 1212: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 14805, timing group from output port.
|
||||
Warning 1212: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 14838, timing group from output port.
|
||||
Differences found at line 83.
|
||||
cell_rise(delay_template_7x7_x1) {
|
||||
cell_rise(delay_template_7x7_x1) {
|
||||
Differences found at line 81.
|
||||
cell_rise(delay_template_7x7) {
|
||||
cell_rise(delay_template_7x7) {
|
||||
Differences found at line 83.
|
||||
cell_rise(delay_template_7x7_x1) {
|
||||
cell_rise(delay_template_7x7_x1) {
|
||||
Differences found at line 90.
|
||||
cell_rise(fakeram7_256x32_mem_out_delay_template) {
|
||||
cell_rise(fakeram7_256x32_mem_out_delay_template) {
|
||||
Warning 1171: ../../test/nangate45/fake_macros.lib line 32, default_max_transition is 0.0.
|
||||
Warning 1212: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_SS_nldm_211120.lib.gz line 13156, timing group from output port.
|
||||
Warning 1212: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_SS_nldm_211120.lib.gz line 13189, timing group from output port.
|
||||
Warning 1212: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_SS_nldm_211120.lib.gz line 13222, timing group from output port.
|
||||
Warning 1212: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_SS_nldm_211120.lib.gz line 13255, timing group from output port.
|
||||
Warning 1212: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_SS_nldm_211120.lib.gz line 13288, timing group from output port.
|
||||
Warning 1212: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_SS_nldm_211120.lib.gz line 13321, timing group from output port.
|
||||
Warning 1212: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_SS_nldm_211120.lib.gz line 13354, timing group from output port.
|
||||
Warning 1212: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_SS_nldm_211120.lib.gz line 14748, timing group from output port.
|
||||
Warning 1212: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_SS_nldm_211120.lib.gz line 14781, timing group from output port.
|
||||
Warning 1212: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_SS_nldm_211120.lib.gz line 14814, timing group from output port.
|
||||
|
|
@ -0,0 +1,221 @@
|
|||
# Test liberty write and verify output for code coverage
|
||||
# Targets: LibertyWriter.cc (all write functions: writeHeader, writeCells, writePort,
|
||||
# writePwrGndPort, writeBusPort, writeTimingArcSet, writeTimingModels,
|
||||
# writeTableModel0/1/2, writeTableTemplates, writeBusDcls, timingTypeString),
|
||||
# TableModel.cc (table iteration during write),
|
||||
# TimingArc.cc (arc iteration during write),
|
||||
# Liberty.cc (property queries during write)
|
||||
source ../../test/helpers.tcl
|
||||
|
||||
proc assert_written_liberty {path lib_name} {
|
||||
if {![file exists $path]} {
|
||||
error "missing written liberty file: $path"
|
||||
}
|
||||
set in [open $path r]
|
||||
set text [read $in]
|
||||
close $in
|
||||
if {[string length $text] <= 0} {
|
||||
error "written liberty file is empty: $path"
|
||||
}
|
||||
|
||||
if {[string first "library (" $text] < 0} {
|
||||
error "written liberty file has no library block: $path"
|
||||
}
|
||||
if {[string first $lib_name $text] < 0} {
|
||||
error "written liberty file does not contain library name '$lib_name': $path"
|
||||
}
|
||||
if {![regexp {cell[[:space:]]*\(} $text]} {
|
||||
error "written liberty file has no cell blocks: $path"
|
||||
}
|
||||
}
|
||||
|
||||
############################################################
|
||||
# Read and write Nangate45 (comprehensive cell library)
|
||||
############################################################
|
||||
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
|
||||
# Write liberty - this exercises most of LibertyWriter.cc
|
||||
set outfile1 [make_result_file liberty_roundtrip_nangate.lib]
|
||||
sta::write_liberty NangateOpenCellLibrary $outfile1
|
||||
assert_written_liberty $outfile1 NangateOpenCellLibrary
|
||||
|
||||
diff_files liberty_roundtrip_nangate.libok $outfile1
|
||||
|
||||
############################################################
|
||||
# Read and write Sky130 (large library with different features)
|
||||
############################################################
|
||||
|
||||
read_liberty ../../test/sky130hd/sky130hd_tt.lib
|
||||
|
||||
set outfile2 [make_result_file liberty_roundtrip_sky130.lib]
|
||||
sta::write_liberty sky130_fd_sc_hd__tt_025C_1v80 $outfile2
|
||||
assert_written_liberty $outfile2 sky130_fd_sc_hd__tt_025C_1v80
|
||||
|
||||
diff_files liberty_roundtrip_sky130.libok $outfile2
|
||||
|
||||
############################################################
|
||||
# Read and write IHP (different vendor format)
|
||||
############################################################
|
||||
|
||||
read_liberty ../../test/ihp-sg13g2/sg13g2_stdcell_typ_1p20V_25C.lib
|
||||
|
||||
set outfile3 [make_result_file liberty_roundtrip_ihp.lib]
|
||||
sta::write_liberty sg13g2_stdcell_typ_1p20V_25C $outfile3
|
||||
assert_written_liberty $outfile3 sg13g2_stdcell_typ_1p20V_25C
|
||||
|
||||
diff_files liberty_roundtrip_ihp.libok $outfile3
|
||||
|
||||
############################################################
|
||||
# Read and write ASAP7 SIMPLE (compressed input)
|
||||
############################################################
|
||||
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz
|
||||
|
||||
set outfile4 [make_result_file liberty_roundtrip_asap7_simple.lib]
|
||||
sta::write_liberty asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120 $outfile4
|
||||
assert_written_liberty $outfile4 asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120
|
||||
|
||||
diff_files liberty_roundtrip_asap7_simple.libok $outfile4
|
||||
|
||||
############################################################
|
||||
# Read and write ASAP7 SEQ (sequential cell writing)
|
||||
############################################################
|
||||
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_SEQ_RVT_FF_nldm_220123.lib
|
||||
|
||||
set outfile5 [make_result_file liberty_roundtrip_asap7_seq.lib]
|
||||
sta::write_liberty asap7sc7p5t_SEQ_RVT_FF_nldm_220123 $outfile5
|
||||
assert_written_liberty $outfile5 asap7sc7p5t_SEQ_RVT_FF_nldm_220123
|
||||
|
||||
diff_files liberty_roundtrip_asap7_seq.libok $outfile5
|
||||
|
||||
############################################################
|
||||
# Read and write ASAP7 INVBUF (compressed input)
|
||||
############################################################
|
||||
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_INVBUF_RVT_FF_nldm_220122.lib.gz
|
||||
|
||||
set outfile6 [make_result_file liberty_roundtrip_asap7_invbuf.lib]
|
||||
sta::write_liberty asap7sc7p5t_INVBUF_RVT_FF_nldm_211120 $outfile6
|
||||
assert_written_liberty $outfile6 asap7sc7p5t_INVBUF_RVT_FF_nldm_211120
|
||||
|
||||
diff_files liberty_roundtrip_asap7_invbuf.libok $outfile6
|
||||
|
||||
############################################################
|
||||
# Read and write ASAP7 AO (AND-OR cells)
|
||||
############################################################
|
||||
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_AO_RVT_FF_nldm_211120.lib.gz
|
||||
|
||||
set outfile7 [make_result_file liberty_roundtrip_asap7_ao.lib]
|
||||
sta::write_liberty asap7sc7p5t_AO_RVT_FF_nldm_211120 $outfile7
|
||||
assert_written_liberty $outfile7 asap7sc7p5t_AO_RVT_FF_nldm_211120
|
||||
|
||||
############################################################
|
||||
# Read and write ASAP7 OA (OR-AND cells)
|
||||
############################################################
|
||||
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_OA_RVT_FF_nldm_211120.lib.gz
|
||||
|
||||
set outfile8 [make_result_file liberty_roundtrip_asap7_oa.lib]
|
||||
sta::write_liberty asap7sc7p5t_OA_RVT_FF_nldm_211120 $outfile8
|
||||
assert_written_liberty $outfile8 asap7sc7p5t_OA_RVT_FF_nldm_211120
|
||||
|
||||
############################################################
|
||||
# Read and write fakeram (SRAM macro with bus ports)
|
||||
############################################################
|
||||
|
||||
read_liberty ../../test/asap7/fakeram7_256x32.lib
|
||||
|
||||
set outfile9 [make_result_file liberty_roundtrip_fakeram.lib]
|
||||
sta::write_liberty fakeram7_256x32 $outfile9
|
||||
assert_written_liberty $outfile9 fakeram7_256x32
|
||||
|
||||
diff_files liberty_roundtrip_fakeram.libok $outfile9
|
||||
|
||||
############################################################
|
||||
# Read and write fake_macros
|
||||
############################################################
|
||||
|
||||
read_liberty ../../test/nangate45/fake_macros.lib
|
||||
|
||||
set outfile10 [make_result_file liberty_roundtrip_fake_macros.lib]
|
||||
sta::write_liberty fake_macros $outfile10
|
||||
assert_written_liberty $outfile10 fake_macros
|
||||
|
||||
############################################################
|
||||
# Read and write Nangate45 fast (different corner parameters)
|
||||
############################################################
|
||||
|
||||
read_liberty ../../test/nangate45/Nangate45_fast.lib
|
||||
|
||||
set outfile11 [make_result_file liberty_roundtrip_nangate_fast.lib]
|
||||
sta::write_liberty NangateOpenCellLibrary_fast $outfile11
|
||||
assert_written_liberty $outfile11 NangateOpenCellLibrary_fast
|
||||
|
||||
############################################################
|
||||
# Read and write Nangate45 slow
|
||||
############################################################
|
||||
|
||||
read_liberty ../../test/nangate45/Nangate45_slow.lib
|
||||
|
||||
set outfile12 [make_result_file liberty_roundtrip_nangate_slow.lib]
|
||||
sta::write_liberty NangateOpenCellLibrary_slow $outfile12
|
||||
assert_written_liberty $outfile12 NangateOpenCellLibrary_slow
|
||||
|
||||
############################################################
|
||||
# Read and write Nangate45 LVT
|
||||
############################################################
|
||||
|
||||
read_liberty ../../test/nangate45/Nangate45_lvt.lib
|
||||
|
||||
set outfile13 [make_result_file liberty_roundtrip_nangate_lvt.lib]
|
||||
sta::write_liberty NangateOpenCellLibrary_lvt $outfile13
|
||||
assert_written_liberty $outfile13 NangateOpenCellLibrary_lvt
|
||||
|
||||
############################################################
|
||||
# Read and write multiple fakeram sizes
|
||||
############################################################
|
||||
|
||||
read_liberty ../../test/nangate45/fakeram45_256x16.lib
|
||||
|
||||
set outfile14 [make_result_file liberty_roundtrip_fakeram45_256x16.lib]
|
||||
sta::write_liberty fakeram45_256x16 $outfile14
|
||||
assert_written_liberty $outfile14 fakeram45_256x16
|
||||
|
||||
read_liberty ../../test/nangate45/fakeram45_64x32.lib
|
||||
|
||||
set outfile15 [make_result_file liberty_roundtrip_fakeram45_64x32.lib]
|
||||
sta::write_liberty fakeram45_64x32 $outfile15
|
||||
assert_written_liberty $outfile15 fakeram45_64x32
|
||||
|
||||
############################################################
|
||||
# Read and write ASAP7 SS corner (different operating conditions)
|
||||
############################################################
|
||||
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_SS_nldm_211120.lib.gz
|
||||
|
||||
set outfile17 [make_result_file liberty_roundtrip_asap7_ss.lib]
|
||||
sta::write_liberty asap7sc7p5t_SIMPLE_RVT_SS_nldm_211120 $outfile17
|
||||
assert_written_liberty $outfile17 asap7sc7p5t_SIMPLE_RVT_SS_nldm_211120
|
||||
|
||||
############################################################
|
||||
# Read and write Sky130 FF corner
|
||||
############################################################
|
||||
|
||||
read_liberty ../../test/sky130hd/sky130_fd_sc_hd__ff_n40C_1v95.lib
|
||||
|
||||
set outfile18 [make_result_file liberty_roundtrip_sky130_ff.lib]
|
||||
sta::write_liberty sky130_fd_sc_hd__ff_n40C_1v95 $outfile18
|
||||
assert_written_liberty $outfile18 sky130_fd_sc_hd__ff_n40C_1v95
|
||||
|
||||
############################################################
|
||||
# Read and write Sky130 SS corner
|
||||
############################################################
|
||||
|
||||
read_liberty ../../test/sky130hd/sky130_fd_sc_hd__ss_n40C_1v40.lib
|
||||
|
||||
set outfile19 [make_result_file liberty_roundtrip_sky130_ss.lib]
|
||||
sta::write_liberty sky130_fd_sc_hd__ss_n40C_1v40 $outfile19
|
||||
assert_written_liberty $outfile19 sky130_fd_sc_hd__ss_n40C_1v40
|
||||
Some files were not shown because too many files have changed in this diff Show More
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Reference in New Issue