1604 lines
52 KiB
Plaintext
1604 lines
52 KiB
Plaintext
--- baseline timing ---
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Startpoint: d1 (input port clocked by clk1)
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Endpoint: q3 (output port clocked by clk1)
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Path Group: clk1
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk1 (rise edge)
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0.00 0.00 clock network delay (ideal)
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1.00 1.00 v input external delay
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0.00 1.00 v d1 (in)
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0.06 1.06 v buf1/Z (BUF_X1)
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0.03 1.09 v and1/ZN (AND2_X1)
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0.03 1.11 ^ nand1/ZN (NAND2_X1)
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0.02 1.13 ^ buf4/Z (BUF_X4)
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0.00 1.13 ^ q3 (out)
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1.13 data arrival time
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10.00 10.00 clock clk1 (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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-1.00 9.00 output external delay
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9.00 data required time
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---------------------------------------------------------
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9.00 data required time
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-1.13 data arrival time
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---------------------------------------------------------
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7.87 slack (MET)
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
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Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
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Path Group: clk2
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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10.00 10.00 clock clk1 (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 ^ reg1/CK (DFF_X1)
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0.08 10.08 v reg1/Q (DFF_X1)
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0.00 10.08 v reg3/D (DFF_X1)
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10.08 data arrival time
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15.00 15.00 clock clk2 (rise edge)
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0.00 15.00 clock network delay (ideal)
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0.00 15.00 clock reconvergence pessimism
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15.00 ^ reg3/CK (DFF_X1)
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-0.04 14.96 library setup time
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14.96 data required time
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---------------------------------------------------------
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14.96 data required time
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-10.08 data arrival time
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---------------------------------------------------------
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4.88 slack (MET)
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Startpoint: d1 (input port clocked by clk1)
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Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
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Path Group: clk1
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Path Type: min
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk1 (rise edge)
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0.00 0.00 clock network delay (ideal)
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1.00 1.00 ^ input external delay
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0.00 1.00 ^ d1 (in)
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0.04 1.04 ^ buf1/Z (BUF_X1)
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0.01 1.05 v nor1/ZN (NOR2_X1)
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0.03 1.07 v and2/ZN (AND2_X2)
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0.00 1.07 v reg1/D (DFF_X1)
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1.07 data arrival time
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0.00 0.00 clock clk1 (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 ^ reg1/CK (DFF_X1)
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0.00 0.00 library hold time
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0.00 data required time
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---------------------------------------------------------
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0.00 data required time
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-1.07 data arrival time
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---------------------------------------------------------
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1.07 slack (MET)
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
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Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
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Path Group: clk2
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Path Type: min
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk1 (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg1/CK (DFF_X1)
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0.08 0.08 v reg1/Q (DFF_X1)
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0.00 0.08 v reg3/D (DFF_X1)
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0.08 data arrival time
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0.00 0.00 clock clk2 (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 ^ reg3/CK (DFF_X1)
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0.00 0.00 library hold time
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0.00 data required time
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---------------------------------------------------------
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0.00 data required time
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-0.08 data arrival time
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---------------------------------------------------------
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0.08 slack (MET)
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Startpoint: d1 (input port clocked by clk1)
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Endpoint: q3 (output port clocked by clk1)
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Path Group: clk1
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk1 (rise edge)
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0.00 0.00 clock network delay (ideal)
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1.00 1.00 v input external delay
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0.00 1.00 v d1 (in)
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0.06 1.06 v buf1/Z (BUF_X1)
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0.03 1.09 v and1/ZN (AND2_X1)
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0.03 1.11 ^ nand1/ZN (NAND2_X1)
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0.02 1.13 ^ buf4/Z (BUF_X4)
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0.00 1.13 ^ q3 (out)
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1.13 data arrival time
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10.00 10.00 clock clk1 (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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-1.00 9.00 output external delay
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9.00 data required time
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---------------------------------------------------------
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9.00 data required time
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-1.13 data arrival time
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---------------------------------------------------------
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7.87 slack (MET)
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
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Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
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Path Group: clk2
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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10.00 10.00 clock clk1 (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 ^ reg1/CK (DFF_X1)
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0.08 10.08 v reg1/Q (DFF_X1)
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0.00 10.08 v reg3/D (DFF_X1)
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10.08 data arrival time
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15.00 15.00 clock clk2 (rise edge)
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0.00 15.00 clock network delay (ideal)
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0.00 15.00 clock reconvergence pessimism
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15.00 ^ reg3/CK (DFF_X1)
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-0.04 14.96 library setup time
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14.96 data required time
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---------------------------------------------------------
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14.96 data required time
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-10.08 data arrival time
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---------------------------------------------------------
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4.88 slack (MET)
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--- timing edges per cell ---
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buf1 edges: 1
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buf2 edges: 1
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inv1 edges: 1
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inv2 edges: 1
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and1 edges: 1
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or1 edges: 1
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nand1 edges: 1
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nor1 edges: 1
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and2 edges: 1
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or2 edges: 1
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reg1 edges: 1
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reg2 edges: 1
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reg3 edges: 1
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buf3 edges: 1
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buf4 edges: 1
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--- specific edge queries ---
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A -> Z combinational
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^ -> ^ 0.04:0.04
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v -> v 0.06:0.06
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A -> ZN combinational
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^ -> v 0.01:0.01
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v -> ^ 0.04:0.04
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A1 -> ZN combinational
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^ -> v 0.02:0.02
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v -> ^ 0.03:0.03
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A2 -> ZN combinational
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^ -> v 0.02:0.02
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v -> ^ 0.03:0.03
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A1 -> ZN combinational
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^ -> v 0.01:0.01
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v -> ^ 0.03:0.03
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A2 -> ZN combinational
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^ -> v 0.02:0.02
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v -> ^ 0.04:0.04
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A1 -> ZN combinational
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^ -> ^ 0.03:0.03
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v -> v 0.03:0.03
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A2 -> ZN combinational
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^ -> ^ 0.03:0.03
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v -> v 0.03:0.03
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A1 -> ZN combinational
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^ -> ^ 0.02:0.02
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v -> v 0.04:0.04
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A2 -> ZN combinational
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^ -> ^ 0.03:0.03
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v -> v 0.04:0.04
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CK -> Q Reg Clk to Q
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^ -> ^ 0.08:0.08
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^ -> v 0.08:0.08
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CK -> Q Reg Clk to Q
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^ -> ^ 0.08:0.08
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^ -> v 0.08:0.08
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CK -> Q Reg Clk to Q
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^ -> ^ 0.08:0.08
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^ -> v 0.08:0.08
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d1 -> buf1/A wire
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^ -> ^ 0.00:0.00
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v -> v 0.00:0.00
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d2 -> buf2/A wire
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^ -> ^ 0.00:0.00
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v -> v 0.00:0.00
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d3 -> inv1/A wire
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^ -> ^ 0.00:0.00
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v -> v 0.00:0.00
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d4 -> inv2/A wire
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^ -> ^ 0.00:0.00
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v -> v 0.00:0.00
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reg2/Q -> q1 wire
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^ -> ^ 0.00:0.00
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v -> v 0.00:0.00
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buf3/Z -> q2 wire
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^ -> ^ 0.00:0.00
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v -> v 0.00:0.00
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buf4/Z -> q3 wire
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^ -> ^ 0.00:0.00
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v -> v 0.00:0.00
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--- slew queries ---
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d1 ^ 0.10:0.10 v 0.10:0.10
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d2 ^ 0.10:0.10 v 0.10:0.10
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d3 ^ 0.10:0.10 v 0.10:0.10
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d4 ^ 0.10:0.10 v 0.10:0.10
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clk1 ^ 0.10:0.10 v 0.10:0.10
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clk2 ^ 0.10:0.10 v 0.10:0.10
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q1 ^ 0.01:0.01 v 0.00:0.00
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q2 ^ 0.00:0.00 v 0.00:0.00
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q3 ^ 0.00:0.00 v 0.00:0.00
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buf1/Z ^ 0.01:0.01 v 0.01:0.01
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buf2/Z ^ 0.01:0.01 v 0.01:0.01
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inv1/ZN ^ 0.02:0.02 v 0.02:0.02
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inv2/ZN ^ 0.02:0.02 v 0.02:0.02
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and1/ZN ^ 0.01:0.01 v 0.01:0.01
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or1/ZN ^ 0.01:0.01 v 0.01:0.01
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nand1/ZN ^ 0.02:0.02 v 0.01:0.01
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nor1/ZN ^ 0.02:0.02 v 0.01:0.01
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and2/ZN ^ 0.01:0.01 v 0.00:0.00
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or2/ZN ^ 0.01:0.01 v 0.01:0.01
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reg1/Q ^ 0.01:0.01 v 0.01:0.01
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reg2/Q ^ 0.01:0.01 v 0.00:0.00
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reg3/Q ^ 0.01:0.01 v 0.01:0.01
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buf3/Z ^ 0.00:0.00 v 0.00:0.00
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buf4/Z ^ 0.00:0.00 v 0.00:0.00
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--- network modification ---
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Startpoint: d1 (input port clocked by clk1)
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Endpoint: q3 (output port clocked by clk1)
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Path Group: clk1
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk1 (rise edge)
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0.00 0.00 clock network delay (ideal)
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1.00 1.00 v input external delay
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0.00 1.00 v d1 (in)
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0.06 1.06 v buf1/Z (BUF_X1)
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0.03 1.09 v and1/ZN (AND2_X1)
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0.03 1.11 ^ nand1/ZN (NAND2_X1)
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0.02 1.13 ^ buf4/Z (BUF_X4)
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0.00 1.13 ^ q3 (out)
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1.13 data arrival time
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10.00 10.00 clock clk1 (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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-1.00 9.00 output external delay
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9.00 data required time
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---------------------------------------------------------
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9.00 data required time
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-1.13 data arrival time
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---------------------------------------------------------
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7.87 slack (MET)
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
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Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
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Path Group: clk2
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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10.00 10.00 clock clk1 (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 ^ reg1/CK (DFF_X1)
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0.08 10.08 v reg1/Q (DFF_X1)
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0.00 10.08 v reg3/D (DFF_X1)
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10.08 data arrival time
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15.00 15.00 clock clk2 (rise edge)
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0.00 15.00 clock network delay (ideal)
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0.00 15.00 clock reconvergence pessimism
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15.00 ^ reg3/CK (DFF_X1)
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-0.04 14.96 library setup time
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14.96 data required time
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---------------------------------------------------------
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14.96 data required time
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-10.08 data arrival time
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---------------------------------------------------------
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4.88 slack (MET)
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Startpoint: d1 (input port clocked by clk1)
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Endpoint: q3 (output port clocked by clk1)
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Path Group: clk1
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk1 (rise edge)
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0.00 0.00 clock network delay (ideal)
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1.00 1.00 v input external delay
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0.00 1.00 v d1 (in)
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0.06 1.06 v buf1/Z (BUF_X1)
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0.03 1.09 v and1/ZN (AND2_X1)
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0.03 1.11 ^ nand1/ZN (NAND2_X1)
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0.02 1.13 ^ buf4/Z (BUF_X4)
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0.00 1.13 ^ q3 (out)
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1.13 data arrival time
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10.00 10.00 clock clk1 (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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-1.00 9.00 output external delay
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9.00 data required time
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---------------------------------------------------------
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9.00 data required time
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-1.13 data arrival time
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---------------------------------------------------------
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7.87 slack (MET)
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
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Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
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Path Group: clk2
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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10.00 10.00 clock clk1 (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 ^ reg1/CK (DFF_X1)
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0.08 10.08 v reg1/Q (DFF_X1)
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0.00 10.08 v reg3/D (DFF_X1)
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10.08 data arrival time
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15.00 15.00 clock clk2 (rise edge)
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0.00 15.00 clock network delay (ideal)
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0.00 15.00 clock reconvergence pessimism
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15.00 ^ reg3/CK (DFF_X1)
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-0.04 14.96 library setup time
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14.96 data required time
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---------------------------------------------------------
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14.96 data required time
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-10.08 data arrival time
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---------------------------------------------------------
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4.88 slack (MET)
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--- replace cell ---
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Startpoint: d2 (input port clocked by clk1)
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Endpoint: q3 (output port clocked by clk1)
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Path Group: clk1
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk1 (rise edge)
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0.00 0.00 clock network delay (ideal)
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1.00 1.00 v input external delay
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0.00 1.00 v d2 (in)
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0.05 1.05 v buf2/Z (BUF_X2)
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0.03 1.08 v and1/ZN (AND2_X1)
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0.03 1.11 ^ nand1/ZN (NAND2_X1)
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0.02 1.13 ^ buf4/Z (BUF_X4)
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0.00 1.13 ^ q3 (out)
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1.13 data arrival time
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10.00 10.00 clock clk1 (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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-1.00 9.00 output external delay
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9.00 data required time
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---------------------------------------------------------
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9.00 data required time
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-1.13 data arrival time
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---------------------------------------------------------
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7.87 slack (MET)
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
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Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
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Path Group: clk2
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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10.00 10.00 clock clk1 (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 ^ reg1/CK (DFF_X1)
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0.08 10.08 v reg1/Q (DFF_X1)
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0.00 10.08 v reg3/D (DFF_X1)
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10.08 data arrival time
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15.00 15.00 clock clk2 (rise edge)
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0.00 15.00 clock network delay (ideal)
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0.00 15.00 clock reconvergence pessimism
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15.00 ^ reg3/CK (DFF_X1)
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-0.04 14.96 library setup time
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14.96 data required time
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---------------------------------------------------------
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14.96 data required time
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-10.08 data arrival time
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---------------------------------------------------------
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4.88 slack (MET)
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A -> Z combinational
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^ -> ^ 0.03:0.03
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v -> v 0.05:0.05
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Startpoint: d1 (input port clocked by clk1)
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Endpoint: q3 (output port clocked by clk1)
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Path Group: clk1
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk1 (rise edge)
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0.00 0.00 clock network delay (ideal)
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1.00 1.00 v input external delay
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0.00 1.00 v d1 (in)
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0.06 1.06 v buf1/Z (BUF_X1)
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0.03 1.09 v and1/ZN (AND2_X1)
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0.03 1.11 ^ nand1/ZN (NAND2_X1)
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0.02 1.13 ^ buf4/Z (BUF_X4)
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0.00 1.13 ^ q3 (out)
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1.13 data arrival time
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10.00 10.00 clock clk1 (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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-1.00 9.00 output external delay
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9.00 data required time
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---------------------------------------------------------
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9.00 data required time
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-1.13 data arrival time
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---------------------------------------------------------
|
|
7.87 slack (MET)
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
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Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
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Path Group: clk2
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Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
10.00 10.00 clock clk1 (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 ^ reg1/CK (DFF_X1)
|
|
0.08 10.08 v reg1/Q (DFF_X1)
|
|
0.00 10.08 v reg3/D (DFF_X1)
|
|
10.08 data arrival time
|
|
|
|
15.00 15.00 clock clk2 (rise edge)
|
|
0.00 15.00 clock network delay (ideal)
|
|
0.00 15.00 clock reconvergence pessimism
|
|
15.00 ^ reg3/CK (DFF_X1)
|
|
-0.04 14.96 library setup time
|
|
14.96 data required time
|
|
---------------------------------------------------------
|
|
14.96 data required time
|
|
-10.08 data arrival time
|
|
---------------------------------------------------------
|
|
4.88 slack (MET)
|
|
|
|
|
|
Startpoint: d1 (input port clocked by clk1)
|
|
Endpoint: q3 (output port clocked by clk1)
|
|
Path Group: clk1
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk1 (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
1.00 1.00 v input external delay
|
|
0.00 1.00 v d1 (in)
|
|
0.06 1.06 v buf1/Z (BUF_X1)
|
|
0.03 1.09 v and1/ZN (AND2_X1)
|
|
0.03 1.11 ^ nand1/ZN (NAND2_X1)
|
|
0.02 1.13 ^ buf4/Z (BUF_X4)
|
|
0.00 1.13 ^ q3 (out)
|
|
1.13 data arrival time
|
|
|
|
10.00 10.00 clock clk1 (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 clock reconvergence pessimism
|
|
-1.00 9.00 output external delay
|
|
9.00 data required time
|
|
---------------------------------------------------------
|
|
9.00 data required time
|
|
-1.13 data arrival time
|
|
---------------------------------------------------------
|
|
7.87 slack (MET)
|
|
|
|
|
|
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
|
|
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
|
|
Path Group: clk2
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
10.00 10.00 clock clk1 (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 ^ reg1/CK (DFF_X1)
|
|
0.08 10.08 v reg1/Q (DFF_X1)
|
|
0.00 10.08 v reg3/D (DFF_X1)
|
|
10.08 data arrival time
|
|
|
|
15.00 15.00 clock clk2 (rise edge)
|
|
0.00 15.00 clock network delay (ideal)
|
|
0.00 15.00 clock reconvergence pessimism
|
|
15.00 ^ reg3/CK (DFF_X1)
|
|
-0.04 14.96 library setup time
|
|
14.96 data required time
|
|
---------------------------------------------------------
|
|
14.96 data required time
|
|
-10.08 data arrival time
|
|
---------------------------------------------------------
|
|
4.88 slack (MET)
|
|
|
|
|
|
Startpoint: d1 (input port clocked by clk1)
|
|
Endpoint: q3 (output port clocked by clk1)
|
|
Path Group: clk1
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk1 (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
1.00 1.00 v input external delay
|
|
0.00 1.00 v d1 (in)
|
|
0.06 1.06 v buf1/Z (BUF_X1)
|
|
0.03 1.09 v and1/ZN (AND2_X1)
|
|
0.03 1.11 ^ nand1/ZN (NAND2_X1)
|
|
0.02 1.13 ^ buf4/Z (BUF_X4)
|
|
0.00 1.13 ^ q3 (out)
|
|
1.13 data arrival time
|
|
|
|
10.00 10.00 clock clk1 (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 clock reconvergence pessimism
|
|
-1.00 9.00 output external delay
|
|
9.00 data required time
|
|
---------------------------------------------------------
|
|
9.00 data required time
|
|
-1.13 data arrival time
|
|
---------------------------------------------------------
|
|
7.87 slack (MET)
|
|
|
|
|
|
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
|
|
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
|
|
Path Group: clk2
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
10.00 10.00 clock clk1 (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 ^ reg1/CK (DFF_X1)
|
|
0.08 10.08 v reg1/Q (DFF_X1)
|
|
0.00 10.08 v reg3/D (DFF_X1)
|
|
10.08 data arrival time
|
|
|
|
15.00 15.00 clock clk2 (rise edge)
|
|
0.00 15.00 clock network delay (ideal)
|
|
0.00 15.00 clock reconvergence pessimism
|
|
15.00 ^ reg3/CK (DFF_X1)
|
|
-0.04 14.96 library setup time
|
|
14.96 data required time
|
|
---------------------------------------------------------
|
|
14.96 data required time
|
|
-10.08 data arrival time
|
|
---------------------------------------------------------
|
|
4.88 slack (MET)
|
|
|
|
|
|
--- disable/enable timing ---
|
|
Startpoint: d2 (input port clocked by clk1)
|
|
Endpoint: q3 (output port clocked by clk1)
|
|
Path Group: clk1
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk1 (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
1.00 1.00 v input external delay
|
|
0.00 1.00 v d2 (in)
|
|
0.05 1.05 v buf2/Z (BUF_X2)
|
|
0.03 1.08 v and1/ZN (AND2_X1)
|
|
0.03 1.11 ^ nand1/ZN (NAND2_X1)
|
|
0.02 1.13 ^ buf4/Z (BUF_X4)
|
|
0.00 1.13 ^ q3 (out)
|
|
1.13 data arrival time
|
|
|
|
10.00 10.00 clock clk1 (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 clock reconvergence pessimism
|
|
-1.00 9.00 output external delay
|
|
9.00 data required time
|
|
---------------------------------------------------------
|
|
9.00 data required time
|
|
-1.13 data arrival time
|
|
---------------------------------------------------------
|
|
7.87 slack (MET)
|
|
|
|
|
|
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
|
|
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
|
|
Path Group: clk2
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
10.00 10.00 clock clk1 (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 ^ reg1/CK (DFF_X1)
|
|
0.08 10.08 v reg1/Q (DFF_X1)
|
|
0.00 10.08 v reg3/D (DFF_X1)
|
|
10.08 data arrival time
|
|
|
|
15.00 15.00 clock clk2 (rise edge)
|
|
0.00 15.00 clock network delay (ideal)
|
|
0.00 15.00 clock reconvergence pessimism
|
|
15.00 ^ reg3/CK (DFF_X1)
|
|
-0.04 14.96 library setup time
|
|
14.96 data required time
|
|
---------------------------------------------------------
|
|
14.96 data required time
|
|
-10.08 data arrival time
|
|
---------------------------------------------------------
|
|
4.88 slack (MET)
|
|
|
|
|
|
Startpoint: d2 (input port clocked by clk1)
|
|
Endpoint: q3 (output port clocked by clk1)
|
|
Path Group: clk1
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk1 (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
1.00 1.00 v input external delay
|
|
0.00 1.00 v d2 (in)
|
|
0.05 1.05 v buf2/Z (BUF_X2)
|
|
0.03 1.08 v and1/ZN (AND2_X1)
|
|
0.03 1.11 ^ nand1/ZN (NAND2_X1)
|
|
0.02 1.13 ^ buf4/Z (BUF_X4)
|
|
0.00 1.13 ^ q3 (out)
|
|
1.13 data arrival time
|
|
|
|
10.00 10.00 clock clk1 (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 clock reconvergence pessimism
|
|
-1.00 9.00 output external delay
|
|
9.00 data required time
|
|
---------------------------------------------------------
|
|
9.00 data required time
|
|
-1.13 data arrival time
|
|
---------------------------------------------------------
|
|
7.87 slack (MET)
|
|
|
|
|
|
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
|
|
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
|
|
Path Group: clk2
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
10.00 10.00 clock clk1 (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 ^ reg1/CK (DFF_X1)
|
|
0.08 10.08 v reg1/Q (DFF_X1)
|
|
0.00 10.08 v reg3/D (DFF_X1)
|
|
10.08 data arrival time
|
|
|
|
15.00 15.00 clock clk2 (rise edge)
|
|
0.00 15.00 clock network delay (ideal)
|
|
0.00 15.00 clock reconvergence pessimism
|
|
15.00 ^ reg3/CK (DFF_X1)
|
|
-0.04 14.96 library setup time
|
|
14.96 data required time
|
|
---------------------------------------------------------
|
|
14.96 data required time
|
|
-10.08 data arrival time
|
|
---------------------------------------------------------
|
|
4.88 slack (MET)
|
|
|
|
|
|
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
|
|
Endpoint: q1 (output port clocked by clk1)
|
|
Path Group: clk1
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk1 (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
0.00 0.00 ^ reg2/CK (DFF_X1)
|
|
0.08 0.08 ^ reg2/Q (DFF_X1)
|
|
0.00 0.08 ^ q1 (out)
|
|
0.08 data arrival time
|
|
|
|
10.00 10.00 clock clk1 (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 clock reconvergence pessimism
|
|
-1.00 9.00 output external delay
|
|
9.00 data required time
|
|
---------------------------------------------------------
|
|
9.00 data required time
|
|
-0.08 data arrival time
|
|
---------------------------------------------------------
|
|
8.92 slack (MET)
|
|
|
|
|
|
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
|
|
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
|
|
Path Group: clk2
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
10.00 10.00 clock clk1 (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 ^ reg1/CK (DFF_X1)
|
|
0.08 10.08 v reg1/Q (DFF_X1)
|
|
0.00 10.08 v reg3/D (DFF_X1)
|
|
10.08 data arrival time
|
|
|
|
15.00 15.00 clock clk2 (rise edge)
|
|
0.00 15.00 clock network delay (ideal)
|
|
0.00 15.00 clock reconvergence pessimism
|
|
15.00 ^ reg3/CK (DFF_X1)
|
|
-0.04 14.96 library setup time
|
|
14.96 data required time
|
|
---------------------------------------------------------
|
|
14.96 data required time
|
|
-10.08 data arrival time
|
|
---------------------------------------------------------
|
|
4.88 slack (MET)
|
|
|
|
|
|
Startpoint: d1 (input port clocked by clk1)
|
|
Endpoint: q3 (output port clocked by clk1)
|
|
Path Group: clk1
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk1 (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
1.00 1.00 v input external delay
|
|
0.00 1.00 v d1 (in)
|
|
0.06 1.06 v buf1/Z (BUF_X1)
|
|
0.03 1.09 v and1/ZN (AND2_X1)
|
|
0.03 1.11 ^ nand1/ZN (NAND2_X1)
|
|
0.02 1.13 ^ buf4/Z (BUF_X4)
|
|
0.00 1.13 ^ q3 (out)
|
|
1.13 data arrival time
|
|
|
|
10.00 10.00 clock clk1 (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 clock reconvergence pessimism
|
|
-1.00 9.00 output external delay
|
|
9.00 data required time
|
|
---------------------------------------------------------
|
|
9.00 data required time
|
|
-1.13 data arrival time
|
|
---------------------------------------------------------
|
|
7.87 slack (MET)
|
|
|
|
|
|
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
|
|
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
|
|
Path Group: clk2
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
10.00 10.00 clock clk1 (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 ^ reg1/CK (DFF_X1)
|
|
0.08 10.08 v reg1/Q (DFF_X1)
|
|
0.00 10.08 v reg3/D (DFF_X1)
|
|
10.08 data arrival time
|
|
|
|
15.00 15.00 clock clk2 (rise edge)
|
|
0.00 15.00 clock network delay (ideal)
|
|
0.00 15.00 clock reconvergence pessimism
|
|
15.00 ^ reg3/CK (DFF_X1)
|
|
-0.04 14.96 library setup time
|
|
14.96 data required time
|
|
---------------------------------------------------------
|
|
14.96 data required time
|
|
-10.08 data arrival time
|
|
---------------------------------------------------------
|
|
4.88 slack (MET)
|
|
|
|
|
|
--- case analysis ---
|
|
Startpoint: d1 (input port clocked by clk1)
|
|
Endpoint: q3 (output port clocked by clk1)
|
|
Path Group: clk1
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk1 (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
1.00 1.00 v input external delay
|
|
0.00 1.00 v d1 (in)
|
|
0.06 1.06 v buf1/Z (BUF_X1)
|
|
0.03 1.09 v and1/ZN (AND2_X1)
|
|
0.03 1.11 ^ nand1/ZN (NAND2_X1)
|
|
0.02 1.13 ^ buf4/Z (BUF_X4)
|
|
0.00 1.13 ^ q3 (out)
|
|
1.13 data arrival time
|
|
|
|
10.00 10.00 clock clk1 (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 clock reconvergence pessimism
|
|
-1.00 9.00 output external delay
|
|
9.00 data required time
|
|
---------------------------------------------------------
|
|
9.00 data required time
|
|
-1.13 data arrival time
|
|
---------------------------------------------------------
|
|
7.87 slack (MET)
|
|
|
|
|
|
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
|
|
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
|
|
Path Group: clk2
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
10.00 10.00 clock clk1 (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 ^ reg1/CK (DFF_X1)
|
|
0.08 10.08 v reg1/Q (DFF_X1)
|
|
0.00 10.08 v reg3/D (DFF_X1)
|
|
10.08 data arrival time
|
|
|
|
15.00 15.00 clock clk2 (rise edge)
|
|
0.00 15.00 clock network delay (ideal)
|
|
0.00 15.00 clock reconvergence pessimism
|
|
15.00 ^ reg3/CK (DFF_X1)
|
|
-0.04 14.96 library setup time
|
|
14.96 data required time
|
|
---------------------------------------------------------
|
|
14.96 data required time
|
|
-10.08 data arrival time
|
|
---------------------------------------------------------
|
|
4.88 slack (MET)
|
|
|
|
|
|
Startpoint: d1 (input port clocked by clk1)
|
|
Endpoint: q3 (output port clocked by clk1)
|
|
Path Group: clk1
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk1 (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
1.00 1.00 v input external delay
|
|
0.00 1.00 v d1 (in)
|
|
0.06 1.06 v buf1/Z (BUF_X1)
|
|
0.03 1.09 v and1/ZN (AND2_X1)
|
|
0.03 1.11 ^ nand1/ZN (NAND2_X1)
|
|
0.02 1.13 ^ buf4/Z (BUF_X4)
|
|
0.00 1.13 ^ q3 (out)
|
|
1.13 data arrival time
|
|
|
|
10.00 10.00 clock clk1 (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 clock reconvergence pessimism
|
|
-1.00 9.00 output external delay
|
|
9.00 data required time
|
|
---------------------------------------------------------
|
|
9.00 data required time
|
|
-1.13 data arrival time
|
|
---------------------------------------------------------
|
|
7.87 slack (MET)
|
|
|
|
|
|
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
|
|
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
|
|
Path Group: clk2
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
10.00 10.00 clock clk1 (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 ^ reg1/CK (DFF_X1)
|
|
0.08 10.08 v reg1/Q (DFF_X1)
|
|
0.00 10.08 v reg3/D (DFF_X1)
|
|
10.08 data arrival time
|
|
|
|
15.00 15.00 clock clk2 (rise edge)
|
|
0.00 15.00 clock network delay (ideal)
|
|
0.00 15.00 clock reconvergence pessimism
|
|
15.00 ^ reg3/CK (DFF_X1)
|
|
-0.04 14.96 library setup time
|
|
14.96 data required time
|
|
---------------------------------------------------------
|
|
14.96 data required time
|
|
-10.08 data arrival time
|
|
---------------------------------------------------------
|
|
4.88 slack (MET)
|
|
|
|
|
|
Startpoint: d1 (input port clocked by clk1)
|
|
Endpoint: q3 (output port clocked by clk1)
|
|
Path Group: clk1
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk1 (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
1.00 1.00 v input external delay
|
|
0.00 1.00 v d1 (in)
|
|
0.06 1.06 v buf1/Z (BUF_X1)
|
|
0.03 1.09 v and1/ZN (AND2_X1)
|
|
0.03 1.11 ^ nand1/ZN (NAND2_X1)
|
|
0.02 1.13 ^ buf4/Z (BUF_X4)
|
|
0.00 1.13 ^ q3 (out)
|
|
1.13 data arrival time
|
|
|
|
10.00 10.00 clock clk1 (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 clock reconvergence pessimism
|
|
-1.00 9.00 output external delay
|
|
9.00 data required time
|
|
---------------------------------------------------------
|
|
9.00 data required time
|
|
-1.13 data arrival time
|
|
---------------------------------------------------------
|
|
7.87 slack (MET)
|
|
|
|
|
|
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
|
|
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
|
|
Path Group: clk2
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
10.00 10.00 clock clk1 (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 ^ reg1/CK (DFF_X1)
|
|
0.08 10.08 v reg1/Q (DFF_X1)
|
|
0.00 10.08 v reg3/D (DFF_X1)
|
|
10.08 data arrival time
|
|
|
|
15.00 15.00 clock clk2 (rise edge)
|
|
0.00 15.00 clock network delay (ideal)
|
|
0.00 15.00 clock reconvergence pessimism
|
|
15.00 ^ reg3/CK (DFF_X1)
|
|
-0.04 14.96 library setup time
|
|
14.96 data required time
|
|
---------------------------------------------------------
|
|
14.96 data required time
|
|
-10.08 data arrival time
|
|
---------------------------------------------------------
|
|
4.88 slack (MET)
|
|
|
|
|
|
Startpoint: d2 (input port clocked by clk1)
|
|
Endpoint: q3 (output port clocked by clk1)
|
|
Path Group: clk1
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk1 (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
1.00 1.00 v input external delay
|
|
0.00 1.00 v d2 (in)
|
|
0.05 1.05 v buf2/Z (BUF_X2)
|
|
0.03 1.08 v and1/ZN (AND2_X1)
|
|
0.03 1.11 ^ nand1/ZN (NAND2_X1)
|
|
0.02 1.13 ^ buf4/Z (BUF_X4)
|
|
0.00 1.13 ^ q3 (out)
|
|
1.13 data arrival time
|
|
|
|
10.00 10.00 clock clk1 (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 clock reconvergence pessimism
|
|
-1.00 9.00 output external delay
|
|
9.00 data required time
|
|
---------------------------------------------------------
|
|
9.00 data required time
|
|
-1.13 data arrival time
|
|
---------------------------------------------------------
|
|
7.87 slack (MET)
|
|
|
|
|
|
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
|
|
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
|
|
Path Group: clk2
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
10.00 10.00 clock clk1 (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 ^ reg1/CK (DFF_X1)
|
|
0.08 10.08 v reg1/Q (DFF_X1)
|
|
0.00 10.08 v reg3/D (DFF_X1)
|
|
10.08 data arrival time
|
|
|
|
15.00 15.00 clock clk2 (rise edge)
|
|
0.00 15.00 clock network delay (ideal)
|
|
0.00 15.00 clock reconvergence pessimism
|
|
15.00 ^ reg3/CK (DFF_X1)
|
|
-0.04 14.96 library setup time
|
|
14.96 data required time
|
|
---------------------------------------------------------
|
|
14.96 data required time
|
|
-10.08 data arrival time
|
|
---------------------------------------------------------
|
|
4.88 slack (MET)
|
|
|
|
|
|
Startpoint: d2 (input port clocked by clk1)
|
|
Endpoint: q3 (output port clocked by clk1)
|
|
Path Group: clk1
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk1 (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
1.00 1.00 v input external delay
|
|
0.00 1.00 v d2 (in)
|
|
0.05 1.05 v buf2/Z (BUF_X2)
|
|
0.03 1.08 v and1/ZN (AND2_X1)
|
|
0.03 1.11 ^ nand1/ZN (NAND2_X1)
|
|
0.02 1.13 ^ buf4/Z (BUF_X4)
|
|
0.00 1.13 ^ q3 (out)
|
|
1.13 data arrival time
|
|
|
|
10.00 10.00 clock clk1 (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 clock reconvergence pessimism
|
|
-1.00 9.00 output external delay
|
|
9.00 data required time
|
|
---------------------------------------------------------
|
|
9.00 data required time
|
|
-1.13 data arrival time
|
|
---------------------------------------------------------
|
|
7.87 slack (MET)
|
|
|
|
|
|
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
|
|
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
|
|
Path Group: clk2
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
10.00 10.00 clock clk1 (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 ^ reg1/CK (DFF_X1)
|
|
0.08 10.08 v reg1/Q (DFF_X1)
|
|
0.00 10.08 v reg3/D (DFF_X1)
|
|
10.08 data arrival time
|
|
|
|
15.00 15.00 clock clk2 (rise edge)
|
|
0.00 15.00 clock network delay (ideal)
|
|
0.00 15.00 clock reconvergence pessimism
|
|
15.00 ^ reg3/CK (DFF_X1)
|
|
-0.04 14.96 library setup time
|
|
14.96 data required time
|
|
---------------------------------------------------------
|
|
14.96 data required time
|
|
-10.08 data arrival time
|
|
---------------------------------------------------------
|
|
4.88 slack (MET)
|
|
|
|
|
|
Startpoint: d1 (input port clocked by clk1)
|
|
Endpoint: q3 (output port clocked by clk1)
|
|
Path Group: clk1
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk1 (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
1.00 1.00 v input external delay
|
|
0.00 1.00 v d1 (in)
|
|
0.06 1.06 v buf1/Z (BUF_X1)
|
|
0.03 1.09 v and1/ZN (AND2_X1)
|
|
0.03 1.11 ^ nand1/ZN (NAND2_X1)
|
|
0.02 1.13 ^ buf4/Z (BUF_X4)
|
|
0.00 1.13 ^ q3 (out)
|
|
1.13 data arrival time
|
|
|
|
10.00 10.00 clock clk1 (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 clock reconvergence pessimism
|
|
-1.00 9.00 output external delay
|
|
9.00 data required time
|
|
---------------------------------------------------------
|
|
9.00 data required time
|
|
-1.13 data arrival time
|
|
---------------------------------------------------------
|
|
7.87 slack (MET)
|
|
|
|
|
|
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
|
|
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
|
|
Path Group: clk2
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
10.00 10.00 clock clk1 (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 ^ reg1/CK (DFF_X1)
|
|
0.08 10.08 v reg1/Q (DFF_X1)
|
|
0.00 10.08 v reg3/D (DFF_X1)
|
|
10.08 data arrival time
|
|
|
|
15.00 15.00 clock clk2 (rise edge)
|
|
0.00 15.00 clock network delay (ideal)
|
|
0.00 15.00 clock reconvergence pessimism
|
|
15.00 ^ reg3/CK (DFF_X1)
|
|
-0.04 14.96 library setup time
|
|
14.96 data required time
|
|
---------------------------------------------------------
|
|
14.96 data required time
|
|
-10.08 data arrival time
|
|
---------------------------------------------------------
|
|
4.88 slack (MET)
|
|
|
|
|
|
--- load changes ---
|
|
Startpoint: d1 (input port clocked by clk1)
|
|
Endpoint: q3 (output port clocked by clk1)
|
|
Path Group: clk1
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk1 (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
1.00 1.00 v input external delay
|
|
0.00 1.00 v d1 (in)
|
|
0.06 1.06 v buf1/Z (BUF_X1)
|
|
0.03 1.09 v and1/ZN (AND2_X1)
|
|
0.03 1.11 ^ nand1/ZN (NAND2_X1)
|
|
0.02 1.13 ^ buf4/Z (BUF_X4)
|
|
0.00 1.13 ^ q3 (out)
|
|
1.13 data arrival time
|
|
|
|
10.00 10.00 clock clk1 (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 clock reconvergence pessimism
|
|
-1.00 9.00 output external delay
|
|
9.00 data required time
|
|
---------------------------------------------------------
|
|
9.00 data required time
|
|
-1.13 data arrival time
|
|
---------------------------------------------------------
|
|
7.87 slack (MET)
|
|
|
|
|
|
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
|
|
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
|
|
Path Group: clk2
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
10.00 10.00 clock clk1 (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 ^ reg1/CK (DFF_X1)
|
|
0.08 10.08 v reg1/Q (DFF_X1)
|
|
0.00 10.08 v reg3/D (DFF_X1)
|
|
10.08 data arrival time
|
|
|
|
15.00 15.00 clock clk2 (rise edge)
|
|
0.00 15.00 clock network delay (ideal)
|
|
0.00 15.00 clock reconvergence pessimism
|
|
15.00 ^ reg3/CK (DFF_X1)
|
|
-0.04 14.96 library setup time
|
|
14.96 data required time
|
|
---------------------------------------------------------
|
|
14.96 data required time
|
|
-10.08 data arrival time
|
|
---------------------------------------------------------
|
|
4.88 slack (MET)
|
|
|
|
|
|
Startpoint: d1 (input port clocked by clk1)
|
|
Endpoint: q3 (output port clocked by clk1)
|
|
Path Group: clk1
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk1 (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
1.00 1.00 v input external delay
|
|
0.00 1.00 v d1 (in)
|
|
0.06 1.06 v buf1/Z (BUF_X1)
|
|
0.03 1.09 v and1/ZN (AND2_X1)
|
|
0.03 1.11 ^ nand1/ZN (NAND2_X1)
|
|
0.02 1.13 ^ buf4/Z (BUF_X4)
|
|
0.00 1.13 ^ q3 (out)
|
|
1.13 data arrival time
|
|
|
|
10.00 10.00 clock clk1 (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 clock reconvergence pessimism
|
|
-1.00 9.00 output external delay
|
|
9.00 data required time
|
|
---------------------------------------------------------
|
|
9.00 data required time
|
|
-1.13 data arrival time
|
|
---------------------------------------------------------
|
|
7.87 slack (MET)
|
|
|
|
|
|
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
|
|
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
|
|
Path Group: clk2
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
10.00 10.00 clock clk1 (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 ^ reg1/CK (DFF_X1)
|
|
0.08 10.08 v reg1/Q (DFF_X1)
|
|
0.00 10.08 v reg3/D (DFF_X1)
|
|
10.08 data arrival time
|
|
|
|
15.00 15.00 clock clk2 (rise edge)
|
|
0.00 15.00 clock network delay (ideal)
|
|
0.00 15.00 clock reconvergence pessimism
|
|
15.00 ^ reg3/CK (DFF_X1)
|
|
-0.04 14.96 library setup time
|
|
14.96 data required time
|
|
---------------------------------------------------------
|
|
14.96 data required time
|
|
-10.08 data arrival time
|
|
---------------------------------------------------------
|
|
4.88 slack (MET)
|
|
|
|
|
|
Startpoint: d1 (input port clocked by clk1)
|
|
Endpoint: q3 (output port clocked by clk1)
|
|
Path Group: clk1
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk1 (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
1.00 1.00 v input external delay
|
|
0.00 1.00 v d1 (in)
|
|
0.06 1.06 v buf1/Z (BUF_X1)
|
|
0.03 1.09 v and1/ZN (AND2_X1)
|
|
0.03 1.11 ^ nand1/ZN (NAND2_X1)
|
|
0.02 1.13 ^ buf4/Z (BUF_X4)
|
|
0.00 1.13 ^ q3 (out)
|
|
1.13 data arrival time
|
|
|
|
10.00 10.00 clock clk1 (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 clock reconvergence pessimism
|
|
-1.00 9.00 output external delay
|
|
9.00 data required time
|
|
---------------------------------------------------------
|
|
9.00 data required time
|
|
-1.13 data arrival time
|
|
---------------------------------------------------------
|
|
7.87 slack (MET)
|
|
|
|
|
|
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
|
|
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
|
|
Path Group: clk2
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
10.00 10.00 clock clk1 (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 ^ reg1/CK (DFF_X1)
|
|
0.08 10.08 v reg1/Q (DFF_X1)
|
|
0.00 10.08 v reg3/D (DFF_X1)
|
|
10.08 data arrival time
|
|
|
|
15.00 15.00 clock clk2 (rise edge)
|
|
0.00 15.00 clock network delay (ideal)
|
|
0.00 15.00 clock reconvergence pessimism
|
|
15.00 ^ reg3/CK (DFF_X1)
|
|
-0.04 14.96 library setup time
|
|
14.96 data required time
|
|
---------------------------------------------------------
|
|
14.96 data required time
|
|
-10.08 data arrival time
|
|
---------------------------------------------------------
|
|
4.88 slack (MET)
|
|
|
|
|
|
--- through pin queries ---
|
|
Startpoint: d1 (input port clocked by clk1)
|
|
Endpoint: q3 (output port clocked by clk1)
|
|
Path Group: clk1
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk1 (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
1.00 1.00 v input external delay
|
|
0.00 1.00 v d1 (in)
|
|
0.06 1.06 v buf1/Z (BUF_X1)
|
|
0.03 1.09 v and1/ZN (AND2_X1)
|
|
0.03 1.11 ^ nand1/ZN (NAND2_X1)
|
|
0.02 1.13 ^ buf4/Z (BUF_X4)
|
|
0.00 1.13 ^ q3 (out)
|
|
1.13 data arrival time
|
|
|
|
10.00 10.00 clock clk1 (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 clock reconvergence pessimism
|
|
-1.00 9.00 output external delay
|
|
9.00 data required time
|
|
---------------------------------------------------------
|
|
9.00 data required time
|
|
-1.13 data arrival time
|
|
---------------------------------------------------------
|
|
7.87 slack (MET)
|
|
|
|
|
|
through nand1: done
|
|
Startpoint: d1 (input port clocked by clk1)
|
|
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
|
|
Path Group: clk1
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk1 (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
1.00 1.00 v input external delay
|
|
0.00 1.00 v d1 (in)
|
|
0.06 1.06 v buf1/Z (BUF_X1)
|
|
0.03 1.09 ^ nor1/ZN (NOR2_X1)
|
|
0.03 1.12 ^ and2/ZN (AND2_X2)
|
|
0.00 1.12 ^ reg1/D (DFF_X1)
|
|
1.12 data arrival time
|
|
|
|
10.00 10.00 clock clk1 (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 clock reconvergence pessimism
|
|
10.00 ^ reg1/CK (DFF_X1)
|
|
-0.03 9.97 library setup time
|
|
9.97 data required time
|
|
---------------------------------------------------------
|
|
9.97 data required time
|
|
-1.12 data arrival time
|
|
---------------------------------------------------------
|
|
8.85 slack (MET)
|
|
|
|
|
|
through nor1: done
|
|
Startpoint: d1 (input port clocked by clk1)
|
|
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
|
|
Path Group: clk1
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk1 (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
1.00 1.00 v input external delay
|
|
0.00 1.00 v d1 (in)
|
|
0.06 1.06 v buf1/Z (BUF_X1)
|
|
0.03 1.09 v and1/ZN (AND2_X1)
|
|
0.03 1.11 ^ nand1/ZN (NAND2_X1)
|
|
0.03 1.14 ^ and2/ZN (AND2_X2)
|
|
0.00 1.14 ^ reg1/D (DFF_X1)
|
|
1.14 data arrival time
|
|
|
|
10.00 10.00 clock clk1 (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 clock reconvergence pessimism
|
|
10.00 ^ reg1/CK (DFF_X1)
|
|
-0.03 9.97 library setup time
|
|
9.97 data required time
|
|
---------------------------------------------------------
|
|
9.97 data required time
|
|
-1.14 data arrival time
|
|
---------------------------------------------------------
|
|
8.82 slack (MET)
|
|
|
|
|
|
through and2: done
|
|
Startpoint: d3 (input port clocked by clk1)
|
|
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
|
|
Path Group: clk1
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk1 (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
1.00 1.00 v input external delay
|
|
0.00 1.00 v d3 (in)
|
|
0.04 1.04 ^ inv1/ZN (INV_X1)
|
|
0.03 1.07 ^ or1/ZN (OR2_X1)
|
|
0.02 1.09 v nand1/ZN (NAND2_X1)
|
|
0.04 1.13 v or2/ZN (OR2_X2)
|
|
0.00 1.13 v reg2/D (DFF_X1)
|
|
1.13 data arrival time
|
|
|
|
10.00 10.00 clock clk1 (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 clock reconvergence pessimism
|
|
10.00 ^ reg2/CK (DFF_X1)
|
|
-0.04 9.96 library setup time
|
|
9.96 data required time
|
|
---------------------------------------------------------
|
|
9.96 data required time
|
|
-1.13 data arrival time
|
|
---------------------------------------------------------
|
|
8.83 slack (MET)
|
|
|
|
|
|
through or2: done
|
|
--- report_check_types ---
|
|
Startpoint: d1 (input port clocked by clk1)
|
|
Endpoint: q3 (output port clocked by clk1)
|
|
Path Group: clk1
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk1 (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
1.00 1.00 v input external delay
|
|
0.00 1.00 v d1 (in)
|
|
0.06 1.06 v buf1/Z (BUF_X1)
|
|
0.03 1.09 v and1/ZN (AND2_X1)
|
|
0.03 1.11 ^ nand1/ZN (NAND2_X1)
|
|
0.02 1.13 ^ buf4/Z (BUF_X4)
|
|
0.00 1.13 ^ q3 (out)
|
|
1.13 data arrival time
|
|
|
|
10.00 10.00 clock clk1 (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 clock reconvergence pessimism
|
|
-1.00 9.00 output external delay
|
|
9.00 data required time
|
|
---------------------------------------------------------
|
|
9.00 data required time
|
|
-1.13 data arrival time
|
|
---------------------------------------------------------
|
|
7.87 slack (MET)
|
|
|
|
|
|
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
|
|
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
|
|
Path Group: clk2
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
10.00 10.00 clock clk1 (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 ^ reg1/CK (DFF_X1)
|
|
0.08 10.08 v reg1/Q (DFF_X1)
|
|
0.00 10.08 v reg3/D (DFF_X1)
|
|
10.08 data arrival time
|
|
|
|
15.00 15.00 clock clk2 (rise edge)
|
|
0.00 15.00 clock network delay (ideal)
|
|
0.00 15.00 clock reconvergence pessimism
|
|
15.00 ^ reg3/CK (DFF_X1)
|
|
-0.04 14.96 library setup time
|
|
14.96 data required time
|
|
---------------------------------------------------------
|
|
14.96 data required time
|
|
-10.08 data arrival time
|
|
---------------------------------------------------------
|
|
4.88 slack (MET)
|
|
|
|
|
|
Startpoint: d1 (input port clocked by clk1)
|
|
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
|
|
Path Group: clk1
|
|
Path Type: min
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk1 (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
1.00 1.00 ^ input external delay
|
|
0.00 1.00 ^ d1 (in)
|
|
0.04 1.04 ^ buf1/Z (BUF_X1)
|
|
0.01 1.05 v nor1/ZN (NOR2_X1)
|
|
0.03 1.07 v and2/ZN (AND2_X2)
|
|
0.00 1.07 v reg1/D (DFF_X1)
|
|
1.07 data arrival time
|
|
|
|
0.00 0.00 clock clk1 (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
0.00 0.00 clock reconvergence pessimism
|
|
0.00 ^ reg1/CK (DFF_X1)
|
|
0.00 0.00 library hold time
|
|
0.00 data required time
|
|
---------------------------------------------------------
|
|
0.00 data required time
|
|
-1.07 data arrival time
|
|
---------------------------------------------------------
|
|
1.07 slack (MET)
|
|
|
|
|
|
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
|
|
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
|
|
Path Group: clk2
|
|
Path Type: min
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk1 (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
0.00 0.00 ^ reg1/CK (DFF_X1)
|
|
0.08 0.08 v reg1/Q (DFF_X1)
|
|
0.00 0.08 v reg3/D (DFF_X1)
|
|
0.08 data arrival time
|
|
|
|
0.00 0.00 clock clk2 (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
0.00 0.00 clock reconvergence pessimism
|
|
0.00 ^ reg3/CK (DFF_X1)
|
|
0.00 0.00 library hold time
|
|
0.00 data required time
|
|
---------------------------------------------------------
|
|
0.00 data required time
|
|
-0.08 data arrival time
|
|
---------------------------------------------------------
|
|
0.08 slack (MET)
|
|
|
|
|