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Merge branch 'master' of github.com:openroadie/OpenSTA-JC

This commit is contained in:
Harsh Vardhan 2023-09-05 21:47:03 -07:00
parent 7cf916ba20 451831edd7
commit 2969b1eeb0
16 changed files with 445 additions and 452 deletions
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22
README.md
View File

@ -56,11 +56,23 @@ OpenSTA is dual licensed. It is released under GPL v3 as OpenSTA and
is also licensed for commerical applications by Parallax Software without
the GPL's requirements.
OpenSTA is open source, meaning the sources are published and can be compiled locally.
Derivative works are supported as long as they adhere to the GPL license requirements.
However, OpenSTA is not supported by a public community of developers as many other
open source projects are. The copyright and develpment are exclusive to Parallax
Software. OpenSTA does not accept external code contributions.
OpenSTA is open source, meaning the sources are published and can be
compiled locally. Derivative works are supported as long as they
adhere to the GPL license requirements. However, OpenSTA is not
supported by a public community of developers as many other open
source projects are. The copyright and develpment are exclusive to
Parallax Software. OpenSTA does not solicit or accept external code
contributions.
Removing copyright and license notices from OpenSTA sources (or any
other open source project for that matter) is illegal. This should be
obvious, but the author of OpenSTA has discovered two different cases
where the copyright and license were removed from source files that
were copied. The Chinese iEDA project from the Peng Cheng Laboratory
of the Institute of Computing Technology, Chinese Academy of Sciences
is one example. The iEDA project copied multiple OpenSTA files and
removed both the license and copyright notices, replacing them with
their own copyright and license.
The official git repository is located at
https://github.com/parallaxsw/OpenSTA.git. Any forks from this code

3
doc/ChangeLog.txt
View File

@ -21,6 +21,9 @@ The read_liberty command latch inference (see OpenSTA.pdf) is now disabled by de
The -no_latch_infer flag is deprecated.
To enable latch inference, use the -infer_latches flag.
The report fanout and capacitance fields are now shown on output pin lines rather
than net lines.
Release 2.3.3 2022/09/24
-------------------------

BIN
doc/OpenSTA.odt
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Binary file not shown.

3
include/sta/Sta.hh
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@ -889,7 +889,8 @@ public:
void setReportPathFields(bool report_input_pin,
bool report_net,
bool report_cap,
bool report_slew);
bool report_slew,
bool report_fanout);
ReportField *findReportPathField(const char *name);
void setReportPathDigits(int digits);
void setReportPathNoSplit(bool no_split);

93
liberty/LibertyBuilder.cc
View File

@ -27,6 +27,14 @@
namespace sta {
void
LibertyBuilder::init(Debug *debug,
Report *report)
{
debug_ = debug;
report_ = report;
}
LibertyCell *
LibertyBuilder::makeCell(LibertyLibrary *library,
const char *name,
@ -127,17 +135,55 @@ LibertyBuilder::makeTimingArcs(LibertyCell *cell,
LibertyPort *from_port,
LibertyPort *to_port,
LibertyPort *related_out,
TimingArcAttrsPtr attrs)
TimingArcAttrsPtr attrs,
int /* line */)
{
FuncExpr *to_func;
Sequential *seq = nullptr;
switch (attrs->timingType()) {
FuncExpr *to_func = to_port->function();
Sequential *seq = (to_func && to_func->port())
? cell->outputPortSequential(to_func->port())
: nullptr;
TimingType timing_type = attrs->timingType();
// Register/latch timing group missing timing_type.
if (attrs->timingType() == TimingType::combinational
&& seq) {
if (seq->clock() && seq->clock()->hasPort(from_port)) {
switch (seq->clock()->portTimingSense(from_port)) {
case TimingSense::positive_unate:
timing_type = TimingType::rising_edge;
break;
case TimingSense::negative_unate:
timing_type = TimingType::rising_edge;
break;
default:
break;
}
}
else if (seq->clear() && seq->clear()->hasPort(from_port)) {
timing_type = TimingType::clear;
if (attrs->timingSense() == TimingSense::unknown) {
// Missing timing_sense also.
TimingSense timing_sense = seq->clear()->portTimingSense(from_port);
attrs->setTimingSense(timing_sense);
}
}
else if (seq->preset() && seq->preset()->hasPort(from_port)) {
timing_type = TimingType::preset;
if (attrs->timingSense() == TimingSense::unknown) {
// Missing timing_sense also.
TimingSense timing_sense = seq->preset()->portTimingSense(from_port);
attrs->setTimingSense(timing_sense);
}
}
}
switch (timing_type) {
case TimingType::combinational:
to_func = to_port->function();
if (to_func && to_func->op() == FuncExpr::op_port)
seq = cell->outputPortSequential(to_func->port());
if (seq && seq->isLatch())
return makeLatchDtoQArcs(cell, from_port, to_port, related_out, attrs);
if (seq
&& seq->isLatch()
&& seq->data()->hasPort(from_port))
// Latch D->Q timing arcs.
return makeLatchDtoQArcs(cell, from_port, to_port,
seq->data()->portTimingSense(from_port),
related_out, attrs);
else
return makeCombinationalArcs(cell, from_port, to_port, related_out,
true, true, attrs);
@ -261,20 +307,26 @@ LibertyBuilder::makeCombinationalArcs(LibertyCell *cell,
TimingArcAttrsPtr attrs)
{
FuncExpr *func = to_port->function();
FuncExpr *enable = to_port->tristateEnable();
TimingArcSet *arc_set = makeTimingArcSet(cell, from_port, to_port, related_out,
TimingRole::combinational(), attrs);
TimingSense sense = attrs->timingSense();
if (sense == TimingSense::unknown && func) {
if (sense == TimingSense::unknown) {
// Timing sense not specified - find it from function.
sense = func->portTimingSense(from_port);
if (sense == TimingSense::none
&& to_port->direction()->isAnyTristate()) {
// from_port is not an input to function, check tristate enable.
FuncExpr *enable = to_port->tristateEnable();
if (enable && enable->hasPort(from_port))
sense = TimingSense::non_unate;
}
if (func && func->hasPort(from_port))
sense = func->portTimingSense(from_port);
// Check tristate enable.
else if (to_port->direction()->isAnyTristate()
&& enable
&& enable->hasPort(from_port))
sense = TimingSense::non_unate;
// Don't warn for functions that reference ff/latch/lut internal ports.
//else if (func->port() && !func->port()->direction()->isInternal())
// report_->fileWarn(172, cell->filename(), line,
// "timing sense cannot be inferred because pin function does not reference related pin %s.",
// from_port->name());
}
TimingModel *model;
RiseFall *to_rf;
switch (sense) {
@ -308,9 +360,6 @@ LibertyBuilder::makeCombinationalArcs(LibertyCell *cell,
break;
case TimingSense::non_unate:
case TimingSense::unknown:
// Timing sense none means function does not mention from_port.
// This can happen if the function references an internal port,
// as in fpga lut cells.
case TimingSense::none:
if (to_fall) {
to_rf = RiseFall::fall();
@ -337,6 +386,7 @@ TimingArcSet *
LibertyBuilder::makeLatchDtoQArcs(LibertyCell *cell,
LibertyPort *from_port,
LibertyPort *to_port,
TimingSense sense,
LibertyPort *related_out,
TimingArcAttrsPtr attrs)
{
@ -346,7 +396,6 @@ LibertyBuilder::makeLatchDtoQArcs(LibertyCell *cell,
TimingModel *model;
RiseFall *to_rf = RiseFall::rise();
model = attrs->model(to_rf);
TimingSense sense = attrs->timingSense();
if (model) {
RiseFall *from_rf = (sense == TimingSense::negative_unate) ?
to_rf->opposite() : to_rf;

11
liberty/LibertyBuilder.hh
View File

@ -26,12 +26,16 @@ namespace sta {
class TimingArcAttrs;
class InternalPowerAttrs;
class LeakagePowerAttrs;
class Debug;
class Report;
class LibertyBuilder
{
public:
LibertyBuilder() {}
virtual ~LibertyBuilder() {}
void init(Debug *debug,
Report *report);
virtual LibertyCell *makeCell(LibertyLibrary *library,
const char *name,
const char *filename);
@ -52,7 +56,8 @@ public:
LibertyPort *from_port,
LibertyPort *to_port,
LibertyPort *related_out,
TimingArcAttrsPtr attrs);
TimingArcAttrsPtr attrs,
int line);
InternalPower *makeInternalPower(LibertyCell *cell,
LibertyPort *port,
LibertyPort *related_port,
@ -112,6 +117,7 @@ protected:
TimingArcSet *makeLatchDtoQArcs(LibertyCell *cell,
LibertyPort *from_port,
LibertyPort *to_port,
TimingSense sense,
LibertyPort *related_out,
TimingArcAttrsPtr attrs);
TimingArcSet *makeRegLatchArcs(LibertyCell *cell,
@ -140,6 +146,9 @@ protected:
bool to_rise,
bool to_fall,
TimingArcAttrsPtr attrs);
Debug *debug_;
Report *report_;
};
} // namespace

315
liberty/LibertyReader.cc
View File

@ -55,14 +55,12 @@ readLibertyFile(const char *filename,
bool infer_latches,
Network *network)
{
LibertyBuilder builder;
LibertyReader reader(&builder);
LibertyReader reader;
return reader.readLibertyFile(filename, infer_latches, network);
}
LibertyReader::LibertyReader(LibertyBuilder *builder) :
LibertyGroupVisitor(),
builder_(builder)
LibertyReader::LibertyReader() :
LibertyGroupVisitor()
{
defineVisitors();
}
@ -137,6 +135,8 @@ LibertyReader::readLibertyFile(const char *filename,
default_operating_condition_ = nullptr;
receiver_model_ = nullptr;
builder_.init(debug_, report_);
for (auto rf_index : RiseFall::rangeIndex()) {
have_input_threshold_[rf_index] = false;
have_output_threshold_[rf_index] = false;
@ -770,7 +770,7 @@ LibertyReader::parseUnits(LibertyAttr *attr,
// Unit format is <multipler_digits><scale_suffix_char><unit_suffix>.
// Find the multiplier digits.
string units = getAttrString(attr);
size_t mult_end = units.find_first_not_of("01234567890");
size_t mult_end = units.find_first_not_of("0123456789");
float mult = 1.0F;
string scale_suffix;
if (mult_end != units.npos) {
@ -789,26 +789,30 @@ LibertyReader::parseUnits(LibertyAttr *attr,
scale_suffix = units;
float scale_mult = 1.0F;
if (scale_suffix.size() >= 2 && scale_suffix.substr(1) == unit_suffix) {
char scale_char = tolower(scale_suffix[0]);
if (scale_char == 'k')
scale_mult = 1E+3F;
else if (scale_char == 'm')
scale_mult = 1E-3F;
else if (scale_char == 'u')
scale_mult = 1E-6F;
else if (scale_char == 'n')
scale_mult = 1E-9F;
else if (scale_char == 'p')
scale_mult = 1E-12F;
else if (scale_char == 'f')
scale_mult = 1E-15F;
if (scale_suffix.size() == strlen(unit_suffix) + 1) {
string suffix = scale_suffix.substr(1);
if (stringEqual(suffix.c_str(), unit_suffix)) {
char scale_char = tolower(scale_suffix[0]);
if (scale_char == 'k')
scale_mult = 1E+3F;
else if (scale_char == 'm')
scale_mult = 1E-3F;
else if (scale_char == 'u')
scale_mult = 1E-6F;
else if (scale_char == 'n')
scale_mult = 1E-9F;
else if (scale_char == 'p')
scale_mult = 1E-12F;
else if (scale_char == 'f')
scale_mult = 1E-15F;
else
libWarn(39, attr, "unknown unit scale %c.", scale_char);
}
else
libWarn(39, attr, "unknown unit scale %c.", scale_char);
libWarn(40, attr, "unknown unit suffix %s.", suffix.c_str());
}
else if (!stringEqual(scale_suffix.c_str(), unit_suffix))
libWarn(40, attr, "unknown unit suffix %s.", scale_suffix.c_str());
libWarn(171, attr, "unknown unit suffix %s.", scale_suffix.c_str());
scale_var = scale_mult * mult;
unit->setScale(scale_var);
}
@ -1859,7 +1863,7 @@ LibertyReader::beginCell(LibertyGroup *group)
const char *name = group->firstName();
if (name) {
debugPrint(debug_, "liberty", 1, "cell %s", name);
cell_ = builder_->makeCell(library_, name, filename_);
cell_ = builder_.makeCell(library_, name, filename_);
in_bus_ = false;
in_bundle_ = false;
}
@ -1900,15 +1904,10 @@ LibertyReader::endCell(LibertyGroup *group)
void
LibertyReader::finishPortGroups()
{
PortGroupSeq::Iterator group_iter(cell_port_groups_);
while (group_iter.hasNext()) {
PortGroup *port_group = group_iter.next();
for (PortGroup *port_group : cell_port_groups_) {
int line = port_group->line();
LibertyPortSeq::Iterator port_iter(port_group->ports());
while (port_iter.hasNext()) {
LibertyPort *port = port_iter.next();
for (LibertyPort *port : *port_group->ports())
checkPort(port, line);
}
makeTimingArcs(port_group);
makeInternalPowers(port_group);
delete port_group;
@ -1935,30 +1934,20 @@ LibertyReader::checkPort(LibertyPort *port,
void
LibertyReader::makeTimingArcs(PortGroup *port_group)
{
TimingGroupSeq::Iterator timing_iter(port_group->timingGroups());
while (timing_iter.hasNext()) {
TimingGroup *timing = timing_iter.next();
for (TimingGroup *timing : port_group->timingGroups()) {
timing->makeTimingModels(library_, this);
LibertyPortSeq::Iterator port_iter(port_group->ports());
while (port_iter.hasNext()) {
LibertyPort *port = port_iter.next();
for (LibertyPort *port : *port_group->ports())
makeTimingArcs(port, timing);
}
}
}
void
LibertyReader::makeInternalPowers(PortGroup *port_group)
{
InternalPowerGroupSeq::Iterator power_iter(port_group->internalPowerGroups());
while (power_iter.hasNext()) {
InternalPowerGroup *power_group = power_iter.next();
LibertyPortSeq::Iterator port_iter(port_group->ports());
while (port_iter.hasNext()) {
LibertyPort *port = port_iter.next();
for (InternalPowerGroup *power_group : port_group->internalPowerGroups()) {
for (LibertyPort *port : *port_group->ports())
makeInternalPowers(port, power_group);
}
cell_->addInternalPowerAttrs(power_group);
}
}
@ -1966,9 +1955,7 @@ LibertyReader::makeInternalPowers(PortGroup *port_group)
void
LibertyReader::makeCellSequentials()
{
SequentialGroupSeq::Iterator seq_iter(cell_sequentials_);
while (seq_iter.hasNext()) {
SequentialGroup *seq = seq_iter.next();
for (SequentialGroup *seq : cell_sequentials_) {
makeCellSequential(seq);
delete seq;
}
@ -2073,10 +2060,8 @@ LibertyReader::checkLatchEnableSense(FuncExpr *enable_func,
void
LibertyReader::makeLeakagePowers()
{
LeakagePowerGroupSeq::Iterator power_iter(leakage_powers_);
while (power_iter.hasNext()) {
LeakagePowerGroup *power_group = power_iter.next();
builder_->makeLeakagePower(cell_, power_group);
for (LeakagePowerGroup *power_group : leakage_powers_) {
builder_.makeLeakagePower(cell_, power_group);
delete power_group;
}
leakage_powers_.clear();
@ -2099,9 +2084,7 @@ LibertyReader::makeLibertyFunc(const char *expr,
void
LibertyReader::parseCellFuncs()
{
LibertyFuncSeq::Iterator func_iter(cell_funcs_);
while (func_iter.hasNext()) {
LibertyFunc *func = func_iter.next();
for (LibertyFunc *func : cell_funcs_) {
FuncExpr *expr = parseFunc(func->expr(), func->attrName(), func->line());
if (func->invert() && expr) {
if (expr->op() == FuncExpr::op_not) {
@ -2201,15 +2184,15 @@ LibertyReader::makeTimingArcs(LibertyPort *to_port,
if (type == TimingType::combinational &&
to_port_dir->isInput())
libWarn(94, line, "combinational timing to an input port.");
StringSeq::Iterator related_port_iter(timing->relatedPortNames());
while (related_port_iter.hasNext()) {
const char *from_port_name = related_port_iter.next();
PortNameBitIterator from_port_iter(cell_, from_port_name, this, line);
if (from_port_iter.hasNext()) {
debugPrint(debug_, "liberty", 2, " timing %s -> %s",
from_port_name, to_port->name());
makeTimingArcs(from_port_name, from_port_iter, to_port,
related_out_port, timing);
if (timing->relatedPortNames()) {
for (const char *from_port_name : *timing->relatedPortNames()) {
PortNameBitIterator from_port_iter(cell_, from_port_name, this, line);
if (from_port_iter.hasNext()) {
debugPrint(debug_, "liberty", 2, " timing %s -> %s",
from_port_name, to_port->name());
makeTimingArcs(from_port_name, from_port_iter, to_port,
related_out_port, timing);
}
}
}
}
@ -2314,8 +2297,8 @@ LibertyReader::makeTimingArcs(const char *from_port_name,
LibertyPort *from_port = from_port_iter.next();
if (from_port->direction()->isOutput())
libWarn(164, timing->line(), "timing group from output port.");
builder_->makeTimingArcs(cell_, from_port, to_port,
related_out_port, timing->attrs());
builder_.makeTimingArcs(cell_, from_port, to_port, related_out_port,
timing->attrs(), timing->line());
}
}
else if (from_port_iter.size() > 1 && !to_port->hasMembers()) {
@ -2324,8 +2307,8 @@ LibertyReader::makeTimingArcs(const char *from_port_name,
LibertyPort *from_port = from_port_iter.next();
if (from_port->direction()->isOutput())
libWarn(165, timing->line(), "timing group from output port.");
builder_->makeTimingArcs(cell_, from_port, to_port,
related_out_port, timing->attrs());
builder_.makeTimingArcs(cell_, from_port, to_port, related_out_port,
timing->attrs(), timing->line());
}
}
else if (from_port_iter.size() == 1 && to_port->hasMembers()) {
@ -2337,8 +2320,8 @@ LibertyReader::makeTimingArcs(const char *from_port_name,
LibertyPortMemberIterator bit_iter(to_port);
while (bit_iter.hasNext()) {
LibertyPort *to_port_bit = bit_iter.next();
builder_->makeTimingArcs(cell_, from_port, to_port_bit,
related_out_port, timing->attrs());
builder_.makeTimingArcs(cell_, from_port, to_port_bit, related_out_port,
timing->attrs(), timing->line());
}
}
}
@ -2352,8 +2335,9 @@ LibertyReader::makeTimingArcs(const char *from_port_name,
LibertyPort *to_port_bit = to_iter.next();
if (from_port_bit->direction()->isOutput())
libWarn(167, timing->line(), "timing group from output port.");
builder_->makeTimingArcs(cell_, from_port_bit, to_port_bit,
related_out_port, timing->attrs());
builder_.makeTimingArcs(cell_, from_port_bit, to_port_bit,
related_out_port, timing->attrs(),
timing->line());
}
}
else
@ -2370,8 +2354,9 @@ LibertyReader::makeTimingArcs(const char *from_port_name,
LibertyPortMemberIterator to_iter(to_port);
while (to_iter.hasNext()) {
LibertyPort *to_port_bit = to_iter.next();
builder_->makeTimingArcs(cell_, from_port_bit, to_port_bit,
related_out_port, timing->attrs());
builder_.makeTimingArcs(cell_, from_port_bit, to_port_bit,
related_out_port, timing->attrs(),
timing->line());
}
}
}
@ -2658,9 +2643,7 @@ LibertyReader::makeInternalPowers(LibertyPort *port,
int line = power_group->line();
StringSeq *related_port_names = power_group->relatedPortNames();
if (related_port_names) {
StringSeq::Iterator related_port_iter(related_port_names);
while (related_port_iter.hasNext()) {
const char *related_port_name = related_port_iter.next();
for (const char *related_port_name : *related_port_names) {
PortNameBitIterator related_port_iter(cell_, related_port_name, this, line);
if (related_port_iter.hasNext()) {
debugPrint(debug_, "liberty", 2, " power %s -> %s",
@ -2674,11 +2657,11 @@ LibertyReader::makeInternalPowers(LibertyPort *port,
LibertyPortMemberIterator bit_iter(port);
while (bit_iter.hasNext()) {
LibertyPort *port_bit = bit_iter.next();
builder_->makeInternalPower(cell_, port_bit, nullptr, power_group);
builder_.makeInternalPower(cell_, port_bit, nullptr, power_group);
}
}
else
builder_->makeInternalPower(cell_, port, nullptr, power_group);
builder_.makeInternalPower(cell_, port, nullptr, power_group);
}
}
@ -2692,14 +2675,14 @@ LibertyReader::makeInternalPowers(LibertyPort *port,
// one -> one
if (related_port_iter.hasNext()) {
LibertyPort *related_port = related_port_iter.next();
builder_->makeInternalPower(cell_, port, related_port, power_group);
builder_.makeInternalPower(cell_, port, related_port, power_group);
}
}
else if (related_port_iter.size() > 1 && !port->hasMembers()) {
// bus -> one
while (related_port_iter.hasNext()) {
LibertyPort *related_port = related_port_iter.next();
builder_->makeInternalPower(cell_, port, related_port, power_group);
builder_.makeInternalPower(cell_, port, related_port, power_group);
}
}
else if (related_port_iter.size() == 1 && port->hasMembers()) {
@ -2709,7 +2692,7 @@ LibertyReader::makeInternalPowers(LibertyPort *port,
LibertyPortMemberIterator bit_iter(port);
while (bit_iter.hasNext()) {
LibertyPort *port_bit = bit_iter.next();
builder_->makeInternalPower(cell_, port_bit, related_port, power_group);
builder_.makeInternalPower(cell_, port_bit, related_port, power_group);
}
}
}
@ -2721,7 +2704,7 @@ LibertyReader::makeInternalPowers(LibertyPort *port,
while (related_port_iter.hasNext() && to_iter.hasNext()) {
LibertyPort *related_port_bit = related_port_iter.next();
LibertyPort *port_bit = to_iter.next();
builder_->makeInternalPower(cell_, port_bit, related_port_bit, power_group);
builder_.makeInternalPower(cell_, port_bit, related_port_bit, power_group);
}
}
else
@ -2736,7 +2719,7 @@ LibertyReader::makeInternalPowers(LibertyPort *port,
LibertyPortMemberIterator to_iter(port);
while (to_iter.hasNext()) {
LibertyPort *port_bit = to_iter.next();
builder_->makeInternalPower(cell_, port_bit, related_port_bit, power_group);
builder_.makeInternalPower(cell_, port_bit, related_port_bit, power_group);
}
}
}
@ -2921,9 +2904,7 @@ LibertyReader::beginPin(LibertyGroup *group)
saved_ports_ = ports_;
saved_port_group_ = port_group_;
ports_ = new LibertyPortSeq;
LibertyAttrValueIterator param_iter(group->params());
while (param_iter.hasNext()) {
LibertyAttrValue *param = param_iter.next();
for (LibertyAttrValue *param : *group->params()) {
if (param->isString()) {
const char *port_name = param->stringValue();
debugPrint(debug_, "liberty", 1, " port %s", port_name);
@ -2941,15 +2922,13 @@ LibertyReader::beginPin(LibertyGroup *group)
saved_ports_ = ports_;
saved_port_group_ = port_group_;
ports_ = new LibertyPortSeq;
LibertyAttrValueIterator param_iter(group->params());
while (param_iter.hasNext()) {
LibertyAttrValue *param = param_iter.next();
for (LibertyAttrValue *param : *group->params()) {
if (param->isString()) {
const char *name = param->stringValue();
debugPrint(debug_, "liberty", 1, " port %s", name);
LibertyPort *port = findPort(name);
if (port == nullptr)
port = builder_->makePort(cell_, name);
port = builder_.makePort(cell_, name);
ports_->push_back(port);
}
else
@ -2959,13 +2938,11 @@ LibertyReader::beginPin(LibertyGroup *group)
else {
ports_ = new LibertyPortSeq;
// Multiple port names can share group def.
LibertyAttrValueIterator param_iter(group->params());
while (param_iter.hasNext()) {
LibertyAttrValue *param = param_iter.next();
for (LibertyAttrValue *param : *group->params()) {
if (param->isString()) {
const char *name = param->stringValue();
debugPrint(debug_, "liberty", 1, " port %s", name);
LibertyPort *port = builder_->makePort(cell_, name);
LibertyPort *port = builder_.makePort(cell_, name);
ports_->push_back(port);
}
else
@ -3000,23 +2977,23 @@ LibertyReader::endPorts()
{
// Capacitances default based on direction so wait until the end
// of the pin group to set them.
LibertyPortSeq::Iterator port_iter(ports_);
while (port_iter.hasNext()) {
LibertyPort *port = port_iter.next();
if (in_bus_ || in_bundle_) {
// Do not clobber member port capacitances by setting the capacitance
// on a bus or bundle.
LibertyPortMemberIterator member_iter(port);
while (member_iter.hasNext()) {
LibertyPort *member = member_iter.next();
setPortCapDefault(member);
if (ports_) {
for (LibertyPort *port : *ports_) {
if (in_bus_ || in_bundle_) {
// Do not clobber member port capacitances by setting the capacitance
// on a bus or bundle.
LibertyPortMemberIterator member_iter(port);
while (member_iter.hasNext()) {
LibertyPort *member = member_iter.next();
setPortCapDefault(member);
}
}
else
setPortCapDefault(port);
}
else
setPortCapDefault(port);
ports_ = nullptr;
port_group_ = nullptr;
}
ports_ = nullptr;
port_group_ = nullptr;
}
void
@ -3057,9 +3034,7 @@ void
LibertyReader::beginBusOrBundle(LibertyGroup *group)
{
// Multiple port names can share group def.
LibertyAttrValueIterator param_iter(group->params());
while (param_iter.hasNext()) {
LibertyAttrValue *param = param_iter.next();
for (LibertyAttrValue *param : *group->params()) {
if (param->isString()) {
const char *name = param->stringValue();
if (name)
@ -3093,11 +3068,9 @@ LibertyReader::visitBusType(LibertyAttr *attr)
if (bus_dcl == nullptr)
bus_dcl = library_->findBusDcl(bus_type);
if (bus_dcl) {
StringSeq::Iterator name_iter(bus_names_);
while (name_iter.hasNext()) {
const char *name = name_iter.next();
for (const char *name : bus_names_) {
debugPrint(debug_, "liberty", 1, " bus %s", name);
LibertyPort *port = builder_->makeBusPort(cell_, name, bus_dcl->from(),
LibertyPort *port = builder_.makeBusPort(cell_, name, bus_dcl->from(),
bus_dcl->to(), bus_dcl);
ports_->push_back(port);
}
@ -3135,25 +3108,21 @@ LibertyReader::visitMembers(LibertyAttr *attr)
{
if (cell_) {
if (attr->isComplex()) {
StringSeq::Iterator name_iter(bus_names_);
while (name_iter.hasNext()) {
const char *name = name_iter.next();
for (const char *name : bus_names_) {
debugPrint(debug_, "liberty", 1, " bundle %s", name);
ConcretePortSeq *members = new ConcretePortSeq;
LibertyAttrValueIterator value_iter(attr->values());
while (value_iter.hasNext()) {
LibertyAttrValue *value = value_iter.next();
for (LibertyAttrValue *value : *attr->values()) {
if (value->isString()) {
const char *port_name = value->stringValue();
LibertyPort *port = findPort(port_name);
if (port == nullptr)
port = builder_->makePort(cell_, port_name);
port = builder_.makePort(cell_, port_name);
members->push_back(port);
}
else
libWarn(107, attr, "member is not a string.");
}
LibertyPort *port = builder_->makeBundlePort(cell_, name, members);
LibertyPort *port = builder_.makeBundlePort(cell_, name, members);
ports_->push_back(port);
}
}
@ -3227,11 +3196,8 @@ LibertyReader::visitFunction(LibertyAttr *attr)
if (ports_) {
const char *func = getAttrString(attr);
if (func) {
LibertyPortSeq::Iterator port_iter(ports_);
while (port_iter.hasNext()) {
LibertyPort *port = port_iter.next();
makeLibertyFunc(func, port->functionRef(), false, "function", attr);
}
for (LibertyPort *port : *ports_)
makeLibertyFunc(func, port->functionRef(), false, "function", attr);
}
}
}
@ -3242,12 +3208,9 @@ LibertyReader::visitThreeState(LibertyAttr *attr)
if (ports_) {
const char *three_state = getAttrString(attr);
if (three_state) {
LibertyPortSeq::Iterator port_iter(ports_);
while (port_iter.hasNext()) {
LibertyPort *port = port_iter.next();
for (LibertyPort *port : *ports_)
makeLibertyFunc(three_state, port->tristateEnableRef(), true,
"three_state", attr);
}
}
}
}
@ -3255,9 +3218,7 @@ LibertyReader::visitThreeState(LibertyAttr *attr)
void
LibertyReader::visitPorts(std::function<void (LibertyPort *port)> func)
{
LibertyPortSeq::Iterator port_iter(ports_);
while (port_iter.hasNext()) {
LibertyPort *port = port_iter.next();
for (LibertyPort *port : *ports_) {
func(port);
LibertyPortMemberIterator member_iter(port);
while (member_iter.hasNext()) {
@ -3274,11 +3235,8 @@ LibertyReader::visitClock(LibertyAttr *attr)
bool is_clk, exists;
getAttrBool(attr, is_clk, exists);
if (exists) {
LibertyPortSeq::Iterator port_iter(ports_);
while (port_iter.hasNext()) {
LibertyPort *port = port_iter.next();
for (LibertyPort *port : *ports_)
port->setIsClock(is_clk);
}
}
}
}
@ -3292,11 +3250,8 @@ LibertyReader::visitCapacitance(LibertyAttr *attr)
getAttrFloat(attr, cap, exists);
if (exists) {
cap *= cap_scale_;
LibertyPortSeq::Iterator port_iter(ports_);
while (port_iter.hasNext()) {
LibertyPort *port = port_iter.next();
for (LibertyPort *port : *ports_)
port->setCapacitance(cap);
}
}
}
if (wireload_) {
@ -3317,9 +3272,7 @@ LibertyReader::visitRiseCap(LibertyAttr *attr)
getAttrFloat(attr, cap, exists);
if (exists) {
cap *= cap_scale_;
LibertyPortSeq::Iterator port_iter(ports_);
while (port_iter.hasNext()) {
LibertyPort *port = port_iter.next();
for (LibertyPort *port : *ports_) {
port->setCapacitance(RiseFall::rise(), MinMax::min(), cap);
port->setCapacitance(RiseFall::rise(), MinMax::max(), cap);
}
@ -3336,9 +3289,7 @@ LibertyReader::visitFallCap(LibertyAttr *attr)
getAttrFloat(attr, cap, exists);
if (exists) {
cap *= cap_scale_;
LibertyPortSeq::Iterator port_iter(ports_);
while (port_iter.hasNext()) {
LibertyPort *port = port_iter.next();
for (LibertyPort *port : *ports_) {
port->setCapacitance(RiseFall::fall(), MinMax::min(), cap);
port->setCapacitance(RiseFall::fall(), MinMax::max(), cap);
}
@ -3356,9 +3307,7 @@ LibertyReader::visitRiseCapRange(LibertyAttr *attr)
if (exists) {
min *= cap_scale_;
max *= cap_scale_;
LibertyPortSeq::Iterator port_iter(ports_);
while (port_iter.hasNext()) {
LibertyPort *port = port_iter.next();
for (LibertyPort *port : *ports_) {
port->setCapacitance(RiseFall::rise(), MinMax::min(), min);
port->setCapacitance(RiseFall::rise(), MinMax::max(), max);
}
@ -3376,9 +3325,7 @@ LibertyReader::visitFallCapRange(LibertyAttr *attr)
if (exists) {
min *= cap_scale_;
max *= cap_scale_;
LibertyPortSeq::Iterator port_iter(ports_);
while (port_iter.hasNext()) {
LibertyPort *port = port_iter.next();
for (LibertyPort *port : *ports_) {
port->setCapacitance(RiseFall::fall(), MinMax::min(), min);
port->setCapacitance(RiseFall::fall(), MinMax::max(), max);
}
@ -3512,11 +3459,8 @@ LibertyReader::visitMinPeriod(LibertyAttr *attr)
bool exists;
getAttrFloat(attr, value, exists);
if (exists) {
LibertyPortSeq::Iterator port_iter(ports_);
while (port_iter.hasNext()) {
LibertyPort *port = port_iter.next();
for (LibertyPort *port : *ports_)
port->setMinPeriod(value * time_scale_);
}
}
}
}
@ -3543,11 +3487,8 @@ LibertyReader::visitMinPulseWidth(LibertyAttr *attr,
getAttrFloat(attr, value, exists);
if (exists) {
value *= time_scale_;
LibertyPortSeq::Iterator port_iter(ports_);
while (port_iter.hasNext()) {
LibertyPort *port = port_iter.next();
for (LibertyPort *port : *ports_)
port->setMinPulseWidth(rf, value);
}
}
}
}
@ -3579,11 +3520,8 @@ LibertyReader::visitPulseClock(LibertyAttr *attr)
else
libWarn(110,attr, "pulse_latch unknown pulse type.");
if (trigger) {
LibertyPortSeq::Iterator port_iter(ports_);
while (port_iter.hasNext()) {
LibertyPort *port = port_iter.next();
for (LibertyPort *port : *ports_)
port->setPulseClk(trigger, sense);
}
}
}
}
@ -3663,11 +3601,8 @@ LibertyReader::visitPortBoolAttr(LibertyAttr *attr,
bool value, exists;
getAttrBool(attr, value, exists);
if (exists) {
LibertyPortSeq::Iterator port_iter(ports_);
while (port_iter.hasNext()) {
LibertyPort *port = port_iter.next();
for (LibertyPort *port : *ports_)
(port->*setter)(value);
}
}
}
}
@ -3737,16 +3672,16 @@ LibertyReader::beginSequential(LibertyGroup *group,
LibertyPort *out_port_inv = nullptr;
if (out_name) {
if (has_size)
out_port = builder_->makeBusPort(cell_, out_name, size - 1, 0, nullptr);
out_port = builder_.makeBusPort(cell_, out_name, size - 1, 0, nullptr);
else
out_port = builder_->makePort(cell_,out_name);
out_port = builder_.makePort(cell_,out_name);
out_port->setDirection(PortDirection::internal());
}
if (out_inv_name) {
if (has_size)
out_port_inv = builder_->makeBusPort(cell_, out_inv_name, size - 1, 0, nullptr);
out_port_inv = builder_.makeBusPort(cell_, out_inv_name, size - 1, 0, nullptr);
else
out_port_inv = builder_->makePort(cell_, out_inv_name);
out_port_inv = builder_.makePort(cell_, out_inv_name);
out_port_inv->setDirection(PortDirection::internal());
}
sequential_ = new SequentialGroup(is_register, is_bank,
@ -3768,9 +3703,7 @@ LibertyReader::seqPortNames(LibertyGroup *group,
out_inv_name = nullptr;
size = 1;
has_size = false;
LibertyAttrValueIterator param_iter(group->params());
while (param_iter.hasNext()) {
LibertyAttrValue *value = param_iter.next();
for (LibertyAttrValue *value : *group->params()) {
if (i == 0)
out_name = value->stringValue();
else if (i == 1)
@ -4339,9 +4272,7 @@ LibertyReader::makeFloatTable(LibertyAttr *attr,
{
FloatTable *table = new FloatTable;
table->reserve(rows);
LibertyAttrValueIterator value_iter(attr->values());
while (value_iter.hasNext()) {
LibertyAttrValue *value = value_iter.next();
for (LibertyAttrValue *value : *attr->values()) {
FloatSeq *row = new FloatSeq;
row->reserve(cols);
table->push_back(row);
@ -4402,9 +4333,7 @@ void
LibertyReader::beginLut(LibertyGroup *group)
{
if (cell_) {
LibertyAttrValueIterator param_iter(group->params());
while (param_iter.hasNext()) {
LibertyAttrValue *param = param_iter.next();
for (LibertyAttrValue *param : *group->params()) {
if (param->isString()) {
const char *names = param->stringValue();
// Parse space separated list of related port names.
@ -4412,7 +4341,7 @@ LibertyReader::beginLut(LibertyGroup *group)
while (parser.hasNext()) {
char *name = parser.next();
if (name[0] != '\0') {
LibertyPort *port = builder_->makePort(cell_, name);
LibertyPort *port = builder_.makePort(cell_, name);
port->setDirection(PortDirection::internal());
}
}
@ -4602,7 +4531,9 @@ LibertyReader::getAttrFloat(LibertyAttr *attr,
// Check that the string is a valid double.
char *end;
value = strtof(string, &end);
if (*end && !isspace(*end))
if ((*end && !isspace(*end))
// strtof support INF as a valid float.
|| stringEqual(string, "inf"))
libWarn(135, attr, "%s value %s is not a float.",
attr->name(),
string);
@ -4944,11 +4875,8 @@ LibertyReader::visitRelatedGroundPin(LibertyAttr *attr)
{
if (ports_) {
const char *related_ground_pin = getAttrString(attr);
LibertyPortSeq::Iterator port_iter(ports_);
while (port_iter.hasNext()) {
LibertyPort *port = port_iter.next();
for (LibertyPort *port : *ports_)
port->setRelatedGroundPin(related_ground_pin);
}
}
}
@ -4957,11 +4885,8 @@ LibertyReader::visitRelatedPowerPin(LibertyAttr *attr)
{
if (ports_) {
const char *related_power_pin = getAttrString(attr);
LibertyPortSeq::Iterator port_iter(ports_);
while (port_iter.hasNext()) {
LibertyPort *port = port_iter.next();
for (LibertyPort *port : *ports_)
port->setRelatedPowerPin(related_power_pin);
}
}
}

8
liberty/LibertyReaderPvt.hh
View File

@ -63,7 +63,7 @@ typedef Vector<OutputWaveform*> OutputWaveformSeq;
class LibertyReader : public LibertyGroupVisitor
{
public:
explicit LibertyReader(LibertyBuilder *builder);
explicit LibertyReader();
virtual ~LibertyReader();
virtual LibertyLibrary *readLibertyFile(const char *filename,
bool infer_latches,
@ -557,7 +557,7 @@ protected:
Report *report_;
Debug *debug_;
Network *network_;
LibertyBuilder *builder_;
LibertyBuilder builder_;
LibertyVariableMap *var_map_;
LibertyLibrary *library_;
LibraryGroupMap group_begin_map_;
@ -674,9 +674,9 @@ public:
int line);
~PortGroup();
LibertyPortSeq *ports() const { return ports_; }
TimingGroupSeq *timingGroups() { return &timings_; }
TimingGroupSeq &timingGroups() { return timings_; }
void addTimingGroup(TimingGroup *timing);
InternalPowerGroupSeq *internalPowerGroups() { return &internal_power_groups_; }
InternalPowerGroupSeq &internalPowerGroups() { return internal_power_groups_; }
void addInternalPowerGroup(InternalPowerGroup *internal_power);
ReceiverModel *receiverModel() const { return receiver_model_; }
void setReceiverModel(ReceiverModelPtr receiver_model);

375
messages.txt
View File

@ -1,16 +1,16 @@
0001 DmpCeff.cc:1597 cell %s delay model not supported on SPF parasitics by DMP delay calculator
0002 Liberty.cc:770 cell %s/%s port %s not found in cell %s/%s.
0003 Liberty.cc:796 cell %s/%s %s -> %s timing group %s not found in cell %s/%s.
0004 Liberty.cc:1746 cell %s/%s %s -> %s latch enable %s_edge is inconsistent with %s -> %s setup_%s check.
0005 Liberty.cc:1760 cell %s/%s %s -> %s latch enable %s_edge is inconsistent with latch group enable function positive sense.
0006 Liberty.cc:1768 cell %s/%s %s -> %s latch enable %s_edge is inconsistent with latch group enable function negative sense.
0004 Liberty.cc:1745 cell %s/%s %s -> %s latch enable %s_edge is inconsistent with %s -> %s setup_%s check.
0005 Liberty.cc:1759 cell %s/%s %s -> %s latch enable %s_edge is inconsistent with latch group enable function positive sense.
0006 Liberty.cc:1767 cell %s/%s %s -> %s latch enable %s_edge is inconsistent with latch group enable function negative sense.
0007 LibertyExpr.cc:82 %s references unknown port %s.
0008 ConcreteNetwork.cc:1917 cell type %s can not be linked.
0008 ConcreteNetwork.cc:1909 cell type %s can not be linked.
0009 CycleAccting.cc:87 No common period was found between clocks %s and %s.
0010 Genclks.cc:274 no master clock found for generated clock %s.
0013 Genclks.cc:938 generated clock %s source pin %s missing paths from master clock %s.
0015 Sim.cc:865 propagated logic value %c differs from constraint value of %c on pin %s.
0016 LibertyReader.cc:1037 default_max_fanout is 0.0.
0016 LibertyReader.cc:1041 default_max_fanout is 0.0.
0017 Sta.cc:2093 '%s' is not a valid endpoint.
0018 Sta.cc:2017 '%s' is not a valid start point.
0021 SpefParse.yy:805 %d is not positive.
@ -31,143 +31,142 @@
0036 LibertyReader.cc:702 slew_upper_threshold_pct_%s not found.
0037 LibertyReader.cc:707 Library %s is missing one or more thresholds.
0038 LibertyReader.cc:786 unknown unit multiplier %s.
0039 LibertyReader.cc:807 unknown unit scale %c.
0040 LibertyReader.cc:810 unknown unit suffix %s.
0041 LibertyReader.cc:836 capacitive_load_units are not ff or pf.
0042 LibertyReader.cc:839 capacitive_load_units are not a string.
0043 LibertyReader.cc:842 capacitive_load_units missing suffix.
0044 LibertyReader.cc:845 capacitive_load_units scale is not a float.
0045 LibertyReader.cc:848 capacitive_load_units missing scale and suffix.
0046 LibertyReader.cc:851 capacitive_load_unit missing values suffix.
0047 LibertyReader.cc:869 delay_model %s not supported.
0048 LibertyReader.cc:873 delay_model %s not supported.
0049 LibertyReader.cc:877 delay_model %s not supported.
0050 LibertyReader.cc:882 delay_model %s not supported.
0039 LibertyReader.cc:809 unknown unit scale %c.
0040 LibertyReader.cc:812 unknown unit suffix %s.
0041 LibertyReader.cc:840 capacitive_load_units are not ff or pf.
0042 LibertyReader.cc:843 capacitive_load_units are not a string.
0043 LibertyReader.cc:846 capacitive_load_units missing suffix.
0044 LibertyReader.cc:849 capacitive_load_units scale is not a float.
0045 LibertyReader.cc:852 capacitive_load_units missing scale and suffix.
0046 LibertyReader.cc:855 capacitive_load_unit missing values suffix.
0047 LibertyReader.cc:873 delay_model %s not supported.
0048 LibertyReader.cc:877 delay_model %s not supported.
0049 LibertyReader.cc:881 delay_model %s not supported.
0050 LibertyReader.cc:886 delay_model %s not supported.
.
0051 LibertyReader.cc:885 unknown delay_model %s
0051 LibertyReader.cc:889 unknown delay_model %s
.
0052 LibertyReader.cc:904 unknown bus_naming_style format.
0052 LibertyReader.cc:908 unknown bus_naming_style format.
0053 LibertyReader.cc:597 library %s already exists.
0054 LibertyReader.cc:925 voltage_map voltage is not a float.
0055 LibertyReader.cc:928 voltage_map missing voltage.
0056 LibertyReader.cc:931 voltage_map supply name is not a string.
0057 LibertyReader.cc:934 voltage_map missing supply name and voltage.
0058 LibertyReader.cc:937 voltage_map missing values suffix.
0059 LibertyReader.cc:1155 default_wire_load_mode %s not found.
0054 LibertyReader.cc:929 voltage_map voltage is not a float.
0055 LibertyReader.cc:932 voltage_map missing voltage.
0056 LibertyReader.cc:935 voltage_map supply name is not a string.
0057 LibertyReader.cc:938 voltage_map missing supply name and voltage.
0058 LibertyReader.cc:941 voltage_map missing values suffix.
0059 LibertyReader.cc:1159 default_wire_load_mode %s not found.
0060 LibertyReader.cc:680 default_operating_condition %s not found.
0061 LibertyReader.cc:1326 table template missing name.
0062 LibertyReader.cc:1371 missing variable_%d attribute.
0063 LibertyReader.cc:1414 axis type %s not supported.
0064 LibertyReader.cc:1474 bus type %s missing bit_from.
0065 LibertyReader.cc:1476 bus type %s missing bit_to.
0066 LibertyReader.cc:1480 type missing name.
0067 LibertyReader.cc:1507 scaling_factors do not have a name.
0068 LibertyReader.cc:1675 operating_conditions missing name.
0069 LibertyReader.cc:1745 wire_load missing name.
0070 LibertyReader.cc:1788 fanout_length is missing length and fanout.
0071 LibertyReader.cc:1803 wire_load_selection missing name.
0072 LibertyReader.cc:1834 wireload %s not found.
0074 LibertyReader.cc:1841 wire_load_from_area min not a float.
0075 LibertyReader.cc:1844 wire_load_from_area max not a float.
0076 LibertyReader.cc:1847 wire_load_from_area missing parameters.
0077 LibertyReader.cc:1850 wire_load_from_area missing parameters.
0078 LibertyReader.cc:1867 cell missing name.
0079 LibertyReader.cc:1890 cell %s ocv_derate_group %s not found.
0080 LibertyReader.cc:1926 port %s function size does not match port size.
0081 LibertyReader.cc:1994 %s %s bus width mismatch.
0082 LibertyReader.cc:2005 %s %s bus width mismatch.
0083 LibertyReader.cc:2015 clear
0084 LibertyReader.cc:2025 preset
0085 LibertyReader.cc:2061 latch enable function is non-unate for port %s.
0086 LibertyReader.cc:2066 latch enable function is unknown for port %s.
0087 LibertyReader.cc:2142 operating conditions %s not found.
0088 LibertyReader.cc:2145 scaled_cell missing operating condition.
0089 LibertyReader.cc:2148 scaled_cell cell %s has not been defined.
0090 LibertyReader.cc:2151 scaled_cell missing name.
0091 LibertyReader.cc:2177 scaled_cell %s, %s port functions do not match cell port functions.
0092 LibertyReader.cc:2182 scaled_cell ports do not match cell ports.
0093 LibertyReader.cc:2184 scaled_cell %s, %s timing does not match cell timing.
0094 LibertyReader.cc:2203 combinational timing to an input port.
0095 LibertyReader.cc:2294 missing %s_transition.
0096 LibertyReader.cc:2296 missing cell_%s.
0099 LibertyReader.cc:2894 scaling_factors %s not found.
0100 LibertyReader.cc:2937 pin name is not a string.
0101 LibertyReader.cc:2956 pin name is not a string.
0102 LibertyReader.cc:2972 pin name is not a string.
0103 LibertyReader.cc:3050 bus %s bus_type not found.
0104 LibertyReader.cc:3106 bus_type %s not found.
0105 LibertyReader.cc:3109 bus_type is not a string.
0106 LibertyReader.cc:3127 bundle %s member not found.
0107 LibertyReader.cc:3154 member is not a string.
0108 LibertyReader.cc:3161 members attribute is missing values.
0109 LibertyReader.cc:3212 unknown port direction.
0110 LibertyReader.cc:3580 pulse_latch unknown pulse type.
0111 LibertyReader.cc:3958 unknown timing_type %s.
0112 LibertyReader.cc:3978 unknown timing_sense %s.
0113 LibertyReader.cc:4018 mode value is not a string.
0114 LibertyReader.cc:4021 missing mode value.
0115 LibertyReader.cc:4024 mode name is not a string.
0116 LibertyReader.cc:4027 mode missing values.
0117 LibertyReader.cc:4030 mode missing mode name and value.
0118 LibertyReader.cc:2541 unsupported model axis.
0119 LibertyReader.cc:4133 unsupported model axis.
0120 LibertyReader.cc:4162 unsupported model axis.
0121 LibertyReader.cc:4197 unsupported model axis.
0122 LibertyReader.cc:4252 table template %s not found.
0123 LibertyReader.cc:4331 %s is missing values.
0124 LibertyReader.cc:4356 %s is not a list of floats.
0125 LibertyReader.cc:4358 table row has %u columns but axis has %d.
0126 LibertyReader.cc:4368 table has %u rows but axis has %d.
0127 LibertyReader.cc:4421 lut output is not a string.
0128 LibertyReader.cc:4463 mode definition missing name.
0129 LibertyReader.cc:4480 mode value missing name.
0130 LibertyReader.cc:4494 when attribute inside table model.
0131 LibertyReader.cc:4543 %s attribute is not a string.
0132 LibertyReader.cc:4546 %s is not a simple attribute.
0133 LibertyReader.cc:4569 %s is not a simple attribute.
0134 LibertyReader.cc:4582 %s is not a simple attribute.
0135 LibertyReader.cc:4606 %s value %s is not a float.
0136 LibertyReader.cc:4635 %s missing values.
0137 LibertyReader.cc:4639 %s missing values.
0138 LibertyReader.cc:4642 %s is not a complex attribute.
0139 LibertyReader.cc:4668 %s is not a float.
0140 LibertyReader.cc:4691 %s is missing values.
0141 LibertyReader.cc:4694 %s has more than one string.
0142 LibertyReader.cc:4703 %s is missing values.
0143 LibertyReader.cc:4728 %s attribute is not boolean.
0144 LibertyReader.cc:4731 %s attribute is not boolean.
0145 LibertyReader.cc:4734 %s is not a simple attribute.
0146 LibertyReader.cc:4750 attribute %s value %s not recognized.
0147 LibertyReader.cc:4781 unknown early/late value.
0148 LibertyReader.cc:5007 OCV derate group named %s not found.
0149 LibertyReader.cc:5023 ocv_derate missing name.
0150 LibertyReader.cc:5076 unknown rise/fall.
0151 LibertyReader.cc:5096 unknown derate type.
0152 LibertyReader.cc:5128 unsupported model axis.
0153 LibertyReader.cc:5160 unsupported model axis.
0154 LibertyReader.cc:5192 unsupported model axis.
0155 LibertyReader.cc:5263 unknown pg_type.
0156 LibertyReader.cc:5658 port %s subscript out of range.
0157 LibertyReader.cc:5662 port range %s of non-bus port %s.
0158 LibertyReader.cc:5676 port %s not found.
0159 LibertyReader.cc:5746 port %s not found.
0160 LibertyReader.cc:1022 default_max_transition is 0.0.
0161 LibertyReader.cc:3468 max_transition is 0.0.
0162 LibertyReader.cc:4566 %s attribute is not an integer.
0163 LibertyReader.cc:1127 default_fanout_load is 0.0.
0164 LibertyReader.cc:2316 timing group from output port.
0165 LibertyReader.cc:2326 timing group from output port.
0166 LibertyReader.cc:2336 timing group from output port.
0167 LibertyReader.cc:2354 timing group from output port.
0168 LibertyReader.cc:2369 timing group from output port.
0169 LibertyReader.cc:4438 cell %s test_cell redefinition.
0170 LibertyReader.cc:3877 timing group missing related_pin/related_bus_pin.
0061 LibertyReader.cc:1330 table template missing name.
0062 LibertyReader.cc:1375 missing variable_%d attribute.
0063 LibertyReader.cc:1418 axis type %s not supported.
0064 LibertyReader.cc:1478 bus type %s missing bit_from.
0065 LibertyReader.cc:1480 bus type %s missing bit_to.
0066 LibertyReader.cc:1484 type missing name.
0067 LibertyReader.cc:1511 scaling_factors do not have a name.
0068 LibertyReader.cc:1679 operating_conditions missing name.
0069 LibertyReader.cc:1749 wire_load missing name.
0070 LibertyReader.cc:1792 fanout_length is missing length and fanout.
0071 LibertyReader.cc:1807 wire_load_selection missing name.
0072 LibertyReader.cc:1838 wireload %s not found.
0074 LibertyReader.cc:1845 wire_load_from_area min not a float.
0075 LibertyReader.cc:1848 wire_load_from_area max not a float.
0076 LibertyReader.cc:1851 wire_load_from_area missing parameters.
0077 LibertyReader.cc:1854 wire_load_from_area missing parameters.
0078 LibertyReader.cc:1871 cell missing name.
0079 LibertyReader.cc:1894 cell %s ocv_derate_group %s not found.
0080 LibertyReader.cc:1925 port %s function size does not match port size.
0081 LibertyReader.cc:1981 %s %s bus width mismatch.
0082 LibertyReader.cc:1992 %s %s bus width mismatch.
0083 LibertyReader.cc:2002 clear
0084 LibertyReader.cc:2012 preset
0085 LibertyReader.cc:2048 latch enable function is non-unate for port %s.
0086 LibertyReader.cc:2053 latch enable function is unknown for port %s.
0087 LibertyReader.cc:2125 operating conditions %s not found.
0088 LibertyReader.cc:2128 scaled_cell missing operating condition.
0089 LibertyReader.cc:2131 scaled_cell cell %s has not been defined.
0090 LibertyReader.cc:2134 scaled_cell missing name.
0091 LibertyReader.cc:2160 scaled_cell %s, %s port functions do not match cell port functions.
0092 LibertyReader.cc:2165 scaled_cell ports do not match cell ports.
0093 LibertyReader.cc:2167 scaled_cell %s, %s timing does not match cell timing.
0094 LibertyReader.cc:2186 combinational timing to an input port.
0095 LibertyReader.cc:2277 missing %s_transition.
0096 LibertyReader.cc:2279 missing cell_%s.
0099 LibertyReader.cc:2877 scaling_factors %s not found.
0100 LibertyReader.cc:2918 pin name is not a string.
0101 LibertyReader.cc:2935 pin name is not a string.
0102 LibertyReader.cc:2949 pin name is not a string.
0103 LibertyReader.cc:3025 bus %s bus_type not found.
0104 LibertyReader.cc:3077 bus_type %s not found.
0105 LibertyReader.cc:3080 bus_type is not a string.
0106 LibertyReader.cc:3098 bundle %s member not found.
0107 LibertyReader.cc:3121 member is not a string.
0108 LibertyReader.cc:3128 members attribute is missing values.
0109 LibertyReader.cc:3179 unknown port direction.
0110 LibertyReader.cc:3519 pulse_latch unknown pulse type.
0111 LibertyReader.cc:3889 unknown timing_type %s.
0112 LibertyReader.cc:3909 unknown timing_sense %s.
0113 LibertyReader.cc:3949 mode value is not a string.
0114 LibertyReader.cc:3952 missing mode value.
0115 LibertyReader.cc:3955 mode name is not a string.
0116 LibertyReader.cc:3958 mode missing values.
0117 LibertyReader.cc:3961 mode missing mode name and value.
0118 LibertyReader.cc:2526 unsupported model axis.
0119 LibertyReader.cc:4064 unsupported model axis.
0120 LibertyReader.cc:4093 unsupported model axis.
0121 LibertyReader.cc:4128 unsupported model axis.
0122 LibertyReader.cc:4183 table template %s not found.
0123 LibertyReader.cc:4262 %s is missing values.
0124 LibertyReader.cc:4285 %s is not a list of floats.
0125 LibertyReader.cc:4287 table row has %u columns but axis has %d.
0126 LibertyReader.cc:4297 table has %u rows but axis has %d.
0127 LibertyReader.cc:4348 lut output is not a string.
0128 LibertyReader.cc:4390 mode definition missing name.
0129 LibertyReader.cc:4407 mode value missing name.
0130 LibertyReader.cc:4421 when attribute inside table model.
0131 LibertyReader.cc:4470 %s attribute is not a string.
0132 LibertyReader.cc:4473 %s is not a simple attribute.
0133 LibertyReader.cc:4496 %s is not a simple attribute.
0134 LibertyReader.cc:4509 %s is not a simple attribute.
0135 LibertyReader.cc:4535 %s value %s is not a float.
0136 LibertyReader.cc:4564 %s missing values.
0137 LibertyReader.cc:4568 %s missing values.
0138 LibertyReader.cc:4571 %s is not a complex attribute.
0139 LibertyReader.cc:4597 %s is not a float.
0140 LibertyReader.cc:4620 %s is missing values.
0141 LibertyReader.cc:4623 %s has more than one string.
0142 LibertyReader.cc:4632 %s is missing values.
0143 LibertyReader.cc:4657 %s attribute is not boolean.
0144 LibertyReader.cc:4660 %s attribute is not boolean.
0145 LibertyReader.cc:4663 %s is not a simple attribute.
0146 LibertyReader.cc:4679 attribute %s value %s not recognized.
0147 LibertyReader.cc:4710 unknown early/late value.
0148 LibertyReader.cc:4930 OCV derate group named %s not found.
0149 LibertyReader.cc:4946 ocv_derate missing name.
0150 LibertyReader.cc:4999 unknown rise/fall.
0151 LibertyReader.cc:5019 unknown derate type.
0152 LibertyReader.cc:5051 unsupported model axis.
0153 LibertyReader.cc:5083 unsupported model axis.
0154 LibertyReader.cc:5115 unsupported model axis.
0155 LibertyReader.cc:5186 unknown pg_type.
0156 LibertyReader.cc:5581 port %s subscript out of range.
0157 LibertyReader.cc:5585 port range %s of non-bus port %s.
0158 LibertyReader.cc:5599 port %s not found.
0159 LibertyReader.cc:5669 port %s not found.
0160 LibertyReader.cc:1026 default_max_transition is 0.0.
0161 LibertyReader.cc:3413 max_transition is 0.0.
0162 LibertyReader.cc:4493 %s attribute is not an integer.
0163 LibertyReader.cc:1131 default_fanout_load is 0.0.
0164 LibertyReader.cc:2299 timing group from output port.
0165 LibertyReader.cc:2309 timing group from output port.
0166 LibertyReader.cc:2319 timing group from output port.
0167 LibertyReader.cc:2337 timing group from output port.
0168 LibertyReader.cc:2353 timing group from output port.
0169 LibertyReader.cc:4365 cell %s test_cell redefinition.
0170 LibertyReader.cc:3808 timing group missing related_pin/related_bus_pin.
0171 LibertyReader.cc:815 unknown unit suffix %s.
0179 SpefReader.cc:734 %s.
0190 VerilogReader.cc:1782 %s is not a verilog module.
0191 VerilogReader.cc:1787 %s is not a verilog module.
0201 StaTcl.i:118 no network has been linked.
0202 StaTcl.i:132 network does not support edits.
0204 StaTcl.i:4123 POCV support requires compilation with SSTA=1.
0204 StaTcl.i:4129 POCV support requires compilation with SSTA=1.
0206 LibertyExpr.cc:175 %s %s.
0207 GraphDelayCalc1.cc:738 port not found in cell
0208 Graph.cc:793 arc_delay_annotated array bounds exceeded
@ -184,20 +183,22 @@
0252 PathEnumed.cc:135 enumerated path required time
0253 PathGroup.cc:399 unknown path end type
0254 PathVertexRep.cc:145 tag group missing tag
0255 ReportPath.cc:287 unsupported path type
0256 ReportPath.cc:308 unsupported path type
0257 ReportPath.cc:347 unsupported path type
0259 ReportPath.cc:2376 unsupported path type
0260 Search.cc:2655 max tag group index exceeded
0261 Search.cc:2891 max tag index exceeded
0262 Search.cc:3618 unexpected filter path
0263 Search.cc:3786 tns incr existing vertex
0264 Sta.cc:4190 corresponding timing arc set not found in equiv cells
0255 ReportPath.cc:289 unsupported path type
0256 ReportPath.cc:310 unsupported path type
0257 ReportPath.cc:349 unsupported path type
0259 ReportPath.cc:2378 unsupported path type
0260 Search.cc:2654 max tag group index exceeded
0261 Search.cc:2890 max tag index exceeded
0262 Search.cc:3617 unexpected filter path
0263 Search.cc:3785 tns incr existing vertex
0264 Sta.cc:4215 corresponding timing arc set not found in equiv cells
0265 TagGroup.cc:297 tag group missing tag
0266 Sta.cc:2090 '%s' is not a valid endpoint.
0267 Sta.cc:2014 '%s' is not a valid start point.
0272 StaTcl.i:4109 unknown common clk pessimism mode.
0273 StaTcl.i:5055 unknown clock sense
0272 StaTcl.i:4115 unknown common clk pessimism mode.
0273 StaTcl.i:5064 unknown clock sense
0274 VerilogReader.cc:1782 %s is not a verilog module.
0275 VerilogReader.cc:1787 %s is not a verilog module.
0299 Power.tcl:241 activity cannot be set on clock ports.
0300 CmdUtil.tcl:44 no commands match '$pattern'.
0301 Power.tcl:218 activity should be 0.0 to 1.0 or 2.0
@ -205,11 +206,11 @@
0303 Sdc.tcl:1586 -clock ignored for clock objects.
0304 Sdc.tcl:2178 -from/-to keywords ignored for lib_pin, port and pin arguments.
0305 CmdArgs.tcl:166 object '$obj' not found.
0313 CmdArgs.tcl:842 unsupported object type $object_type.
0314 CmdArgs.tcl:857 $arg_name must be a single net.
0315 CmdArgs.tcl:863 $arg_name '$object_type' is not a net.
0316 CmdArgs.tcl:868 $arg_name '$arg' not found.
0318 Search.tcl:1057 unknown path group '$name'.
0313 CmdArgs.tcl:873 unsupported object type $object_type.
0314 CmdArgs.tcl:888 $arg_name must be a single net.
0315 CmdArgs.tcl:894 $arg_name '$object_type' is not a net.
0316 CmdArgs.tcl:899 $arg_name '$arg' not found.
0318 Search.tcl:1060 unknown path group '$name'.
0319 Sdc.tcl:288 $unit scale [format %.0e $scale] does not match library scale [format %.0e $unit_scale].
0320 Sdc.tcl:437 current_design for other than top cell not supported.
0321 Sdc.tcl:474 patterns argument not supported with -of_objects.
@ -262,7 +263,7 @@
0369 Sdc.tcl:3303 no valid objects specified for $key.
0370 Sdc.tcl:3336 no valid objects specified for $key
0371 Sdc.tcl:3497 set_wire_load_min_block_size not supported.
0372 NetworkEdit.tcl:129 connect_pins is deprecated. Use connect_pin.
0372 NetworkEdit.tcl:137 connect_pins is deprecated. Use connect_pin.
0373 Sdc.tcl:3647 define_corners must be called before read_liberty.
0374 Sta.cc:2416 maximum corner count exceeded
0400 Util.tcl:44 $cmd $key missing value.
@ -346,14 +347,14 @@
0480 CmdArgs.tcl:558 $arg_name type '$object_type' is not a library.
0481 CmdArgs.tcl:563 library '$arg' not found.
0482 CmdArgs.tcl:580 $arg_name must be a single lib cell.
0483 CmdArgs.tcl:636 $arg_name must be a single instance.
0484 CmdArgs.tcl:642 $arg_name type '$object_type' is not an instance.
0485 CmdArgs.tcl:647 instance '$arg' not found.
0486 CmdArgs.tcl:666 $arg_name type '$object_type' is not an instance.
0487 CmdArgs.tcl:673 instance '$arg' not found.
0488 CmdArgs.tcl:734 $arg_name type '$object_type' is not a pin or port.
0489 CmdArgs.tcl:741 pin '$arg' not found.
0490 CmdArgs.tcl:761 $arg_name type '$object_type' is not a port.
0483 CmdArgs.tcl:667 $arg_name must be a single instance.
0484 CmdArgs.tcl:673 $arg_name type '$object_type' is not an instance.
0485 CmdArgs.tcl:678 instance '$arg' not found.
0486 CmdArgs.tcl:697 $arg_name type '$object_type' is not an instance.
0487 CmdArgs.tcl:704 instance '$arg' not found.
0488 CmdArgs.tcl:765 $arg_name type '$object_type' is not a pin or port.
0489 CmdArgs.tcl:772 pin '$arg' not found.
0490 CmdArgs.tcl:792 $arg_name type '$object_type' is not a port.
0491 Property.tcl:32 $cmd object is null.
0492 Property.tcl:37 $cmd $type_key must be specified with object name argument.
0493 Property.tcl:80 get_property $object is not an object.
@ -444,13 +445,13 @@
0583 Sdc.tcl:3525 no wire load model specified.
0584 Sdc.tcl:3586 wire load selection group '$selection_name' not found.
0585 Sdc.tcl:3717 no default operating conditions found.
0586 NetworkEdit.tcl:99 unsupported object type $object_type.
0587 NetworkEdit.tcl:198 unsupported object type $object_type.
0588 NetworkEdit.tcl:216 unsupported object type $object_type.
0586 NetworkEdit.tcl:107 unsupported object type $object_type.
0587 NetworkEdit.tcl:206 unsupported object type $object_type.
0588 NetworkEdit.tcl:224 unsupported object type $object_type.
0589 CmdUtil.tcl:226 unknown namespace $namespc.
0590 Network.tcl:35 instance $instance_path not found.
0591 Network.tcl:241 net $net_path not found.
0592 Network.tcl:244 net $net_path not found.
0591 Network.tcl:221 net $net_path not found.
0592 Network.tcl:224 net $net_path not found.
0593 Link.tcl:34 missing top_cell_name argument and no current_design.
0594 DelayNormal1.cc:203 unknown early/late value.
0595 DelayNormal2.cc:378 unknown early/late value.
@ -462,13 +463,13 @@
0604 Sdc.tcl:281 unknown $unit prefix '$prefix'.
0605 Sdc.tcl:3547 wire load model '$model_name' not found.
0606 Property.tcl:77 get_property unsupported object type $object_type.
0607 StaTcl.i:4359 unknown report path field %s
0608 StaTcl.i:4371 unknown report path field %s
0607 StaTcl.i:4367 unknown report path field %s
0608 StaTcl.i:4379 unknown report path field %s
0609 Search.tcl:411 -all_violators is deprecated. Use -violators
0610 Search.tcl:491 -max_transition deprecated. Use -max_slew.
0611 Search.tcl:496 -min_transition deprecated. Use -min_slew.
0612 Sdf.tcl:41 -cond_use must be min, max or min_max.
0616 Search.tcl:1008 specify one of -setup and -hold.
0616 Search.tcl:1011 specify one of -setup and -hold.
0617 Sdf.tcl:50 -analysis_type is deprecated. Use set_operating_conditions -analysis_type.
0618 DmpCeff.cc:1581 parasitic Pi model has NaNs.
0619 PathEnum.cc:474 path diversion missing edge.
@ -477,13 +478,14 @@
0622 PathVertex.cc:279 missing requireds.
0623 PathVertexRep.cc:153 missing arrivals.
0624 PathVertexRep.cc:150 missing arrivals
0701 LibertyWriter.cc:411 %s/%s/%s timing model not supported.
0702 LibertyWriter.cc:431 3 axis table models not supported.
0703 LibertyWriter.cc:571 %s/%s/%s timing arc type %s not supported.
0704 LibertyWriter.cc:284 %s/%s bundled ports not supported.
0625 Liberty.tcl:33 -no_latch_infer is deprecated.
0701 LibertyWriter.cc:413 %s/%s/%s timing model not supported.
0702 LibertyWriter.cc:433 3 axis table models not supported.
0703 LibertyWriter.cc:573 %s/%s/%s timing arc type %s not supported.
0704 LibertyWriter.cc:286 %s/%s bundled ports not supported.
0705 Liberty.cc:815 Liberty cell %s/%s for corner %s/%s not found.
0706 Parasitics.tcl:70 read_spef -increment is deprecated.
0710 LumpedCapDelayCalc.cc:169 gate delay input variable is NaN
0710 LumpedCapDelayCalc.cc:173 gate delay input variable is NaN
0800 VcdReader.cc:110 unhandled vcd command.
0801 VcdReader.cc:146 timescale syntax error.
0802 VcdReader.cc:160 Unknown timescale unit.
@ -491,16 +493,17 @@
0805 Vcd.cc:172 Unknown variable %s ID %s
0806 ReadVcdActivities.cc:247 clock %s vcd period %s differs from SDC clock period %s
0807 Sdc.tcl:394 only one of -cells, -data_pins, -clock_pins, -async_pins, -output_pins are suppported.
0810 MakeTimingModel.cc:202 clock %s pin %s is inside model block.
0900 LibertyReader.cc:2834 level_shifter_type must be HL, LH, or HL_LH
0901 LibertyReader.cc:2870 switch_cell_type must be coarse_grain or fine_grain
0902 LibertyReader.cc:2452 unsupported model axis.
0903 LibertyReader.cc:4213 %s group not in timing group.
0904 LibertyReader.cc:2435 receiver_capacitance group not in timing or pin group.
0906 LibertyReader.cc:4106 unsupported model axis.
0907 LibertyReader.cc:2480 output_current_%s group not in timing group.
0908 LibertyReader.cc:2585 vector reference_time not found.
0912 LibertyReader.cc:2583 vector index_1 and index_2 must have exactly one value.
0913 LibertyReader.cc:2521 output current waveform %.2e %.2e not found.
0914 LibertyReader.cc:2618 normalized_driver_waveform variable_2 must be normalized_voltage
0915 LibertyReader.cc:2621 normalized_driver_waveform variable_1 must be input_net_transition
0810 MakeTimingModel.cc:203 clock %s pin %s is inside model block.
0900 LibertyReader.cc:2817 level_shifter_type must be HL, LH, or HL_LH
0901 LibertyReader.cc:2853 switch_cell_type must be coarse_grain or fine_grain
0902 LibertyReader.cc:2437 unsupported model axis.
0903 LibertyReader.cc:4144 %s group not in timing group.
0904 LibertyReader.cc:2420 receiver_capacitance group not in timing or pin group.
0906 LibertyReader.cc:4037 unsupported model axis.
0907 LibertyReader.cc:2465 output_current_%s group not in timing group.
0908 LibertyReader.cc:2570 vector reference_time not found.
0912 LibertyReader.cc:2568 vector index_1 and index_2 must have exactly one value.
0913 LibertyReader.cc:2506 output current waveform %.2e %.2e not found.
0914 LibertyReader.cc:2603 normalized_driver_waveform variable_2 must be normalized_voltage
0915 LibertyReader.cc:2606 normalized_driver_waveform variable_1 must be input_net_transition
1640 Search.tcl:904 The transition_time field is deprecated. Use slew instead.

18
search/ReportPath.cc
View File

@ -122,7 +122,7 @@ ReportPath::ReportPath(StaState *sta) :
{
setDigits(2);
makeFields();
setReportFields(false, false, false, false);
setReportFields(false, false, false, false, false);
}
ReportPath::~ReportPath()
@ -224,7 +224,8 @@ void
ReportPath::setReportFields(bool report_input_pin,
bool report_net,
bool report_cap,
bool report_slew)
bool report_slew,
bool report_fanout)
{
report_input_pin_ = report_input_pin;
report_net_ = report_net;
@ -232,6 +233,7 @@ ReportPath::setReportFields(bool report_input_pin,
field_fanout_->setEnabled(report_net_);
field_capacitance_->setEnabled(report_cap);
field_slew_->setEnabled(report_slew);
field_fanout_->setEnabled(report_fanout);
// for debug
field_case_->setEnabled(false);
}
@ -2648,13 +2650,16 @@ ReportPath::reportPath5(const Path *path,
&& !prev_arc->role()->isWire())) {
bool is_driver = network_->isDriver(pin);
float cap = field_blank_;
float fanout = field_blank_;
// Don't show capacitance field for input pins.
if (is_driver && field_capacitance_->enabled())
cap = loadCap(pin, rf, dcalc_ap);
// Don't show fanout field for input pins.
if (is_driver && field_fanout_->enabled())
fanout = drvrFanout(vertex, dcalc_ap->corner(), min_max);
auto what = descriptionField(vertex);
if (report_net_ && is_driver) {
// Capacitance field is reported on the net line.
reportLine(what.c_str(), field_blank_, slew, field_blank_,
reportLine(what.c_str(), cap, slew, fanout,
incr, time, false, min_max, rf, line_case);
string what2;
if (network_->isTopLevelPort(pin)) {
@ -2671,13 +2676,12 @@ ReportPath::reportPath5(const Path *path,
else
what2 = "(unconnected)";
}
float fanout = drvrFanout(vertex, dcalc_ap->corner(), min_max);
reportLine(what2.c_str(), cap, field_blank_, fanout,
reportLine(what2.c_str(), field_blank_, field_blank_, field_blank_,
field_blank_, field_blank_, false, min_max,
nullptr, line_case);
}
else
reportLine(what.c_str(), cap, slew, field_blank_,
reportLine(what.c_str(), cap, slew, fanout,
incr, time, false, min_max, rf, line_case);
prev_time = time;
}

3
search/ReportPath.hh
View File

@ -43,7 +43,8 @@ public:
void setReportFields(bool report_input_pin,
bool report_net,
bool report_cap,
bool report_slew);
bool report_slew,
bool report_fanout);
int digits() const { return digits_; }
void setDigits(int digits);
void setNoSplit(bool no_split);

5
search/Sta.cc
View File

@ -2506,10 +2506,11 @@ void
Sta::setReportPathFields(bool report_input_pin,
bool report_net,
bool report_cap,
bool report_slew)
bool report_slew,
bool report_fanout)
{
report_path_->setReportFields(report_input_pin, report_net, report_cap,
report_slew);
report_slew, report_fanout);
}
ReportField *

20
tcl/Network.tcl
View File

@ -184,26 +184,6 @@ proc report_lib_cell_ { cell corner } {
$iter finish
}
proc report_cell_ { cell } {
set lib [$cell library]
report_line "Cell [get_name $cell]"
report_line "Library [get_name $lib]"
set filename [liberty_cell_property $cell "filename"]
if { $filename != "" } {
report_line "File $filename"
}
set iter [$cell port_iterator]
while {[$iter has_next]} {
set port [$iter next]
if { [$port is_bus] } {
report_line " [$port bus_name] [port_direction $port]"
} else {
report_line " [get_name $port] [port_direction $port]"
}
}
$iter finish
}
################################################################
define_cmd_args "report_net" \

11
tcl/Search.tcl
View File

@ -898,17 +898,20 @@ proc parse_report_path_options { cmd args_var default_format
set report_input_pin [expr [lsearch $fields "input*"] != -1]
set report_cap [expr [lsearch $fields "cap*"] != -1]
set report_net [expr [lsearch $fields "net*"] != -1]
# transition_time - compatibility 06/24/2019
set report_slew [expr [lsearch $fields "slew*"] != -1 \
|| [lsearch $fields "trans*"] != -1]
set report_slew [expr [lsearch $fields "slew*"] != -1]
set report_fanout [expr [lsearch $fields "fanout*"] != -1]
if { [expr [lsearch $fields "trans*"] != -1] } {
sta_warn 1640 "The transition_time field is deprecated. Use slew instead."
}
} else {
set report_input_pin 0
set report_cap 0
set report_net 0
set report_slew 0
set report_fanout 0
}
set_report_path_fields $report_input_pin $report_net \
$report_cap $report_slew
$report_cap $report_slew $report_fanout
set_report_path_no_split [info exists path_options(-no_line_splits)]
}

6
tcl/StaTcl.i
View File

@ -4343,12 +4343,14 @@ void
set_report_path_fields(bool report_input_pin,
bool report_net,
bool report_cap,
bool report_slew)
bool report_slew,
bool report_fanout)
{
Sta::sta()->setReportPathFields(report_input_pin,
report_net,
report_cap,
report_slew);
report_slew,
report_fanout);
}
void

4
verilog/VerilogReader.cc
View File

@ -1779,12 +1779,12 @@ VerilogReader::linkNetwork(const char *top_cell_name,
return top_instance;
}
else {
report->error(190, "%s is not a verilog module.", top_cell_name);
report->error(274, "%s is not a verilog module.", top_cell_name);
return nullptr;
}
}
else {
report->error(191, "%s is not a verilog module.", top_cell_name);
report->error(275, "%s is not a verilog module.", top_cell_name);
return nullptr;
}
}