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OpenSTA
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Merge branch 'master' into gc_arrivals

This commit is contained in:
James Cherry 2021-09-17 19:35:59 -07:00
parent d25f6878a2 85f437bc59
commit 24e5b5bed2
5 changed files with 32 additions and 24 deletions
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12
graph/Graph.cc
View File

@ -343,11 +343,13 @@ Graph::makeWireEdge(Pin *from_pin,
Vertex *from_vertex, *from_bidirect_drvr_vertex; Vertex *from_vertex, *from_bidirect_drvr_vertex;
pinVertices(from_pin, from_vertex, from_bidirect_drvr_vertex); pinVertices(from_pin, from_vertex, from_bidirect_drvr_vertex);
Vertex *to_vertex = pinLoadVertex(to_pin); Vertex *to_vertex = pinLoadVertex(to_pin);
// From and/or to can be bidirect, but edge is always from driver to load. if (from_vertex && to_vertex) {
if (from_bidirect_drvr_vertex) // From and/or to can be bidirect, but edge is always from driver to load.
makeEdge(from_bidirect_drvr_vertex, to_vertex, arc_set); if (from_bidirect_drvr_vertex)
else makeEdge(from_bidirect_drvr_vertex, to_vertex, arc_set);
makeEdge(from_vertex, to_vertex, arc_set); else
makeEdge(from_vertex, to_vertex, arc_set);
}
} }
//////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////

2
include/sta/Sta.hh
View File

@ -897,6 +897,8 @@ public:
// loops until the arrivals converge. // loops until the arrivals converge.
// If full=false update arrivals incrementally. // If full=false update arrivals incrementally.
// If full=true update all arrivals from scratch. // If full=true update all arrivals from scratch.
// There is rarely any reason to call updateTiming directly because
// arrival/required/slack functions implicitly update timing incrementally.
void updateTiming(bool full); void updateTiming(bool full);
// Invalidate all delay calculations. Arrivals also invalidated. // Invalidate all delay calculations. Arrivals also invalidated.
void delaysInvalid(); void delaysInvalid();

4
network/Network.cc
View File

@ -521,7 +521,9 @@ Network::isLoad(const Pin *pin) const
const Instance *inst = instance(pin); const Instance *inst = instance(pin);
return (isLeaf(inst) && dir->isAnyInput()) return (isLeaf(inst) && dir->isAnyInput())
// isTopLevelPort(pin) // isTopLevelPort(pin)
|| (isTopInstance(inst) && dir->isAnyOutput()); || (isTopInstance(inst) && dir->isAnyOutput())
// Black box unknown ports are treated as loads.
|| dir->isUnknown();
} }
bool bool

34
search/Sta.cc
View File

@ -4135,23 +4135,25 @@ Sta::connectPinAfter(Pin *pin)
else { else {
Vertex *vertex, *bidir_drvr_vertex; Vertex *vertex, *bidir_drvr_vertex;
graph_->pinVertices(pin, vertex, bidir_drvr_vertex); graph_->pinVertices(pin, vertex, bidir_drvr_vertex);
search_->arrivalInvalid(vertex); if (vertex) {
search_->requiredInvalid(vertex); search_->arrivalInvalid(vertex);
if (bidir_drvr_vertex) { search_->requiredInvalid(vertex);
search_->arrivalInvalid(bidir_drvr_vertex); if (bidir_drvr_vertex) {
search_->requiredInvalid(bidir_drvr_vertex); search_->arrivalInvalid(bidir_drvr_vertex);
} search_->requiredInvalid(bidir_drvr_vertex);
}
// Make interconnect edges from/to pin. // Make interconnect edges from/to pin.
if (network_->isDriver(pin)) { if (network_->isDriver(pin)) {
graph_->makeWireEdgesFromPin(pin); graph_->makeWireEdgesFromPin(pin);
connectDrvrPinAfter(bidir_drvr_vertex ? bidir_drvr_vertex : vertex); connectDrvrPinAfter(bidir_drvr_vertex ? bidir_drvr_vertex : vertex);
} }
// Note that a bidirect is both a driver and a load so this // Note that a bidirect is both a driver and a load so this
// is NOT an else clause for the above "if". // is NOT an else clause for the above "if".
if (network_->isLoad(pin)) { if (network_->isLoad(pin)) {
graph_->makeWireEdgesToPin(pin); graph_->makeWireEdgesToPin(pin);
connectLoadPinAfter(vertex); connectLoadPinAfter(vertex);
}
} }
} }
} }

4
verilog/VerilogReader.cc
View File

@ -2058,7 +2058,7 @@ VerilogReader::makeBlackBoxNamedPorts(Cell *cell,
Port *port = (size == 1) Port *port = (size == 1)
? network_->makePort(cell, port_name) ? network_->makePort(cell, port_name)
: network_->makeBusPort(cell, port_name, 0, size - 1); : network_->makeBusPort(cell, port_name, 0, size - 1);
network_->setDirection(port, PortDirection::bidirect()); network_->setDirection(port, PortDirection::unknown());
} }
} }
@ -2077,7 +2077,7 @@ VerilogReader::makeBlackBoxOrderedPorts(Cell *cell,
? network_->makePort(cell, port_name) ? network_->makePort(cell, port_name)
: network_->makeBusPort(cell, port_name, size - 1, 0); : network_->makeBusPort(cell, port_name, size - 1, 0);
stringDelete(port_name); stringDelete(port_name);
network_->setDirection(port, PortDirection::bidirect()); network_->setDirection(port, PortDirection::unknown());
port_index++; port_index++;
} }
} }