clang tidy

Signed-off-by: James Cherry <cherry@parallaxsw.com>

.clang-tidy

@@ -59,6 +59,7 @@ Checks: >
   -modernize-use-transparent-functors,
   misc-*,
   -misc-const-correctness,
+  -misc-multiple-inheritance,
   -misc-no-recursion,
   -misc-non-private-member-variables-in-classes,
   -misc-redundant-expression,
@@ -72,6 +73,8 @@ Checks: >
 # Excludes system and third-party paths such as /opt/local/include.
 HeaderFilterRegex: '.*/(app|cmake|dcalc|graph|liberty|network|parasitics|power|sdc|sdf|search|spice|tcl|util|verilog|include/sta|build/include/sta)/.*'
 
-# Bison-generated parser headers (build/{Liberty,Verilog,...}Parse.hh); gzstream (e.g. util/gzstream.hh).
+# util/gzstream.hh
-ExcludeHeaderFilterRegex: '.*/(gzstream\.h(?:h)?|(?:Liberty|Verilog|Sdf|Spef|Saif|LibExpr)Parse\.hh)$'
+# util/FlexDisableRegister.hh
+# Bison-generated parser headers (build/{Liberty,Verilog,...}Parse.hh)
+ExcludeHeaderFilterRegex: '(.*/)?(gzstream\.hh|FlexDisableRegister\.hh|(Liberty|Verilog|Sdf|Spef|Saif|LibExpr)Parse\.hh)$'
 FormatStyle: none

dcalc/ArcDcalcWaveforms.cc

@@ -22,16 +22,16 @@
 // 
 // This notice may not be removed or altered from any source distribution.
 
-#include <memory>
-
 #include "ArcDcalcWaveforms.hh"
 
-#include "Report.hh"
+#include <memory>
+
+#include "ArcDelayCalc.hh"
+#include "Graph.hh"
+#include "GraphDelayCalc.hh"
 #include "Liberty.hh"
 #include "Network.hh"
-#include "Graph.hh"
+#include "Report.hh"
-#include "ArcDelayCalc.hh"
-#include "GraphDelayCalc.hh"
 
 namespace sta {
 

dcalc/ArcDelayCalc.cc

@@ -27,12 +27,12 @@
 #include <cstdlib>
 #include <string>
 
-#include "StringUtil.hh"
-#include "Units.hh"
-#include "Liberty.hh"
-#include "TimingArc.hh"
-#include "Network.hh"
 #include "Graph.hh"
+#include "Liberty.hh"
+#include "Network.hh"
+#include "StringUtil.hh"
+#include "TimingArc.hh"
+#include "Units.hh"
 
 namespace sta {
 
@@ -165,17 +165,7 @@ ArcDcalcArg::ArcDcalcArg(const Pin *in_pin,
 {
 }
 
-ArcDcalcArg::ArcDcalcArg(const ArcDcalcArg &arg) :
+ArcDcalcArg::ArcDcalcArg(const ArcDcalcArg &arg) = default;
-  in_pin_(arg.in_pin_),
-  drvr_pin_(arg.drvr_pin_),
-  edge_(arg.edge_),
-  arc_(arg.arc_),
-  in_slew_(arg.in_slew_),
-  load_cap_(arg.load_cap_),
-  parasitic_(arg.parasitic_),
-  input_delay_(arg.input_delay_)
-{
-}
 
 const RiseFall *
 ArcDcalcArg::inEdge() const

dcalc/Arnoldi.hh

@@ -45,7 +45,7 @@ class arnoldi1
 public:
   arnoldi1() { order=0; n=0; d=nullptr; e=nullptr; U=nullptr; ctot=0.0; sqc=0.0; }
   ~arnoldi1();
-  double elmore(int term_index);
+  double elmore(int k);
 
   //
   // calculate poles/residues for given rdrive
@@ -70,12 +70,12 @@ class rcmodel : public ConcreteParasitic,
 {
 public:
   rcmodel();
-  virtual ~rcmodel();
+  ~rcmodel() override;
-  virtual float capacitance() const;
+  float capacitance() const override;
-  virtual PinSet unannotatedLoads(const Pin *drvr_pin,
+  PinSet unannotatedLoads(const Pin *drvr_pin,
-                                  const Parasitics *parasitics) const;
+                          const Parasitics *parasitics) const override;
 
-  const Pin **pinV; // [n]
+  const Pin **pinV{nullptr}; // [n]
 };
 
 struct timing_table

dcalc/ArnoldiDelayCalc.cc

@@ -28,30 +28,34 @@
 
 #include "ArnoldiDelayCalc.hh"
 
-#include <cstdio>
+#include <algorithm>
 #include <cmath> // abs
+#include <cstddef>
+#include <cstdio>
+#include <numbers>
 
-#include "Report.hh"
-#include "Debug.hh"
-#include "Units.hh"
-#include "Liberty.hh"
-#include "TimingModel.hh"
-#include "TimingArc.hh"
-#include "TableModel.hh"
-#include "PortDirection.hh"
-#include "Network.hh"
-#include "Graph.hh"
-#include "Parasitics.hh"
-#include "Sdc.hh"
-#include "DelayCalc.hh"
 #include "ArcDelayCalc.hh"
-#include "LumpedCapDelayCalc.hh"
-#include "GraphDelayCalc.hh"
-#include "Variables.hh"
 #include "Arnoldi.hh"
 #include "ArnoldiReduce.hh"
+#include "Debug.hh"
+#include "DelayCalc.hh"
+#include "Graph.hh"
+#include "GraphDelayCalc.hh"
+#include "Liberty.hh"
+#include "LumpedCapDelayCalc.hh"
+#include "Network.hh"
+#include "Parasitics.hh"
+#include "PortDirection.hh"
+#include "Report.hh"
+#include "Sdc.hh"
+#include "TableModel.hh"
+#include "TimingArc.hh"
+#include "TimingModel.hh"
+#include "Units.hh"
+#include "Variables.hh"
 
 namespace sta {
+// NOLINTBEGIN(modernize-avoid-c-style-cast)
 
 // wireload8 is n^2
 // do not delete arnoldi parasitics
@@ -76,7 +80,11 @@ delay_work_get_residues(delay_work *D,
                         int term_index);
 
 static bool
-tridiagEV(int n,double *d,double *e,double *p,double **v);
+tridiagEV(int n,
+          const double *din,
+          const double *ein,
+          double *d,
+          double **v);
 
 //////////////////////////////////////////////////////////////
 
@@ -229,7 +237,7 @@ private:
                  double *c_x1,
                  double *c_y1);
 
-  rcmodel *rcmodel_;
+  rcmodel *rcmodel_{nullptr};
   int _pinNmax;
   double *_delayV;
   double *_slewV;
@@ -246,7 +254,6 @@ makeArnoldiDelayCalc(StaState *sta)
 
 ArnoldiDelayCalc::ArnoldiDelayCalc(StaState *sta) :
   LumpedCapDelayCalc(sta),
-  rcmodel_(nullptr),
   reduce_(new ArnoldiReduce(sta)),
   delay_work_(delay_work_create())
 {
@@ -362,7 +369,7 @@ ArnoldiDelayCalc::inputPortDelay(const Pin *,
 
     for (int j=1;j<pin_n_;j++) {
       double elmore = rcmodel_->elmore(j);
-      double wire_delay = 0.6931472*elmore;
+      double wire_delay = std::numbers::ln2 * elmore;
       double load_slew = in_slew + c_log*elmore/slew_derate;
       _delayV[j] = wire_delay;
       _slewV[j] = load_slew;
@@ -487,7 +494,7 @@ ArnoldiDelayCalc::reportGateDelay(const Pin *drvr_pin,
 arnoldi1::~arnoldi1()
 {
   free(d);
-  free(U);
+  free(reinterpret_cast<void *>(U));
 }
 
 double
@@ -506,13 +513,16 @@ delay_work_create()
   int j;
   delay_work *D = (delay_work*)malloc(sizeof(delay_work));
   D->nmax = 256;
-  D->resi = (double**)malloc(D->nmax*sizeof(double*));
+  D->resi = (double**)malloc(static_cast<size_t>(D->nmax) * sizeof(double *));
-  D->resi[0] = (double*)malloc(D->nmax*32*sizeof(double));
+  D->resi[0] = (double*)malloc(static_cast<size_t>(D->nmax) * 32u * sizeof(double));
-  for (j=1;j<D->nmax;j++) D->resi[j] = D->resi[0] + j*32;
+  for (j=1;j<D->nmax;j++)
-  D->v[0] = (double*)malloc(32*32*sizeof(double));
+    D->resi[j] = D->resi[0] + static_cast<ptrdiff_t>(j) * 32;
-  for (j=1;j<32;j++) D->v[j] = D->v[0] + j*32;
+  D->v[0] = (double*)malloc(static_cast<size_t>(32) * 32u * sizeof(double));
-  D->w[0] = (double*)malloc(32*D->nmax*sizeof(double));
+  for (j=1;j<32;j++)
-  for (j=1;j<32;j++) D->w[j] = D->w[0] + j*D->nmax;
+    D->v[j] = D->v[0] + static_cast<ptrdiff_t>(j) * 32;
+  D->w[0] = (double*)malloc(32u * static_cast<size_t>(D->nmax) * sizeof(double));
+  for (j=1;j<32;j++)
+    D->w[j] = D->w[0] + static_cast<ptrdiff_t>(j) * D->nmax;
   D->lo_thresh = 0.0;
   D->hi_thresh = 0.0;
   D->slew_derate = 0.0;
@@ -535,7 +545,7 @@ static void
 delay_work_destroy(delay_work *D)
 {
   free(D->resi[0]);
-  free(D->resi);
+  free(reinterpret_cast<void *>(D->resi));
   free(D->v[0]);
   free(D->w[0]);
   free(D);
@@ -547,15 +557,17 @@ delay_work_alloc(delay_work *D,int n)
   if (n<=D->nmax) return;
   free(D->w[0]);
   free(D->resi[0]);
-  free(D->resi);
+  free(reinterpret_cast<void *>(D->resi));
   D->nmax *= 2;
-  if (n > D->nmax) D->nmax = n;
+  D->nmax = std::max(n, D->nmax);
   int j;
-  D->resi = (double**)malloc(D->nmax*sizeof(double*));
+  D->resi = (double**)malloc(static_cast<size_t>(D->nmax) * sizeof(double *));
-  D->resi[0] = (double*)malloc(D->nmax*32*sizeof(double));
+  D->resi[0] = (double*)malloc(static_cast<size_t>(D->nmax) * 32u * sizeof(double));
-  for (j=1;j<D->nmax;j++) D->resi[j] = D->resi[0] + j*32;
+  for (j=1;j<D->nmax;j++)
-  D->w[0] = (double*)malloc(32*D->nmax*sizeof(double));
+    D->resi[j] = D->resi[0] + static_cast<ptrdiff_t>(j) * 32;
-  for (j=1;j<32;j++) D->w[j] = D->w[0] + j*D->nmax;
+  D->w[0] = (double*)malloc(32u * static_cast<size_t>(D->nmax) * sizeof(double));
+  for (j=1;j<32;j++)
+    D->w[j] = D->w[0] + static_cast<ptrdiff_t>(j) * D->nmax;
 }
 
 void
@@ -622,8 +634,7 @@ void arnoldi1::calculate_poles_res(delay_work *D,
   d[0] = dsave;
 
   for (h=0;h<order;h++) {
-    if (p[h]<1e-14) // .01ps
+    p[h] = std::max(p[h], 1e-14); // .01ps floor
-      p[h]=1e-14;
     p[h] = 1.0/p[h];
   }
 
@@ -653,10 +664,10 @@ void arnoldi1::calculate_poles_res(delay_work *D,
 //  tridiagonal eigenvalues and eigenvectors
 //   assuming all eigenvalues are positive
 //
-//  tridiagEV(int n,double *d,double *e,double *p,double **v)
+//  tridiagEV(n, din, ein, d, v)
-//   d[0]..d[n-1]  diagonal elements
+//   din[0]..din[n-1]  diagonal elements (input)
-//   e[0]..e[n-2]  off-diagonal elements
+//   ein[0]..ein[n-2]  off-diagonal elements (input)
-//   p[0],..p[n-1] the eigenvalues
+//   d[0],..d[n-1] the eigenvalues (output)
 //   v[0],..v[n-1] the eigenvectors
 //    M*v[j] = p[j]*v[j]
 //
@@ -665,7 +676,11 @@ void arnoldi1::calculate_poles_res(delay_work *D,
 //   (M*v[j])[n-1] = d[n-1]*v[j][n-1]+e[n-2]*v[j][n-2]
 //
 static bool
-tridiagEV(int n,double *din,double *ein,double *d,double **v)
+tridiagEV(int n,
+          const double *din,
+          const double *ein,
+          double *d,
+          double **v)
 {
   int j,k;
   for (j=0;j<n;j++) for (k=0;k<n;k++) v[j][k]=0.0;
@@ -747,7 +762,12 @@ tridiagEV(int n,double *din,double *ein,double *d,double **v)
 
 // get a waveform point
 static void
-pr_get_v(double t, double s, int order, double *p, double *rr, double *va)
+pr_get_v(double t,
+         double s,
+         int order,
+         const double *p,
+         const double *rr,
+         double *va)
 {
   *va = 0.0;
   int h;
@@ -765,8 +785,13 @@ pr_get_v(double t, double s, int order, double *p, double *rr, double *va)
 }
 
 static void
-get_dv(double t, double s, int order, double *p, double *rr,
+get_dv(double t,
-       double *va, double *dva)
+       double s,
+       int order,
+       const double *p,
+       const double *rr,
+       double *va,
+       double *dva)
 {
   *va = 0.0;
   *dva = 0.0;
@@ -790,12 +815,19 @@ get_dv(double t, double s, int order, double *p, double *rr,
 }
 
 static double
-solve_t_bracketed(double s,int order,double *p,double *rr,
+solve_t_bracketed(double s,
-                  double val,double x1,double x2,double v1,double v2)
+                  int order,
+                  const double *p,
+                  const double *rr,
+                  double val,
+                  double x1,
+                  double x2,
+                  double v1,
+                  double v2)
 {
   int j;
   double df,dx,dxold,f,f2,f1;
-  double temp,xh,xl,rts;
+  double temp,xh,x_lo,rts;
   double xacc = .001e-12; // .001ps
   f1 = v1-val;
   f2 = v2-val;
@@ -803,12 +835,12 @@ solve_t_bracketed(double s,int order,double *p,double *rr,
   if (f2==0.0) return x2;
   rts = (f1*x2-f2*x1)/(f1-f2);
   if (f1<f2) {
-    xl = x1;
+    x_lo = x1;
     xh = x2;
     if (0.0<f1) return x1;
     if (f2<0.0) return x2;
   } else {
-    xl = x2;
+    x_lo = x2;
     xh = x1;
     if (0.0<f2) return x2;
     if (f1<0.0) return x1;
@@ -819,19 +851,19 @@ solve_t_bracketed(double s,int order,double *p,double *rr,
   f -= val;
   double flast = 0.0;
   for (j=1;j<10;j++) {
-    if ((((rts-xh)*df-f)*((rts-xl)*df-f) >= 0.0)
+    if ((((rts-xh)*df-f)*((rts-x_lo)*df-f) >= 0.0)
         || (std::abs(2.0*f) > std::abs(dxold*df))) {
       dxold = dx;
-      dx = 0.5*(xh-xl);
+      dx = 0.5*(xh-x_lo);
       if (flast*f >0.0) {
         // 2 successive bisections in same direction,
         // accelerate
-        if (f<0.0) dx = 0.9348*(xh-xl);
+        if (f<0.0) dx = 0.9348*(xh-x_lo);
-        else dx = 0.0625*(xh-xl);
+        else dx = 0.0625*(xh-x_lo);
       }
       flast = f;
-      rts = xl+dx;
+      rts = x_lo+dx;
-      if (xl == rts) {
+      if (x_lo == rts) {
         return rts;
       }
     } else {
@@ -849,13 +881,13 @@ solve_t_bracketed(double s,int order,double *p,double *rr,
     }
     get_dv(rts,s,order,p,rr,&f,&df); f -= val;
     if (f<0.0)
-      xl = rts;
+      x_lo = rts;
     else
       xh = rts;
   }
   if (std::abs(f)<1e-6) // 1uV
     return rts;
-  return 0.5*(xl+xh);
+  return 0.5*(x_lo+xh);
 }
 
 void
@@ -949,8 +981,7 @@ ArnoldiDelayCalc::pr_solve3(double s,
     for (h=1;h<order;h++) if (rr[h]>0.3 && rr[h]>rr[0]) { h0 = h; break; }
   }
   double p0 = p[h0];
-  if (p0>10e+9)  // 1/10ns
+  p0 = std::min(p0, 10e+9);  // 1/10ns cap
-    p0=10e+9;
   double ps,vs,ta,va;
   vs = 0.0;
   for (h=0;h<order;h++) {
@@ -1034,7 +1065,9 @@ ArnoldiDelayCalc::pr_solve3(double s,
     ta = s + 0.7/p0;
     pr_get_v(ta,s,order,p,rr,&va);
     while (va>vmid) {
-      tmin5 = tmin8 = ta; vmin5 = tmin8 = va;
+      tmin5 = ta;
+      tmin8 = ta;
+      vmin5 = va;
       ta += 0.7/p0;
       pr_get_v(ta,s,order,p,rr,&va);
     }
@@ -1064,18 +1097,14 @@ ArnoldiDelayCalc::pr_solve3(double s,
       pr_get_v(ta,s,order,p,rr,&va);
     }
     tmax2 = ta; vmax2 = va;
-    if (va < vmid) {
+    while (va > vmid) {
-      tmax5 = ta; vmax5 = va;
-    } else while (va > vmid) {
       tmin5 = tmin8 = ta;
       vmin5 = vmin8 = va;
       ta += 1.0/p0;
       pr_get_v(ta,s,order,p,rr,&va);
     }
     tmax5 = ta; vmax5 = va;
-    if (va < vlo) {
+    while (va > vlo) {
-      tmax8 = ta; vmax8 = va;
-    } else while (va > vlo) {
       tmin8 = ta;
       vmin8 = va;
       ta += 1.0/p0;
@@ -1248,11 +1277,12 @@ ArnoldiDelayCalc::ra_solve_for_s(delay_work *D,
 
   if (x <= x1) {
     y = y1 - 0.5*(x-x1);
-    if (y>1.0) y=1.0;
+    y = std::min(y, 1.0);
   } else {
     y =  y1 - (x-x1)*(0.5 + 8*(x-x1));
-    if (y<y2) y=y2;
+    y = std::max(y, y2);
   }
+  (void)y;
 
   ra_solve_for_pt(p*s,vlo,&ptlo,&dlo);
   ra_solve_for_pt(p*s,vhi,&pthi,&dhi);
@@ -1405,7 +1435,6 @@ ArnoldiDelayCalc::ar1_ceff_delay(delay_work *D,
   if (rdelay == 0.0) {
     rdelay = 1e+3; // 1kohm
   }
-  r = rdelay;
   r = ra_get_r(D,tab,rdelay,ctot);
   if (! (r>0.0
          && r<100e+3)) // 100khom
@@ -1436,9 +1465,6 @@ ArnoldiDelayCalc::ar1_ceff_delay(delay_work *D,
                units_->timeUnit()->asString(tlox-thix));
   }
   ceff = ctot;
-  tab->table->gateDelay(tab->pvt, tab->in_slew, ceff, df, sf);
-  t50_sy = delayAsFloat(df);
-  t50_sr = ra_solve_for_t(1.0/(r*ceff),s,0.5);
 
   // calculate s,r,mod -> t50_srmod,
   // then   t50_srmod+t50_sy-t50_sr
@@ -1488,4 +1514,5 @@ ArnoldiDelayCalc::ar1_ceff_delay(delay_work *D,
   }
 }
 
+// NOLINTEND(modernize-avoid-c-style-cast)
 } // namespace sta

dcalc/ArnoldiReduce.cc

@@ -28,19 +28,22 @@
 
 #include "ArnoldiReduce.hh"
 
-#include "Debug.hh"
+#include <algorithm>
-#include "MinMax.hh"
+
-#include "Sdc.hh"
-#include "Network.hh"
-#include "Units.hh"
 #include "Arnoldi.hh"
+#include "Debug.hh"
 #include "Format.hh"
+#include "MinMax.hh"
+#include "Network.hh"
+#include "Sdc.hh"
+#include "Units.hh"
 #include "parasitics/ConcreteParasiticsPvt.hh"
 
 namespace sta {
+// This is legacy C-style code.
+// NOLINTBEGIN(modernize-avoid-c-style-cast, bugprone-multi-level-implicit-pointer-conversion, bugprone-implicit-widening-of-multiplication-result)
 
-rcmodel::rcmodel() :
+rcmodel::rcmodel()
-  pinV(nullptr)
 {
 }
 
@@ -87,11 +90,7 @@ const int ArnoldiReduce::ts_point_count_incr_ = 1024;
 const int ArnoldiReduce::ts_edge_count_incr_ = 1024;
 
 ArnoldiReduce::ArnoldiReduce(StaState *sta) :
-  StaState(sta),
+  StaState(sta)
-  ts_pointNmax(1024),
-  ts_edgeNmax(1024),
-  termNmax(256),
-  dNmax(8)
 {
   ts_pointV = (ts_point *)malloc(ts_pointNmax * sizeof(ts_point));
   ts_ordV = (int *)malloc(ts_pointNmax * sizeof(int));
@@ -351,14 +350,14 @@ ArnoldiReduce::makeRcmodelDfs(ts_point *pdrv)
   ts_point *p0 = ts_pointV;
   ts_point *pend = p0 + ts_pointN;
   for (p = p0; p != pend; p++)
-    p->visited = 0;
+    p->visited = false;
   ts_edge *e;
 
   ts_edge **stackV = ts_stackV;
   int stackN = 1;
   stackV[0] = e = pdrv->eV[0];
   ts_orient(pdrv, e);
-  pdrv->visited = 1;
+  pdrv->visited = true;
   pdrv->in_edge = nullptr;
   pdrv->ts = 0;
   ts_ordV[0] = pdrv - p0;
@@ -376,7 +375,7 @@ ArnoldiReduce::makeRcmodelDfs(ts_point *pdrv)
     }
     else {
       // try to descend
-      q->visited = 1;
+      q->visited = true;
       q->ts = ts_ordN++;
       ts_pordV[q->ts] = q;
       ts_ordV[q->ts] = q - p0;
@@ -531,9 +530,7 @@ ArnoldiReduce::makeRcmodelFromTs()
   u0 = _u0;
   u1 = _u1;
   double sum, e1;
-  order = max_order;
+  order = std::min(n, max_order);
-  if (n < order)
-    order = n;
 
   par[0] = -1;
   r[0] = 0.0;
@@ -682,4 +679,5 @@ ArnoldiReduce::makeRcmodelFromW()
   return mod;
 }
 
+// NOLINTEND(modernize-avoid-c-style-cast, bugprone-multi-level-implicit-pointer-conversion, bugprone-implicit-widening-of-multiplication-result)
 }  // namespace sta

dcalc/ArnoldiReduce.hh

@@ -52,7 +52,7 @@ class ArnoldiReduce : public StaState
 {
 public:
   ArnoldiReduce(StaState *sta);
-  ~ArnoldiReduce();
+  ~ArnoldiReduce() override;
   rcmodel *reduceToArnoldi(Parasitic *parasitic,
                            const Pin *drvr_pin,
                            float coupling_cap_factor,
@@ -86,11 +86,11 @@ protected:
   // rcWork
   ts_point *ts_pointV;
   int ts_pointN;
-  int ts_pointNmax;
+  int ts_pointNmax{1024};
   static const int ts_point_count_incr_;
   ts_edge *ts_edgeV;
   int ts_edgeN;
-  int ts_edgeNmax;
+  int ts_edgeNmax{1024};
   static const int ts_edge_count_incr_;
   ts_edge **ts_eV;
   ts_edge **ts_stackV;
@@ -98,14 +98,14 @@ protected:
   ts_point **ts_pordV;
   int ts_ordN;
 
-  int termNmax;
+  int termNmax{256};
   int termN;
   ts_point *pterm0;
   const Pin **pinV; // fixed order, offset from pterm0
   int *termV; // from drv-ordered to fixed order
   int *outV;  // from drv-ordered to ts_pordV
 
-  int dNmax;
+  int dNmax{8};
   double *d;
   double *e;
   double *U0;

dcalc/CcsCeffDelayCalc.cc

@@ -24,19 +24,20 @@
 
 #include "CcsCeffDelayCalc.hh"
 
+#include <algorithm>
 #include <cmath>
 
 #include "Debug.hh"
-#include "Units.hh"
-#include "Liberty.hh"
-#include "TimingArc.hh"
-#include "Network.hh"
-#include "Graph.hh"
-#include "Scene.hh"
-#include "Parasitics.hh"
-#include "GraphDelayCalc.hh"
 #include "DmpDelayCalc.hh"
 #include "FindRoot.hh"
+#include "Graph.hh"
+#include "GraphDelayCalc.hh"
+#include "Liberty.hh"
+#include "Network.hh"
+#include "Parasitics.hh"
+#include "Scene.hh"
+#include "TimingArc.hh"
+#include "Units.hh"
 
 namespace sta {
 
@@ -53,10 +54,6 @@ makeCcsCeffDelayCalc(StaState *sta)
 
 CcsCeffDelayCalc::CcsCeffDelayCalc(StaState *sta) :
   LumpedCapDelayCalc(sta),
-  output_waveforms_(nullptr),
-  // Includes the Vh:Vdd region.
-  region_count_(0),
-  vl_fail_(false),
   watch_pin_values_(network_),
   capacitance_unit_(units_->capacitanceUnit()),
   table_dcalc_(makeDmpCeffElmoreDelayCalc(sta))
@@ -176,8 +173,8 @@ CcsCeffDelayCalc::gateDelaySlew(const LibertyLibrary *drvr_library,
     }
 
     for (size_t i = 0; i < region_count_; i++) {
-      double v1 = region_volts_[i];
+      double seg_v1 = region_volts_[i];
-      double v2 = region_volts_[i + 1];
+      double seg_v2 = region_volts_[i + 1];
       double t1 = region_times_[i];
       double t2 = region_times_[i + 1];
 
@@ -186,11 +183,11 @@ CcsCeffDelayCalc::gateDelaySlew(const LibertyLibrary *drvr_library,
       // for the charge on c1 from previous segments so it does not
       // work well.
       double c1_v1, c1_v2, ignore;
-      vl(t1, rpi_ * c1_, c1_v1, ignore);
+      vLoad(t1, rpi_ * c1_, c1_v1, ignore);
-      vl(t2, rpi_ * c1_, c1_v2, ignore);
+      vLoad(t2, rpi_ * c1_, c1_v2, ignore);
-      double q1 = v1 * c2_ + c1_v1 * c1_;
+      double q1 = seg_v1 * c2_ + c1_v1 * c1_;
-      double q2 = v2 * c2_ + c1_v2 * c1_;
+      double q2 = seg_v2 * c2_ + c1_v2 * c1_;
-      double ceff = (q2 - q1) / (v2 - v1);
+      double ceff = (q2 - q1) / (seg_v2 - seg_v1);
 
       debugPrint(debug_, "ccs_dcalc", 2, "ceff {}",
                  capacitance_unit_->asString(ceff));
@@ -297,7 +294,7 @@ CcsCeffDelayCalc::initRegions(const LibertyLibrary *drvr_library,
       report_->error(1701, "unsupported ccs region count.");
       break;
   }
-  fill(region_ceff_.begin(), region_ceff_.end(), c2_ + c1_);
+  std::ranges::fill(region_ceff_, c2_ + c1_);
 }
 
 void
@@ -402,11 +399,11 @@ rampElmoreV(double t,
 
 // Elmore (one pole) response to 2 segment ramps [0, vth] slew1, [vth, vdd] slew2.
 void
-CcsCeffDelayCalc::vl(double t,
+CcsCeffDelayCalc::vLoad(double t,
-                     double elmore,
+                        double elmore,
-                     // Return values.
+                        // Return values.
-                     double &vl,
+                        double &vl,
-                     double &dvl_dt)
+                        double &dvl_dt)
 {
   vl = 0.0;
   dvl_dt = 0.0;
@@ -431,11 +428,11 @@ CcsCeffDelayCalc::vl(double t,
 
 // for debugging
 double
-CcsCeffDelayCalc::vl(double t,
+CcsCeffDelayCalc::vLoad(double t,
-                     double elmore)
+                        double elmore)
 {
   double vl1, dvl_dt;
-  vl(t, elmore, vl1, dvl_dt);
+  vLoad(t, elmore, vl1, dvl_dt);
   return vl1;
 }
 
@@ -447,7 +444,7 @@ CcsCeffDelayCalc::findVlTime(double v,
   double t_final = region_ramp_times_[region_count_];
   auto [time, failed] =
     findRoot([&](double t, double &y, double &dy) {
-      vl(t, elmore, y, dy);
+      vLoad(t, elmore, y, dy);
       y -= v;
     },
       t_init, t_final + elmore * 3.0, .001, 20);
@@ -539,7 +536,7 @@ CcsCeffDelayCalc::loadWaveform(const Pin *load_pin)
         load_times->push_back(t);
 
         double ignore;
-        vl(t, elmore, v, ignore);
+        vLoad(t, elmore, v, ignore);
         double v1 = (drvr_rf_ == RiseFall::rise()) ? v : vdd_ - v;
         load_volts->push_back(v1);
       }

dcalc/CcsCeffDelayCalc.hh

@@ -24,8 +24,8 @@
 
 #pragma once
 
-#include "LumpedCapDelayCalc.hh"
 #include "ArcDcalcWaveforms.hh"
+#include "LumpedCapDelayCalc.hh"
 
 namespace sta {
 
@@ -39,7 +39,7 @@ class CcsCeffDelayCalc : public LumpedCapDelayCalc,
 {
 public:
   CcsCeffDelayCalc(StaState *sta);
-  virtual ~CcsCeffDelayCalc();
+  ~CcsCeffDelayCalc() override;
   ArcDelayCalc *copy() override;
   std::string_view name() const override { return "ccs_ceff"; }
   bool reduceSupported() const override { return true; }
@@ -68,7 +68,7 @@ public:
   Waveform watchWaveform(const Pin *pin) override;
 
 protected:
-  typedef std::vector<double> Region;
+  using Region = std::vector<double>;
 
   void gateDelaySlew(const LibertyLibrary *drvr_library,
                      // Return values.
@@ -106,13 +106,13 @@ protected:
                             const Pin *load_pin,
                             const Scene *scene,
                             const MinMax *min_max);
-  void vl(double t,
+  void vLoad(double t,
-          double elmore,
+             double elmore,
-          // Return values.
+             // Return values.
-          double &vl,
+             double &vl,
-          double &dvl_dt);
+             double &dvl_dt);
-  double vl(double t,
+  double vLoad(double t,
-           double elmore);
+               double elmore);
   void fail(std::string_view reason);
 
   const Pin *drvr_pin_;
@@ -122,7 +122,7 @@ protected:
   Parasitics *parasitics_;
   const Parasitic *parasitic_;
 
-  OutputWaveforms *output_waveforms_;
+  OutputWaveforms *output_waveforms_{nullptr};
   double ref_time_;
   float vdd_;
   float vth_;
@@ -133,7 +133,7 @@ protected:
   float rpi_;
   float c1_;
 
-  size_t region_count_;
+  size_t region_count_{0};
   size_t region_vl_idx_;
   size_t region_vth_idx_;
   size_t region_vh_idx_;
@@ -146,7 +146,7 @@ protected:
   Region region_time_offsets_;
   Region region_ramp_times_;
   Region region_ramp_slopes_;
-  bool vl_fail_;
+  bool vl_fail_{false};
   // Waveform recording.
   WatchPinValuesMap watch_pin_values_;
 

dcalc/Delay.cc

@@ -26,10 +26,10 @@
 
 #include <cmath>
 
-#include "StaConfig.hh"
 #include "Fuzzy.hh"
-#include "Units.hh"
+#include "StaConfig.hh"
 #include "StaState.hh"
+#include "Units.hh"
 #include "Variables.hh"
 
 namespace sta {

dcalc/DelayCalc.cc

@@ -27,18 +27,18 @@
 #include <map>
 #include <string>
 
-#include "ContainerHelpers.hh"
-#include "StringUtil.hh"
-#include "UnitDelayCalc.hh"
-#include "LumpedCapDelayCalc.hh"
-#include "DmpDelayCalc.hh"
 #include "ArnoldiDelayCalc.hh"
 #include "CcsCeffDelayCalc.hh"
+#include "ContainerHelpers.hh"
+#include "DmpDelayCalc.hh"
+#include "LumpedCapDelayCalc.hh"
 #include "PrimaDelayCalc.hh"
+#include "StringUtil.hh"
+#include "UnitDelayCalc.hh"
 
 namespace sta {
 
-typedef std::map<std::string, MakeArcDelayCalc, std::less<>> DelayCalcMap;
+using DelayCalcMap = std::map<std::string, MakeArcDelayCalc, std::less<>>;
 
 static DelayCalcMap delay_calcs;
 

dcalc/DelayCalc.i

@@ -28,11 +28,11 @@
 
 %{
 
-#include "DelayCalc.hh"
 #include "ArcDelayCalc.hh"
+#include "DelayCalc.hh"
+#include "Sta.hh"
 #include "dcalc/ArcDcalcWaveforms.hh"
 #include "dcalc/PrimaDelayCalc.hh"
-#include "Sta.hh"
 
 %}
 

dcalc/DelayCalcBase.cc

@@ -24,16 +24,16 @@
 
 #include "DelayCalcBase.hh"
 
+#include "Graph.hh"
+#include "GraphDelayCalc.hh"
 #include "Liberty.hh"
-#include "TimingArc.hh"
-#include "TimingModel.hh"
-#include "TableModel.hh"
 #include "Network.hh"
 #include "Parasitics.hh"
-#include "Graph.hh"
-#include "Sdc.hh"
 #include "Scene.hh"
-#include "GraphDelayCalc.hh"
+#include "Sdc.hh"
+#include "TableModel.hh"
+#include "TimingArc.hh"
+#include "TimingModel.hh"
 #include "Variables.hh"
 
 namespace sta {

dcalc/DelayCalcBase.hh

@@ -72,7 +72,7 @@ protected:
   void thresholdAdjust(const Pin *load_pin,
                        const LibertyLibrary *drvr_library,
                        const RiseFall *rf,
-                       double &load_delay,
+                       double &wire_delay,
                        double &load_slew);
   // Helper function for input ports driving dspf parasitic.
   void dspfWireDelaySlew(const Pin *load_pin,

dcalc/DelayNormal.cc

@@ -27,10 +27,10 @@
 #include <cmath> // sqrt
 
 #include "Error.hh"
-#include "Fuzzy.hh"
-#include "Units.hh"
 #include "Format.hh"
+#include "Fuzzy.hh"
 #include "StaState.hh"
+#include "Units.hh"
 #include "Variables.hh"
 
 namespace sta {

dcalc/DelayScalar.cc

@@ -27,8 +27,8 @@
 #include "DelayScalar.hh"
 
 #include "Fuzzy.hh"
-#include "Units.hh"
 #include "StaState.hh"
+#include "Units.hh"
 
 namespace sta {
 

dcalc/DelaySkewNormal.cc

@@ -27,10 +27,10 @@
 #include <cmath> // sqrt
 
 #include "Error.hh"
-#include "Fuzzy.hh"
-#include "Units.hh"
 #include "Format.hh"
+#include "Fuzzy.hh"
 #include "StaState.hh"
+#include "Units.hh"
 #include "Variables.hh"
 
 namespace sta {

dcalc/DmpCeff.cc

@@ -40,17 +40,17 @@
 #include <tuple>
 #include <utility>
 
-#include "Format.hh"
-#include "Report.hh"
-#include "Debug.hh"
-#include "Units.hh"
-#include "TimingArc.hh"
-#include "TableModel.hh"
-#include "Liberty.hh"
-#include "Sdc.hh"
-#include "Parasitics.hh"
 #include "ArcDelayCalc.hh"
+#include "Debug.hh"
 #include "FindRoot.hh"
+#include "Format.hh"
+#include "Liberty.hh"
+#include "Parasitics.hh"
+#include "Report.hh"
+#include "Sdc.hh"
+#include "TableModel.hh"
+#include "TimingArc.hh"
+#include "Units.hh"
 #include "Variables.hh"
 
 namespace sta {
@@ -72,7 +72,7 @@ class DmpError : public Exception
 {
 public:
   DmpError(std::string_view what);
-  virtual const char *what() const noexcept { return what_.c_str(); }
+  const char *what() const noexcept override { return what_.c_str(); }
 
 private:
   std::string what_;
@@ -127,7 +127,7 @@ protected:
   void newtonRaphson();
   // Find driver parameters t0, delta_t, Ceff.
   void findDriverParams(double ceff);
-  std::pair<double, double> gateCapDelaySlew(double cl);
+  std::pair<double, double> gateCapDelaySlew(double ceff);
   std::tuple<double, double, double> gateDelays(double ceff);
   // Partial derivatives of y(t) jacobian (dydt0, dyddt, dydcl).
   std::tuple<double, double, double> dy(double t,
@@ -143,12 +143,12 @@ protected:
   void showJacobian();
   std::pair<double, double> findDriverDelaySlew();
   double findVoCrossing(double vth,
-                        double lower_bound,
+                        double t_lower,
-                        double upper_bound);
+                        double t_upper);
   void showVo();
   double findVlCrossing(double vth,
-                        double lower_bound,
+                        double t_lower,
-                        double upper_bound);
+                        double t_upper);
   void showVl();
   void fail(std::string_view reason);
 
@@ -177,9 +177,9 @@ protected:
   const Pvt *pvt_;
   const GateTableModel *gate_model_;
   double in_slew_;
-  double c2_;
+  double c2_{0.0};
-  double rpi_;
+  double rpi_{0.0};
-  double c1_;
+  double c1_{0.0};
 
   double rd_;
   // Logic threshold (percentage of supply voltage).
@@ -232,9 +232,6 @@ protected:
 DmpAlg::DmpAlg(int nr_order,
                StaState *sta) :
   StaState(sta),
-  c2_(0.0),
-  rpi_(0.0),
-  c1_(0.0),
   nr_order_(nr_order)
 {
 }
@@ -465,8 +462,13 @@ DmpAlg::showVo()
 {
   report_->report("  t    vo(t)");
   double ub = voCrossingUpperBound();
-  for (double t = t0_; t < t0_ + ub; t += dt_ / 10.0)
+  const double step = dt_ / 10.0;
+  for (int i = 0;; ++i) {
+    double t = t0_ + step * i;
+    if (!(t < t0_ + ub))
+      break;
     report_->report(" {:g} {:g}", t, Vo(t).first);
+  }
 }
 
 std::pair<double, double>
@@ -567,8 +569,14 @@ DmpAlg::showVl()
 {
   report_->report("  t    vl(t)");
   double ub = vlCrossingUpperBound();
-  for (double t = t0_; t < t0_ + ub * 2.0; t += ub / 10.0)
+  const double step = ub / 10.0;
+  const double t_end = t0_ + ub * 2.0;
+  for (int i = 0;; ++i) {
+    double t = t0_ + step * i;
+    if (!(t < t_end))
+      break;
     report_->report(" {:g} {:g}", t, Vl(t).first);
+  }
 }
 
 void
@@ -605,9 +613,9 @@ public:
   std::pair<double, double> loadDelaySlew(const Pin *,
                                            double elmore) override;
   void evalDmpEqns() override;
-  double voCrossingUpperBound() override;
 
-private:
+protected:
+  double voCrossingUpperBound() override;
   std::pair<double, double> V0(double t) override;
   std::pair<double, double> Vl0(double t) override;
 };
@@ -702,7 +710,11 @@ public:
             double c1) override;
   std::pair<double, double> gateDelaySlew() override;
   void evalDmpEqns() override;
+
+protected:
   double voCrossingUpperBound() override;
+  std::pair<double, double> V0(double t) override;
+  std::pair<double, double> Vl0(double t) override;
 
 private:
   void findDriverParamsPi();
@@ -710,39 +722,26 @@ private:
                   double dt,
                   double ceff_time,
                   double ceff);
-  std::pair<double, double> V0(double t) override;
-  std::pair<double, double> Vl0(double t) override;
 
   // Poles/zero.
-  double p1_;
+  double p1_{0.0};
-  double p2_;
+  double p2_{0.0};
-  double z1_;
+  double z1_{0.0};
   // Residues.
-  double k0_;
+  double k0_{0.0};
-  double k1_;
+  double k1_{0.0};
-  double k2_;
+  double k2_{0.0};
-  double k3_;
+  double k3_{0.0};
-  double k4_;
+  double k4_{0.0};
   // Ipi coefficients.
-  double A_;
+  double A_{0.0};
-  double B_;
+  double B_{0.0};
-  double D_;
+  double D_{0.0};
 };
 
 DmpPi::DmpPi(StaState *sta) :
   DmpAlg(3,
-         sta),
+         sta)
-  p1_(0.0),
-  p2_(0.0),
-  z1_(0.0),
-  k0_(0.0),
-  k1_(0.0),
-  k2_(0.0),
-  k3_(0.0),
-  k4_(0.0),
-  A_(0.0),
-  B_(0.0),
-  D_(0.0)
 {
 }
 
@@ -846,8 +845,7 @@ DmpPi::evalDmpEqns()
     throw DmpError("eqn eval failed: slew = 0");
 
   double ceff_time = slew / (vh_ - vl_);
-  if (ceff_time > 1.4 * dt)
+  ceff_time = std::min(ceff_time, 1.4 * dt);
-    ceff_time = 1.4 * dt;
 
   if (dt <= 0.0)
     throw DmpError("eqn eval failed: dt < 0");
@@ -949,6 +947,8 @@ class DmpOnePole : public DmpAlg
 public:
   DmpOnePole(StaState *sta);
   void evalDmpEqns() override;
+
+protected:
   double voCrossingUpperBound() override;
 };
 
@@ -1018,29 +1018,24 @@ public:
             double c1) override;
   std::pair<double, double> gateDelaySlew() override;
 
-private:
+protected:
   std::pair<double, double> V0(double t) override;
   std::pair<double, double> Vl0(double t) override;
   double voCrossingUpperBound() override;
 
+private:
   // Pole/zero.
-  double p1_;
+  double p1_{0.0};
-  double z1_;
+  double z1_{0.0};
   // Residues.
-  double k0_;
+  double k0_{0.0};
-  double k1_;
+  double k1_{0.0};
-  double k2_;
+  double k2_{0.0};
-  double k3_;
+  double k3_{0.0};
 };
 
 DmpZeroC2::DmpZeroC2(StaState *sta) :
-  DmpOnePole(sta),
+  DmpOnePole(sta)
-  p1_(0.0),
-  z1_(0.0),
-  k0_(0.0),
-  k1_(0.0),
-  k2_(0.0),
-  k3_(0.0)
 {
 }
 
@@ -1172,8 +1167,7 @@ DmpAlg::luDecomp()
     double big = 0.0;
     for (int j = 0; j < size; j++) {
       double temp = std::abs(fjac_[i][j]);
-      if (temp > big)
+      big = std::max(temp, big);
-        big = temp;
     }
     if (big == 0.0)
       throw DmpError("LU decomposition: no non-zero row element");
@@ -1268,8 +1262,7 @@ DmpCeffDelayCalc::DmpCeffDelayCalc(StaState *sta) :
   LumpedCapDelayCalc(sta),
   dmp_cap_(new DmpCap(sta)),
   dmp_pi_(new DmpPi(sta)),
-  dmp_zero_c2_(new DmpZeroC2(sta)),
+  dmp_zero_c2_(new DmpZeroC2(sta))
-  dmp_alg_(nullptr)
 {
 }
 

dcalc/DmpCeff.hh

@@ -44,7 +44,7 @@ class DmpCeffDelayCalc : public LumpedCapDelayCalc
 {
 public:
   DmpCeffDelayCalc(StaState *sta);
-  virtual ~DmpCeffDelayCalc();
+  ~DmpCeffDelayCalc() override;
   bool reduceSupported() const override { return true; }
   ArcDcalcResult gateDelay(const Pin *drvr_pin,
                            const TimingArc *arc,
@@ -98,7 +98,7 @@ private:
   DmpCap *dmp_cap_;
   DmpPi *dmp_pi_;
   DmpZeroC2 *dmp_zero_c2_;
-  DmpAlg *dmp_alg_;
+  DmpAlg *dmp_alg_{nullptr};
 };
 
 } // namespace sta

dcalc/DmpDelayCalc.cc

@@ -24,15 +24,15 @@
 
 #include "DmpDelayCalc.hh"
 
+#include "DmpCeff.hh"
+#include "GraphDelayCalc.hh"
+#include "Liberty.hh"
+#include "Network.hh"
+#include "Parasitics.hh"
+#include "PortDirection.hh"
+#include "Sdc.hh"
 #include "TableModel.hh"
 #include "TimingArc.hh"
-#include "Liberty.hh"
-#include "PortDirection.hh"
-#include "Network.hh"
-#include "Sdc.hh"
-#include "Parasitics.hh"
-#include "GraphDelayCalc.hh"
-#include "DmpCeff.hh"
 
 namespace sta {
 
@@ -164,7 +164,7 @@ public:
                            const Scene *scene,
                            const MinMax *min_max) override;
 
-private:
+protected:
   void loadDelaySlew(const Pin *load_pin,
                      double drvr_slew,
                      const RiseFall *rf,
@@ -173,6 +173,8 @@ private:
                      // Return values.
                      double &wire_delay,
                      double &load_slew) override;
+
+private:
   void loadDelay(double drvr_slew,
                  Parasitic *pole_residue,
                  double p1,
@@ -190,11 +192,11 @@ private:
                   double tt,
                   double y_tt);
 
-  bool parasitic_is_pole_residue_;
+  bool parasitic_is_pole_residue_{false};
-  float vth_;
+  float vth_{0.0F};
-  float vl_;
+  float vl_{0.0F};
-  float vh_;
+  float vh_{0.0F};
-  float slew_derate_;
+  float slew_derate_{0.0F};
 };
 
 ArcDelayCalc *
@@ -204,12 +206,7 @@ makeDmpCeffTwoPoleDelayCalc(StaState *sta)
 }
 
 DmpCeffTwoPoleDelayCalc::DmpCeffTwoPoleDelayCalc(StaState *sta) :
-  DmpCeffDelayCalc(sta),
+  DmpCeffDelayCalc(sta)
-  parasitic_is_pole_residue_(false),
-  vth_(0.0),
-  vl_(0.0),
-  vh_(0.0),
-  slew_derate_(0.0)
 {
 }
 
@@ -334,7 +331,7 @@ DmpCeffTwoPoleDelayCalc::loadDelaySlew(const Pin *load_pin,
   // Should handle PiElmore parasitic.
   wire_delay = 0.0;
   load_slew = drvr_slew;
-  Parasitic *pole_residue = 0;
+  Parasitic *pole_residue = nullptr;
   if (parasitic_is_pole_residue_)
     pole_residue = parasitics_->findPoleResidue(parasitic, load_pin);
   if (pole_residue) {

dcalc/FindRoot.cc

@@ -29,7 +29,7 @@
 namespace sta {
 
 std::pair<double, bool>
-findRoot(FindRootFunc func,
+findRoot(const FindRootFunc &func,
          double x1,
          double x2,
          double x_tol,
@@ -42,7 +42,7 @@ findRoot(FindRootFunc func,
 }
 
 std::pair<double, bool>
-findRoot(FindRootFunc func,
+findRoot(const FindRootFunc &func,
          double x1,
          double y1,
          double x2,

dcalc/FindRoot.hh

@@ -36,7 +36,7 @@ using FindRootFunc = const std::function<void (double x,
 
 // first: root estimate; second: true if the search failed.
 std::pair<double, bool>
-findRoot(FindRootFunc func,
+findRoot(const FindRootFunc &func,
          double x1,
          double x2,
          double x_tol,
@@ -44,7 +44,7 @@ findRoot(FindRootFunc func,
 
 // first: root estimate; second: true if the search failed.
 std::pair<double, bool>
-findRoot(FindRootFunc func,
+findRoot(const FindRootFunc &func,
          double x1,
          double y1,
          double x2,

dcalc/GraphDelayCalc.cc

@@ -24,35 +24,35 @@
 
 #include "GraphDelayCalc.hh"
 
-#include <cmath>
 #include <array>
+#include <cmath>
 #include <set>
 #include <string_view>
 
+#include "ArcDelayCalc.hh"
+#include "Bfs.hh"
+#include "ClkNetwork.hh"
 #include "ContainerHelpers.hh"
 #include "Debug.hh"
-#include "Stats.hh"
-#include "MinMax.hh"
-#include "Mutex.hh"
-#include "TimingRole.hh"
-#include "TimingArc.hh"
-#include "Liberty.hh"
-#include "PortDirection.hh"
-#include "Network.hh"
-#include "InputDrive.hh"
-#include "Sdc.hh"
-#include "Mode.hh"
 #include "Graph.hh"
+#include "InputDrive.hh"
+#include "Liberty.hh"
+#include "MinMax.hh"
+#include "Mode.hh"
+#include "Mutex.hh"
+#include "NetCaps.hh"
+#include "Network.hh"
 #include "Parasitics.hh"
-#include "search/Levelize.hh"
+#include "PortDirection.hh"
+#include "Sdc.hh"
 #include "Scene.hh"
 #include "SearchPred.hh"
-#include "Bfs.hh"
+#include "Stats.hh"
-#include "ArcDelayCalc.hh"
+#include "TimingArc.hh"
-#include "NetCaps.hh"
+#include "TimingRole.hh"
-#include "ClkNetwork.hh"
 #include "Variables.hh"
 #include "search/Latches.hh"
+#include "search/Levelize.hh"
 
 namespace sta {
 
@@ -143,15 +143,10 @@ DcalcNonLatchPred::searchThru(Edge *edge,
 
 GraphDelayCalc::GraphDelayCalc(StaState *sta) :
   StaState(sta),
-  observer_(nullptr),
-  delays_seeded_(false),
-  incremental_(false),
-  delays_exist_(false),
   invalid_delays_(makeVertexSet(this)),
   search_pred_(new DcalcPred(sta)),
   search_non_latch_pred_(new DcalcNonLatchPred(sta)),
-  iter_(new BfsFwdIterator(BfsIndex::dcalc, search_non_latch_pred_, sta)),
+  iter_(new BfsFwdIterator(BfsIndex::dcalc, search_non_latch_pred_, sta))
-  incremental_delay_tolerance_(0.0)
 {
 }
 
@@ -297,9 +292,9 @@ class FindVertexDelays : public VertexVisitor
 {
 public:
   FindVertexDelays(GraphDelayCalc *graph_delay_calc1);
-  virtual ~FindVertexDelays();
+  ~FindVertexDelays() override;
-  virtual void visit(Vertex *vertex);
+  void visit(Vertex *vertex) override;
-  virtual VertexVisitor *copy() const;
+  VertexVisitor *copy() const override;
 
 protected:
   GraphDelayCalc *graph_delay_calc_;
@@ -419,7 +414,7 @@ GraphDelayCalc::seedDrvrSlew(Vertex *drvr_vertex,
         if (drive) {
           const LibertyCell *drvr_cell;
           const LibertyPort *from_port, *to_port;
-          float *from_slews;
+          const DriveCellSlews *from_slews;
           drive->driveCell(rf, min_max, drvr_cell, from_port,
                            from_slews, to_port);
           if (drvr_cell) {
@@ -562,7 +557,7 @@ LibertyPort *
 GraphDelayCalc::driveCellDefaultFromPort(const LibertyCell *cell,
                                          const LibertyPort *to_port)
 {
-  LibertyPort *from_port = 0;
+  LibertyPort *from_port = nullptr;
   int from_port_index = 0;
   for (TimingArcSet *arc_set : cell->timingArcSetsTo(to_port)) {
     LibertyPort *set_from_port = arc_set->from();
@@ -599,7 +594,7 @@ GraphDelayCalc::findInputDriverDelay(const LibertyCell *drvr_cell,
                                      Vertex *drvr_vertex,
                                      const RiseFall *rf,
                                      const LibertyPort *from_port,
-                                     float *from_slews,
+                                     const DriveCellSlews *from_slews,
                                      const LibertyPort *to_port,
                                      const Scene *scene,
                                      const MinMax *min_max,
@@ -611,7 +606,7 @@ GraphDelayCalc::findInputDriverDelay(const LibertyCell *drvr_cell,
   for (TimingArcSet *arc_set : drvr_cell->timingArcSets(from_port, to_port)) {
     for (TimingArc *arc : arc_set->arcs()) {
       if (arc->toEdge()->asRiseFall() == rf) {
-        float from_slew = from_slews[arc->fromEdge()->index()];
+        float from_slew = (*from_slews)[arc->fromEdge()->index()];
         findInputArcDelay(drvr_pin, drvr_vertex, arc, from_slew, scene, min_max,
                           arc_delay_calc);
       }
@@ -1270,19 +1265,19 @@ GraphDelayCalc::annotateLoadDelays(Vertex *drvr_vertex,
       bool load_changed = false;
       if (!load_vertex->slewAnnotated(drvr_rf, min_max)) {
         if (drvr_vertex->slewAnnotated(drvr_rf, min_max)) {
-	  // Copy the driver slew to the load if it is annotated.
+          // Copy the driver slew to the load if it is annotated.
-	  const Slew drvr_slew = graph_->slew(drvr_vertex,drvr_rf,ap_index);
+          const Slew drvr_slew = graph_->slew(drvr_vertex, drvr_rf, ap_index);
-	  graph_->setSlew(load_vertex, drvr_rf, ap_index, drvr_slew);
+          graph_->setSlew(load_vertex, drvr_rf, ap_index, drvr_slew);
           load_changed = true;
-	}
+        }
-	else {
+        else {
-	  const Slew slew = graph_->slew(load_vertex, drvr_rf, ap_index);
+          const Slew slew = graph_->slew(load_vertex, drvr_rf, ap_index);
-	  if (!merge
+          if (!merge
               || delayGreater(load_slew, slew, min_max, this)) {
-	    graph_->setSlew(load_vertex, drvr_rf, ap_index, load_slew);
+            graph_->setSlew(load_vertex, drvr_rf, ap_index, load_slew);
             load_changed = true;
           }
-	}
+        }
       }
       if (!graph_->wireDelayAnnotated(wire_edge, drvr_rf, ap_index)) {
 	// Multiple timing arcs with the same output transition
@@ -1594,9 +1589,9 @@ GraphDelayCalc::findCheckEdgeDelays(Edge *edge,
     const RiseFall *to_rf = arc->toEdge()->asRiseFall();
     if (from_rf && to_rf) {
       const LibertyPort *related_out_port = arc_set->relatedOut();
-      const Pin *related_out_pin = 0;
+      const Pin *related_out_pin = nullptr;
       if (related_out_port)
-	related_out_pin = network_->findPin(inst, related_out_port);
+        related_out_pin = network_->findPin(inst, related_out_port);
 
       for (Scene *scene : scenes_) {
         for (const MinMax *min_max : MinMax::range()) {
@@ -1677,7 +1672,7 @@ GraphDelayCalc::reportDelayCalc(const Edge *edge,
   const RiseFall *to_rf = arc->toEdge()->asRiseFall();
   if (from_rf && to_rf) {
     const LibertyPort *related_out_port = arc_set->relatedOut();
-    const Pin *related_out_pin = 0;
+    const Pin *related_out_pin = nullptr;
     if (related_out_port)
       related_out_pin = network_->findPin(inst, related_out_port);
     float related_out_cap = 0.0;
@@ -1767,11 +1762,6 @@ GraphDelayCalc::minPeriod(const Pin *pin,
 
 ////////////////////////////////////////////////////////////////
 
-MultiDrvrNet::MultiDrvrNet() :
-  dcalc_drvr_(nullptr)
-{
-}
-
 void
 MultiDrvrNet::netCaps(const RiseFall *drvr_rf,
                       const Scene *scene,

dcalc/LumpedCapDelayCalc.cc

@@ -27,15 +27,15 @@
 #include <cmath>  // isnan
 
 #include "Debug.hh"
-#include "Units.hh"
+#include "GraphDelayCalc.hh"
+#include "Liberty.hh"
+#include "Network.hh"
+#include "Parasitics.hh"
+#include "PortDirection.hh"
+#include "Sdc.hh"
 #include "TimingArc.hh"
 #include "TimingModel.hh"
-#include "Liberty.hh"
+#include "Units.hh"
-#include "PortDirection.hh"
-#include "Network.hh"
-#include "Sdc.hh"
-#include "Parasitics.hh"
-#include "GraphDelayCalc.hh"
 #include "Variables.hh"
 
 namespace sta {

dcalc/LumpedCapDelayCalc.hh

@@ -61,7 +61,7 @@ public:
                            const LoadPinIndexMap &load_pin_index_map,
                            const Scene *scene,
                            const MinMax *min_max) override;
-  std::string reportGateDelay(const Pin *drvr_pin,
+  std::string reportGateDelay(const Pin *check_pin,
                               const TimingArc *arc,
                               const Slew &in_slew,
                               float load_cap,

dcalc/NetCaps.cc

@@ -26,10 +26,6 @@
 
 namespace sta {
 
-NetCaps::NetCaps()
-{
-}
-
 NetCaps::NetCaps(float pin_cap,
                  float wire_cap,
                  float fanout,

dcalc/NetCaps.hh

@@ -30,7 +30,7 @@ namespace sta {
 class NetCaps
 {
 public:
-  NetCaps();
+  NetCaps() = default;
   NetCaps(float pin_cap,
           float wire_cap,
           float fanout,

dcalc/ParallelDelayCalc.cc

@@ -24,13 +24,13 @@
 
 #include "ParallelDelayCalc.hh"
 
-#include "TimingArc.hh"
-#include "Scene.hh"
-#include "Network.hh"
 #include "Graph.hh"
-#include "Sdc.hh"
-#include "Liberty.hh"
 #include "GraphDelayCalc.hh"
+#include "Liberty.hh"
+#include "Network.hh"
+#include "Scene.hh"
+#include "Sdc.hh"
+#include "TimingArc.hh"
 
 namespace sta {
 

dcalc/ParallelDelayCalc.hh

@@ -24,8 +24,8 @@
 
 #pragma once
 
-#include <vector>
 #include <map>
+#include <vector>
 
 #include "DelayCalcBase.hh"
 

dcalc/PrimaDelayCalc.cc

@@ -24,32 +24,27 @@
 
 #include "PrimaDelayCalc.hh"
 
+#include <Eigen/LU>
+#include <Eigen/QR>
 #include <cmath>  // abs
 #include <string_view>
 
 #include "Debug.hh"
-#include "Units.hh"
-#include "TimingArc.hh"
-#include "Liberty.hh"
-#include "PortDirection.hh"
-#include "Network.hh"
-#include "Sdc.hh"
-#include "Scene.hh"
-#include "Graph.hh"
-#include "Parasitics.hh"
-#include "GraphDelayCalc.hh"
 #include "DmpDelayCalc.hh"
 #include "Format.hh"
-
+#include "Graph.hh"
-#include <Eigen/LU>
+#include "GraphDelayCalc.hh"
-#include <Eigen/QR>
+#include "Liberty.hh"
+#include "Network.hh"
+#include "Parasitics.hh"
+#include "PortDirection.hh"
+#include "Scene.hh"
+#include "Sdc.hh"
+#include "TimingArc.hh"
+#include "Units.hh"
 
 namespace sta {
 
-using Eigen::ColPivHouseholderQR;
-using Eigen::HouseholderQR;
-using Eigen::SparseLU;
-
 // Lawrence Pillage - “Electronic Circuit & System Simulation Methods” 1998
 // McGraw-Hill, Inc. New York, NY.
 
@@ -61,17 +56,7 @@ makePrimaDelayCalc(StaState *sta)
 
 PrimaDelayCalc::PrimaDelayCalc(StaState *sta) :
   DelayCalcBase(sta),
-  dcalc_args_(nullptr),
-  scene_(nullptr),
-  min_max_(nullptr),
-  parasitics_(nullptr),
-  parasitic_network_(nullptr),
-  load_pin_index_map_(nullptr),
   pin_node_map_(network_),
-  prima_order_(3),
-  make_waveforms_(false),
-  waveform_drvr_pin_(nullptr),
-  waveform_load_pin_(nullptr),
   watch_pin_values_(network_),
   table_dcalc_(makeDmpCeffElmoreDelayCalc(sta))
 {
@@ -79,20 +64,18 @@ PrimaDelayCalc::PrimaDelayCalc(StaState *sta) :
 
 PrimaDelayCalc::PrimaDelayCalc(const PrimaDelayCalc &dcalc) :
   DelayCalcBase(dcalc),
-  dcalc_args_(nullptr),
-  load_pin_index_map_(nullptr),
   pin_node_map_(network_),
   node_index_map_(dcalc.node_index_map_),
   prima_order_(dcalc.prima_order_),
-  make_waveforms_(false),
-  waveform_drvr_pin_(nullptr),
-  waveform_load_pin_(nullptr),
   watch_pin_values_(network_),
   table_dcalc_(makeDmpCeffElmoreDelayCalc(this))
 {
 }
 
-PrimaDelayCalc::~PrimaDelayCalc() { delete table_dcalc_; }
+PrimaDelayCalc::~PrimaDelayCalc()
+{
+  delete table_dcalc_;
+}
 
 ArcDelayCalc *
 PrimaDelayCalc::copy()
@@ -359,7 +342,7 @@ PrimaDelayCalc::simulate1(const MatrixSd &G,
                           const Eigen::MatrixXd &B,
                           const Eigen::VectorXd &x_init,
                           const Eigen::MatrixXd &x_to_v,
-                          const size_t order)
+                          size_t order)
 {
   Eigen::VectorXd x(order);
   Eigen::VectorXd x_prev(order);
@@ -379,7 +362,7 @@ PrimaDelayCalc::simulate1(const MatrixSd &G,
   MatrixSd A(order, order);
   A = G + (2.0 / time_step_) * C;
   A.makeCompressed();
-  SparseLU<MatrixSd> A_solver;
+  Eigen::SparseLU<MatrixSd> A_solver;
   A_solver.compute(A);
 
   // Initial time depends on ceff which impact delay, so use a sim step
@@ -403,7 +386,10 @@ PrimaDelayCalc::simulate1(const MatrixSd &G,
   if (make_waveforms_)
     recordWaveformStep(time_begin);
 
-  for (double time = time_begin; time <= time_end; time += time_step_) {
+  for (size_t step = 0;; ++step) {
+    const double time = time_begin + step * time_step_;
+    if (time > time_end)
+      break;
     setPortCurrents();
     rhs = B * u_ + (1.0 / time_step_) * C * (3.0 * x_prev - x_prev2);
     x = A_solver.solve(rhs);
@@ -850,7 +836,7 @@ PrimaDelayCalc::primaReduce()
 {
   G_.makeCompressed();
   // Step 3: solve G*R = B for R
-  SparseLU<MatrixSd> G_solver(G_);
+  Eigen::SparseLU<MatrixSd> G_solver(G_);
   if (G_solver.info() != Eigen::Success)
     report_->error(1752, "G matrix is singular.");
   Eigen::MatrixXd R(order_, port_count_);
@@ -1038,7 +1024,7 @@ PinSeq
 PrimaDelayCalc::watchPins() const
 {
   PinSeq pins;
-  for (auto pin_values : watch_pin_values_) {
+  for (const auto &pin_values : watch_pin_values_) {
     const Pin *pin = pin_values.first;
     pins.push_back(pin);
   }
@@ -1117,10 +1103,8 @@ void
 PrimaDelayCalc::reportMatrix(Eigen::VectorXd &matrix)
 {
   std::string line = "| ";
-  for (Eigen::Index i = 0; i < matrix.rows(); i++) {
+  for (Eigen::Index i = 0; i < matrix.rows(); i++)
-    std::string entry = 
     line += sta::format("{:10.3e}", matrix.coeff(i)) + " ";
-  }
   line += "|";
   report_->reportLine(line);
 }
@@ -1129,8 +1113,8 @@ void
 PrimaDelayCalc::reportVector(std::vector<double> &matrix)
 {
   std::string line = "| ";
-  for (size_t i = 0; i < matrix.size(); i++)
+  for (const double &entry : matrix)
-    line += sta::format("{:10.3e}", matrix[i]) + " ";
+    line += sta::format("{:10.3e}", entry) + " ";
   line += "|";
   report_->reportLine(line);
 }

dcalc/PrimaDelayCalc.hh

@@ -24,13 +24,14 @@
 
 #pragma once
 
-#include <vector>
-#include <map>
 #include <Eigen/SparseCore>
 #include <Eigen/SparseLU>
+#include <array>
+#include <map>
+#include <vector>
 
-#include "LumpedCapDelayCalc.hh"
 #include "ArcDcalcWaveforms.hh"
+#include "LumpedCapDelayCalc.hh"
 #include "Parasitics.hh"
 
 namespace sta {
@@ -57,7 +58,7 @@ class PrimaDelayCalc : public DelayCalcBase,
 public:
   PrimaDelayCalc(StaState *sta);
   PrimaDelayCalc(const PrimaDelayCalc &dcalc);
-  ~PrimaDelayCalc();
+  ~PrimaDelayCalc() override;
   ArcDelayCalc *copy() override;
   void copyState(const StaState *sta) override;
   std::string_view name() const override { return "prima"; }
@@ -123,7 +124,7 @@ protected:
                  const Eigen::MatrixXd &B,
                  const Eigen::VectorXd &x_init,
                  const Eigen::MatrixXd &x_to_v,
-                 const size_t order);
+                 size_t order);
   double maxTime();
   double timeStep();
   float driverResistance();
@@ -178,15 +179,15 @@ protected:
   void reportMatrix(Eigen::VectorXd &matrix);
   void reportVector(std::vector<double> &matrix);
 
-  ArcDcalcArgSeq *dcalc_args_;
+  ArcDcalcArgSeq *dcalc_args_{nullptr};
   size_t drvr_count_;
   float load_cap_;
-  const Scene *scene_;
+  const Scene *scene_{nullptr};
-  const MinMax *min_max_;
+  const MinMax *min_max_{nullptr};
-  Parasitics *parasitics_;
+  Parasitics *parasitics_{nullptr};
-  const Parasitic *parasitic_network_;
+  const Parasitic *parasitic_network_{nullptr};
   const RiseFall *drvr_rf_;
-  const LoadPinIndexMap *load_pin_index_map_;
+  const LoadPinIndexMap *load_pin_index_map_{nullptr};
 
   PinNodeMap pin_node_map_;     // Parasitic pin -> array index
   NodeIndexMap node_index_map_; // Parasitic node -> array index
@@ -210,7 +211,7 @@ protected:
   Eigen::VectorXd u_;
 
   // Prima reduced MNA eqns
-  size_t prima_order_;
+  size_t prima_order_{3};
   Eigen::MatrixXd Vq_;
   MatrixSd Gq_;
   MatrixSd Cq_;
@@ -231,9 +232,9 @@ protected:
   double time_step_prev_;
 
   // Waveform recording.
-  bool make_waveforms_;
+  bool make_waveforms_{false};
-  const Pin *waveform_drvr_pin_;
+  const Pin *waveform_drvr_pin_{nullptr};
-  const Pin *waveform_load_pin_;
+  const Pin *waveform_load_pin_{nullptr};
   FloatSeq drvr_voltages_;
   FloatSeq load_voltages_;
   WatchPinValuesMap watch_pin_values_;
@@ -248,7 +249,7 @@ protected:
   static constexpr size_t threshold_vth = 1;
   static constexpr size_t threshold_vh = 2;
   static constexpr size_t measure_threshold_count_ = 3;
-  typedef std::array<double, measure_threshold_count_> ThresholdTimes;
+  using ThresholdTimes = std::array<double, measure_threshold_count_>;
   // Vl Vth Vh
   ThresholdTimes measure_thresholds_;
   // Indexed by node number.

graph/Graph.cc

@@ -26,16 +26,16 @@
 
 #include "ContainerHelpers.hh"
 #include "Debug.hh"
-#include "Stats.hh"
+#include "FuncExpr.hh"
+#include "Liberty.hh"
 #include "MinMax.hh"
 #include "Mutex.hh"
-#include "Transition.hh"
-#include "TimingRole.hh"
-#include "TimingArc.hh"
-#include "Liberty.hh"
-#include "PortDirection.hh"
 #include "Network.hh"
-#include "FuncExpr.hh"
+#include "PortDirection.hh"
+#include "Stats.hh"
+#include "TimingArc.hh"
+#include "TimingRole.hh"
+#include "Transition.hh"
 #include "Variables.hh"
 
 namespace sta {
@@ -49,8 +49,6 @@ namespace sta {
 Graph::Graph(StaState *sta,
              DcalcAPIndex ap_count) :
   StaState(sta),
-  vertices_(nullptr),
-  edges_(nullptr),
   ap_count_(ap_count),
   period_check_annotations_(network_),
   reg_clk_vertices_(makeVertexSet(this))
@@ -342,11 +340,10 @@ class MakeEdgesThruHierPin : public HierPinThruVisitor
 {
 public:
   MakeEdgesThruHierPin(Graph *graph);
-
-private:
   void visit(const Pin *drvr,
              const Pin *load) override;
 
+private:
   Graph *graph_;
 };
 
@@ -585,7 +582,7 @@ Graph::slew(const Vertex *vertex,
   size_t slew_index = ap_index * RiseFall::index_count + rf->index();
   const float *slews_flt = vertex->slewsFloat();
   if (variables_->pocvEnabled()) {
-    const Slew *slews = std::bit_cast<const Slew*>(slews_flt);
+    const Slew *slews = reinterpret_cast<const Slew*>(slews_flt);
     return slews[slew_index];
   }
   else
@@ -598,7 +595,7 @@ Graph::slew(const Vertex *vertex,
 {
   const float *slews_flt = vertex->slewsFloat();
   if (variables_->pocvEnabled()) {
-    const Slew *slews = std::bit_cast<const Slew*>(slews_flt);
+    const Slew *slews = reinterpret_cast<const Slew*>(slews_flt);
     return slews[index];
   }
   else
@@ -678,7 +675,7 @@ Graph::arcDelay(const Edge *edge,
 {
   size_t index = arc->index() * ap_count_ + ap_index;
   if (variables_->pocvEnabled()) {
-    ArcDelay *delays = std::bit_cast<ArcDelay*>(edge->arcDelays());
+    const ArcDelay *delays = reinterpret_cast<const ArcDelay*>(edge->arcDelays());
     return delays[index];
   }
   else {
@@ -695,7 +692,7 @@ Graph::setArcDelay(Edge *edge,
 {
   size_t index = arc->index() * ap_count_ + ap_index;
   if (variables_->pocvEnabled()) {
-    ArcDelay *delays = std::bit_cast<ArcDelay*>(edge->arcDelays());
+    ArcDelay *delays = reinterpret_cast<ArcDelay*>(edge->arcDelays());
     delays[index] = delay;
   }
   else {
@@ -711,7 +708,7 @@ Graph::wireArcDelay(const Edge *edge,
 {
   size_t index = rf->index() * ap_count_ + ap_index;
   if (variables_->pocvEnabled()) {
-    ArcDelay *delays = std::bit_cast<ArcDelay*>(edge->arcDelays());
+    const ArcDelay *delays = reinterpret_cast<const ArcDelay*>(edge->arcDelays());
     return delays[index];
   }
   else {
@@ -728,7 +725,7 @@ Graph::setWireArcDelay(Edge *edge,
 {
   size_t index = rf->index() * ap_count_ + ap_index;
   if (variables_->pocvEnabled()) {
-    ArcDelay *delays = std::bit_cast<ArcDelay*>(edge->arcDelays());
+    ArcDelay *delays = reinterpret_cast<ArcDelay*>(edge->arcDelays());
     delays[index] = delay;
   }
   else {
@@ -753,7 +750,7 @@ Graph::setArcDelayAnnotated(Edge *edge,
                             DcalcAPIndex ap_index,
                             bool annotated)
 {
-  return edge->setArcDelayAnnotated(arc, ap_index, ap_count_, annotated);
+  edge->setArcDelayAnnotated(arc, ap_index, ap_count_, annotated);
 }
 
 bool
@@ -774,7 +771,7 @@ Graph::setWireDelayAnnotated(Edge *edge,
 {
   int arc_index = TimingArcSet::wireArcIndex(rf);
   TimingArc *arc = TimingArcSet::wireTimingArcSet()->findTimingArc(arc_index);
-  return edge->setArcDelayAnnotated(arc, ap_index, ap_count_, annotated);
+  edge->setArcDelayAnnotated(arc, ap_index, ap_count_, annotated);
 }
 
 void
@@ -819,7 +816,7 @@ Graph::initSlews(Vertex *vertex)
 {
   size_t slew_count = slewCount();
   if (variables_->pocvEnabled()) {
-    float *slews = std::bit_cast<float*>(new Slew[slew_count]{});
+    float *slews = reinterpret_cast<float*>(new Slew[slew_count]{});
     vertex->setSlews(slews);
   }
   else {
@@ -840,7 +837,7 @@ Graph::initArcDelays(Edge *edge)
   size_t arc_count = edge->timingArcSet()->arcCount();
   size_t delay_count = arc_count * ap_count_;
   if (variables_->pocvEnabled()) {
-    float *delays = std::bit_cast<float*>(new ArcDelay[delay_count]{});
+    float *delays = reinterpret_cast<float*>(new ArcDelay[delay_count]{});
     edge->setArcDelays(delays);
   }
   else {
@@ -1187,7 +1184,7 @@ Vertex::setHasDownstreamClkPin(bool has_clk_pin)
 bool
 Vertex::bfsInQueue(BfsIndex index) const
 {
-  return (bfs_in_queue_ >> unsigned(index)) & 1;
+  return (bfs_in_queue_ >> static_cast<unsigned>(index)) & 1;
 }
 
 void
@@ -1195,9 +1192,9 @@ Vertex::setBfsInQueue(BfsIndex index,
                       bool value)
 {
   if (value)
-    bfs_in_queue_ |= 1 << int(index);
+    bfs_in_queue_ |= 1 << static_cast<unsigned>(index);
   else
-    bfs_in_queue_ &= ~(1 << int(index));
+    bfs_in_queue_ &= ~(1 << static_cast<unsigned>(index));
 }
 
 ////////////////////////////////////////////////////////////////
@@ -1400,10 +1397,7 @@ VertexIterator::VertexIterator(Graph *graph) :
   graph_(graph),
   network_(graph->network()),
   top_inst_(network_->topInstance()),
-  inst_iter_(network_->leafInstanceIterator()),
+  inst_iter_(network_->leafInstanceIterator())
-  pin_iter_(nullptr),
-  vertex_(nullptr),
-  bidir_vertex_(nullptr)
 {
   if (inst_iter_)
     findNext();

graph/Graph.i

@@ -25,16 +25,16 @@
 %module graph
 
 %{
-#include "Graph.hh"
+#include "Clock.hh"
 #include "FuncExpr.hh"
-#include "TimingRole.hh"
+#include "Graph.hh"
 #include "Liberty.hh"
 #include "Network.hh"
-#include "Clock.hh"
 #include "Scene.hh"
 #include "Search.hh"
 #include "Sdc.hh"
 #include "Sta.hh"
+#include "TimingRole.hh"
 
 using namespace sta;
 

graph/GraphCmp.cc

@@ -22,12 +22,13 @@
 // 
 // This notice may not be removed or altered from any source distribution.
 
+#include "GraphCmp.hh"
+
 #include "ContainerHelpers.hh"
-#include "StringUtil.hh"
+#include "Graph.hh"
 #include "Network.hh"
 #include "NetworkCmp.hh"
-#include "Graph.hh"
+#include "StringUtil.hh"
-#include "GraphCmp.hh"
 
 namespace sta {
 
@@ -73,4 +74,4 @@ sortEdges(EdgeSeq *edges,
   sort(edges, EdgeLess(network, graph));
 }
 
-}
+} // namespace sta

include/sta/ArcDelayCalc.hh

@@ -24,20 +24,20 @@
 
 #pragma once
 
+#include <map>
 #include <string>
 #include <string_view>
 #include <vector>
-#include <map>
 
-#include "MinMax.hh"
-#include "LibertyClass.hh"
-#include "TimingArc.hh"
-#include "TableModel.hh"
-#include "NetworkClass.hh"
-#include "GraphClass.hh"
 #include "Delay.hh"
+#include "GraphClass.hh"
+#include "LibertyClass.hh"
+#include "MinMax.hh"
+#include "NetworkClass.hh"
 #include "ParasiticsClass.hh"
 #include "StaState.hh"
+#include "TableModel.hh"
+#include "TimingArc.hh"
 
 namespace sta {
 
@@ -70,7 +70,7 @@ public:
               const Pin *drvr_pin,
               Edge *edge,
               const TimingArc *arc,
-              float in_delay);
+              float input_delay);
   const Pin *inPin() const { return in_pin_; }
   const RiseFall *inEdge() const;
   const Pin *drvrPin() const { return drvr_pin_; }

include/sta/Bdd.hh

@@ -26,8 +26,8 @@
 
 #include <map>
 
-#include "StaState.hh"
 #include "LibertyClass.hh"
+#include "StaState.hh"
 
 struct DdNode;
 struct DdManager;

include/sta/Bfs.hh

@@ -27,10 +27,10 @@
 #include <mutex>
 #include <vector>
 
-#include "Iterator.hh"
 #include "GraphClass.hh"
-#include "VertexVisitor.hh"
+#include "Iterator.hh"
 #include "StaState.hh"
+#include "VertexVisitor.hh"
 
 namespace sta {
 

include/sta/BoundedHeap.hh

@@ -24,10 +24,10 @@
 
 #pragma once
 
-#include <vector>
 #include <algorithm>
 #include <functional>
 #include <optional>
+#include <vector>
 
 namespace sta {
 

include/sta/ClkNetwork.hh

@@ -26,10 +26,10 @@
 
 #include <map>
 
-#include "StaState.hh"
-#include "NetworkClass.hh"
 #include "GraphClass.hh"
+#include "NetworkClass.hh"
 #include "SdcClass.hh"
+#include "StaState.hh"
 
 namespace sta {
 

include/sta/Clock.hh

@@ -27,11 +27,11 @@
 #include <map>
 #include <string>
 
+#include "GraphClass.hh"
 #include "MinMax.hh"
 #include "RiseFallMinMax.hh"
 #include "SdcClass.hh"
 #include "SdcCmdComment.hh"
-#include "GraphClass.hh"
 
 namespace sta {
 
@@ -170,31 +170,31 @@ protected:
 
   std::string name_;
   PinSet pins_;
-  bool add_to_pins_;
+  bool add_to_pins_{false};
   // Hierarchical pins in pins_ become driver pins through the pin.
   PinSet leaf_pins_;
-  float period_;
+  float period_{0.0};
-  FloatSeq *waveform_;
+  FloatSeq *waveform_{nullptr};
-  bool waveform_valid_;
+  bool waveform_valid_{false};
   const int index_;
-  ClockEdge **clk_edges_;
+  ClockEdge **clk_edges_{nullptr};
-  bool is_propagated_;
+  bool is_propagated_{false};
   RiseFallMinMax slews_;
   RiseFallMinMax slew_limits_[path_clk_or_data_count];
-  ClockUncertainties *uncertainties_;
+  ClockUncertainties *uncertainties_{nullptr};
-  bool is_generated_;
+  bool is_generated_{false};
   // Generated clock variables.
-  Pin *src_pin_;
+  Pin *src_pin_{nullptr};
-  Clock *master_clk_;
+  Clock *master_clk_{nullptr};
   // True if the master clock is infered rather than specified by command.
-  bool master_clk_infered_;
+  bool master_clk_infered_{false};
-  int divide_by_;
+  int divide_by_{0};
-  int multiply_by_;
+  int multiply_by_{0};
-  float duty_cycle_;
+  float duty_cycle_{0};
-  bool invert_;
+  bool invert_{false};
-  bool combinational_;
+  bool combinational_{false};
-  IntSeq *edges_;
+  IntSeq *edges_{nullptr};
-  FloatSeq *edge_shifts_;
+  FloatSeq *edge_shifts_{nullptr};
 
 private:
   friend class Sdc;
@@ -205,7 +205,6 @@ class ClockEdge
 {
 public:
   Clock *clock() const { return clock_; }
-  ~ClockEdge();
   const RiseFall *transition() const { return rf_; }
   float time() const { return time_; }
   const std::string &name() const { return name_; }
@@ -223,7 +222,7 @@ private:
   Clock *clock_;
   const RiseFall *rf_;
   std::string name_;
-  float time_;
+  float time_{0.0};
   int index_;
 };
 

include/sta/ClockGatingCheck.hh

@@ -24,22 +24,21 @@
 
 #pragma once
 
-#include "SdcClass.hh"
 #include "RiseFallMinMax.hh"
+#include "SdcClass.hh"
 
 namespace sta {
 
 class ClockGatingCheck
 {
 public:
-  ClockGatingCheck();
   RiseFallMinMax *margins() { return &margins_; }
   void setActiveValue(LogicValue value);
   LogicValue activeValue() const { return active_value_; }
 
 private:
   RiseFallMinMax margins_;
-  LogicValue active_value_;
+  LogicValue active_value_{LogicValue::unknown};
 };
 
 } // namespace sta

include/sta/ClockGroups.hh

@@ -26,8 +26,8 @@
 
 #include <string>
 
-#include "SdcCmdComment.hh"
 #include "SdcClass.hh"
+#include "SdcCmdComment.hh"
 
 namespace sta {
 

include/sta/ClockInsertion.hh

@@ -26,8 +26,8 @@
 
 #include "MinMax.hh"
 #include "NetworkClass.hh"
-#include "SdcClass.hh"
 #include "RiseFallMinMax.hh"
+#include "SdcClass.hh"
 #include "Transition.hh"
 
 namespace sta {

include/sta/ClockLatency.hh

@@ -26,9 +26,9 @@
 
 #include "MinMax.hh"
 #include "NetworkClass.hh"
-#include "Transition.hh"
-#include "SdcClass.hh"
 #include "RiseFallMinMax.hh"
+#include "SdcClass.hh"
+#include "Transition.hh"
 
 namespace sta {
 

include/sta/ConcreteLibrary.hh

@@ -25,12 +25,12 @@
 #pragma once
 
 #include <functional>
+#include <map>
 #include <string_view>
 #include <vector>
-#include <map>
 
-#include "StringUtil.hh"
 #include "NetworkClass.hh"
+#include "StringUtil.hh"
 
 // The classes defined in this file are a contrete implementation of
 // the library API.  They can be used by a reader to construct classes
@@ -84,8 +84,8 @@ protected:
   ObjectId id_;
   std::string filename_;
   bool is_liberty_;
-  char bus_brkt_left_;
+  char bus_brkt_left_{'['};
-  char bus_brkt_right_;
+  char bus_brkt_right_{']'};
   ConcreteCellMap cell_map_;
 
 private:
@@ -129,7 +129,7 @@ public:
   // Group previously defined bus bit ports together.
   void groupBusPorts(char bus_brkt_left,
                      char bus_brkt_right,
-                     std::function<bool(std::string_view)> port_msb_first);
+                     const std::function<bool(std::string_view)> &port_msb_first);
   size_t portCount() const;
   void setName(std::string_view name);
   virtual void addPort(ConcretePort *port);
@@ -149,7 +149,7 @@ protected:
                        int from_index,
                        int to_index);
   // Bus port bit (internal to makeBusPortBits).
-  ConcretePort *makePort(std::string bit_name,
+  ConcretePort *makePort(std::string_view bit_name,
                          int bit_index);
   void makeBusPortBit(ConcretePort *bus_port,
                       std::string_view bus_name,
@@ -160,14 +160,14 @@ protected:
   // Filename is optional.
   std::string filename_;
   ConcreteLibrary *library_;
-  LibertyCell *liberty_cell_;
+  LibertyCell *liberty_cell_{nullptr};
   // External application cell.
-  void *ext_cell_;
+  void *ext_cell_{nullptr};
   // Non-bus and bus ports (but no expanded bus bit ports).
   ConcretePortSeq ports_;
   ConcretePortMap port_map_;
   // Port bit count (expanded buses).
-  int port_bit_count_;
+  int port_bit_count_{0};
   bool is_leaf_;
   AttributeMap attribute_map_;
 
@@ -242,10 +242,10 @@ protected:
   ObjectId id_;
   ConcreteCell *cell_;
   PortDirection *direction_;
-  LibertyPort *liberty_port_;
+  LibertyPort *liberty_port_{nullptr};
   // External application port.
-  void *ext_port_;
+  void *ext_port_{nullptr};
-  int pin_index_;
+  int pin_index_{-1};
   bool is_bundle_;
   bool is_bus_;
   int from_index_;
@@ -253,7 +253,7 @@ protected:
   // Expanded bus bit ports (ordered by from_index_ to to_index_)
   // or bundle member ports.
   ConcretePortSeq *member_ports_;
-  ConcretePort *bundle_port_;
+  ConcretePort *bundle_port_{nullptr};
 
 private:
   friend class ConcreteCell;
@@ -271,8 +271,8 @@ private:
 
   const ConcretePortSeq &ports_;
   ConcretePortSeq::const_iterator port_iter_;
-  ConcretePortMemberIterator *member_iter_;
+  ConcretePortMemberIterator *member_iter_{nullptr};
-  ConcretePort *next_;
+  ConcretePort *next_{nullptr};
 };
 
 } // namespace sta

include/sta/ConcreteNetwork.hh

@@ -25,14 +25,14 @@
 #pragma once
 
 #include <functional>
-#include <string_view>
-#include <vector>
 #include <map>
 #include <set>
+#include <string_view>
+#include <vector>
 
-#include "StringUtil.hh"
-#include "Network.hh"
 #include "LibertyClass.hh"
+#include "Network.hh"
+#include "StringUtil.hh"
 
 namespace  sta {
 
@@ -263,6 +263,9 @@ public:
   using Network::isLeaf;
 
 protected:
+  void clearImpl();
+  void deleteCellNetworkViewsImpl();
+  void deleteInstanceImpl(Instance *inst);
   void addLibrary(ConcreteLibrary *library);
   void setName(std::string_view name);
   void clearConstantNets();
@@ -280,8 +283,8 @@ protected:
   // Cell lookup search order sequence.
   ConcreteLibrarySeq library_seq_;
   ConcreteLibraryMap library_map_;
-  Instance *top_instance_;
+  Instance *top_instance_{nullptr};
-  NetSet constant_nets_[2];  // LogicValue::zero/one
+  NetSet constant_nets_[2]{NetSet(this), NetSet(this)};  // LogicValue::zero/one
   LinkNetworkFunc link_func_;
   CellNetworkViewMap cell_network_view_map_;
   static ObjectId object_id_;
@@ -293,7 +296,7 @@ private:
 class ConcreteInstance
 {
 public:
-  std::string_view name() const { return name_; }
+  const std::string &name() const { return name_; }
   ObjectId id() const { return id_; }
   Cell *cell() const;
   ConcreteInstance *parent() const { return parent_; }
@@ -332,8 +335,8 @@ protected:
   ConcreteInstance *parent_;
   // Array of pins indexed by pin->port->index().
   ConcretePinSeq pins_;
-  ConcreteInstanceChildMap *children_;
+  ConcreteInstanceChildMap *children_{nullptr};
-  ConcreteInstanceNetMap *nets_;
+  ConcreteInstanceNetMap *nets_{nullptr};
   AttributeMap attribute_map_;
 
 private:
@@ -344,7 +347,7 @@ private:
 class ConcretePin
 {
 public:
-  std::string_view name() const;
+  const std::string &name() const;
   ConcreteInstance *instance() const { return instance_; }
   ConcreteNet *net() const { return net_; }
   ConcretePort *port() const { return port_; }
@@ -362,12 +365,12 @@ protected:
   ConcreteInstance *instance_;
   ConcretePort *port_;
   ConcreteNet *net_;
-  ConcreteTerm *term_;
+  ConcreteTerm *term_{nullptr};
   ObjectId id_;
   // Doubly linked list of net pins.
-  ConcretePin *net_next_;
+  ConcretePin *net_next_{nullptr};
-  ConcretePin *net_prev_;
+  ConcretePin *net_prev_{nullptr};
-  VertexId vertex_id_;
+  VertexId vertex_id_{vertex_id_null};
 
 private:
   friend class ConcreteNetwork;
@@ -378,7 +381,7 @@ private:
 class ConcreteTerm
 {
 public:
-  std::string_view name() const;
+  const std::string &name() const;
   ObjectId id() const { return id_; }
   ConcreteNet *net() const { return net_; }
   ConcretePin *pin() const { return pin_; }
@@ -392,7 +395,7 @@ protected:
   ConcreteNet *net_;
   ObjectId id_;
   // Linked list of net terms.
-  ConcreteTerm *net_next_;
+  ConcreteTerm *net_next_{nullptr};
 
 private:
   friend class ConcreteNetwork;
@@ -403,7 +406,7 @@ private:
 class ConcreteNet
 {
 public:
-  std::string_view name() const { return name_; }
+  const std::string &name() const { return name_; }
   ObjectId id() const { return id_; }
   ConcreteInstance *instance() const { return instance_; }
   void addPin(ConcretePin *pin);
@@ -420,12 +423,12 @@ protected:
   ObjectId id_;
   ConcreteInstance *instance_;
   // Pointer to head of linked list of pins.
-  ConcretePin *pins_;
+  ConcretePin *pins_{nullptr};
   // Pointer to head of linked list of terminals.
   // These terminals correspond to the pins attached to the instance that
   // contains this net in the hierarchy level above.
-  ConcreteTerm *terms_;
+  ConcreteTerm *terms_{nullptr};
-  ConcreteNet *merged_into_;
+  ConcreteNet *merged_into_{nullptr};
 
   friend class ConcreteNetwork;
   friend class ConcreteNetTermIterator;

include/sta/CycleAccting.hh

@@ -27,9 +27,9 @@
 #include <unordered_set>
 
 #include "MinMax.hh"
-#include "TimingRole.hh"
-#include "StaState.hh"
 #include "SdcClass.hh"
+#include "StaState.hh"
+#include "TimingRole.hh"
 
 namespace sta {
 
@@ -127,7 +127,7 @@ private:
   int src_cycle_[TimingRole::index_max + 1];
   // Target clock cycle offset.
   int tgt_cycle_[TimingRole::index_max + 1];
-  bool max_cycles_exceeded_;
+  bool max_cycles_exceeded_{false};
 };
 
 } // namespace sta

include/sta/DataCheck.hh

@@ -24,12 +24,12 @@
 
 #pragma once
 
-#include "MinMax.hh"
 #include "LibertyClass.hh"
+#include "MinMax.hh"
 #include "NetworkClass.hh"
 #include "NetworkCmp.hh"
-#include "SdcClass.hh"
 #include "RiseFallMinMax.hh"
+#include "SdcClass.hh"
 
 namespace sta {
 

include/sta/Debug.hh

@@ -24,10 +24,10 @@
 
 #pragma once
 
-#include <string>
-#include <string_view>
 #include <map>
 #include <mutex>
+#include <string>
+#include <string_view>
 
 #include "Format.hh"
 #include "Report.hh"

include/sta/Delay.hh

@@ -27,8 +27,8 @@
 #include <array>
 #include <cstddef>
 
-#include "StaConfig.hh"
 #include "MinMax.hh"
+#include "StaConfig.hh"
 
 namespace sta {
 
@@ -78,7 +78,7 @@ class DelayDbl
 {
 public:
   DelayDbl() noexcept;
-  DelayDbl(double value) noexcept;
+  DelayDbl(double mean) noexcept;
   double mean() const { return values_[0]; }
   void setMean(double mean);
   double meanShift() const { return values_[1]; }

include/sta/DeratingFactors.hh

@@ -24,10 +24,10 @@
 
 #pragma once
 
-#include "MinMax.hh"
 #include "LibertyClass.hh"
-#include "SdcClass.hh"
+#include "MinMax.hh"
 #include "RiseFallMinMax.hh"
+#include "SdcClass.hh"
 
 namespace sta {
 
@@ -111,10 +111,4 @@ private:
   DeratingFactors factors_[timing_derate_cell_type_count];
 };
 
-class DeratingFactorsNet : public DeratingFactors
-{
-public:
-  DeratingFactorsNet();
-};
-
 } // namespace sta

include/sta/DisabledPorts.hh

@@ -27,8 +27,8 @@
 #include <set>
 #include <vector>
 
-#include "NetworkClass.hh"
 #include "LibertyClass.hh"
+#include "NetworkClass.hh"
 #include "SdcClass.hh"
 
 namespace sta {
@@ -46,7 +46,6 @@ using TimingArcSetSet = std::set<TimingArcSet*, TimingArcSetLess>;
 class DisabledPorts
 {
 public:
-  DisabledPorts();
   ~DisabledPorts();
   void setDisabledAll();
   void removeDisabledAll();
@@ -67,10 +66,10 @@ public:
   [[nodiscard]] bool all() const { return all_; }
 
 private:
-  bool all_;
+  bool all_{false};
-  LibertyPortSet *from_;
+  LibertyPortSet *from_{nullptr};
-  LibertyPortSet *to_;
+  LibertyPortSet *to_{nullptr};
-  LibertyPortPairSet *from_to_;
+  LibertyPortPairSet *from_to_{nullptr};
 };
 
 // set_disable_timing cell [-from] [-to]
@@ -89,7 +88,7 @@ public:
 
 private:
   LibertyCell *cell_;
-  TimingArcSetSet *arc_sets_;
+  TimingArcSetSet *arc_sets_{nullptr};
 };
 
 // set_disable_timing instance [-from] [-to]

include/sta/DispatchQueue.hh

@@ -5,14 +5,14 @@
 
 #pragma once
 
-#include <thread>
-#include <functional>
-#include <vector>
-#include <cstdint>
-#include <queue>
-#include <mutex>
-#include <condition_variable>
 #include <atomic>
+#include <condition_variable>
+#include <cstdint>
+#include <functional>
+#include <mutex>
+#include <queue>
+#include <thread>
+#include <vector>
 
 namespace sta {
 

include/sta/Error.hh

@@ -35,7 +35,6 @@ namespace sta {
 class Exception : public std::exception
 {
 public:
-  Exception();
   const char *what() const noexcept override = 0;
 };
 

include/sta/ExceptionPath.hh

@@ -29,8 +29,8 @@
 #include <vector>
 
 #include "Error.hh"
-#include "SdcCmdComment.hh"
 #include "SdcClass.hh"
+#include "SdcCmdComment.hh"
 
 namespace sta {
 
@@ -145,7 +145,7 @@ protected:
   const MinMaxAll *min_max_;
   bool own_pts_;
   int priority_;
-  size_t id_;                   // Unique ID assigned by Sdc.
+  size_t id_{0};                   // Unique ID assigned by Sdc.
   ExceptionState *states_;
 };
 
@@ -301,7 +301,6 @@ public:
             ExceptionTo *to,
             bool own_pts,
             std::string_view comment);
-  ~GroupPath() override;
   ExceptionPath *clone(ExceptionFrom *from,
                        ExceptionThruSeq *thrus,
                        ExceptionTo *to,
@@ -367,7 +366,7 @@ protected:
   bool own_pts_;
   // Hash is cached because there may be many objects to speed up
   // exception merging.
-  size_t hash_;
+  size_t hash_{0};
 
   // Maximum number of objects for to_string() to show.
   static const int to_string_max_objects_;
@@ -583,7 +582,7 @@ protected:
   // Leaf/port pins.
   PinSet *pins_;
   // Graph edges that traverse thru hierarchical pins.
-  EdgePinsSet *edges_;
+  EdgePinsSet *edges_{nullptr};
   NetSet *nets_;
   InstanceSet *insts_;
 };
@@ -602,9 +601,9 @@ public:
 
 private:
   const ExceptionPath *exception_;
-  bool from_done_;
+  bool from_done_{false};
   ExceptionThruSeq::iterator thru_iter_;
-  bool to_done_;
+  bool to_done_{false};
 };
 
 // Visitor for exception point sets expanded into single object paths.
@@ -665,7 +664,7 @@ public:
 private:
   ExceptionPath *exception_;
   ExceptionThru *next_thru_;
-  ExceptionState *next_state_;
+  ExceptionState *next_state_{nullptr};
   int index_;
 };
 

include/sta/FilterObjects.hh

@@ -41,52 +41,52 @@ class Report;
 
 PortSeq
 filterPorts(std::string_view filter_expression,
-            PortSeq *objects,
+            PortSeq *ports,
             Sta *sta);
 
 InstanceSeq
 filterInstances(std::string_view filter_expression,
-                InstanceSeq *objects,
+                InstanceSeq *insts,
                 Sta *sta);
 
 PinSeq
 filterPins(std::string_view filter_expression,
-           PinSeq *objects,
+           PinSeq *pins,
            Sta *sta);
 
 NetSeq
 filterNets(std::string_view filter_expression,
-           NetSeq *objects,
+           NetSeq *nets,
            Sta *sta);
 
 ClockSeq
 filterClocks(std::string_view filter_expression,
-             ClockSeq *objects,
+             ClockSeq *clks,
              Sta *sta);
 
 LibertyCellSeq
 filterLibCells(std::string_view filter_expression,
-               LibertyCellSeq *objects,
+               LibertyCellSeq *cells,
                Sta *sta);
 
 LibertyPortSeq
 filterLibPins(std::string_view filter_expression,
-              LibertyPortSeq *objects,
+              LibertyPortSeq *ports,
               Sta *sta);
 
 LibertyLibrarySeq
 filterLibertyLibraries(std::string_view filter_expression,
-                       LibertyLibrarySeq *objects,
+                       LibertyLibrarySeq *libs,
                        Sta *sta);
 
 EdgeSeq
 filterTimingArcs(std::string_view filter_expression,
-                  EdgeSeq *objects,
+                  EdgeSeq *edges,
                   Sta *sta);
 
 PathEndSeq
 filterPathEnds(std::string_view filter_expression,
-               PathEndSeq *objects,
+               PathEndSeq *ends,
                Sta *sta);
 
 // For FilterExpr unit tests.

include/sta/FuncExpr.hh

@@ -26,8 +26,8 @@
 
 #include <string>
 
-#include "NetworkClass.hh"
 #include "LibertyClass.hh"
+#include "NetworkClass.hh"
 
 namespace sta {
 

include/sta/Graph.hh

@@ -24,19 +24,19 @@
 
 #pragma once
 
-#include <mutex>
 #include <atomic>
 #include <map>
+#include <mutex>
 
-#include "Iterator.hh"
-#include "ObjectTable.hh"
-#include "LibertyClass.hh"
-#include "NetworkClass.hh"
 #include "Delay.hh"
 #include "GraphClass.hh"
-#include "VertexId.hh"
+#include "Iterator.hh"
+#include "LibertyClass.hh"
+#include "NetworkClass.hh"
+#include "ObjectTable.hh"
 #include "Path.hh"
 #include "StaState.hh"
+#include "VertexId.hh"
 
 namespace sta {
 
@@ -102,7 +102,7 @@ public:
                const Slew &slew);
 
   // Edge functions.
-  Edge *edge(EdgeId edge_index) const;
+  Edge *edge(EdgeId edge_id) const;
   EdgeId id(const Edge *edge) const;
   Edge *makeEdge(Vertex *from,
                  Vertex *to,
@@ -211,8 +211,8 @@ protected:
   void initArcDelays(Edge *edge);
   void removeDelayAnnotated(Edge *edge);
 
-  VertexTable *vertices_;
+  VertexTable *vertices_{nullptr};
-  EdgeTable *edges_;
+  EdgeTable *edges_{nullptr};
   // Bidirect pins are split into two vertices:
   //  load/sink (top level output, instance pin input) vertex in pin_vertex_map
   //  driver/source (top level input, instance pin output) vertex
@@ -436,9 +436,9 @@ private:
   Network *network_;
   Instance *top_inst_;
   LeafInstanceIterator *inst_iter_;
-  InstancePinIterator *pin_iter_;
+  InstancePinIterator *pin_iter_{nullptr};
-  Vertex *vertex_;
+  Vertex *vertex_{nullptr};
-  Vertex *bidir_vertex_;
+  Vertex *bidir_vertex_{nullptr};
 };
 
 class VertexInEdgeIterator : public VertexEdgeIterator

include/sta/GraphClass.hh

@@ -25,13 +25,13 @@
 #pragma once
 
 #include <limits>
-#include <vector>
 #include <set>
+#include <vector>
 
-#include "ObjectId.hh"
-#include "MinMax.hh"
-#include "Transition.hh"
 #include "Delay.hh"
+#include "MinMax.hh"
+#include "ObjectId.hh"
+#include "Transition.hh"
 
 namespace sta {
 

include/sta/GraphCmp.hh

@@ -24,9 +24,9 @@
 
 #pragma once
 
+#include "GraphClass.hh"
 #include "NetworkClass.hh"
 #include "NetworkCmp.hh"
-#include "GraphClass.hh"
 
 namespace sta {
 

include/sta/GraphDelayCalc.hh

@@ -25,16 +25,16 @@
 #pragma once
 
 #include <array>
-#include <vector>
 #include <map>
 #include <mutex>
+#include <vector>
 
-#include "NetworkClass.hh"
-#include "GraphClass.hh"
-#include "SearchClass.hh"
-#include "SdcClass.hh"
-#include "StaState.hh"
 #include "ArcDelayCalc.hh"
+#include "GraphClass.hh"
+#include "NetworkClass.hh"
+#include "SdcClass.hh"
+#include "SearchClass.hh"
+#include "StaState.hh"
 
 namespace sta {
 
@@ -104,7 +104,7 @@ public:
                float &pin_cap,
                float &wire_cap,
                float &fanout,
-               bool &has_set_load) const;
+               bool &has_net_load) const;
   void parasiticLoad(const Pin *drvr_pin,
                      const RiseFall *rf,
                      const Scene *scene,
@@ -171,7 +171,7 @@ protected:
 			    Vertex *drvr_vertex,
 			    const RiseFall *rf,
 			    const LibertyPort *from_port,
-			    float *from_slews,
+                            const DriveCellSlews *from_slews,
 			    const LibertyPort *to_port,
                             const Scene *scene,
                             const MinMax *min_max,
@@ -191,7 +191,7 @@ protected:
 			ArcDelayCalc *arc_delay_calc,
                         LoadPinIndexMap &load_pin_index_map);
   MultiDrvrNet *multiDrvrNet(const Vertex *drvr_vertex) const;
-  MultiDrvrNet *findMultiDrvrNet(Vertex *drvr_pin);
+  MultiDrvrNet *findMultiDrvrNet(Vertex *drvr_vertex);
   MultiDrvrNet *makeMultiDrvrNet(Vertex *drvr_vertex);
   bool hasMultiDrvrs(Vertex *drvr_vertex);
   Vertex *firstLoad(Vertex *drvr_vertex);
@@ -235,7 +235,7 @@ protected:
 		       ArcDelayCalc *arc_delay_calc,
 		       bool propagate);
   DrvrLoadSlews loadSlews(LoadPinIndexMap &load_pin_index_map);
-  bool loadSlewsChanged(DrvrLoadSlews &prev_load_slews,
+  bool loadSlewsChanged(DrvrLoadSlews &load_slews_prev,
                         LoadPinIndexMap &load_pin_index_map);
   void enqueueTimingChecksEdges(Vertex *vertex);
   bool annotateDelaysSlews(Edge *edge,
@@ -294,10 +294,10 @@ protected:
                bool &has_net_load) const;
 
   // Observer for edge delay changes.
-  DelayCalcObserver *observer_;
+  DelayCalcObserver *observer_{nullptr};
-  bool delays_seeded_;
+  bool delays_seeded_{false};
-  bool incremental_;
+  bool incremental_{false};
-  bool delays_exist_;
+  bool delays_exist_{false};
   // Vertices with invalid -to delays.
   VertexSet invalid_delays_;
   // Timing check edges with invalid delays.
@@ -313,7 +313,7 @@ protected:
   std::mutex multi_drvr_lock_;
   // Percentage (0.0:1.0) change in delay that causes downstream
   // delays to be recomputed during incremental delay calculation.
-  float incremental_delay_tolerance_;
+  float incremental_delay_tolerance_{0.0};
 
   friend class FindVertexDelays;
   friend class MultiDrvrNet;
@@ -334,7 +334,6 @@ public:
 class MultiDrvrNet
 {
 public:
-  MultiDrvrNet();
   VertexSeq &drvrs() { return drvrs_; }
   const VertexSeq &drvrs() const { return drvrs_; }
   bool parallelGates(const Network *network) const;
@@ -352,7 +351,7 @@ public:
 
 private:
   // Driver that triggers delay calculation for all the drivers on the net.
-  Vertex *dcalc_drvr_;
+  Vertex *dcalc_drvr_{nullptr};
   VertexSeq drvrs_;
   // [drvr_rf->index][dcalc_ap->index]
   std::vector<NetCaps> net_caps_;

include/sta/Hash.hh

@@ -24,8 +24,8 @@
 
 #pragma once
 
-#include <cstdint>
 #include <cstddef>
+#include <cstdint>
 #include <string_view>
 
 namespace sta {

include/sta/InputDrive.hh

@@ -24,10 +24,11 @@
 
 #pragma once
 
-#include "MinMax.hh"
 #include "LibertyClass.hh"
+#include "MinMax.hh"
 #include "NetworkClass.hh"
 #include "RiseFallMinMax.hh"
+#include "SdcClass.hh"
 
 namespace sta {
 
@@ -58,7 +59,7 @@ public:
   void setDriveCell(const LibertyLibrary *library,
                     const LibertyCell *cell,
                     const LibertyPort *from_port,
-                    float *from_slews,
+                    const DriveCellSlews &from_slews,
                     const LibertyPort *to_port,
                     const RiseFallBoth *rf,
                     const MinMaxAll *min_max);
@@ -67,7 +68,7 @@ public:
                  // Return values.
                  const LibertyCell *&cell,
                  const LibertyPort *&from_port,
-                 float *&from_slews,
+                 const DriveCellSlews *&from_slews,
                  const LibertyPort *&to_port) const;
   InputDriveCell *driveCell(const RiseFall *rf,
                             const MinMax *min_max) const;
@@ -94,7 +95,7 @@ public:
   InputDriveCell(const LibertyLibrary *library,
                  const LibertyCell *cell,
                  const LibertyPort *from_port,
-                 float *from_slews,
+                 const DriveCellSlews &from_slews,
                  const LibertyPort *to_port);
   const LibertyLibrary *library() const { return library_; }
   void setLibrary(const LibertyLibrary *library);
@@ -102,8 +103,8 @@ public:
   void setCell(const LibertyCell *cell);
   const LibertyPort *fromPort() const { return from_port_; }
   void setFromPort(const LibertyPort *from_port);
-  float *fromSlews() { return from_slews_; }
+  const DriveCellSlews &fromSlews() const { return from_slews_; }
-  void setFromSlews(float *from_slews);
+  void setFromSlews(const DriveCellSlews &from_slews);
   const LibertyPort *toPort() const { return to_port_; }
   void setToPort(const LibertyPort *to_port);
   bool equal(const InputDriveCell *drive) const;
@@ -112,7 +113,7 @@ private:
   const LibertyLibrary *library_;
   const LibertyCell *cell_;
   const LibertyPort *from_port_;
-  float from_slews_[RiseFall::index_count];
+  DriveCellSlews from_slews_;
   const LibertyPort *to_port_;
 };
 

include/sta/Liberty.hh

@@ -24,27 +24,27 @@
 
 #pragma once
 
-#include <memory>
-#include <mutex>
 #include <atomic>
 #include <functional>
-#include <set>
 #include <map>
+#include <memory>
+#include <mutex>
+#include <set>
 #include <string>
 #include <string_view>
 #include <vector>
 
-#include "ContainerHelpers.hh"
-#include "MinMax.hh"
-#include "RiseFallMinMax.hh"
 #include "ConcreteLibrary.hh"
-#include "RiseFallValues.hh"
+#include "ContainerHelpers.hh"
-#include "MinMaxValues.hh"
-#include "Transition.hh"
 #include "Delay.hh"
 #include "InternalPower.hh"
 #include "LeakagePower.hh"
 #include "LibertyClass.hh"
+#include "MinMax.hh"
+#include "MinMaxValues.hh"
+#include "RiseFallMinMax.hh"
+#include "RiseFallValues.hh"
+#include "Transition.hh"
 
 namespace sta {
 

include/sta/LibertyClass.hh

@@ -24,10 +24,10 @@
 
 #pragma once
 
-#include <memory>
-#include <vector>
 #include <map>
+#include <memory>
 #include <set>
+#include <vector>
 
 namespace sta {
 

include/sta/MinMax.hh

@@ -25,8 +25,8 @@
 #pragma once
 
 #include <array>
-#include <vector>
 #include <string>
+#include <vector>
 
 #include "Iterator.hh"
 

include/sta/MinMaxValues.hh

@@ -24,8 +24,8 @@
 
 #pragma once
 
-#include "MinMax.hh"
 #include "Error.hh"
+#include "MinMax.hh"
 
 namespace sta {
 

include/sta/Network.hh

@@ -29,11 +29,11 @@
 #include <string>
 #include <string_view>
 
-#include "StringUtil.hh"
 #include "LibertyClass.hh"
-#include "VertexId.hh"
 #include "NetworkClass.hh"
 #include "StaState.hh"
+#include "StringUtil.hh"
+#include "VertexId.hh"
 
 namespace sta {
 
@@ -93,7 +93,7 @@ using NetDrvrPinsMap = std::map<const Net*, PinSet*>;
 class Network : public StaState
 {
 public:
-  Network();
+  Network() = default;
   ~Network() override;
   virtual void clear();
 
@@ -446,7 +446,7 @@ protected:
   void findInstancesMatching1(const Instance *context,
                               size_t context_name_length,
                               const PatternMatch *pattern,
-                              InstanceSeq &insts) const;
+                              InstanceSeq &matches) const;
   void findInstancesHierMatching1(const Instance *instance,
                                   const PatternMatch *pattern,
                                   InstanceSeq &matches) const;
@@ -475,7 +475,7 @@ protected:
                                     const PatternMatch *pattern,
                                     // Return value.
                                     PinSeq &matches) const;
-  void findInstPinsHierMatching(const Instance *parent,
+  void findInstPinsHierMatching(const Instance *instance,
                                 const PatternMatch *pattern,
                                 // Return value.
                                 PinSeq &matches) const;
@@ -490,9 +490,9 @@ protected:
   // nets may be connected across hierarchy levels.
   void clearNetDrvrPinMap();
 
-  LibertyLibrary *default_liberty_;
+  LibertyLibrary *default_liberty_{nullptr};
-  char divider_;
+  char divider_{'/'};
-  char escape_;
+  char escape_{'\\'};
   NetDrvrPinsMap net_drvr_pin_map_;
 };
 
@@ -500,7 +500,7 @@ protected:
 class NetworkEdit : public Network
 {
 public:
-  NetworkEdit();
+  NetworkEdit() = default;
   bool isEditable() const override { return true; }
   virtual Instance *makeInstance(LibertyCell *cell,
                                  std::string_view name,
@@ -619,7 +619,7 @@ private:
                         PinSet &pins);
 
   const Network *network_;
-  PinSet constant_pins_[2];
+  PinSet constant_pins_[2]{PinSet(network_), PinSet(network_)};
   LogicValue value_;
   PinSet::iterator pin_iter_;
 };

include/sta/NetworkClass.hh

@@ -25,11 +25,11 @@
 #pragma once
 
 #include <cstdint>
-#include <string>
-#include <vector>
 #include <map>
 #include <set>
+#include <string>
 #include <unordered_set>
+#include <vector>
 
 #include "Iterator.hh"
 

include/sta/Parasitics.hh

@@ -28,11 +28,11 @@
 #include <map>
 #include <vector>
 
-#include "StaState.hh"
 #include "LibertyClass.hh"
 #include "NetworkClass.hh"
-#include "SdcClass.hh"
 #include "ParasiticsClass.hh"
+#include "SdcClass.hh"
+#include "StaState.hh"
 
 namespace sta {
 
@@ -164,12 +164,12 @@ public:
   // Parasitic network component builders.
   virtual ParasiticNode *findParasiticNode(Parasitic *parasitic,
                                            const Net *net,
-                                           int id,
+                                           uint32_t id,
                                            const Network *network) const = 0;
   // Make a subnode of the parasitic network net.
   virtual ParasiticNode *ensureParasiticNode(Parasitic *parasitic,
                                              const Net *net,
-                                             int id,
+                                             uint32_t id,
                                              const Network *network) = 0;
   // Find the parasitic node connected to pin.
   virtual ParasiticNode *findParasiticNode(const Parasitic *parasitic,
@@ -195,11 +195,11 @@ public:
 
   // Coupling capacitor between parasitic nodes on a net.
   virtual void makeCapacitor(Parasitic *parasitic,
-                             size_t id,
+                             uint32_t id,
                              float cap,
                              ParasiticNode *node1,
                              ParasiticNode *node2) = 0;
-  virtual size_t id(const ParasiticCapacitor *capacitor) const = 0;
+  virtual uint32_t id(const ParasiticCapacitor *capacitor) const = 0;
   virtual float value(const ParasiticCapacitor *capacitor) const = 0;
   virtual ParasiticNode *node1(const ParasiticCapacitor *capacitor) const = 0;
   virtual ParasiticNode *node2(const ParasiticCapacitor *capacitor) const = 0;
@@ -207,15 +207,15 @@ public:
                                    ParasiticNode *node) const;
 
   virtual void makeResistor(Parasitic *parasitic,
-                            size_t id,
+                            uint32_t id,
                             float res,
                             ParasiticNode *node1,
                             ParasiticNode *node2) = 0;
-  virtual size_t id(const ParasiticResistor *resistor) const = 0;
+  virtual uint32_t id(const ParasiticResistor *resistor) const = 0;
   virtual float value(const ParasiticResistor *resistor) const = 0;
   virtual ParasiticNode *node1(const ParasiticResistor *resistor) const = 0;
   virtual ParasiticNode *node2(const ParasiticResistor *resistor) const = 0;
-  virtual ParasiticNode *otherNode(const ParasiticResistor *capacitor,
+  virtual ParasiticNode *otherNode(const ParasiticResistor *resistor,
                                    ParasiticNode *node) const;
 
   // Iteration over resistors connected to a nodes.
@@ -287,7 +287,7 @@ protected:
 
   const Net *findParasiticNet(const Pin *pin) const;
 
-  float coupling_cap_factor_;
+  float coupling_cap_factor_ {1.0};
 };
 
 class ParasiticNodeLess

include/sta/Path.hh

@@ -24,14 +24,14 @@
 
 #pragma once
 
+#include "Delay.hh"
+#include "GraphClass.hh"
 #include "MinMax.hh"
 #include "NetworkClass.hh"
 #include "SdcClass.hh"
-#include "Transition.hh"
-#include "GraphClass.hh"
-#include "Delay.hh"
-#include "StaState.hh"
 #include "SearchClass.hh"
+#include "StaState.hh"
+#include "Transition.hh"
 
 namespace sta {
 

include/sta/PathEnd.hh

@@ -26,11 +26,11 @@
 
 #include <string>
 
-#include "LibertyClass.hh"
 #include "GraphClass.hh"
+#include "LibertyClass.hh"
+#include "Path.hh"
 #include "SdcClass.hh"
 #include "SearchClass.hh"
-#include "Path.hh"
 #include "StaState.hh"
 
 namespace sta {

include/sta/PathExpanded.hh

@@ -24,11 +24,11 @@
 
 #pragma once
 
-#include "TimingArc.hh"
 #include "GraphClass.hh"
-#include "SearchClass.hh"
 #include "Path.hh"
+#include "SearchClass.hh"
 #include "StaState.hh"
+#include "TimingArc.hh"
 
 namespace sta {
 

include/sta/PathGroup.hh

@@ -24,17 +24,17 @@
 
 #pragma once
 
+#include <map>
+#include <mutex>
 #include <string>
 #include <string_view>
 #include <vector>
-#include <map>
-#include <mutex>
 
-#include "SdcClass.hh"
-#include "StaState.hh"
-#include "SearchClass.hh"
-#include "StringUtil.hh"
 #include "PathEnd.hh"
+#include "SdcClass.hh"
+#include "SearchClass.hh"
+#include "StaState.hh"
+#include "StringUtil.hh"
 
 namespace sta {
 

include/sta/PortDelay.hh

@@ -59,9 +59,9 @@ protected:
 
   const Pin *pin_;
   const ClockEdge *clk_edge_;
-  bool source_latency_included_;
+  bool source_latency_included_{false};
-  bool network_latency_included_;
+  bool network_latency_included_{false};
-  const Pin *ref_pin_;
+  const Pin *ref_pin_{nullptr};
   RiseFallMinMax delays_;
   PinSet leaf_pins_;
 };

include/sta/PortExtCap.hh

@@ -25,10 +25,10 @@
 #pragma once
 
 #include "MinMax.hh"
-#include "Transition.hh"
-#include "RiseFallMinMax.hh"
 #include "MinMaxValues.hh"
 #include "NetworkClass.hh"
+#include "RiseFallMinMax.hh"
+#include "Transition.hh"
 
 namespace sta {
 
@@ -38,7 +38,6 @@ using FanoutValues = MinMaxIntValues;
 class PortExtCap
 {
 public:
-  PortExtCap();
   const Port *port() { return port_; }
   void pinCap(const RiseFall *rf,
               const MinMax *min_max,
@@ -70,7 +69,7 @@ public:
   const FanoutValues *fanout() const { return &fanout_; }
 
 private:
-  const Port *port_;
+  const Port *port_{nullptr};
   RiseFallMinMax pin_cap_;
   RiseFallMinMax wire_cap_;
   FanoutValues fanout_;

include/sta/PowerClass.hh

@@ -24,12 +24,13 @@
 
 #pragma once
 
-#include <vector>
 #include <utility>
+#include <vector>
 
 namespace sta {
 
 class Power;
+class Instance;
 
 enum class PwrActivityOrigin
 {

include/sta/Property.hh

@@ -24,16 +24,16 @@
 
 #pragma once
 
+#include <functional>
 #include <map>
 #include <string>
 #include <string_view>
-#include <functional>
 
 #include "LibertyClass.hh"
 #include "NetworkClass.hh"
-#include "SearchClass.hh"
-#include "SdcClass.hh"
 #include "PowerClass.hh"
+#include "SdcClass.hh"
+#include "SearchClass.hh"
 
 namespace sta {
 

include/sta/Report.hh

@@ -24,15 +24,15 @@
 
 #pragma once
 
-#include <stdio.h>
 #include <cstdarg>
-#include <string>
-#include <string_view>
 #include <mutex>
 #include <set>
+#include <cstdio>
+#include <string>
+#include <string_view>
 
-#include "Machine.hh"  // __attribute__
 #include "Format.hh"
+#include "Machine.hh"  // __attribute__
 
 struct Tcl_Interp;
 

include/sta/RiseFallMinMaxDelay.hh

@@ -24,9 +24,9 @@
 
 #pragma once
 
+#include "Delay.hh"
 #include "MinMax.hh"
 #include "Transition.hh"
-#include "Delay.hh"
 
 namespace sta {
 

include/sta/Scene.hh

@@ -24,9 +24,9 @@
 
 #pragma once
 
+#include <set>
 #include <string>
 #include <vector>
-#include <set>
 
 #include "GraphClass.hh"
 #include "SearchClass.hh"

include/sta/Sdc.hh

@@ -24,25 +24,25 @@
 
 #pragma once
 
-#include <vector>
 #include <map>
-#include <unordered_map>
 #include <mutex>
 #include <string_view>
+#include <unordered_map>
+#include <vector>
 
-#include "StringUtil.hh"
-#include "MinMax.hh"
-#include "StaState.hh"
-#include "NetworkClass.hh"
-#include "LibertyClass.hh"
-#include "GraphClass.hh"
-#include "SdcClass.hh"
-#include "RiseFallValues.hh"
 #include "Clock.hh"
-#include "DataCheck.hh"
 #include "CycleAccting.hh"
+#include "DataCheck.hh"
 #include "ExceptionPath.hh"
+#include "GraphClass.hh"
+#include "LibertyClass.hh"
+#include "MinMax.hh"
+#include "NetworkClass.hh"
 #include "PinPair.hh"
+#include "RiseFallValues.hh"
+#include "SdcClass.hh"
+#include "StaState.hh"
+#include "StringUtil.hh"
 
 namespace sta {
 
@@ -54,7 +54,7 @@ class DisabledPorts;
 class GraphLoop;
 class DeratingFactors;
 class DeratingFactorsGlobal;
-class DeratingFactorsNet;
+class DeratingFactors;
 class DeratingFactorsCell;
 class PatternMatch;
 class FindNetCaps;
@@ -174,7 +174,7 @@ using InstancePvtMap = std::map<const Instance*, Pvt*>;
 using PinMinPulseWidthMap = std::map<const Pin*, RiseFallValues*>;
 using ClockMinPulseWidthMap = std::map<const Clock*, RiseFallValues*>;
 using InstMinPulseWidthMap = std::map<const Instance*, RiseFallValues*>;
-using NetDeratingFactorsMap = std::map<const Net*, DeratingFactorsNet*>;
+using NetDeratingFactorsMap = std::map<const Net*, DeratingFactors*>;
 using InstDeratingFactorsMap = std::map<const Instance*, DeratingFactorsCell*>;
 using CellDeratingFactorsMap = std::map<const LibertyCell*, DeratingFactorsCell*>;
 using ClockGroupsSet = std::set<ClockGroups*>;
@@ -279,7 +279,7 @@ public:
                     const LibertyCell *cell,
                     const Port *port,
                     const LibertyPort *from_port,
-                    float *from_slews,
+                    const DriveCellSlews &from_slews,
                     const LibertyPort *to_port,
                     const RiseFallBoth *rf,
                     const MinMaxAll *min_max);

include/sta/SdcClass.hh

@@ -29,9 +29,10 @@
 #include <vector>
 
 #include "LibertyClass.hh"
-#include "NetworkClass.hh"
 #include "MinMaxValues.hh"
+#include "NetworkClass.hh"
 #include "PinPair.hh"
+#include "Transition.hh"
 
 namespace sta {
 
@@ -126,11 +127,13 @@ using ExceptionStateSet = std::set<ExceptionState*, ExceptionStateLess>;
 // Constraint applies to clock or data paths.
 enum class PathClkOrData { clk, data };
 
-const int path_clk_or_data_count = 2;
+const size_t path_clk_or_data_count = 2;
 
 enum class TimingDerateType { cell_delay, cell_check, net_delay };
-constexpr int timing_derate_type_count = 3;
+constexpr size_t timing_derate_type_count = 3;
 enum class TimingDerateCellType { cell_delay, cell_check };
-constexpr int timing_derate_cell_type_count = 2;
+constexpr size_t timing_derate_cell_type_count = 2;
+
+using DriveCellSlews = std::array<float, RiseFall::index_count>;
 
 } // namespace sta

include/sta/SdcNetwork.hh

@@ -217,15 +217,15 @@ public:
   InstanceSeq findInstancesMatching(const Instance *context,
                                     const PatternMatch *pattern) const override;
   Net *findNet(std::string_view path_name) const override;
-  Net *findNetRelative(const Instance *instance,
+  Net *findNetRelative(const Instance *inst,
-                       std::string_view net_name) const override;
+                       std::string_view path_name) const override;
   Net *findNet(const Instance *instance,
                std::string_view net_name) const override;
   NetSeq findNetsMatching(const Instance *parent,
                           const PatternMatch *pattern) const override;
   void findInstNetsMatching(const Instance *instance,
                             const PatternMatch *pattern,
-                            NetSeq &nets) const override;
+                            NetSeq &matches) const override;
   Instance *findChild(const Instance *parent,
                       std::string_view name) const override;
   Pin *findPin(std::string_view path_name) const override;
@@ -266,9 +266,9 @@ protected:
                  std::string &path_tail) const;
   bool visitMatches(const Instance *parent,
                     const PatternMatch *pattern,
-                    std::function<bool (const Instance *instance,
+                    const std::function<bool (const Instance *instance,
-                                        const PatternMatch *tail)>
+                                              const PatternMatch *tail)>
-                    visit_tail) const;
+                    &visit_tail) const;
   bool visitPinTail(const Instance *instance,
                     const PatternMatch *tail,
                     PinSeq &matches) const;

include/sta/Search.hh

@@ -24,23 +24,23 @@
 
 #pragma once
 
-#include <mutex>
 #include <atomic>
+#include <mutex>
 #include <unordered_set>
 
-#include "MinMax.hh"
-#include "Transition.hh"
-#include "LibertyClass.hh"
-#include "NetworkClass.hh"
-#include "GraphClass.hh"
 #include "Delay.hh"
+#include "GraphClass.hh"
+#include "LibertyClass.hh"
+#include "MinMax.hh"
+#include "NetworkClass.hh"
+#include "Path.hh"
 #include "SdcClass.hh"
-#include "StaState.hh"
 #include "SearchClass.hh"
 #include "SearchPred.hh"
-#include "VertexVisitor.hh"
+#include "StaState.hh"
-#include "Path.hh"
 #include "StringUtil.hh"
+#include "Transition.hh"
+#include "VertexVisitor.hh"
 
 namespace sta {
 
@@ -696,7 +696,6 @@ protected:
 
 // Class for visiting fanin/fanout paths of a vertex.
 // This used by forward/backward search to find arrival/required path times.
-// NOLINTNEXTLINE(misc-multiple-inheritance)
 class PathVisitor : public VertexVisitor,
                     public StaState
 {

include/sta/SearchClass.hh

@@ -25,14 +25,14 @@
 #pragma once
 
 #include <limits>
-#include <vector>
 #include <map>
+#include <vector>
 
-#include "VectorMap.hh"
-#include "MinMaxValues.hh"
 #include "Delay.hh"
-#include "NetworkClass.hh"
 #include "GraphClass.hh"
+#include "MinMaxValues.hh"
+#include "NetworkClass.hh"
+#include "VectorMap.hh"
 
 namespace sta {
 

include/sta/SearchPred.hh

@@ -24,9 +24,9 @@
 
 #pragma once
 
-#include "NetworkClass.hh"
 #include "GraphClass.hh"
 #include "LibertyClass.hh"
+#include "NetworkClass.hh"
 #include "StaState.hh"
 
 namespace sta {

include/sta/Sta.hh

@@ -24,27 +24,27 @@
 
 #pragma once
 
-#include <vector>
+#include <functional>
 #include <string>
 #include <string_view>
-#include <functional>
+#include <vector>
 
-#include "StringUtil.hh"
-#include "LibertyClass.hh"
-#include "NetworkClass.hh"
-#include "SdcClass.hh"
-#include "Scene.hh"
-#include "GraphClass.hh"
-#include "ParasiticsClass.hh"
-#include "StaState.hh"
-#include "VertexVisitor.hh"
-#include "SearchClass.hh"
-#include "PowerClass.hh"
 #include "ArcDelayCalc.hh"
 #include "CircuitSim.hh"
-#include "Variables.hh"
+#include "GraphClass.hh"
+#include "LibertyClass.hh"
+#include "NetworkClass.hh"
+#include "ParasiticsClass.hh"
+#include "PowerClass.hh"
 #include "Property.hh"
 #include "RiseFallMinMaxDelay.hh"
+#include "Scene.hh"
+#include "SdcClass.hh"
+#include "SearchClass.hh"
+#include "StaState.hh"
+#include "StringUtil.hh"
+#include "Variables.hh"
+#include "VertexVisitor.hh"
 
 struct Tcl_Interp;
 
@@ -267,7 +267,7 @@ public:
                     const LibertyCell *cell,
                     const Port *port,
                     const LibertyPort *from_port,
-                    float *from_slews,
+                    const DriveCellSlews &from_slews,
                     const LibertyPort *to_port,
                     const RiseFallBoth *rf,
                     const MinMaxAll *min_max,

include/sta/StringUtil.hh

@@ -28,10 +28,10 @@
 #include <cctype>
 #include <cstdarg>
 #include <cstring>
+#include <set>
 #include <string>
 #include <string_view>
 #include <vector>
-#include <set>
 
 #include "Machine.hh" // __attribute__
 

include/sta/TableModel.hh

@@ -30,10 +30,10 @@
 #include <string_view>
 #include <vector>
 
-#include "MinMax.hh"
-#include "Transition.hh"
 #include "LibertyClass.hh"
+#include "MinMax.hh"
 #include "TimingModel.hh"
+#include "Transition.hh"
 #include "Variables.hh"
 
 namespace sta {

include/sta/TclTypeHelpers.hh

@@ -30,17 +30,17 @@
 namespace sta {
 
 #if TCL_MAJOR_VERSION < 9
-    typedef int Tcl_Size;
+    using Tcl_Size = int ;
 #endif
 
 StringSeq
-tclListStringSeq(Tcl_Obj *const source,
+tclListStringSeq(Tcl_Obj *source,
                  Tcl_Interp *interp);
 StringSeq *
-tclListStringSeqPtr(Tcl_Obj *const source,
+tclListStringSeqPtr(Tcl_Obj *source,
                     Tcl_Interp *interp);
 StringSet *
-tclListStringSet(Tcl_Obj *const source,
+tclListStringSet(Tcl_Obj *source,
                  Tcl_Interp *interp);
 
 void

include/sta/TimingArc.hh

@@ -24,14 +24,14 @@
 
 #pragma once
 
+#include <map>
 #include <memory>
 #include <string>
 #include <vector>
-#include <map>
 
-#include "Transition.hh"
 #include "Delay.hh"
 #include "LibertyClass.hh"
+#include "Transition.hh"
 
 namespace sta {
 

include/sta/Variables.hh

@@ -34,7 +34,6 @@ enum class CrprMode { same_pin, same_transition };
 class Variables
 {
 public:
-  Variables();
   // TCL variable sta_crpr_enabled.
   bool crprEnabled() const { return crpr_enabled_; }
   void setCrprEnabled(bool enabled);
@@ -78,23 +77,23 @@ public:
   PocvMode pocvMode() const { return pocv_mode_; }
   void setPocvMode(PocvMode mode);
   float pocvQuantile() const { return pocv_quantile_; }
-  void setPocvQuantile(float quartile);
+  void setPocvQuantile(float quantile);
 
 private:
-  bool crpr_enabled_;
+  bool crpr_enabled_{true};
-  CrprMode crpr_mode_;
+  CrprMode crpr_mode_{CrprMode::same_pin};
-  bool propagate_gated_clock_enable_;
+  bool propagate_gated_clock_enable_{true};
-  bool preset_clr_arcs_enabled_;
+  bool preset_clr_arcs_enabled_{false};
-  bool cond_default_arcs_enabled_;
+  bool cond_default_arcs_enabled_{true};
-  bool bidirect_inst_paths_enabled_;
+  bool bidirect_inst_paths_enabled_{false};
-  bool recovery_removal_checks_enabled_;
+  bool recovery_removal_checks_enabled_{true};
-  bool gated_clk_checks_enabled_;
+  bool gated_clk_checks_enabled_{true};
-  bool clk_thru_tristate_enabled_;
+  bool clk_thru_tristate_enabled_{false};
-  bool dynamic_loop_breaking_;
+  bool dynamic_loop_breaking_{false};
-  bool propagate_all_clks_;
+  bool propagate_all_clks_{false};
-  bool use_default_arrival_clock_;
+  bool use_default_arrival_clock_{false};
-  PocvMode pocv_mode_;
+  PocvMode pocv_mode_{PocvMode::scalar};
-  float pocv_quantile_;
+  float pocv_quantile_{3.0};
 };
 
 } // namespace sta

include/sta/VectorMap.hh

@@ -24,12 +24,12 @@
 
 #pragma once
 
-#include <vector>
 #include <algorithm>
-#include <utility>
 #include <iterator>
 #include <stdexcept>
 #include <type_traits>
+#include <utility>
+#include <vector>
 
 namespace sta {
 

include/sta/VerilogNamespace.hh

@@ -39,12 +39,12 @@ std::string
 portVerilogName(std::string_view sta_name);
 
 std::string
-moduleVerilogToSta(std::string_view sta_name);
+moduleVerilogToSta(std::string_view module_name);
 std::string
-instanceVerilogToSta(std::string_view sta_name);
+instanceVerilogToSta(std::string_view inst_name);
 std::string
-netVerilogToSta(std::string_view sta_name);
+netVerilogToSta(std::string_view net_name);
 std::string
-portVerilogToSta(std::string_view sta_name);
+portVerilogToSta(std::string_view port_name);
 
 } // namespace sta

include/sta/VerilogReader.hh

@@ -24,15 +24,15 @@
 
 #pragma once
 
+#include <map>
 #include <string>
 #include <string_view>
 #include <vector>
-#include <map>
 
 #include "Format.hh"
+#include "NetworkClass.hh"
 #include "Report.hh"
 #include "StringUtil.hh"
-#include "NetworkClass.hh"
 
 namespace sta {
 
@@ -104,12 +104,12 @@ public:
   ~VerilogReader();
   bool read(std::string_view filename);
 
-  void makeModule(std::string_view module_name,
+  void makeModule(std::string_view module_vname,
                   VerilogNetSeq *ports,
                   VerilogStmtSeq *stmts,
                   VerilogAttrStmtSeq *attr_stmts,
                   int line);
-  void makeModule(std::string_view module_name,
+  void makeModule(std::string_view module_vname,
                   VerilogStmtSeq *port_dcls,
                   VerilogStmtSeq *stmts,
                   VerilogAttrStmtSeq *attr_stmts,
@@ -122,8 +122,8 @@ public:
                       VerilogDclArg *arg,
                       VerilogAttrStmtSeq *attr_stmts,
                       int line);
-  VerilogDclArg *makeDclArg(std::string_view net_name);
+  VerilogDclArg *makeDclArg(std::string_view net_vname);
-  VerilogDclArg*makeDclArg(VerilogAssign *assign);
+  VerilogDclArg *makeDclArg(VerilogAssign *assign);
   VerilogDclBus *makeDclBus(PortDirection *dir,
                             int from_index,
                             int to_index,
@@ -136,8 +136,8 @@ public:
                             VerilogDclArgSeq *args,
                             VerilogAttrStmtSeq *attr_stmts,
                             int line);
-  VerilogInst *makeModuleInst(std::string_view module_name,
+  VerilogInst *makeModuleInst(std::string_view module_vname,
-                              std::string_view inst_name,
+                              std::string_view inst_vname,
                               VerilogNetSeq *pins,
                               VerilogAttrStmtSeq *attr_stmts,
                               int line);
@@ -146,17 +146,17 @@ public:
                             int line);
   VerilogNetScalar *makeNetScalar(std::string_view name);
   VerilogNetPortRef *makeNetNamedPortRefScalarNet(std::string_view port_vname);
-  VerilogNetPortRef *makeNetNamedPortRefScalarNet(std::string_view port_name,
+  VerilogNetPortRef *makeNetNamedPortRefScalarNet(std::string_view port_vname,
-                                                  std::string_view net_name);
+                                                  std::string_view net_vname);
-  VerilogNetPortRef *makeNetNamedPortRefBitSelect(std::string_view port_name,
+  VerilogNetPortRef *makeNetNamedPortRefBitSelect(std::string_view port_vname,
-                                                  std::string_view bus_name,
+                                                  std::string_view bus_vname,
                                                   int index);
-  VerilogNetPortRef *makeNetNamedPortRefScalar(std::string_view port_name,
+  VerilogNetPortRef *makeNetNamedPortRefScalar(std::string_view port_vname,
                                                VerilogNet *net);
-  VerilogNetPortRef *makeNetNamedPortRefBit(std::string_view port_name,
+  VerilogNetPortRef *makeNetNamedPortRefBit(std::string_view port_vname,
                                             int index,
                                             VerilogNet *net);
-  VerilogNetPortRef *makeNetNamedPortRefPart(std::string_view port_name,
+  VerilogNetPortRef *makeNetNamedPortRefPart(std::string_view port_vname,
                                              int from_index,
                                              int to_index,
                                              VerilogNet *net);
@@ -306,8 +306,8 @@ protected:
   Debug *debug_;
   NetworkReader *network_;
 
-  Library *library_;
+  Library *library_{nullptr};
-  int black_box_index_;
+  int black_box_index_{0};
   VerilogModuleMap module_map_;
   VerilogErrorSeq link_errors_;
   const std::string zero_net_name_;

include/sta/VertexVisitor.hh

@@ -24,8 +24,8 @@
 
 #pragma once
 
-#include "NetworkClass.hh"
 #include "GraphClass.hh"
+#include "NetworkClass.hh"
 
 namespace sta {
 

include/sta/VisitPathEnds.hh

@@ -24,8 +24,8 @@
 
 #pragma once
 
-#include "SdcClass.hh"
 #include "GraphClass.hh"
+#include "SdcClass.hh"
 #include "SearchClass.hh"
 #include "StaState.hh"
 

network/ConcreteLibrary.cc

@@ -28,11 +28,11 @@
 #include <cstdlib>
 #include <limits>
 
+#include "ConcreteNetwork.hh"
 #include "ContainerHelpers.hh"
+#include "ParseBus.hh"
 #include "PatternMatch.hh"
 #include "PortDirection.hh"
-#include "ParseBus.hh"
-#include "ConcreteNetwork.hh"
 
 namespace sta {
 
@@ -44,9 +44,7 @@ ConcreteLibrary::ConcreteLibrary(std::string_view name,
   name_(name),
   id_(ConcreteNetwork::nextObjectId()),
   filename_(filename),
-  is_liberty_(is_liberty),
+  is_liberty_(is_liberty)
-  bus_brkt_left_('['),
-  bus_brkt_right_(']')
 {
 }
 
@@ -125,9 +123,6 @@ ConcreteCell::ConcreteCell(std::string_view name,
   id_(ConcreteNetwork::nextObjectId()),
   filename_(filename),
   library_(library),
-  liberty_cell_(nullptr),
-  ext_cell_(nullptr),
-  port_bit_count_(0),
   is_leaf_(is_leaf)
 {
 }
@@ -234,7 +229,7 @@ ConcreteCell::makeBusPortBit(ConcretePort *bus_port,
 }
 
 ConcretePort *
-ConcreteCell::makePort(std::string bit_name,
+ConcreteCell::makePort(std::string_view bit_name,
                        int bit_index)
 {
   ConcretePort *port = new ConcretePort(bit_name, false,
@@ -353,7 +348,7 @@ BusPort::addBusBit(ConcretePort *port,
 void
 ConcreteCell::groupBusPorts(char bus_brkt_left,
                             char bus_brkt_right,
-                            std::function<bool(std::string_view)> port_msb_first)
+                            const std::function<bool(std::string_view)> &port_msb_first)
 {
   const char bus_brkts_left[2]{bus_brkt_left, '\0'};
   const char bus_brkts_right[2]{bus_brkt_right, '\0'};
@@ -415,15 +410,11 @@ ConcretePort::ConcretePort(std::string_view name,
   id_(ConcreteNetwork::nextObjectId()),
   cell_(cell),
   direction_(PortDirection::unknown()),
-  liberty_port_(nullptr),
-  ext_port_(nullptr),
-  pin_index_(-1),
   is_bundle_(is_bundle),
   is_bus_(is_bus),
   from_index_(from_index),
   to_index_(to_index),
-  member_ports_(member_ports),
+  member_ports_(member_ports)
-  bundle_port_(nullptr)
 {
 }
 
@@ -575,9 +566,7 @@ ConcretePort::memberIterator() const
 
 ConcreteCellPortBitIterator::ConcreteCellPortBitIterator(const ConcreteCell* cell) :
   ports_(cell->ports_),
-  port_iter_(ports_.begin()),
+  port_iter_(ports_.begin())
-  member_iter_(nullptr),
-  next_(nullptr)
 {
   findNext();
 }

network/ConcreteNetwork.cc

@@ -24,15 +24,16 @@
 
 #include "ConcreteNetwork.hh"
 
+#include <algorithm>
 #include <map>
 #include <string_view>
 
-#include "PatternMatch.hh"
-#include "Report.hh"
-#include "Liberty.hh"
-#include "PortDirection.hh"
 #include "ConcreteLibrary.hh"
+#include "Liberty.hh"
 #include "Network.hh"
+#include "PatternMatch.hh"
+#include "PortDirection.hh"
+#include "Report.hh"
 
 namespace sta {
 
@@ -105,13 +106,12 @@ private:
 
   ConcreteInstanceNetMap *nets_;
   ConcreteInstanceNetMap::iterator iter_;
-  ConcreteNet *next_;
+  ConcreteNet *next_{nullptr};
 };
 
 ConcreteInstanceNetIterator::
 ConcreteInstanceNetIterator(ConcreteInstanceNetMap *nets):
-  nets_(nets),
+  nets_(nets)
-  next_(nullptr)
 {
   if (nets) {
     iter_ = nets->begin();
@@ -161,7 +161,7 @@ private:
 
   const ConcretePinSeq &pins_;
   int pin_count_;
-  int pin_index_;
+  int pin_index_{0};
   ConcretePin *next_;
 };
 
@@ -169,8 +169,7 @@ ConcreteInstancePinIterator::
 ConcreteInstancePinIterator(const ConcreteInstance *inst,
                             int pin_count) :
   pins_(inst->pins_),
-  pin_count_(pin_count),
+  pin_count_(pin_count)
-  pin_index_(0)
 {
   findNext();
 }
@@ -271,24 +270,31 @@ ObjectId ConcreteNetwork::object_id_ = 0;
 
 ConcreteNetwork::ConcreteNetwork() :
   NetworkReader(),
-  top_instance_(nullptr),
-  constant_nets_{NetSet(this), NetSet(this)},
   link_func_(nullptr)
 {
 }
 
 ConcreteNetwork::~ConcreteNetwork()
 {
-  clear();
+  // Cannot call virtual functions in destructor.
+  clearImpl();
+}
+
+void
+ConcreteNetwork::clearImpl()
+{
+  if (top_instance_)
+    deleteInstanceImpl(top_instance_);
+  top_instance_ = nullptr;
+  deleteCellNetworkViewsImpl();
+  deleteContents(library_seq_);
+  library_map_.clear();
 }
 
 void
 ConcreteNetwork::clear()
 {
-  deleteTopInstance();
+  clearImpl();
-  deleteCellNetworkViews();
-  deleteContents(library_seq_);
-  library_map_.clear();
   Network::clear();
 }
 
@@ -303,6 +309,12 @@ ConcreteNetwork::deleteTopInstance()
 
 void
 ConcreteNetwork::deleteCellNetworkViews()
+{
+  deleteCellNetworkViewsImpl();
+}
+
+void
+ConcreteNetwork::deleteCellNetworkViewsImpl()
 {
   for (auto [cell, view] : cell_network_view_map_) {
     if (view)
@@ -361,7 +373,6 @@ class ConcreteLibertyLibraryIterator : public Iterator<LibertyLibrary*>
 {
 public:
   ConcreteLibertyLibraryIterator(const ConcreteNetwork *network);
-  virtual ~ConcreteLibertyLibraryIterator();
   bool hasNext() override;
   LibertyLibrary *next() override;
 
@@ -370,22 +381,17 @@ private:
 
   const ConcreteLibrarySeq &libs_;
   ConcreteLibrarySeq::const_iterator iter_;
-  LibertyLibrary *next_;
+  LibertyLibrary *next_{nullptr};
 };
 
 ConcreteLibertyLibraryIterator::
 ConcreteLibertyLibraryIterator(const ConcreteNetwork *network):
   libs_(network->library_seq_),
-  iter_(libs_.begin()),
+  iter_(libs_.begin())
-  next_(nullptr)
 {
   findNext();
 }
 
-ConcreteLibertyLibraryIterator::~ConcreteLibertyLibraryIterator()
-{
-}
-
 bool
 ConcreteLibertyLibraryIterator::hasNext()
 {
@@ -462,7 +468,7 @@ ConcreteNetwork::deleteLibrary(Library *library)
 {
   ConcreteLibrary *clib = reinterpret_cast<ConcreteLibrary*>(library);
   library_map_.erase(clib->name());
-  library_seq_.erase(std::find(library_seq_.begin(), library_seq_.end(), clib));
+  library_seq_.erase(std::ranges::find(library_seq_, clib));
   delete clib;
 }
 
@@ -721,7 +727,7 @@ class ConcreteCellPortIterator1 : public CellPortIterator
 {
 public:
   ConcreteCellPortIterator1(const ConcreteCell *cell);
-  ~ConcreteCellPortIterator1();
+  ~ConcreteCellPortIterator1() override;
   bool hasNext() override { return iter_->hasNext(); }
   Port *next() override;
 
@@ -758,7 +764,7 @@ class ConcreteCellPortBitIterator1 : public CellPortIterator
 {
 public:
   ConcreteCellPortBitIterator1(const ConcreteCell *cell);
-  ~ConcreteCellPortBitIterator1();
+  ~ConcreteCellPortBitIterator1() override;
   bool hasNext() override { return iter_->hasNext(); }
   Port *next() override;
 
@@ -905,19 +911,18 @@ class ConcretePortMemberIterator1 : public PortMemberIterator
 {
 public:
   ConcretePortMemberIterator1(const ConcretePort *port);
-  ~ConcretePortMemberIterator1();
+  ~ConcretePortMemberIterator1() override;
   bool hasNext() override;
   Port *next() override;
 
 private:
   ConcretePortMemberIterator *iter_;
-  ConcretePort *next_;
+  ConcretePort *next_{nullptr};
 };
 
 ConcretePortMemberIterator1::ConcretePortMemberIterator1(const ConcretePort *
                                                          port) :
-  iter_(port->memberIterator()),
+  iter_(port->memberIterator())
-  next_(nullptr)
 {
 }
 
@@ -1051,7 +1056,7 @@ ConcreteNetwork::findInstNetsMatching(const Instance *instance,
 {
   const ConcreteInstance *inst =
     reinterpret_cast<const ConcreteInstance*>(instance);
-  return inst->findNetsMatching(pattern, matches);
+  inst->findNetsMatching(pattern, matches);
 }
 
 ////////////////////////////////////////////////////////////////
@@ -1191,13 +1196,13 @@ ConcreteNetwork::instance(const Net *net) const
 bool
 ConcreteNetwork::isPower(const Net *net) const
 {
-  return constant_nets_[int(LogicValue::one)].contains(const_cast<Net*>(net));
+  return constant_nets_[static_cast<int>(LogicValue::one)].contains(const_cast<Net*>(net));
 }
 
 bool
 ConcreteNetwork::isGround(const Net *net) const
 {
-  return constant_nets_[int(LogicValue::zero)].contains(const_cast<Net*>(net));
+  return constant_nets_[static_cast<int>(LogicValue::zero)].contains(const_cast<Net*>(net));
 }
 
 NetPinIterator *
@@ -1308,6 +1313,12 @@ ConcreteNetwork::replaceCell(Instance *inst,
 
 void
 ConcreteNetwork::deleteInstance(Instance *inst)
+{
+  deleteInstanceImpl(inst);
+}
+
+void
+ConcreteNetwork::deleteInstanceImpl(Instance *inst)
 {
   ConcreteInstance *cinst = reinterpret_cast<ConcreteInstance*>(inst);
   ConcreteInstanceNetMap *nets = cinst->nets_;
@@ -1504,8 +1515,7 @@ ConcreteNetwork::deletePin(Pin *pin)
   ConcreteNet *cnet = cpin->net();
   if (cnet)
     disconnectNetPin(cnet, cpin);
-  ConcreteInstance *cinst =
+  ConcreteInstance *cinst = cpin->instance();
-    reinterpret_cast<ConcreteInstance*>(cpin->instance());
   if (cinst)
     cinst->deletePin(cpin);
   delete cpin;
@@ -1533,16 +1543,15 @@ ConcreteNetwork::deleteNet(Net *net)
     pin->net_ = nullptr;
   }
 
-  constant_nets_[int(LogicValue::zero)].erase(net);
+  constant_nets_[static_cast<int>(LogicValue::zero)].erase(net);
-  constant_nets_[int(LogicValue::one)].erase(net);
+  constant_nets_[static_cast<int>(LogicValue::one)].erase(net);
   PinSet *drvrs = findKey(net_drvr_pin_map_, net);
   if (drvrs) {
     delete drvrs;
     net_drvr_pin_map_.erase(net);
   }
 
-  ConcreteInstance *cinst =
+  ConcreteInstance *cinst = cnet->instance();
-    reinterpret_cast<ConcreteInstance*>(cnet->instance());
   cinst->deleteNet(cnet);
   delete cnet;
 }
@@ -1550,8 +1559,8 @@ ConcreteNetwork::deleteNet(Net *net)
 void
 ConcreteNetwork::clearConstantNets()
 {
-  constant_nets_[int(LogicValue::zero)].clear();
+  constant_nets_[static_cast<int>(LogicValue::zero)].clear();
-  constant_nets_[int(LogicValue::one)].clear();
+  constant_nets_[static_cast<int>(LogicValue::one)].clear();
 }
 
 void
@@ -1560,15 +1569,15 @@ ConcreteNetwork::addConstantNet(Net *net,
 {
   if (value == LogicValue::zero
       || value == LogicValue::one)
-    constant_nets_[int(value)].insert(net);
+    constant_nets_[static_cast<int>(value)].insert(net);
 }
 
 ConstantPinIterator *
 ConcreteNetwork::constantPinIterator()
 {
   return new NetworkConstantPinIterator(this,
-                                        constant_nets_[int(LogicValue::zero)],
+                                        constant_nets_[static_cast<int>(LogicValue::zero)],
-                                        constant_nets_[int(LogicValue::one)]);
+                                        constant_nets_[static_cast<int>(LogicValue::one)]);
 }
 
 ////////////////////////////////////////////////////////////////
@@ -1617,9 +1626,7 @@ ConcreteInstance::ConcreteInstance(std::string_view name,
   name_(name),
   id_(ConcreteNetwork::nextObjectId()),
   cell_(cell),
-  parent_(parent),
+  parent_(parent)
-  children_(nullptr),
-  nets_(nullptr)
 {
   initPins();
 }
@@ -1738,13 +1745,13 @@ ConcreteInstance::addChild(ConcreteInstance *child)
 {
   if (children_ == nullptr)
     children_ = new ConcreteInstanceChildMap;
-  (*children_)[child->name().data()] = child;
+  (*children_)[child->name()] = child;
 }
 
 void
 ConcreteInstance::deleteChild(ConcreteInstance *child)
 {
-  children_->erase(child->name().data());
+  children_->erase(child->name());
 }
 
 void
@@ -1769,7 +1776,7 @@ ConcreteInstance::addNet(ConcreteNet *net)
 {
   if (nets_ == nullptr)
     nets_ = new ConcreteInstanceNetMap;
-  (*nets_)[net->name().data()] = net;
+  (*nets_)[net->name()] = net;
 }
 
 void
@@ -1778,13 +1785,13 @@ ConcreteInstance::addNet(std::string_view,
 {
   if (nets_ == nullptr)
     nets_ = new ConcreteInstanceNetMap;
-  (*nets_)[net->name().data()] = net;
+  (*nets_)[net->name()] = net;
 }
 
 void
 ConcreteInstance::deleteNet(ConcreteNet *net)
 {
-  nets_->erase(net->name().data());
+  nets_->erase(net->name());
 }
 
 void
@@ -1801,15 +1808,11 @@ ConcretePin::ConcretePin(ConcreteInstance *instance,
   instance_(instance),
   port_(port),
   net_(net),
-  term_(nullptr),
+  id_(ConcreteNetwork::nextObjectId())
-  id_(ConcreteNetwork::nextObjectId()),
-  net_next_(nullptr),
-  net_prev_(nullptr),
-  vertex_id_(vertex_id_null)
 {
 }
 
-std::string_view
+const std::string&
 ConcretePin::name() const
 {
   return port_->name();
@@ -1823,12 +1826,11 @@ ConcretePin::setVertexId(VertexId id)
 
 ////////////////////////////////////////////////////////////////
 
-std::string_view
+const std::string &
 ConcreteTerm::name() const
 {
   ConcretePin *cpin = reinterpret_cast<ConcretePin*>(pin_);
-  const ConcretePort *cport =
+  const ConcretePort *cport = cpin->port();
-    reinterpret_cast<const ConcretePort*>(cpin->port());
   return cport->name();
 }
 
@@ -1836,8 +1838,7 @@ ConcreteTerm::ConcreteTerm(ConcretePin *pin,
                            ConcreteNet *net) :
   pin_(pin),
   net_(net),
-  id_(ConcreteNetwork::nextObjectId()),
+  id_(ConcreteNetwork::nextObjectId())
-  net_next_(nullptr)
 {
 }
 
@@ -1847,10 +1848,7 @@ ConcreteNet::ConcreteNet(std::string_view name,
                          ConcreteInstance *instance) :
   name_(name),
   id_(ConcreteNetwork::nextObjectId()),
-  instance_(instance),
+  instance_(instance)
-  pins_(nullptr),
-  terms_(nullptr),
-  merged_into_(nullptr)
 {
 }