From 21848bcdd2dd36515c0db7b3047661f78514a8b9 Mon Sep 17 00:00:00 2001 From: James Cherry Date: Wed, 15 Apr 2026 09:38:10 -0700 Subject: [PATCH] clang tidy Signed-off-by: James Cherry --- .clang-tidy | 7 +- dcalc/ArcDcalcWaveforms.cc | 12 +- dcalc/ArcDelayCalc.cc | 22 +-- dcalc/Arnoldi.hh | 12 +- dcalc/ArnoldiDelayCalc.cc | 177 ++++++++++++++---------- dcalc/ArnoldiReduce.cc | 34 +++-- dcalc/ArnoldiReduce.hh | 10 +- dcalc/CcsCeffDelayCalc.cc | 57 ++++---- dcalc/CcsCeffDelayCalc.hh | 26 ++-- dcalc/Delay.cc | 4 +- dcalc/DelayCalc.cc | 12 +- dcalc/DelayCalc.i | 4 +- dcalc/DelayCalcBase.cc | 12 +- dcalc/DelayCalcBase.hh | 2 +- dcalc/DelayNormal.cc | 4 +- dcalc/DelayScalar.cc | 2 +- dcalc/DelaySkewNormal.cc | 4 +- dcalc/DmpCeff.cc | 133 +++++++++--------- dcalc/DmpCeff.hh | 4 +- dcalc/DmpDelayCalc.cc | 37 +++-- dcalc/FindRoot.cc | 4 +- dcalc/FindRoot.hh | 4 +- dcalc/GraphDelayCalc.cc | 84 +++++------ dcalc/LumpedCapDelayCalc.cc | 14 +- dcalc/LumpedCapDelayCalc.hh | 2 +- dcalc/NetCaps.cc | 4 - dcalc/NetCaps.hh | 2 +- dcalc/ParallelDelayCalc.cc | 10 +- dcalc/ParallelDelayCalc.hh | 2 +- dcalc/PrimaDelayCalc.cc | 70 ++++------ dcalc/PrimaDelayCalc.hh | 33 ++--- graph/Graph.cc | 50 +++---- graph/Graph.i | 6 +- graph/GraphCmp.cc | 9 +- include/sta/ArcDelayCalc.hh | 16 +-- include/sta/Bdd.hh | 2 +- include/sta/Bfs.hh | 4 +- include/sta/BoundedHeap.hh | 2 +- include/sta/ClkNetwork.hh | 4 +- include/sta/Clock.hh | 41 +++--- include/sta/ClockGatingCheck.hh | 5 +- include/sta/ClockGroups.hh | 2 +- include/sta/ClockInsertion.hh | 2 +- include/sta/ClockLatency.hh | 4 +- include/sta/ConcreteLibrary.hh | 30 ++-- include/sta/ConcreteNetwork.hh | 43 +++--- include/sta/CycleAccting.hh | 6 +- include/sta/DataCheck.hh | 4 +- include/sta/Debug.hh | 4 +- include/sta/Delay.hh | 4 +- include/sta/DeratingFactors.hh | 10 +- include/sta/DisabledPorts.hh | 13 +- include/sta/DispatchQueue.hh | 14 +- include/sta/Error.hh | 1 - include/sta/ExceptionPath.hh | 15 +- include/sta/FilterObjects.hh | 20 +-- include/sta/FuncExpr.hh | 2 +- include/sta/Graph.hh | 24 ++-- include/sta/GraphClass.hh | 8 +- include/sta/GraphCmp.hh | 2 +- include/sta/GraphDelayCalc.hh | 33 +++-- include/sta/Hash.hh | 2 +- include/sta/InputDrive.hh | 15 +- include/sta/Liberty.hh | 18 +-- include/sta/LibertyClass.hh | 4 +- include/sta/MinMax.hh | 2 +- include/sta/MinMaxValues.hh | 2 +- include/sta/Network.hh | 20 +-- include/sta/NetworkClass.hh | 4 +- include/sta/Parasitics.hh | 20 +-- include/sta/Path.hh | 8 +- include/sta/PathEnd.hh | 4 +- include/sta/PathExpanded.hh | 4 +- include/sta/PathGroup.hh | 12 +- include/sta/PortDelay.hh | 6 +- include/sta/PortExtCap.hh | 7 +- include/sta/PowerClass.hh | 3 +- include/sta/Property.hh | 6 +- include/sta/Report.hh | 8 +- include/sta/RiseFallMinMaxDelay.hh | 2 +- include/sta/Scene.hh | 2 +- include/sta/Sdc.hh | 28 ++-- include/sta/SdcClass.hh | 11 +- include/sta/SdcNetwork.hh | 12 +- include/sta/Search.hh | 19 ++- include/sta/SearchClass.hh | 8 +- include/sta/SearchPred.hh | 2 +- include/sta/Sta.hh | 30 ++-- include/sta/StringUtil.hh | 2 +- include/sta/TableModel.hh | 4 +- include/sta/TclTypeHelpers.hh | 8 +- include/sta/TimingArc.hh | 4 +- include/sta/Variables.hh | 31 ++--- include/sta/VectorMap.hh | 4 +- include/sta/VerilogNamespace.hh | 8 +- include/sta/VerilogReader.hh | 34 ++--- include/sta/VertexVisitor.hh | 2 +- include/sta/VisitPathEnds.hh | 2 +- network/ConcreteLibrary.cc | 25 +--- network/ConcreteNetwork.cc | 136 +++++++++--------- network/HpinDrvrLoad.cc | 10 +- network/Network.cc | 46 ++---- network/Network.i | 4 +- network/NetworkCmp.cc | 2 +- network/ParseBus.cc | 4 +- network/SdcNetwork.cc | 12 +- network/VerilogNamespace.cc | 4 +- parasitics/ConcreteParasitics.cc | 73 +++++----- parasitics/ConcreteParasitics.hh | 15 +- parasitics/ConcreteParasiticsPvt.hh | 77 +++++------ parasitics/EstimateParasitics.cc | 35 +---- parasitics/EstimateParasitics.hh | 6 +- parasitics/Parasitics.cc | 15 +- parasitics/ReduceParasitics.cc | 46 +++--- parasitics/ReportParasiticAnnotation.cc | 18 +-- parasitics/SpefParse.yy | 8 ++ parasitics/SpefReader.cc | 40 ++---- parasitics/SpefReader.hh | 4 +- parasitics/SpefReaderPvt.hh | 34 ++--- parasitics/SpefScanner.hh | 2 +- power/Power.cc | 4 +- power/Power.hh | 12 +- power/Power.i | 9 +- power/ReportPower.cc | 6 +- power/ReportPower.hh | 2 +- power/SaifParse.yy | 4 + power/SaifReader.cc | 17 +-- power/SaifReaderPvt.hh | 20 +-- power/SaifScanner.hh | 3 +- power/VcdParse.cc | 13 +- power/VcdParse.hh | 12 +- power/VcdReader.cc | 43 +++--- sdc/Clock.cc | 62 +++------ sdc/ClockGatingCheck.cc | 5 - sdc/CycleAccting.cc | 11 +- sdc/DataCheck.cc | 4 +- sdc/DeratingFactors.cc | 34 ++--- sdc/DisabledPorts.cc | 24 +--- sdc/ExceptionPath.cc | 42 ++---- sdc/FilterObjects.cc | 16 +-- sdc/InputDrive.cc | 20 +-- sdc/PortDelay.cc | 6 +- sdc/PortExtCap.cc | 5 - sdc/Sdc.cc | 10 +- sdc/Sdc.i | 10 +- sdc/SdcCmdComment.cc | 3 +- sdc/Variables.cc | 18 --- sdc/WriteSdc.cc | 78 +++++------ sdc/WriteSdcPvt.hh | 6 +- sdf/ReportAnnotation.cc | 20 +-- sdf/Sdf.i | 5 +- sdf/SdfParse.yy | 16 +++ sdf/SdfReader.cc | 40 +++--- sdf/SdfReaderPvt.hh | 30 ++-- sdf/SdfScanner.hh | 2 +- sdf/SdfWriter.cc | 25 ++-- search/CheckCapacitances.cc | 2 +- search/CheckFanouts.cc | 4 +- search/CheckSlews.cc | 2 +- search/Sta.cc | 2 +- spice/WritePathSpice.cc | 34 +++-- spice/WriteSpice.cc | 33 ++--- spice/WriteSpice.hh | 24 ++-- util/Error.cc | 4 - util/FlexDisableRegister.hh | 1 - util/gzstream.hh | 2 +- verilog/Verilog.i | 2 +- verilog/VerilogParse.yy | 25 ++++ verilog/VerilogReader.cc | 35 +++-- verilog/VerilogReaderPvt.hh | 14 +- verilog/VerilogScanner.hh | 3 +- verilog/VerilogWriter.cc | 9 +- 172 files changed, 1402 insertions(+), 1589 deletions(-) diff --git a/.clang-tidy b/.clang-tidy index 19aed656..c095fa1b 100644 --- a/.clang-tidy +++ b/.clang-tidy @@ -59,6 +59,7 @@ Checks: > -modernize-use-transparent-functors, misc-*, -misc-const-correctness, + -misc-multiple-inheritance, -misc-no-recursion, -misc-non-private-member-variables-in-classes, -misc-redundant-expression, @@ -72,6 +73,8 @@ Checks: > # Excludes system and third-party paths such as /opt/local/include. HeaderFilterRegex: '.*/(app|cmake|dcalc|graph|liberty|network|parasitics|power|sdc|sdf|search|spice|tcl|util|verilog|include/sta|build/include/sta)/.*' -# Bison-generated parser headers (build/{Liberty,Verilog,...}Parse.hh); gzstream (e.g. util/gzstream.hh). -ExcludeHeaderFilterRegex: '.*/(gzstream\.h(?:h)?|(?:Liberty|Verilog|Sdf|Spef|Saif|LibExpr)Parse\.hh)$' +# util/gzstream.hh +# util/FlexDisableRegister.hh +# Bison-generated parser headers (build/{Liberty,Verilog,...}Parse.hh) +ExcludeHeaderFilterRegex: '(.*/)?(gzstream\.hh|FlexDisableRegister\.hh|(Liberty|Verilog|Sdf|Spef|Saif|LibExpr)Parse\.hh)$' FormatStyle: none diff --git a/dcalc/ArcDcalcWaveforms.cc b/dcalc/ArcDcalcWaveforms.cc index 6de6bdb6..184607e6 100644 --- a/dcalc/ArcDcalcWaveforms.cc +++ b/dcalc/ArcDcalcWaveforms.cc @@ -22,16 +22,16 @@ // // This notice may not be removed or altered from any source distribution. -#include - #include "ArcDcalcWaveforms.hh" -#include "Report.hh" +#include + +#include "ArcDelayCalc.hh" +#include "Graph.hh" +#include "GraphDelayCalc.hh" #include "Liberty.hh" #include "Network.hh" -#include "Graph.hh" -#include "ArcDelayCalc.hh" -#include "GraphDelayCalc.hh" +#include "Report.hh" namespace sta { diff --git a/dcalc/ArcDelayCalc.cc b/dcalc/ArcDelayCalc.cc index 38000cd0..b615ca47 100644 --- a/dcalc/ArcDelayCalc.cc +++ b/dcalc/ArcDelayCalc.cc @@ -27,12 +27,12 @@ #include #include -#include "StringUtil.hh" -#include "Units.hh" -#include "Liberty.hh" -#include "TimingArc.hh" -#include "Network.hh" #include "Graph.hh" +#include "Liberty.hh" +#include "Network.hh" +#include "StringUtil.hh" +#include "TimingArc.hh" +#include "Units.hh" namespace sta { @@ -165,17 +165,7 @@ ArcDcalcArg::ArcDcalcArg(const Pin *in_pin, { } -ArcDcalcArg::ArcDcalcArg(const ArcDcalcArg &arg) : - in_pin_(arg.in_pin_), - drvr_pin_(arg.drvr_pin_), - edge_(arg.edge_), - arc_(arg.arc_), - in_slew_(arg.in_slew_), - load_cap_(arg.load_cap_), - parasitic_(arg.parasitic_), - input_delay_(arg.input_delay_) -{ -} +ArcDcalcArg::ArcDcalcArg(const ArcDcalcArg &arg) = default; const RiseFall * ArcDcalcArg::inEdge() const diff --git a/dcalc/Arnoldi.hh b/dcalc/Arnoldi.hh index 73fc26b2..ccfbb002 100644 --- a/dcalc/Arnoldi.hh +++ b/dcalc/Arnoldi.hh @@ -45,7 +45,7 @@ class arnoldi1 public: arnoldi1() { order=0; n=0; d=nullptr; e=nullptr; U=nullptr; ctot=0.0; sqc=0.0; } ~arnoldi1(); - double elmore(int term_index); + double elmore(int k); // // calculate poles/residues for given rdrive @@ -70,12 +70,12 @@ class rcmodel : public ConcreteParasitic, { public: rcmodel(); - virtual ~rcmodel(); - virtual float capacitance() const; - virtual PinSet unannotatedLoads(const Pin *drvr_pin, - const Parasitics *parasitics) const; + ~rcmodel() override; + float capacitance() const override; + PinSet unannotatedLoads(const Pin *drvr_pin, + const Parasitics *parasitics) const override; - const Pin **pinV; // [n] + const Pin **pinV{nullptr}; // [n] }; struct timing_table diff --git a/dcalc/ArnoldiDelayCalc.cc b/dcalc/ArnoldiDelayCalc.cc index efacb54a..502a73eb 100644 --- a/dcalc/ArnoldiDelayCalc.cc +++ b/dcalc/ArnoldiDelayCalc.cc @@ -28,30 +28,34 @@ #include "ArnoldiDelayCalc.hh" -#include +#include #include // abs +#include +#include +#include -#include "Report.hh" -#include "Debug.hh" -#include "Units.hh" -#include "Liberty.hh" -#include "TimingModel.hh" -#include "TimingArc.hh" -#include "TableModel.hh" -#include "PortDirection.hh" -#include "Network.hh" -#include "Graph.hh" -#include "Parasitics.hh" -#include "Sdc.hh" -#include "DelayCalc.hh" #include "ArcDelayCalc.hh" -#include "LumpedCapDelayCalc.hh" -#include "GraphDelayCalc.hh" -#include "Variables.hh" #include "Arnoldi.hh" #include "ArnoldiReduce.hh" +#include "Debug.hh" +#include "DelayCalc.hh" +#include "Graph.hh" +#include "GraphDelayCalc.hh" +#include "Liberty.hh" +#include "LumpedCapDelayCalc.hh" +#include "Network.hh" +#include "Parasitics.hh" +#include "PortDirection.hh" +#include "Report.hh" +#include "Sdc.hh" +#include "TableModel.hh" +#include "TimingArc.hh" +#include "TimingModel.hh" +#include "Units.hh" +#include "Variables.hh" namespace sta { +// NOLINTBEGIN(modernize-avoid-c-style-cast) // wireload8 is n^2 // do not delete arnoldi parasitics @@ -76,7 +80,11 @@ delay_work_get_residues(delay_work *D, int term_index); static bool -tridiagEV(int n,double *d,double *e,double *p,double **v); +tridiagEV(int n, + const double *din, + const double *ein, + double *d, + double **v); ////////////////////////////////////////////////////////////// @@ -229,7 +237,7 @@ private: double *c_x1, double *c_y1); - rcmodel *rcmodel_; + rcmodel *rcmodel_{nullptr}; int _pinNmax; double *_delayV; double *_slewV; @@ -246,7 +254,6 @@ makeArnoldiDelayCalc(StaState *sta) ArnoldiDelayCalc::ArnoldiDelayCalc(StaState *sta) : LumpedCapDelayCalc(sta), - rcmodel_(nullptr), reduce_(new ArnoldiReduce(sta)), delay_work_(delay_work_create()) { @@ -362,7 +369,7 @@ ArnoldiDelayCalc::inputPortDelay(const Pin *, for (int j=1;jelmore(j); - double wire_delay = 0.6931472*elmore; + double wire_delay = std::numbers::ln2 * elmore; double load_slew = in_slew + c_log*elmore/slew_derate; _delayV[j] = wire_delay; _slewV[j] = load_slew; @@ -487,7 +494,7 @@ ArnoldiDelayCalc::reportGateDelay(const Pin *drvr_pin, arnoldi1::~arnoldi1() { free(d); - free(U); + free(reinterpret_cast(U)); } double @@ -506,13 +513,16 @@ delay_work_create() int j; delay_work *D = (delay_work*)malloc(sizeof(delay_work)); D->nmax = 256; - D->resi = (double**)malloc(D->nmax*sizeof(double*)); - D->resi[0] = (double*)malloc(D->nmax*32*sizeof(double)); - for (j=1;jnmax;j++) D->resi[j] = D->resi[0] + j*32; - D->v[0] = (double*)malloc(32*32*sizeof(double)); - for (j=1;j<32;j++) D->v[j] = D->v[0] + j*32; - D->w[0] = (double*)malloc(32*D->nmax*sizeof(double)); - for (j=1;j<32;j++) D->w[j] = D->w[0] + j*D->nmax; + D->resi = (double**)malloc(static_cast(D->nmax) * sizeof(double *)); + D->resi[0] = (double*)malloc(static_cast(D->nmax) * 32u * sizeof(double)); + for (j=1;jnmax;j++) + D->resi[j] = D->resi[0] + static_cast(j) * 32; + D->v[0] = (double*)malloc(static_cast(32) * 32u * sizeof(double)); + for (j=1;j<32;j++) + D->v[j] = D->v[0] + static_cast(j) * 32; + D->w[0] = (double*)malloc(32u * static_cast(D->nmax) * sizeof(double)); + for (j=1;j<32;j++) + D->w[j] = D->w[0] + static_cast(j) * D->nmax; D->lo_thresh = 0.0; D->hi_thresh = 0.0; D->slew_derate = 0.0; @@ -535,7 +545,7 @@ static void delay_work_destroy(delay_work *D) { free(D->resi[0]); - free(D->resi); + free(reinterpret_cast(D->resi)); free(D->v[0]); free(D->w[0]); free(D); @@ -547,15 +557,17 @@ delay_work_alloc(delay_work *D,int n) if (n<=D->nmax) return; free(D->w[0]); free(D->resi[0]); - free(D->resi); + free(reinterpret_cast(D->resi)); D->nmax *= 2; - if (n > D->nmax) D->nmax = n; + D->nmax = std::max(n, D->nmax); int j; - D->resi = (double**)malloc(D->nmax*sizeof(double*)); - D->resi[0] = (double*)malloc(D->nmax*32*sizeof(double)); - for (j=1;jnmax;j++) D->resi[j] = D->resi[0] + j*32; - D->w[0] = (double*)malloc(32*D->nmax*sizeof(double)); - for (j=1;j<32;j++) D->w[j] = D->w[0] + j*D->nmax; + D->resi = (double**)malloc(static_cast(D->nmax) * sizeof(double *)); + D->resi[0] = (double*)malloc(static_cast(D->nmax) * 32u * sizeof(double)); + for (j=1;jnmax;j++) + D->resi[j] = D->resi[0] + static_cast(j) * 32; + D->w[0] = (double*)malloc(32u * static_cast(D->nmax) * sizeof(double)); + for (j=1;j<32;j++) + D->w[j] = D->w[0] + static_cast(j) * D->nmax; } void @@ -622,8 +634,7 @@ void arnoldi1::calculate_poles_res(delay_work *D, d[0] = dsave; for (h=0;h= 0.0) + if ((((rts-xh)*df-f)*((rts-x_lo)*df-f) >= 0.0) || (std::abs(2.0*f) > std::abs(dxold*df))) { dxold = dx; - dx = 0.5*(xh-xl); + dx = 0.5*(xh-x_lo); if (flast*f >0.0) { // 2 successive bisections in same direction, // accelerate - if (f<0.0) dx = 0.9348*(xh-xl); - else dx = 0.0625*(xh-xl); + if (f<0.0) dx = 0.9348*(xh-x_lo); + else dx = 0.0625*(xh-x_lo); } flast = f; - rts = xl+dx; - if (xl == rts) { + rts = x_lo+dx; + if (x_lo == rts) { return rts; } } else { @@ -849,13 +881,13 @@ solve_t_bracketed(double s,int order,double *p,double *rr, } get_dv(rts,s,order,p,rr,&f,&df); f -= val; if (f<0.0) - xl = rts; + x_lo = rts; else xh = rts; } if (std::abs(f)<1e-6) // 1uV return rts; - return 0.5*(xl+xh); + return 0.5*(x_lo+xh); } void @@ -949,8 +981,7 @@ ArnoldiDelayCalc::pr_solve3(double s, for (h=1;h0.3 && rr[h]>rr[0]) { h0 = h; break; } } double p0 = p[h0]; - if (p0>10e+9) // 1/10ns - p0=10e+9; + p0 = std::min(p0, 10e+9); // 1/10ns cap double ps,vs,ta,va; vs = 0.0; for (h=0;hvmid) { - tmin5 = tmin8 = ta; vmin5 = tmin8 = va; + tmin5 = ta; + tmin8 = ta; + vmin5 = va; ta += 0.7/p0; pr_get_v(ta,s,order,p,rr,&va); } @@ -1064,18 +1097,14 @@ ArnoldiDelayCalc::pr_solve3(double s, pr_get_v(ta,s,order,p,rr,&va); } tmax2 = ta; vmax2 = va; - if (va < vmid) { - tmax5 = ta; vmax5 = va; - } else while (va > vmid) { + while (va > vmid) { tmin5 = tmin8 = ta; vmin5 = vmin8 = va; ta += 1.0/p0; pr_get_v(ta,s,order,p,rr,&va); } tmax5 = ta; vmax5 = va; - if (va < vlo) { - tmax8 = ta; vmax8 = va; - } else while (va > vlo) { + while (va > vlo) { tmin8 = ta; vmin8 = va; ta += 1.0/p0; @@ -1248,11 +1277,12 @@ ArnoldiDelayCalc::ra_solve_for_s(delay_work *D, if (x <= x1) { y = y1 - 0.5*(x-x1); - if (y>1.0) y=1.0; + y = std::min(y, 1.0); } else { y = y1 - (x-x1)*(0.5 + 8*(x-x1)); - if (y0.0 && r<100e+3)) // 100khom @@ -1436,9 +1465,6 @@ ArnoldiDelayCalc::ar1_ceff_delay(delay_work *D, units_->timeUnit()->asString(tlox-thix)); } ceff = ctot; - tab->table->gateDelay(tab->pvt, tab->in_slew, ceff, df, sf); - t50_sy = delayAsFloat(df); - t50_sr = ra_solve_for_t(1.0/(r*ceff),s,0.5); // calculate s,r,mod -> t50_srmod, // then t50_srmod+t50_sy-t50_sr @@ -1488,4 +1514,5 @@ ArnoldiDelayCalc::ar1_ceff_delay(delay_work *D, } } +// NOLINTEND(modernize-avoid-c-style-cast) } // namespace sta diff --git a/dcalc/ArnoldiReduce.cc b/dcalc/ArnoldiReduce.cc index 046e8e8d..236c01a6 100644 --- a/dcalc/ArnoldiReduce.cc +++ b/dcalc/ArnoldiReduce.cc @@ -28,19 +28,22 @@ #include "ArnoldiReduce.hh" -#include "Debug.hh" -#include "MinMax.hh" -#include "Sdc.hh" -#include "Network.hh" -#include "Units.hh" +#include + #include "Arnoldi.hh" +#include "Debug.hh" #include "Format.hh" +#include "MinMax.hh" +#include "Network.hh" +#include "Sdc.hh" +#include "Units.hh" #include "parasitics/ConcreteParasiticsPvt.hh" namespace sta { +// This is legacy C-style code. +// NOLINTBEGIN(modernize-avoid-c-style-cast, bugprone-multi-level-implicit-pointer-conversion, bugprone-implicit-widening-of-multiplication-result) -rcmodel::rcmodel() : - pinV(nullptr) +rcmodel::rcmodel() { } @@ -87,11 +90,7 @@ const int ArnoldiReduce::ts_point_count_incr_ = 1024; const int ArnoldiReduce::ts_edge_count_incr_ = 1024; ArnoldiReduce::ArnoldiReduce(StaState *sta) : - StaState(sta), - ts_pointNmax(1024), - ts_edgeNmax(1024), - termNmax(256), - dNmax(8) + StaState(sta) { ts_pointV = (ts_point *)malloc(ts_pointNmax * sizeof(ts_point)); ts_ordV = (int *)malloc(ts_pointNmax * sizeof(int)); @@ -351,14 +350,14 @@ ArnoldiReduce::makeRcmodelDfs(ts_point *pdrv) ts_point *p0 = ts_pointV; ts_point *pend = p0 + ts_pointN; for (p = p0; p != pend; p++) - p->visited = 0; + p->visited = false; ts_edge *e; ts_edge **stackV = ts_stackV; int stackN = 1; stackV[0] = e = pdrv->eV[0]; ts_orient(pdrv, e); - pdrv->visited = 1; + pdrv->visited = true; pdrv->in_edge = nullptr; pdrv->ts = 0; ts_ordV[0] = pdrv - p0; @@ -376,7 +375,7 @@ ArnoldiReduce::makeRcmodelDfs(ts_point *pdrv) } else { // try to descend - q->visited = 1; + q->visited = true; q->ts = ts_ordN++; ts_pordV[q->ts] = q; ts_ordV[q->ts] = q - p0; @@ -531,9 +530,7 @@ ArnoldiReduce::makeRcmodelFromTs() u0 = _u0; u1 = _u1; double sum, e1; - order = max_order; - if (n < order) - order = n; + order = std::min(n, max_order); par[0] = -1; r[0] = 0.0; @@ -682,4 +679,5 @@ ArnoldiReduce::makeRcmodelFromW() return mod; } +// NOLINTEND(modernize-avoid-c-style-cast, bugprone-multi-level-implicit-pointer-conversion, bugprone-implicit-widening-of-multiplication-result) } // namespace sta diff --git a/dcalc/ArnoldiReduce.hh b/dcalc/ArnoldiReduce.hh index 0ee70c84..16232d5c 100644 --- a/dcalc/ArnoldiReduce.hh +++ b/dcalc/ArnoldiReduce.hh @@ -52,7 +52,7 @@ class ArnoldiReduce : public StaState { public: ArnoldiReduce(StaState *sta); - ~ArnoldiReduce(); + ~ArnoldiReduce() override; rcmodel *reduceToArnoldi(Parasitic *parasitic, const Pin *drvr_pin, float coupling_cap_factor, @@ -86,11 +86,11 @@ protected: // rcWork ts_point *ts_pointV; int ts_pointN; - int ts_pointNmax; + int ts_pointNmax{1024}; static const int ts_point_count_incr_; ts_edge *ts_edgeV; int ts_edgeN; - int ts_edgeNmax; + int ts_edgeNmax{1024}; static const int ts_edge_count_incr_; ts_edge **ts_eV; ts_edge **ts_stackV; @@ -98,14 +98,14 @@ protected: ts_point **ts_pordV; int ts_ordN; - int termNmax; + int termNmax{256}; int termN; ts_point *pterm0; const Pin **pinV; // fixed order, offset from pterm0 int *termV; // from drv-ordered to fixed order int *outV; // from drv-ordered to ts_pordV - int dNmax; + int dNmax{8}; double *d; double *e; double *U0; diff --git a/dcalc/CcsCeffDelayCalc.cc b/dcalc/CcsCeffDelayCalc.cc index fec6f032..848ac227 100644 --- a/dcalc/CcsCeffDelayCalc.cc +++ b/dcalc/CcsCeffDelayCalc.cc @@ -24,19 +24,20 @@ #include "CcsCeffDelayCalc.hh" +#include #include #include "Debug.hh" -#include "Units.hh" -#include "Liberty.hh" -#include "TimingArc.hh" -#include "Network.hh" -#include "Graph.hh" -#include "Scene.hh" -#include "Parasitics.hh" -#include "GraphDelayCalc.hh" #include "DmpDelayCalc.hh" #include "FindRoot.hh" +#include "Graph.hh" +#include "GraphDelayCalc.hh" +#include "Liberty.hh" +#include "Network.hh" +#include "Parasitics.hh" +#include "Scene.hh" +#include "TimingArc.hh" +#include "Units.hh" namespace sta { @@ -53,10 +54,6 @@ makeCcsCeffDelayCalc(StaState *sta) CcsCeffDelayCalc::CcsCeffDelayCalc(StaState *sta) : LumpedCapDelayCalc(sta), - output_waveforms_(nullptr), - // Includes the Vh:Vdd region. - region_count_(0), - vl_fail_(false), watch_pin_values_(network_), capacitance_unit_(units_->capacitanceUnit()), table_dcalc_(makeDmpCeffElmoreDelayCalc(sta)) @@ -176,8 +173,8 @@ CcsCeffDelayCalc::gateDelaySlew(const LibertyLibrary *drvr_library, } for (size_t i = 0; i < region_count_; i++) { - double v1 = region_volts_[i]; - double v2 = region_volts_[i + 1]; + double seg_v1 = region_volts_[i]; + double seg_v2 = region_volts_[i + 1]; double t1 = region_times_[i]; double t2 = region_times_[i + 1]; @@ -186,11 +183,11 @@ CcsCeffDelayCalc::gateDelaySlew(const LibertyLibrary *drvr_library, // for the charge on c1 from previous segments so it does not // work well. double c1_v1, c1_v2, ignore; - vl(t1, rpi_ * c1_, c1_v1, ignore); - vl(t2, rpi_ * c1_, c1_v2, ignore); - double q1 = v1 * c2_ + c1_v1 * c1_; - double q2 = v2 * c2_ + c1_v2 * c1_; - double ceff = (q2 - q1) / (v2 - v1); + vLoad(t1, rpi_ * c1_, c1_v1, ignore); + vLoad(t2, rpi_ * c1_, c1_v2, ignore); + double q1 = seg_v1 * c2_ + c1_v1 * c1_; + double q2 = seg_v2 * c2_ + c1_v2 * c1_; + double ceff = (q2 - q1) / (seg_v2 - seg_v1); debugPrint(debug_, "ccs_dcalc", 2, "ceff {}", capacitance_unit_->asString(ceff)); @@ -297,7 +294,7 @@ CcsCeffDelayCalc::initRegions(const LibertyLibrary *drvr_library, report_->error(1701, "unsupported ccs region count."); break; } - fill(region_ceff_.begin(), region_ceff_.end(), c2_ + c1_); + std::ranges::fill(region_ceff_, c2_ + c1_); } void @@ -402,11 +399,11 @@ rampElmoreV(double t, // Elmore (one pole) response to 2 segment ramps [0, vth] slew1, [vth, vdd] slew2. void -CcsCeffDelayCalc::vl(double t, - double elmore, - // Return values. - double &vl, - double &dvl_dt) +CcsCeffDelayCalc::vLoad(double t, + double elmore, + // Return values. + double &vl, + double &dvl_dt) { vl = 0.0; dvl_dt = 0.0; @@ -431,11 +428,11 @@ CcsCeffDelayCalc::vl(double t, // for debugging double -CcsCeffDelayCalc::vl(double t, - double elmore) +CcsCeffDelayCalc::vLoad(double t, + double elmore) { double vl1, dvl_dt; - vl(t, elmore, vl1, dvl_dt); + vLoad(t, elmore, vl1, dvl_dt); return vl1; } @@ -447,7 +444,7 @@ CcsCeffDelayCalc::findVlTime(double v, double t_final = region_ramp_times_[region_count_]; auto [time, failed] = findRoot([&](double t, double &y, double &dy) { - vl(t, elmore, y, dy); + vLoad(t, elmore, y, dy); y -= v; }, t_init, t_final + elmore * 3.0, .001, 20); @@ -539,7 +536,7 @@ CcsCeffDelayCalc::loadWaveform(const Pin *load_pin) load_times->push_back(t); double ignore; - vl(t, elmore, v, ignore); + vLoad(t, elmore, v, ignore); double v1 = (drvr_rf_ == RiseFall::rise()) ? v : vdd_ - v; load_volts->push_back(v1); } diff --git a/dcalc/CcsCeffDelayCalc.hh b/dcalc/CcsCeffDelayCalc.hh index 81fb2450..07a659b9 100644 --- a/dcalc/CcsCeffDelayCalc.hh +++ b/dcalc/CcsCeffDelayCalc.hh @@ -24,8 +24,8 @@ #pragma once -#include "LumpedCapDelayCalc.hh" #include "ArcDcalcWaveforms.hh" +#include "LumpedCapDelayCalc.hh" namespace sta { @@ -39,7 +39,7 @@ class CcsCeffDelayCalc : public LumpedCapDelayCalc, { public: CcsCeffDelayCalc(StaState *sta); - virtual ~CcsCeffDelayCalc(); + ~CcsCeffDelayCalc() override; ArcDelayCalc *copy() override; std::string_view name() const override { return "ccs_ceff"; } bool reduceSupported() const override { return true; } @@ -68,7 +68,7 @@ public: Waveform watchWaveform(const Pin *pin) override; protected: - typedef std::vector Region; + using Region = std::vector; void gateDelaySlew(const LibertyLibrary *drvr_library, // Return values. @@ -106,13 +106,13 @@ protected: const Pin *load_pin, const Scene *scene, const MinMax *min_max); - void vl(double t, - double elmore, - // Return values. - double &vl, - double &dvl_dt); - double vl(double t, - double elmore); + void vLoad(double t, + double elmore, + // Return values. + double &vl, + double &dvl_dt); + double vLoad(double t, + double elmore); void fail(std::string_view reason); const Pin *drvr_pin_; @@ -122,7 +122,7 @@ protected: Parasitics *parasitics_; const Parasitic *parasitic_; - OutputWaveforms *output_waveforms_; + OutputWaveforms *output_waveforms_{nullptr}; double ref_time_; float vdd_; float vth_; @@ -133,7 +133,7 @@ protected: float rpi_; float c1_; - size_t region_count_; + size_t region_count_{0}; size_t region_vl_idx_; size_t region_vth_idx_; size_t region_vh_idx_; @@ -146,7 +146,7 @@ protected: Region region_time_offsets_; Region region_ramp_times_; Region region_ramp_slopes_; - bool vl_fail_; + bool vl_fail_{false}; // Waveform recording. WatchPinValuesMap watch_pin_values_; diff --git a/dcalc/Delay.cc b/dcalc/Delay.cc index bdec1906..295cd453 100644 --- a/dcalc/Delay.cc +++ b/dcalc/Delay.cc @@ -26,10 +26,10 @@ #include -#include "StaConfig.hh" #include "Fuzzy.hh" -#include "Units.hh" +#include "StaConfig.hh" #include "StaState.hh" +#include "Units.hh" #include "Variables.hh" namespace sta { diff --git a/dcalc/DelayCalc.cc b/dcalc/DelayCalc.cc index 3ce3cbc9..2b8fc826 100644 --- a/dcalc/DelayCalc.cc +++ b/dcalc/DelayCalc.cc @@ -27,18 +27,18 @@ #include #include -#include "ContainerHelpers.hh" -#include "StringUtil.hh" -#include "UnitDelayCalc.hh" -#include "LumpedCapDelayCalc.hh" -#include "DmpDelayCalc.hh" #include "ArnoldiDelayCalc.hh" #include "CcsCeffDelayCalc.hh" +#include "ContainerHelpers.hh" +#include "DmpDelayCalc.hh" +#include "LumpedCapDelayCalc.hh" #include "PrimaDelayCalc.hh" +#include "StringUtil.hh" +#include "UnitDelayCalc.hh" namespace sta { -typedef std::map> DelayCalcMap; +using DelayCalcMap = std::map>; static DelayCalcMap delay_calcs; diff --git a/dcalc/DelayCalc.i b/dcalc/DelayCalc.i index 992ecade..9aaa3f3f 100644 --- a/dcalc/DelayCalc.i +++ b/dcalc/DelayCalc.i @@ -28,11 +28,11 @@ %{ -#include "DelayCalc.hh" #include "ArcDelayCalc.hh" +#include "DelayCalc.hh" +#include "Sta.hh" #include "dcalc/ArcDcalcWaveforms.hh" #include "dcalc/PrimaDelayCalc.hh" -#include "Sta.hh" %} diff --git a/dcalc/DelayCalcBase.cc b/dcalc/DelayCalcBase.cc index c41eb94f..214aec7d 100644 --- a/dcalc/DelayCalcBase.cc +++ b/dcalc/DelayCalcBase.cc @@ -24,16 +24,16 @@ #include "DelayCalcBase.hh" +#include "Graph.hh" +#include "GraphDelayCalc.hh" #include "Liberty.hh" -#include "TimingArc.hh" -#include "TimingModel.hh" -#include "TableModel.hh" #include "Network.hh" #include "Parasitics.hh" -#include "Graph.hh" -#include "Sdc.hh" #include "Scene.hh" -#include "GraphDelayCalc.hh" +#include "Sdc.hh" +#include "TableModel.hh" +#include "TimingArc.hh" +#include "TimingModel.hh" #include "Variables.hh" namespace sta { diff --git a/dcalc/DelayCalcBase.hh b/dcalc/DelayCalcBase.hh index 2cfdc650..a2d4666b 100644 --- a/dcalc/DelayCalcBase.hh +++ b/dcalc/DelayCalcBase.hh @@ -72,7 +72,7 @@ protected: void thresholdAdjust(const Pin *load_pin, const LibertyLibrary *drvr_library, const RiseFall *rf, - double &load_delay, + double &wire_delay, double &load_slew); // Helper function for input ports driving dspf parasitic. void dspfWireDelaySlew(const Pin *load_pin, diff --git a/dcalc/DelayNormal.cc b/dcalc/DelayNormal.cc index 2120bded..c73de069 100644 --- a/dcalc/DelayNormal.cc +++ b/dcalc/DelayNormal.cc @@ -27,10 +27,10 @@ #include // sqrt #include "Error.hh" -#include "Fuzzy.hh" -#include "Units.hh" #include "Format.hh" +#include "Fuzzy.hh" #include "StaState.hh" +#include "Units.hh" #include "Variables.hh" namespace sta { diff --git a/dcalc/DelayScalar.cc b/dcalc/DelayScalar.cc index 73f217b4..0ec8543e 100644 --- a/dcalc/DelayScalar.cc +++ b/dcalc/DelayScalar.cc @@ -27,8 +27,8 @@ #include "DelayScalar.hh" #include "Fuzzy.hh" -#include "Units.hh" #include "StaState.hh" +#include "Units.hh" namespace sta { diff --git a/dcalc/DelaySkewNormal.cc b/dcalc/DelaySkewNormal.cc index b8c9c8e5..7e492a03 100644 --- a/dcalc/DelaySkewNormal.cc +++ b/dcalc/DelaySkewNormal.cc @@ -27,10 +27,10 @@ #include // sqrt #include "Error.hh" -#include "Fuzzy.hh" -#include "Units.hh" #include "Format.hh" +#include "Fuzzy.hh" #include "StaState.hh" +#include "Units.hh" #include "Variables.hh" namespace sta { diff --git a/dcalc/DmpCeff.cc b/dcalc/DmpCeff.cc index 108bf798..7ce3e903 100644 --- a/dcalc/DmpCeff.cc +++ b/dcalc/DmpCeff.cc @@ -40,17 +40,17 @@ #include #include -#include "Format.hh" -#include "Report.hh" -#include "Debug.hh" -#include "Units.hh" -#include "TimingArc.hh" -#include "TableModel.hh" -#include "Liberty.hh" -#include "Sdc.hh" -#include "Parasitics.hh" #include "ArcDelayCalc.hh" +#include "Debug.hh" #include "FindRoot.hh" +#include "Format.hh" +#include "Liberty.hh" +#include "Parasitics.hh" +#include "Report.hh" +#include "Sdc.hh" +#include "TableModel.hh" +#include "TimingArc.hh" +#include "Units.hh" #include "Variables.hh" namespace sta { @@ -72,7 +72,7 @@ class DmpError : public Exception { public: DmpError(std::string_view what); - virtual const char *what() const noexcept { return what_.c_str(); } + const char *what() const noexcept override { return what_.c_str(); } private: std::string what_; @@ -127,7 +127,7 @@ protected: void newtonRaphson(); // Find driver parameters t0, delta_t, Ceff. void findDriverParams(double ceff); - std::pair gateCapDelaySlew(double cl); + std::pair gateCapDelaySlew(double ceff); std::tuple gateDelays(double ceff); // Partial derivatives of y(t) jacobian (dydt0, dyddt, dydcl). std::tuple dy(double t, @@ -143,12 +143,12 @@ protected: void showJacobian(); std::pair findDriverDelaySlew(); double findVoCrossing(double vth, - double lower_bound, - double upper_bound); + double t_lower, + double t_upper); void showVo(); double findVlCrossing(double vth, - double lower_bound, - double upper_bound); + double t_lower, + double t_upper); void showVl(); void fail(std::string_view reason); @@ -177,9 +177,9 @@ protected: const Pvt *pvt_; const GateTableModel *gate_model_; double in_slew_; - double c2_; - double rpi_; - double c1_; + double c2_{0.0}; + double rpi_{0.0}; + double c1_{0.0}; double rd_; // Logic threshold (percentage of supply voltage). @@ -232,9 +232,6 @@ protected: DmpAlg::DmpAlg(int nr_order, StaState *sta) : StaState(sta), - c2_(0.0), - rpi_(0.0), - c1_(0.0), nr_order_(nr_order) { } @@ -465,8 +462,13 @@ DmpAlg::showVo() { report_->report(" t vo(t)"); double ub = voCrossingUpperBound(); - for (double t = t0_; t < t0_ + ub; t += dt_ / 10.0) + const double step = dt_ / 10.0; + for (int i = 0;; ++i) { + double t = t0_ + step * i; + if (!(t < t0_ + ub)) + break; report_->report(" {:g} {:g}", t, Vo(t).first); + } } std::pair @@ -567,8 +569,14 @@ DmpAlg::showVl() { report_->report(" t vl(t)"); double ub = vlCrossingUpperBound(); - for (double t = t0_; t < t0_ + ub * 2.0; t += ub / 10.0) + const double step = ub / 10.0; + const double t_end = t0_ + ub * 2.0; + for (int i = 0;; ++i) { + double t = t0_ + step * i; + if (!(t < t_end)) + break; report_->report(" {:g} {:g}", t, Vl(t).first); + } } void @@ -605,9 +613,9 @@ public: std::pair loadDelaySlew(const Pin *, double elmore) override; void evalDmpEqns() override; - double voCrossingUpperBound() override; -private: +protected: + double voCrossingUpperBound() override; std::pair V0(double t) override; std::pair Vl0(double t) override; }; @@ -702,7 +710,11 @@ public: double c1) override; std::pair gateDelaySlew() override; void evalDmpEqns() override; + +protected: double voCrossingUpperBound() override; + std::pair V0(double t) override; + std::pair Vl0(double t) override; private: void findDriverParamsPi(); @@ -710,39 +722,26 @@ private: double dt, double ceff_time, double ceff); - std::pair V0(double t) override; - std::pair Vl0(double t) override; // Poles/zero. - double p1_; - double p2_; - double z1_; + double p1_{0.0}; + double p2_{0.0}; + double z1_{0.0}; // Residues. - double k0_; - double k1_; - double k2_; - double k3_; - double k4_; + double k0_{0.0}; + double k1_{0.0}; + double k2_{0.0}; + double k3_{0.0}; + double k4_{0.0}; // Ipi coefficients. - double A_; - double B_; - double D_; + double A_{0.0}; + double B_{0.0}; + double D_{0.0}; }; DmpPi::DmpPi(StaState *sta) : DmpAlg(3, - sta), - p1_(0.0), - p2_(0.0), - z1_(0.0), - k0_(0.0), - k1_(0.0), - k2_(0.0), - k3_(0.0), - k4_(0.0), - A_(0.0), - B_(0.0), - D_(0.0) + sta) { } @@ -846,8 +845,7 @@ DmpPi::evalDmpEqns() throw DmpError("eqn eval failed: slew = 0"); double ceff_time = slew / (vh_ - vl_); - if (ceff_time > 1.4 * dt) - ceff_time = 1.4 * dt; + ceff_time = std::min(ceff_time, 1.4 * dt); if (dt <= 0.0) throw DmpError("eqn eval failed: dt < 0"); @@ -949,6 +947,8 @@ class DmpOnePole : public DmpAlg public: DmpOnePole(StaState *sta); void evalDmpEqns() override; + +protected: double voCrossingUpperBound() override; }; @@ -1018,29 +1018,24 @@ public: double c1) override; std::pair gateDelaySlew() override; -private: +protected: std::pair V0(double t) override; std::pair Vl0(double t) override; double voCrossingUpperBound() override; +private: // Pole/zero. - double p1_; - double z1_; + double p1_{0.0}; + double z1_{0.0}; // Residues. - double k0_; - double k1_; - double k2_; - double k3_; + double k0_{0.0}; + double k1_{0.0}; + double k2_{0.0}; + double k3_{0.0}; }; DmpZeroC2::DmpZeroC2(StaState *sta) : - DmpOnePole(sta), - p1_(0.0), - z1_(0.0), - k0_(0.0), - k1_(0.0), - k2_(0.0), - k3_(0.0) + DmpOnePole(sta) { } @@ -1172,8 +1167,7 @@ DmpAlg::luDecomp() double big = 0.0; for (int j = 0; j < size; j++) { double temp = std::abs(fjac_[i][j]); - if (temp > big) - big = temp; + big = std::max(temp, big); } if (big == 0.0) throw DmpError("LU decomposition: no non-zero row element"); @@ -1268,8 +1262,7 @@ DmpCeffDelayCalc::DmpCeffDelayCalc(StaState *sta) : LumpedCapDelayCalc(sta), dmp_cap_(new DmpCap(sta)), dmp_pi_(new DmpPi(sta)), - dmp_zero_c2_(new DmpZeroC2(sta)), - dmp_alg_(nullptr) + dmp_zero_c2_(new DmpZeroC2(sta)) { } diff --git a/dcalc/DmpCeff.hh b/dcalc/DmpCeff.hh index 15f44640..1ca6209e 100644 --- a/dcalc/DmpCeff.hh +++ b/dcalc/DmpCeff.hh @@ -44,7 +44,7 @@ class DmpCeffDelayCalc : public LumpedCapDelayCalc { public: DmpCeffDelayCalc(StaState *sta); - virtual ~DmpCeffDelayCalc(); + ~DmpCeffDelayCalc() override; bool reduceSupported() const override { return true; } ArcDcalcResult gateDelay(const Pin *drvr_pin, const TimingArc *arc, @@ -98,7 +98,7 @@ private: DmpCap *dmp_cap_; DmpPi *dmp_pi_; DmpZeroC2 *dmp_zero_c2_; - DmpAlg *dmp_alg_; + DmpAlg *dmp_alg_{nullptr}; }; } // namespace sta diff --git a/dcalc/DmpDelayCalc.cc b/dcalc/DmpDelayCalc.cc index c9c63f5a..f94d2086 100644 --- a/dcalc/DmpDelayCalc.cc +++ b/dcalc/DmpDelayCalc.cc @@ -24,15 +24,15 @@ #include "DmpDelayCalc.hh" +#include "DmpCeff.hh" +#include "GraphDelayCalc.hh" +#include "Liberty.hh" +#include "Network.hh" +#include "Parasitics.hh" +#include "PortDirection.hh" +#include "Sdc.hh" #include "TableModel.hh" #include "TimingArc.hh" -#include "Liberty.hh" -#include "PortDirection.hh" -#include "Network.hh" -#include "Sdc.hh" -#include "Parasitics.hh" -#include "GraphDelayCalc.hh" -#include "DmpCeff.hh" namespace sta { @@ -164,7 +164,7 @@ public: const Scene *scene, const MinMax *min_max) override; -private: +protected: void loadDelaySlew(const Pin *load_pin, double drvr_slew, const RiseFall *rf, @@ -173,6 +173,8 @@ private: // Return values. double &wire_delay, double &load_slew) override; + +private: void loadDelay(double drvr_slew, Parasitic *pole_residue, double p1, @@ -190,11 +192,11 @@ private: double tt, double y_tt); - bool parasitic_is_pole_residue_; - float vth_; - float vl_; - float vh_; - float slew_derate_; + bool parasitic_is_pole_residue_{false}; + float vth_{0.0F}; + float vl_{0.0F}; + float vh_{0.0F}; + float slew_derate_{0.0F}; }; ArcDelayCalc * @@ -204,12 +206,7 @@ makeDmpCeffTwoPoleDelayCalc(StaState *sta) } DmpCeffTwoPoleDelayCalc::DmpCeffTwoPoleDelayCalc(StaState *sta) : - DmpCeffDelayCalc(sta), - parasitic_is_pole_residue_(false), - vth_(0.0), - vl_(0.0), - vh_(0.0), - slew_derate_(0.0) + DmpCeffDelayCalc(sta) { } @@ -334,7 +331,7 @@ DmpCeffTwoPoleDelayCalc::loadDelaySlew(const Pin *load_pin, // Should handle PiElmore parasitic. wire_delay = 0.0; load_slew = drvr_slew; - Parasitic *pole_residue = 0; + Parasitic *pole_residue = nullptr; if (parasitic_is_pole_residue_) pole_residue = parasitics_->findPoleResidue(parasitic, load_pin); if (pole_residue) { diff --git a/dcalc/FindRoot.cc b/dcalc/FindRoot.cc index 97e1c62d..58e8dde8 100644 --- a/dcalc/FindRoot.cc +++ b/dcalc/FindRoot.cc @@ -29,7 +29,7 @@ namespace sta { std::pair -findRoot(FindRootFunc func, +findRoot(const FindRootFunc &func, double x1, double x2, double x_tol, @@ -42,7 +42,7 @@ findRoot(FindRootFunc func, } std::pair -findRoot(FindRootFunc func, +findRoot(const FindRootFunc &func, double x1, double y1, double x2, diff --git a/dcalc/FindRoot.hh b/dcalc/FindRoot.hh index d0c1921f..61daac86 100644 --- a/dcalc/FindRoot.hh +++ b/dcalc/FindRoot.hh @@ -36,7 +36,7 @@ using FindRootFunc = const std::function -findRoot(FindRootFunc func, +findRoot(const FindRootFunc &func, double x1, double x2, double x_tol, @@ -44,7 +44,7 @@ findRoot(FindRootFunc func, // first: root estimate; second: true if the search failed. std::pair -findRoot(FindRootFunc func, +findRoot(const FindRootFunc &func, double x1, double y1, double x2, diff --git a/dcalc/GraphDelayCalc.cc b/dcalc/GraphDelayCalc.cc index eddd3235..741353bf 100644 --- a/dcalc/GraphDelayCalc.cc +++ b/dcalc/GraphDelayCalc.cc @@ -24,35 +24,35 @@ #include "GraphDelayCalc.hh" -#include #include +#include #include #include +#include "ArcDelayCalc.hh" +#include "Bfs.hh" +#include "ClkNetwork.hh" #include "ContainerHelpers.hh" #include "Debug.hh" -#include "Stats.hh" -#include "MinMax.hh" -#include "Mutex.hh" -#include "TimingRole.hh" -#include "TimingArc.hh" -#include "Liberty.hh" -#include "PortDirection.hh" -#include "Network.hh" -#include "InputDrive.hh" -#include "Sdc.hh" -#include "Mode.hh" #include "Graph.hh" +#include "InputDrive.hh" +#include "Liberty.hh" +#include "MinMax.hh" +#include "Mode.hh" +#include "Mutex.hh" +#include "NetCaps.hh" +#include "Network.hh" #include "Parasitics.hh" -#include "search/Levelize.hh" +#include "PortDirection.hh" +#include "Sdc.hh" #include "Scene.hh" #include "SearchPred.hh" -#include "Bfs.hh" -#include "ArcDelayCalc.hh" -#include "NetCaps.hh" -#include "ClkNetwork.hh" +#include "Stats.hh" +#include "TimingArc.hh" +#include "TimingRole.hh" #include "Variables.hh" #include "search/Latches.hh" +#include "search/Levelize.hh" namespace sta { @@ -143,15 +143,10 @@ DcalcNonLatchPred::searchThru(Edge *edge, GraphDelayCalc::GraphDelayCalc(StaState *sta) : StaState(sta), - observer_(nullptr), - delays_seeded_(false), - incremental_(false), - delays_exist_(false), invalid_delays_(makeVertexSet(this)), search_pred_(new DcalcPred(sta)), search_non_latch_pred_(new DcalcNonLatchPred(sta)), - iter_(new BfsFwdIterator(BfsIndex::dcalc, search_non_latch_pred_, sta)), - incremental_delay_tolerance_(0.0) + iter_(new BfsFwdIterator(BfsIndex::dcalc, search_non_latch_pred_, sta)) { } @@ -297,9 +292,9 @@ class FindVertexDelays : public VertexVisitor { public: FindVertexDelays(GraphDelayCalc *graph_delay_calc1); - virtual ~FindVertexDelays(); - virtual void visit(Vertex *vertex); - virtual VertexVisitor *copy() const; + ~FindVertexDelays() override; + void visit(Vertex *vertex) override; + VertexVisitor *copy() const override; protected: GraphDelayCalc *graph_delay_calc_; @@ -419,7 +414,7 @@ GraphDelayCalc::seedDrvrSlew(Vertex *drvr_vertex, if (drive) { const LibertyCell *drvr_cell; const LibertyPort *from_port, *to_port; - float *from_slews; + const DriveCellSlews *from_slews; drive->driveCell(rf, min_max, drvr_cell, from_port, from_slews, to_port); if (drvr_cell) { @@ -562,7 +557,7 @@ LibertyPort * GraphDelayCalc::driveCellDefaultFromPort(const LibertyCell *cell, const LibertyPort *to_port) { - LibertyPort *from_port = 0; + LibertyPort *from_port = nullptr; int from_port_index = 0; for (TimingArcSet *arc_set : cell->timingArcSetsTo(to_port)) { LibertyPort *set_from_port = arc_set->from(); @@ -599,7 +594,7 @@ GraphDelayCalc::findInputDriverDelay(const LibertyCell *drvr_cell, Vertex *drvr_vertex, const RiseFall *rf, const LibertyPort *from_port, - float *from_slews, + const DriveCellSlews *from_slews, const LibertyPort *to_port, const Scene *scene, const MinMax *min_max, @@ -611,7 +606,7 @@ GraphDelayCalc::findInputDriverDelay(const LibertyCell *drvr_cell, for (TimingArcSet *arc_set : drvr_cell->timingArcSets(from_port, to_port)) { for (TimingArc *arc : arc_set->arcs()) { if (arc->toEdge()->asRiseFall() == rf) { - float from_slew = from_slews[arc->fromEdge()->index()]; + float from_slew = (*from_slews)[arc->fromEdge()->index()]; findInputArcDelay(drvr_pin, drvr_vertex, arc, from_slew, scene, min_max, arc_delay_calc); } @@ -1270,19 +1265,19 @@ GraphDelayCalc::annotateLoadDelays(Vertex *drvr_vertex, bool load_changed = false; if (!load_vertex->slewAnnotated(drvr_rf, min_max)) { if (drvr_vertex->slewAnnotated(drvr_rf, min_max)) { - // Copy the driver slew to the load if it is annotated. - const Slew drvr_slew = graph_->slew(drvr_vertex,drvr_rf,ap_index); - graph_->setSlew(load_vertex, drvr_rf, ap_index, drvr_slew); + // Copy the driver slew to the load if it is annotated. + const Slew drvr_slew = graph_->slew(drvr_vertex, drvr_rf, ap_index); + graph_->setSlew(load_vertex, drvr_rf, ap_index, drvr_slew); load_changed = true; - } - else { - const Slew slew = graph_->slew(load_vertex, drvr_rf, ap_index); - if (!merge + } + else { + const Slew slew = graph_->slew(load_vertex, drvr_rf, ap_index); + if (!merge || delayGreater(load_slew, slew, min_max, this)) { - graph_->setSlew(load_vertex, drvr_rf, ap_index, load_slew); + graph_->setSlew(load_vertex, drvr_rf, ap_index, load_slew); load_changed = true; } - } + } } if (!graph_->wireDelayAnnotated(wire_edge, drvr_rf, ap_index)) { // Multiple timing arcs with the same output transition @@ -1594,9 +1589,9 @@ GraphDelayCalc::findCheckEdgeDelays(Edge *edge, const RiseFall *to_rf = arc->toEdge()->asRiseFall(); if (from_rf && to_rf) { const LibertyPort *related_out_port = arc_set->relatedOut(); - const Pin *related_out_pin = 0; + const Pin *related_out_pin = nullptr; if (related_out_port) - related_out_pin = network_->findPin(inst, related_out_port); + related_out_pin = network_->findPin(inst, related_out_port); for (Scene *scene : scenes_) { for (const MinMax *min_max : MinMax::range()) { @@ -1677,7 +1672,7 @@ GraphDelayCalc::reportDelayCalc(const Edge *edge, const RiseFall *to_rf = arc->toEdge()->asRiseFall(); if (from_rf && to_rf) { const LibertyPort *related_out_port = arc_set->relatedOut(); - const Pin *related_out_pin = 0; + const Pin *related_out_pin = nullptr; if (related_out_port) related_out_pin = network_->findPin(inst, related_out_port); float related_out_cap = 0.0; @@ -1767,11 +1762,6 @@ GraphDelayCalc::minPeriod(const Pin *pin, //////////////////////////////////////////////////////////////// -MultiDrvrNet::MultiDrvrNet() : - dcalc_drvr_(nullptr) -{ -} - void MultiDrvrNet::netCaps(const RiseFall *drvr_rf, const Scene *scene, diff --git a/dcalc/LumpedCapDelayCalc.cc b/dcalc/LumpedCapDelayCalc.cc index 936fc77a..b245c1d6 100644 --- a/dcalc/LumpedCapDelayCalc.cc +++ b/dcalc/LumpedCapDelayCalc.cc @@ -27,15 +27,15 @@ #include // isnan #include "Debug.hh" -#include "Units.hh" +#include "GraphDelayCalc.hh" +#include "Liberty.hh" +#include "Network.hh" +#include "Parasitics.hh" +#include "PortDirection.hh" +#include "Sdc.hh" #include "TimingArc.hh" #include "TimingModel.hh" -#include "Liberty.hh" -#include "PortDirection.hh" -#include "Network.hh" -#include "Sdc.hh" -#include "Parasitics.hh" -#include "GraphDelayCalc.hh" +#include "Units.hh" #include "Variables.hh" namespace sta { diff --git a/dcalc/LumpedCapDelayCalc.hh b/dcalc/LumpedCapDelayCalc.hh index 7c7643da..d9b24d74 100644 --- a/dcalc/LumpedCapDelayCalc.hh +++ b/dcalc/LumpedCapDelayCalc.hh @@ -61,7 +61,7 @@ public: const LoadPinIndexMap &load_pin_index_map, const Scene *scene, const MinMax *min_max) override; - std::string reportGateDelay(const Pin *drvr_pin, + std::string reportGateDelay(const Pin *check_pin, const TimingArc *arc, const Slew &in_slew, float load_cap, diff --git a/dcalc/NetCaps.cc b/dcalc/NetCaps.cc index 80a7c801..d1eaa45b 100644 --- a/dcalc/NetCaps.cc +++ b/dcalc/NetCaps.cc @@ -26,10 +26,6 @@ namespace sta { -NetCaps::NetCaps() -{ -} - NetCaps::NetCaps(float pin_cap, float wire_cap, float fanout, diff --git a/dcalc/NetCaps.hh b/dcalc/NetCaps.hh index 7c09cc66..a968ddda 100644 --- a/dcalc/NetCaps.hh +++ b/dcalc/NetCaps.hh @@ -30,7 +30,7 @@ namespace sta { class NetCaps { public: - NetCaps(); + NetCaps() = default; NetCaps(float pin_cap, float wire_cap, float fanout, diff --git a/dcalc/ParallelDelayCalc.cc b/dcalc/ParallelDelayCalc.cc index 1cb7c94e..8a47956c 100644 --- a/dcalc/ParallelDelayCalc.cc +++ b/dcalc/ParallelDelayCalc.cc @@ -24,13 +24,13 @@ #include "ParallelDelayCalc.hh" -#include "TimingArc.hh" -#include "Scene.hh" -#include "Network.hh" #include "Graph.hh" -#include "Sdc.hh" -#include "Liberty.hh" #include "GraphDelayCalc.hh" +#include "Liberty.hh" +#include "Network.hh" +#include "Scene.hh" +#include "Sdc.hh" +#include "TimingArc.hh" namespace sta { diff --git a/dcalc/ParallelDelayCalc.hh b/dcalc/ParallelDelayCalc.hh index 46d3f826..f20f4b74 100644 --- a/dcalc/ParallelDelayCalc.hh +++ b/dcalc/ParallelDelayCalc.hh @@ -24,8 +24,8 @@ #pragma once -#include #include +#include #include "DelayCalcBase.hh" diff --git a/dcalc/PrimaDelayCalc.cc b/dcalc/PrimaDelayCalc.cc index 93388a10..a38da6ac 100644 --- a/dcalc/PrimaDelayCalc.cc +++ b/dcalc/PrimaDelayCalc.cc @@ -24,32 +24,27 @@ #include "PrimaDelayCalc.hh" +#include +#include #include // abs #include #include "Debug.hh" -#include "Units.hh" -#include "TimingArc.hh" -#include "Liberty.hh" -#include "PortDirection.hh" -#include "Network.hh" -#include "Sdc.hh" -#include "Scene.hh" -#include "Graph.hh" -#include "Parasitics.hh" -#include "GraphDelayCalc.hh" #include "DmpDelayCalc.hh" #include "Format.hh" - -#include -#include +#include "Graph.hh" +#include "GraphDelayCalc.hh" +#include "Liberty.hh" +#include "Network.hh" +#include "Parasitics.hh" +#include "PortDirection.hh" +#include "Scene.hh" +#include "Sdc.hh" +#include "TimingArc.hh" +#include "Units.hh" namespace sta { -using Eigen::ColPivHouseholderQR; -using Eigen::HouseholderQR; -using Eigen::SparseLU; - // Lawrence Pillage - “Electronic Circuit & System Simulation Methods” 1998 // McGraw-Hill, Inc. New York, NY. @@ -61,17 +56,7 @@ makePrimaDelayCalc(StaState *sta) PrimaDelayCalc::PrimaDelayCalc(StaState *sta) : DelayCalcBase(sta), - dcalc_args_(nullptr), - scene_(nullptr), - min_max_(nullptr), - parasitics_(nullptr), - parasitic_network_(nullptr), - load_pin_index_map_(nullptr), pin_node_map_(network_), - prima_order_(3), - make_waveforms_(false), - waveform_drvr_pin_(nullptr), - waveform_load_pin_(nullptr), watch_pin_values_(network_), table_dcalc_(makeDmpCeffElmoreDelayCalc(sta)) { @@ -79,20 +64,18 @@ PrimaDelayCalc::PrimaDelayCalc(StaState *sta) : PrimaDelayCalc::PrimaDelayCalc(const PrimaDelayCalc &dcalc) : DelayCalcBase(dcalc), - dcalc_args_(nullptr), - load_pin_index_map_(nullptr), pin_node_map_(network_), node_index_map_(dcalc.node_index_map_), prima_order_(dcalc.prima_order_), - make_waveforms_(false), - waveform_drvr_pin_(nullptr), - waveform_load_pin_(nullptr), watch_pin_values_(network_), table_dcalc_(makeDmpCeffElmoreDelayCalc(this)) { } -PrimaDelayCalc::~PrimaDelayCalc() { delete table_dcalc_; } +PrimaDelayCalc::~PrimaDelayCalc() +{ + delete table_dcalc_; +} ArcDelayCalc * PrimaDelayCalc::copy() @@ -359,7 +342,7 @@ PrimaDelayCalc::simulate1(const MatrixSd &G, const Eigen::MatrixXd &B, const Eigen::VectorXd &x_init, const Eigen::MatrixXd &x_to_v, - const size_t order) + size_t order) { Eigen::VectorXd x(order); Eigen::VectorXd x_prev(order); @@ -379,7 +362,7 @@ PrimaDelayCalc::simulate1(const MatrixSd &G, MatrixSd A(order, order); A = G + (2.0 / time_step_) * C; A.makeCompressed(); - SparseLU A_solver; + Eigen::SparseLU A_solver; A_solver.compute(A); // Initial time depends on ceff which impact delay, so use a sim step @@ -403,7 +386,10 @@ PrimaDelayCalc::simulate1(const MatrixSd &G, if (make_waveforms_) recordWaveformStep(time_begin); - for (double time = time_begin; time <= time_end; time += time_step_) { + for (size_t step = 0;; ++step) { + const double time = time_begin + step * time_step_; + if (time > time_end) + break; setPortCurrents(); rhs = B * u_ + (1.0 / time_step_) * C * (3.0 * x_prev - x_prev2); x = A_solver.solve(rhs); @@ -850,7 +836,7 @@ PrimaDelayCalc::primaReduce() { G_.makeCompressed(); // Step 3: solve G*R = B for R - SparseLU G_solver(G_); + Eigen::SparseLU G_solver(G_); if (G_solver.info() != Eigen::Success) report_->error(1752, "G matrix is singular."); Eigen::MatrixXd R(order_, port_count_); @@ -1038,7 +1024,7 @@ PinSeq PrimaDelayCalc::watchPins() const { PinSeq pins; - for (auto pin_values : watch_pin_values_) { + for (const auto &pin_values : watch_pin_values_) { const Pin *pin = pin_values.first; pins.push_back(pin); } @@ -1117,10 +1103,8 @@ void PrimaDelayCalc::reportMatrix(Eigen::VectorXd &matrix) { std::string line = "| "; - for (Eigen::Index i = 0; i < matrix.rows(); i++) { - std::string entry = + for (Eigen::Index i = 0; i < matrix.rows(); i++) line += sta::format("{:10.3e}", matrix.coeff(i)) + " "; - } line += "|"; report_->reportLine(line); } @@ -1129,8 +1113,8 @@ void PrimaDelayCalc::reportVector(std::vector &matrix) { std::string line = "| "; - for (size_t i = 0; i < matrix.size(); i++) - line += sta::format("{:10.3e}", matrix[i]) + " "; + for (const double &entry : matrix) + line += sta::format("{:10.3e}", entry) + " "; line += "|"; report_->reportLine(line); } diff --git a/dcalc/PrimaDelayCalc.hh b/dcalc/PrimaDelayCalc.hh index a925efdf..4d5b1346 100644 --- a/dcalc/PrimaDelayCalc.hh +++ b/dcalc/PrimaDelayCalc.hh @@ -24,13 +24,14 @@ #pragma once -#include -#include #include #include +#include +#include +#include -#include "LumpedCapDelayCalc.hh" #include "ArcDcalcWaveforms.hh" +#include "LumpedCapDelayCalc.hh" #include "Parasitics.hh" namespace sta { @@ -57,7 +58,7 @@ class PrimaDelayCalc : public DelayCalcBase, public: PrimaDelayCalc(StaState *sta); PrimaDelayCalc(const PrimaDelayCalc &dcalc); - ~PrimaDelayCalc(); + ~PrimaDelayCalc() override; ArcDelayCalc *copy() override; void copyState(const StaState *sta) override; std::string_view name() const override { return "prima"; } @@ -123,7 +124,7 @@ protected: const Eigen::MatrixXd &B, const Eigen::VectorXd &x_init, const Eigen::MatrixXd &x_to_v, - const size_t order); + size_t order); double maxTime(); double timeStep(); float driverResistance(); @@ -178,15 +179,15 @@ protected: void reportMatrix(Eigen::VectorXd &matrix); void reportVector(std::vector &matrix); - ArcDcalcArgSeq *dcalc_args_; + ArcDcalcArgSeq *dcalc_args_{nullptr}; size_t drvr_count_; float load_cap_; - const Scene *scene_; - const MinMax *min_max_; - Parasitics *parasitics_; - const Parasitic *parasitic_network_; + const Scene *scene_{nullptr}; + const MinMax *min_max_{nullptr}; + Parasitics *parasitics_{nullptr}; + const Parasitic *parasitic_network_{nullptr}; const RiseFall *drvr_rf_; - const LoadPinIndexMap *load_pin_index_map_; + const LoadPinIndexMap *load_pin_index_map_{nullptr}; PinNodeMap pin_node_map_; // Parasitic pin -> array index NodeIndexMap node_index_map_; // Parasitic node -> array index @@ -210,7 +211,7 @@ protected: Eigen::VectorXd u_; // Prima reduced MNA eqns - size_t prima_order_; + size_t prima_order_{3}; Eigen::MatrixXd Vq_; MatrixSd Gq_; MatrixSd Cq_; @@ -231,9 +232,9 @@ protected: double time_step_prev_; // Waveform recording. - bool make_waveforms_; - const Pin *waveform_drvr_pin_; - const Pin *waveform_load_pin_; + bool make_waveforms_{false}; + const Pin *waveform_drvr_pin_{nullptr}; + const Pin *waveform_load_pin_{nullptr}; FloatSeq drvr_voltages_; FloatSeq load_voltages_; WatchPinValuesMap watch_pin_values_; @@ -248,7 +249,7 @@ protected: static constexpr size_t threshold_vth = 1; static constexpr size_t threshold_vh = 2; static constexpr size_t measure_threshold_count_ = 3; - typedef std::array ThresholdTimes; + using ThresholdTimes = std::array; // Vl Vth Vh ThresholdTimes measure_thresholds_; // Indexed by node number. diff --git a/graph/Graph.cc b/graph/Graph.cc index fa92605c..74996842 100644 --- a/graph/Graph.cc +++ b/graph/Graph.cc @@ -26,16 +26,16 @@ #include "ContainerHelpers.hh" #include "Debug.hh" -#include "Stats.hh" +#include "FuncExpr.hh" +#include "Liberty.hh" #include "MinMax.hh" #include "Mutex.hh" -#include "Transition.hh" -#include "TimingRole.hh" -#include "TimingArc.hh" -#include "Liberty.hh" -#include "PortDirection.hh" #include "Network.hh" -#include "FuncExpr.hh" +#include "PortDirection.hh" +#include "Stats.hh" +#include "TimingArc.hh" +#include "TimingRole.hh" +#include "Transition.hh" #include "Variables.hh" namespace sta { @@ -49,8 +49,6 @@ namespace sta { Graph::Graph(StaState *sta, DcalcAPIndex ap_count) : StaState(sta), - vertices_(nullptr), - edges_(nullptr), ap_count_(ap_count), period_check_annotations_(network_), reg_clk_vertices_(makeVertexSet(this)) @@ -342,11 +340,10 @@ class MakeEdgesThruHierPin : public HierPinThruVisitor { public: MakeEdgesThruHierPin(Graph *graph); - -private: void visit(const Pin *drvr, const Pin *load) override; +private: Graph *graph_; }; @@ -585,7 +582,7 @@ Graph::slew(const Vertex *vertex, size_t slew_index = ap_index * RiseFall::index_count + rf->index(); const float *slews_flt = vertex->slewsFloat(); if (variables_->pocvEnabled()) { - const Slew *slews = std::bit_cast(slews_flt); + const Slew *slews = reinterpret_cast(slews_flt); return slews[slew_index]; } else @@ -598,7 +595,7 @@ Graph::slew(const Vertex *vertex, { const float *slews_flt = vertex->slewsFloat(); if (variables_->pocvEnabled()) { - const Slew *slews = std::bit_cast(slews_flt); + const Slew *slews = reinterpret_cast(slews_flt); return slews[index]; } else @@ -678,7 +675,7 @@ Graph::arcDelay(const Edge *edge, { size_t index = arc->index() * ap_count_ + ap_index; if (variables_->pocvEnabled()) { - ArcDelay *delays = std::bit_cast(edge->arcDelays()); + const ArcDelay *delays = reinterpret_cast(edge->arcDelays()); return delays[index]; } else { @@ -695,7 +692,7 @@ Graph::setArcDelay(Edge *edge, { size_t index = arc->index() * ap_count_ + ap_index; if (variables_->pocvEnabled()) { - ArcDelay *delays = std::bit_cast(edge->arcDelays()); + ArcDelay *delays = reinterpret_cast(edge->arcDelays()); delays[index] = delay; } else { @@ -711,7 +708,7 @@ Graph::wireArcDelay(const Edge *edge, { size_t index = rf->index() * ap_count_ + ap_index; if (variables_->pocvEnabled()) { - ArcDelay *delays = std::bit_cast(edge->arcDelays()); + const ArcDelay *delays = reinterpret_cast(edge->arcDelays()); return delays[index]; } else { @@ -728,7 +725,7 @@ Graph::setWireArcDelay(Edge *edge, { size_t index = rf->index() * ap_count_ + ap_index; if (variables_->pocvEnabled()) { - ArcDelay *delays = std::bit_cast(edge->arcDelays()); + ArcDelay *delays = reinterpret_cast(edge->arcDelays()); delays[index] = delay; } else { @@ -753,7 +750,7 @@ Graph::setArcDelayAnnotated(Edge *edge, DcalcAPIndex ap_index, bool annotated) { - return edge->setArcDelayAnnotated(arc, ap_index, ap_count_, annotated); + edge->setArcDelayAnnotated(arc, ap_index, ap_count_, annotated); } bool @@ -774,7 +771,7 @@ Graph::setWireDelayAnnotated(Edge *edge, { int arc_index = TimingArcSet::wireArcIndex(rf); TimingArc *arc = TimingArcSet::wireTimingArcSet()->findTimingArc(arc_index); - return edge->setArcDelayAnnotated(arc, ap_index, ap_count_, annotated); + edge->setArcDelayAnnotated(arc, ap_index, ap_count_, annotated); } void @@ -819,7 +816,7 @@ Graph::initSlews(Vertex *vertex) { size_t slew_count = slewCount(); if (variables_->pocvEnabled()) { - float *slews = std::bit_cast(new Slew[slew_count]{}); + float *slews = reinterpret_cast(new Slew[slew_count]{}); vertex->setSlews(slews); } else { @@ -840,7 +837,7 @@ Graph::initArcDelays(Edge *edge) size_t arc_count = edge->timingArcSet()->arcCount(); size_t delay_count = arc_count * ap_count_; if (variables_->pocvEnabled()) { - float *delays = std::bit_cast(new ArcDelay[delay_count]{}); + float *delays = reinterpret_cast(new ArcDelay[delay_count]{}); edge->setArcDelays(delays); } else { @@ -1187,7 +1184,7 @@ Vertex::setHasDownstreamClkPin(bool has_clk_pin) bool Vertex::bfsInQueue(BfsIndex index) const { - return (bfs_in_queue_ >> unsigned(index)) & 1; + return (bfs_in_queue_ >> static_cast(index)) & 1; } void @@ -1195,9 +1192,9 @@ Vertex::setBfsInQueue(BfsIndex index, bool value) { if (value) - bfs_in_queue_ |= 1 << int(index); + bfs_in_queue_ |= 1 << static_cast(index); else - bfs_in_queue_ &= ~(1 << int(index)); + bfs_in_queue_ &= ~(1 << static_cast(index)); } //////////////////////////////////////////////////////////////// @@ -1400,10 +1397,7 @@ VertexIterator::VertexIterator(Graph *graph) : graph_(graph), network_(graph->network()), top_inst_(network_->topInstance()), - inst_iter_(network_->leafInstanceIterator()), - pin_iter_(nullptr), - vertex_(nullptr), - bidir_vertex_(nullptr) + inst_iter_(network_->leafInstanceIterator()) { if (inst_iter_) findNext(); diff --git a/graph/Graph.i b/graph/Graph.i index 371e929c..7b31ebc0 100644 --- a/graph/Graph.i +++ b/graph/Graph.i @@ -25,16 +25,16 @@ %module graph %{ -#include "Graph.hh" +#include "Clock.hh" #include "FuncExpr.hh" -#include "TimingRole.hh" +#include "Graph.hh" #include "Liberty.hh" #include "Network.hh" -#include "Clock.hh" #include "Scene.hh" #include "Search.hh" #include "Sdc.hh" #include "Sta.hh" +#include "TimingRole.hh" using namespace sta; diff --git a/graph/GraphCmp.cc b/graph/GraphCmp.cc index 3c3a5dfc..8ad693df 100644 --- a/graph/GraphCmp.cc +++ b/graph/GraphCmp.cc @@ -22,12 +22,13 @@ // // This notice may not be removed or altered from any source distribution. +#include "GraphCmp.hh" + #include "ContainerHelpers.hh" -#include "StringUtil.hh" +#include "Graph.hh" #include "Network.hh" #include "NetworkCmp.hh" -#include "Graph.hh" -#include "GraphCmp.hh" +#include "StringUtil.hh" namespace sta { @@ -73,4 +74,4 @@ sortEdges(EdgeSeq *edges, sort(edges, EdgeLess(network, graph)); } -} +} // namespace sta diff --git a/include/sta/ArcDelayCalc.hh b/include/sta/ArcDelayCalc.hh index b21d524c..eacad445 100644 --- a/include/sta/ArcDelayCalc.hh +++ b/include/sta/ArcDelayCalc.hh @@ -24,20 +24,20 @@ #pragma once +#include #include #include #include -#include -#include "MinMax.hh" -#include "LibertyClass.hh" -#include "TimingArc.hh" -#include "TableModel.hh" -#include "NetworkClass.hh" -#include "GraphClass.hh" #include "Delay.hh" +#include "GraphClass.hh" +#include "LibertyClass.hh" +#include "MinMax.hh" +#include "NetworkClass.hh" #include "ParasiticsClass.hh" #include "StaState.hh" +#include "TableModel.hh" +#include "TimingArc.hh" namespace sta { @@ -70,7 +70,7 @@ public: const Pin *drvr_pin, Edge *edge, const TimingArc *arc, - float in_delay); + float input_delay); const Pin *inPin() const { return in_pin_; } const RiseFall *inEdge() const; const Pin *drvrPin() const { return drvr_pin_; } diff --git a/include/sta/Bdd.hh b/include/sta/Bdd.hh index 0cc101bf..834696fc 100644 --- a/include/sta/Bdd.hh +++ b/include/sta/Bdd.hh @@ -26,8 +26,8 @@ #include -#include "StaState.hh" #include "LibertyClass.hh" +#include "StaState.hh" struct DdNode; struct DdManager; diff --git a/include/sta/Bfs.hh b/include/sta/Bfs.hh index 10c90f17..5c11ab1c 100644 --- a/include/sta/Bfs.hh +++ b/include/sta/Bfs.hh @@ -27,10 +27,10 @@ #include #include -#include "Iterator.hh" #include "GraphClass.hh" -#include "VertexVisitor.hh" +#include "Iterator.hh" #include "StaState.hh" +#include "VertexVisitor.hh" namespace sta { diff --git a/include/sta/BoundedHeap.hh b/include/sta/BoundedHeap.hh index ff0ee39d..6ae23ce0 100644 --- a/include/sta/BoundedHeap.hh +++ b/include/sta/BoundedHeap.hh @@ -24,10 +24,10 @@ #pragma once -#include #include #include #include +#include namespace sta { diff --git a/include/sta/ClkNetwork.hh b/include/sta/ClkNetwork.hh index 1d25b57c..493446c8 100644 --- a/include/sta/ClkNetwork.hh +++ b/include/sta/ClkNetwork.hh @@ -26,10 +26,10 @@ #include -#include "StaState.hh" -#include "NetworkClass.hh" #include "GraphClass.hh" +#include "NetworkClass.hh" #include "SdcClass.hh" +#include "StaState.hh" namespace sta { diff --git a/include/sta/Clock.hh b/include/sta/Clock.hh index aae3e58b..48cfb88d 100644 --- a/include/sta/Clock.hh +++ b/include/sta/Clock.hh @@ -27,11 +27,11 @@ #include #include +#include "GraphClass.hh" #include "MinMax.hh" #include "RiseFallMinMax.hh" #include "SdcClass.hh" #include "SdcCmdComment.hh" -#include "GraphClass.hh" namespace sta { @@ -170,31 +170,31 @@ protected: std::string name_; PinSet pins_; - bool add_to_pins_; + bool add_to_pins_{false}; // Hierarchical pins in pins_ become driver pins through the pin. PinSet leaf_pins_; - float period_; - FloatSeq *waveform_; - bool waveform_valid_; + float period_{0.0}; + FloatSeq *waveform_{nullptr}; + bool waveform_valid_{false}; const int index_; - ClockEdge **clk_edges_; - bool is_propagated_; + ClockEdge **clk_edges_{nullptr}; + bool is_propagated_{false}; RiseFallMinMax slews_; RiseFallMinMax slew_limits_[path_clk_or_data_count]; - ClockUncertainties *uncertainties_; - bool is_generated_; + ClockUncertainties *uncertainties_{nullptr}; + bool is_generated_{false}; // Generated clock variables. - Pin *src_pin_; - Clock *master_clk_; + Pin *src_pin_{nullptr}; + Clock *master_clk_{nullptr}; // True if the master clock is infered rather than specified by command. - bool master_clk_infered_; - int divide_by_; - int multiply_by_; - float duty_cycle_; - bool invert_; - bool combinational_; - IntSeq *edges_; - FloatSeq *edge_shifts_; + bool master_clk_infered_{false}; + int divide_by_{0}; + int multiply_by_{0}; + float duty_cycle_{0}; + bool invert_{false}; + bool combinational_{false}; + IntSeq *edges_{nullptr}; + FloatSeq *edge_shifts_{nullptr}; private: friend class Sdc; @@ -205,7 +205,6 @@ class ClockEdge { public: Clock *clock() const { return clock_; } - ~ClockEdge(); const RiseFall *transition() const { return rf_; } float time() const { return time_; } const std::string &name() const { return name_; } @@ -223,7 +222,7 @@ private: Clock *clock_; const RiseFall *rf_; std::string name_; - float time_; + float time_{0.0}; int index_; }; diff --git a/include/sta/ClockGatingCheck.hh b/include/sta/ClockGatingCheck.hh index dad7bdeb..f460472f 100644 --- a/include/sta/ClockGatingCheck.hh +++ b/include/sta/ClockGatingCheck.hh @@ -24,22 +24,21 @@ #pragma once -#include "SdcClass.hh" #include "RiseFallMinMax.hh" +#include "SdcClass.hh" namespace sta { class ClockGatingCheck { public: - ClockGatingCheck(); RiseFallMinMax *margins() { return &margins_; } void setActiveValue(LogicValue value); LogicValue activeValue() const { return active_value_; } private: RiseFallMinMax margins_; - LogicValue active_value_; + LogicValue active_value_{LogicValue::unknown}; }; } // namespace sta diff --git a/include/sta/ClockGroups.hh b/include/sta/ClockGroups.hh index f725b6e9..7a3540b1 100644 --- a/include/sta/ClockGroups.hh +++ b/include/sta/ClockGroups.hh @@ -26,8 +26,8 @@ #include -#include "SdcCmdComment.hh" #include "SdcClass.hh" +#include "SdcCmdComment.hh" namespace sta { diff --git a/include/sta/ClockInsertion.hh b/include/sta/ClockInsertion.hh index 256e7dbe..a33423b3 100644 --- a/include/sta/ClockInsertion.hh +++ b/include/sta/ClockInsertion.hh @@ -26,8 +26,8 @@ #include "MinMax.hh" #include "NetworkClass.hh" -#include "SdcClass.hh" #include "RiseFallMinMax.hh" +#include "SdcClass.hh" #include "Transition.hh" namespace sta { diff --git a/include/sta/ClockLatency.hh b/include/sta/ClockLatency.hh index 87ddb3b7..54c4dff2 100644 --- a/include/sta/ClockLatency.hh +++ b/include/sta/ClockLatency.hh @@ -26,9 +26,9 @@ #include "MinMax.hh" #include "NetworkClass.hh" -#include "Transition.hh" -#include "SdcClass.hh" #include "RiseFallMinMax.hh" +#include "SdcClass.hh" +#include "Transition.hh" namespace sta { diff --git a/include/sta/ConcreteLibrary.hh b/include/sta/ConcreteLibrary.hh index 50182a1e..75018056 100644 --- a/include/sta/ConcreteLibrary.hh +++ b/include/sta/ConcreteLibrary.hh @@ -25,12 +25,12 @@ #pragma once #include +#include #include #include -#include -#include "StringUtil.hh" #include "NetworkClass.hh" +#include "StringUtil.hh" // The classes defined in this file are a contrete implementation of // the library API. They can be used by a reader to construct classes @@ -84,8 +84,8 @@ protected: ObjectId id_; std::string filename_; bool is_liberty_; - char bus_brkt_left_; - char bus_brkt_right_; + char bus_brkt_left_{'['}; + char bus_brkt_right_{']'}; ConcreteCellMap cell_map_; private: @@ -129,7 +129,7 @@ public: // Group previously defined bus bit ports together. void groupBusPorts(char bus_brkt_left, char bus_brkt_right, - std::function port_msb_first); + const std::function &port_msb_first); size_t portCount() const; void setName(std::string_view name); virtual void addPort(ConcretePort *port); @@ -149,7 +149,7 @@ protected: int from_index, int to_index); // Bus port bit (internal to makeBusPortBits). - ConcretePort *makePort(std::string bit_name, + ConcretePort *makePort(std::string_view bit_name, int bit_index); void makeBusPortBit(ConcretePort *bus_port, std::string_view bus_name, @@ -160,14 +160,14 @@ protected: // Filename is optional. std::string filename_; ConcreteLibrary *library_; - LibertyCell *liberty_cell_; + LibertyCell *liberty_cell_{nullptr}; // External application cell. - void *ext_cell_; + void *ext_cell_{nullptr}; // Non-bus and bus ports (but no expanded bus bit ports). ConcretePortSeq ports_; ConcretePortMap port_map_; // Port bit count (expanded buses). - int port_bit_count_; + int port_bit_count_{0}; bool is_leaf_; AttributeMap attribute_map_; @@ -242,10 +242,10 @@ protected: ObjectId id_; ConcreteCell *cell_; PortDirection *direction_; - LibertyPort *liberty_port_; + LibertyPort *liberty_port_{nullptr}; // External application port. - void *ext_port_; - int pin_index_; + void *ext_port_{nullptr}; + int pin_index_{-1}; bool is_bundle_; bool is_bus_; int from_index_; @@ -253,7 +253,7 @@ protected: // Expanded bus bit ports (ordered by from_index_ to to_index_) // or bundle member ports. ConcretePortSeq *member_ports_; - ConcretePort *bundle_port_; + ConcretePort *bundle_port_{nullptr}; private: friend class ConcreteCell; @@ -271,8 +271,8 @@ private: const ConcretePortSeq &ports_; ConcretePortSeq::const_iterator port_iter_; - ConcretePortMemberIterator *member_iter_; - ConcretePort *next_; + ConcretePortMemberIterator *member_iter_{nullptr}; + ConcretePort *next_{nullptr}; }; } // namespace sta diff --git a/include/sta/ConcreteNetwork.hh b/include/sta/ConcreteNetwork.hh index 592a65a6..593c444c 100644 --- a/include/sta/ConcreteNetwork.hh +++ b/include/sta/ConcreteNetwork.hh @@ -25,14 +25,14 @@ #pragma once #include -#include -#include #include #include +#include +#include -#include "StringUtil.hh" -#include "Network.hh" #include "LibertyClass.hh" +#include "Network.hh" +#include "StringUtil.hh" namespace sta { @@ -263,6 +263,9 @@ public: using Network::isLeaf; protected: + void clearImpl(); + void deleteCellNetworkViewsImpl(); + void deleteInstanceImpl(Instance *inst); void addLibrary(ConcreteLibrary *library); void setName(std::string_view name); void clearConstantNets(); @@ -280,8 +283,8 @@ protected: // Cell lookup search order sequence. ConcreteLibrarySeq library_seq_; ConcreteLibraryMap library_map_; - Instance *top_instance_; - NetSet constant_nets_[2]; // LogicValue::zero/one + Instance *top_instance_{nullptr}; + NetSet constant_nets_[2]{NetSet(this), NetSet(this)}; // LogicValue::zero/one LinkNetworkFunc link_func_; CellNetworkViewMap cell_network_view_map_; static ObjectId object_id_; @@ -293,7 +296,7 @@ private: class ConcreteInstance { public: - std::string_view name() const { return name_; } + const std::string &name() const { return name_; } ObjectId id() const { return id_; } Cell *cell() const; ConcreteInstance *parent() const { return parent_; } @@ -332,8 +335,8 @@ protected: ConcreteInstance *parent_; // Array of pins indexed by pin->port->index(). ConcretePinSeq pins_; - ConcreteInstanceChildMap *children_; - ConcreteInstanceNetMap *nets_; + ConcreteInstanceChildMap *children_{nullptr}; + ConcreteInstanceNetMap *nets_{nullptr}; AttributeMap attribute_map_; private: @@ -344,7 +347,7 @@ private: class ConcretePin { public: - std::string_view name() const; + const std::string &name() const; ConcreteInstance *instance() const { return instance_; } ConcreteNet *net() const { return net_; } ConcretePort *port() const { return port_; } @@ -362,12 +365,12 @@ protected: ConcreteInstance *instance_; ConcretePort *port_; ConcreteNet *net_; - ConcreteTerm *term_; + ConcreteTerm *term_{nullptr}; ObjectId id_; // Doubly linked list of net pins. - ConcretePin *net_next_; - ConcretePin *net_prev_; - VertexId vertex_id_; + ConcretePin *net_next_{nullptr}; + ConcretePin *net_prev_{nullptr}; + VertexId vertex_id_{vertex_id_null}; private: friend class ConcreteNetwork; @@ -378,7 +381,7 @@ private: class ConcreteTerm { public: - std::string_view name() const; + const std::string &name() const; ObjectId id() const { return id_; } ConcreteNet *net() const { return net_; } ConcretePin *pin() const { return pin_; } @@ -392,7 +395,7 @@ protected: ConcreteNet *net_; ObjectId id_; // Linked list of net terms. - ConcreteTerm *net_next_; + ConcreteTerm *net_next_{nullptr}; private: friend class ConcreteNetwork; @@ -403,7 +406,7 @@ private: class ConcreteNet { public: - std::string_view name() const { return name_; } + const std::string &name() const { return name_; } ObjectId id() const { return id_; } ConcreteInstance *instance() const { return instance_; } void addPin(ConcretePin *pin); @@ -420,12 +423,12 @@ protected: ObjectId id_; ConcreteInstance *instance_; // Pointer to head of linked list of pins. - ConcretePin *pins_; + ConcretePin *pins_{nullptr}; // Pointer to head of linked list of terminals. // These terminals correspond to the pins attached to the instance that // contains this net in the hierarchy level above. - ConcreteTerm *terms_; - ConcreteNet *merged_into_; + ConcreteTerm *terms_{nullptr}; + ConcreteNet *merged_into_{nullptr}; friend class ConcreteNetwork; friend class ConcreteNetTermIterator; diff --git a/include/sta/CycleAccting.hh b/include/sta/CycleAccting.hh index ca4aa3b8..8eb36907 100644 --- a/include/sta/CycleAccting.hh +++ b/include/sta/CycleAccting.hh @@ -27,9 +27,9 @@ #include #include "MinMax.hh" -#include "TimingRole.hh" -#include "StaState.hh" #include "SdcClass.hh" +#include "StaState.hh" +#include "TimingRole.hh" namespace sta { @@ -127,7 +127,7 @@ private: int src_cycle_[TimingRole::index_max + 1]; // Target clock cycle offset. int tgt_cycle_[TimingRole::index_max + 1]; - bool max_cycles_exceeded_; + bool max_cycles_exceeded_{false}; }; } // namespace sta diff --git a/include/sta/DataCheck.hh b/include/sta/DataCheck.hh index e96e067c..e14c6331 100644 --- a/include/sta/DataCheck.hh +++ b/include/sta/DataCheck.hh @@ -24,12 +24,12 @@ #pragma once -#include "MinMax.hh" #include "LibertyClass.hh" +#include "MinMax.hh" #include "NetworkClass.hh" #include "NetworkCmp.hh" -#include "SdcClass.hh" #include "RiseFallMinMax.hh" +#include "SdcClass.hh" namespace sta { diff --git a/include/sta/Debug.hh b/include/sta/Debug.hh index 0bc4be1d..876009a4 100644 --- a/include/sta/Debug.hh +++ b/include/sta/Debug.hh @@ -24,10 +24,10 @@ #pragma once -#include -#include #include #include +#include +#include #include "Format.hh" #include "Report.hh" diff --git a/include/sta/Delay.hh b/include/sta/Delay.hh index 983e6889..6a6984bd 100644 --- a/include/sta/Delay.hh +++ b/include/sta/Delay.hh @@ -27,8 +27,8 @@ #include #include -#include "StaConfig.hh" #include "MinMax.hh" +#include "StaConfig.hh" namespace sta { @@ -78,7 +78,7 @@ class DelayDbl { public: DelayDbl() noexcept; - DelayDbl(double value) noexcept; + DelayDbl(double mean) noexcept; double mean() const { return values_[0]; } void setMean(double mean); double meanShift() const { return values_[1]; } diff --git a/include/sta/DeratingFactors.hh b/include/sta/DeratingFactors.hh index a068a6da..00531830 100644 --- a/include/sta/DeratingFactors.hh +++ b/include/sta/DeratingFactors.hh @@ -24,10 +24,10 @@ #pragma once -#include "MinMax.hh" #include "LibertyClass.hh" -#include "SdcClass.hh" +#include "MinMax.hh" #include "RiseFallMinMax.hh" +#include "SdcClass.hh" namespace sta { @@ -111,10 +111,4 @@ private: DeratingFactors factors_[timing_derate_cell_type_count]; }; -class DeratingFactorsNet : public DeratingFactors -{ -public: - DeratingFactorsNet(); -}; - } // namespace sta diff --git a/include/sta/DisabledPorts.hh b/include/sta/DisabledPorts.hh index 5628d85c..2352b8a3 100644 --- a/include/sta/DisabledPorts.hh +++ b/include/sta/DisabledPorts.hh @@ -27,8 +27,8 @@ #include #include -#include "NetworkClass.hh" #include "LibertyClass.hh" +#include "NetworkClass.hh" #include "SdcClass.hh" namespace sta { @@ -46,7 +46,6 @@ using TimingArcSetSet = std::set; class DisabledPorts { public: - DisabledPorts(); ~DisabledPorts(); void setDisabledAll(); void removeDisabledAll(); @@ -67,10 +66,10 @@ public: [[nodiscard]] bool all() const { return all_; } private: - bool all_; - LibertyPortSet *from_; - LibertyPortSet *to_; - LibertyPortPairSet *from_to_; + bool all_{false}; + LibertyPortSet *from_{nullptr}; + LibertyPortSet *to_{nullptr}; + LibertyPortPairSet *from_to_{nullptr}; }; // set_disable_timing cell [-from] [-to] @@ -89,7 +88,7 @@ public: private: LibertyCell *cell_; - TimingArcSetSet *arc_sets_; + TimingArcSetSet *arc_sets_{nullptr}; }; // set_disable_timing instance [-from] [-to] diff --git a/include/sta/DispatchQueue.hh b/include/sta/DispatchQueue.hh index 9baa0099..ceda2e78 100644 --- a/include/sta/DispatchQueue.hh +++ b/include/sta/DispatchQueue.hh @@ -5,14 +5,14 @@ #pragma once -#include -#include -#include -#include -#include -#include -#include #include +#include +#include +#include +#include +#include +#include +#include namespace sta { diff --git a/include/sta/Error.hh b/include/sta/Error.hh index 7459e315..5754a99b 100644 --- a/include/sta/Error.hh +++ b/include/sta/Error.hh @@ -35,7 +35,6 @@ namespace sta { class Exception : public std::exception { public: - Exception(); const char *what() const noexcept override = 0; }; diff --git a/include/sta/ExceptionPath.hh b/include/sta/ExceptionPath.hh index 07987e94..c67270ae 100644 --- a/include/sta/ExceptionPath.hh +++ b/include/sta/ExceptionPath.hh @@ -29,8 +29,8 @@ #include #include "Error.hh" -#include "SdcCmdComment.hh" #include "SdcClass.hh" +#include "SdcCmdComment.hh" namespace sta { @@ -145,7 +145,7 @@ protected: const MinMaxAll *min_max_; bool own_pts_; int priority_; - size_t id_; // Unique ID assigned by Sdc. + size_t id_{0}; // Unique ID assigned by Sdc. ExceptionState *states_; }; @@ -301,7 +301,6 @@ public: ExceptionTo *to, bool own_pts, std::string_view comment); - ~GroupPath() override; ExceptionPath *clone(ExceptionFrom *from, ExceptionThruSeq *thrus, ExceptionTo *to, @@ -367,7 +366,7 @@ protected: bool own_pts_; // Hash is cached because there may be many objects to speed up // exception merging. - size_t hash_; + size_t hash_{0}; // Maximum number of objects for to_string() to show. static const int to_string_max_objects_; @@ -583,7 +582,7 @@ protected: // Leaf/port pins. PinSet *pins_; // Graph edges that traverse thru hierarchical pins. - EdgePinsSet *edges_; + EdgePinsSet *edges_{nullptr}; NetSet *nets_; InstanceSet *insts_; }; @@ -602,9 +601,9 @@ public: private: const ExceptionPath *exception_; - bool from_done_; + bool from_done_{false}; ExceptionThruSeq::iterator thru_iter_; - bool to_done_; + bool to_done_{false}; }; // Visitor for exception point sets expanded into single object paths. @@ -665,7 +664,7 @@ public: private: ExceptionPath *exception_; ExceptionThru *next_thru_; - ExceptionState *next_state_; + ExceptionState *next_state_{nullptr}; int index_; }; diff --git a/include/sta/FilterObjects.hh b/include/sta/FilterObjects.hh index 3de0dd84..71bea6c0 100644 --- a/include/sta/FilterObjects.hh +++ b/include/sta/FilterObjects.hh @@ -41,52 +41,52 @@ class Report; PortSeq filterPorts(std::string_view filter_expression, - PortSeq *objects, + PortSeq *ports, Sta *sta); InstanceSeq filterInstances(std::string_view filter_expression, - InstanceSeq *objects, + InstanceSeq *insts, Sta *sta); PinSeq filterPins(std::string_view filter_expression, - PinSeq *objects, + PinSeq *pins, Sta *sta); NetSeq filterNets(std::string_view filter_expression, - NetSeq *objects, + NetSeq *nets, Sta *sta); ClockSeq filterClocks(std::string_view filter_expression, - ClockSeq *objects, + ClockSeq *clks, Sta *sta); LibertyCellSeq filterLibCells(std::string_view filter_expression, - LibertyCellSeq *objects, + LibertyCellSeq *cells, Sta *sta); LibertyPortSeq filterLibPins(std::string_view filter_expression, - LibertyPortSeq *objects, + LibertyPortSeq *ports, Sta *sta); LibertyLibrarySeq filterLibertyLibraries(std::string_view filter_expression, - LibertyLibrarySeq *objects, + LibertyLibrarySeq *libs, Sta *sta); EdgeSeq filterTimingArcs(std::string_view filter_expression, - EdgeSeq *objects, + EdgeSeq *edges, Sta *sta); PathEndSeq filterPathEnds(std::string_view filter_expression, - PathEndSeq *objects, + PathEndSeq *ends, Sta *sta); // For FilterExpr unit tests. diff --git a/include/sta/FuncExpr.hh b/include/sta/FuncExpr.hh index 93db8d68..72f7bf96 100644 --- a/include/sta/FuncExpr.hh +++ b/include/sta/FuncExpr.hh @@ -26,8 +26,8 @@ #include -#include "NetworkClass.hh" #include "LibertyClass.hh" +#include "NetworkClass.hh" namespace sta { diff --git a/include/sta/Graph.hh b/include/sta/Graph.hh index 2d3024a7..233d363c 100644 --- a/include/sta/Graph.hh +++ b/include/sta/Graph.hh @@ -24,19 +24,19 @@ #pragma once -#include #include #include +#include -#include "Iterator.hh" -#include "ObjectTable.hh" -#include "LibertyClass.hh" -#include "NetworkClass.hh" #include "Delay.hh" #include "GraphClass.hh" -#include "VertexId.hh" +#include "Iterator.hh" +#include "LibertyClass.hh" +#include "NetworkClass.hh" +#include "ObjectTable.hh" #include "Path.hh" #include "StaState.hh" +#include "VertexId.hh" namespace sta { @@ -102,7 +102,7 @@ public: const Slew &slew); // Edge functions. - Edge *edge(EdgeId edge_index) const; + Edge *edge(EdgeId edge_id) const; EdgeId id(const Edge *edge) const; Edge *makeEdge(Vertex *from, Vertex *to, @@ -211,8 +211,8 @@ protected: void initArcDelays(Edge *edge); void removeDelayAnnotated(Edge *edge); - VertexTable *vertices_; - EdgeTable *edges_; + VertexTable *vertices_{nullptr}; + EdgeTable *edges_{nullptr}; // Bidirect pins are split into two vertices: // load/sink (top level output, instance pin input) vertex in pin_vertex_map // driver/source (top level input, instance pin output) vertex @@ -436,9 +436,9 @@ private: Network *network_; Instance *top_inst_; LeafInstanceIterator *inst_iter_; - InstancePinIterator *pin_iter_; - Vertex *vertex_; - Vertex *bidir_vertex_; + InstancePinIterator *pin_iter_{nullptr}; + Vertex *vertex_{nullptr}; + Vertex *bidir_vertex_{nullptr}; }; class VertexInEdgeIterator : public VertexEdgeIterator diff --git a/include/sta/GraphClass.hh b/include/sta/GraphClass.hh index bb030924..cdf7539b 100644 --- a/include/sta/GraphClass.hh +++ b/include/sta/GraphClass.hh @@ -25,13 +25,13 @@ #pragma once #include -#include #include +#include -#include "ObjectId.hh" -#include "MinMax.hh" -#include "Transition.hh" #include "Delay.hh" +#include "MinMax.hh" +#include "ObjectId.hh" +#include "Transition.hh" namespace sta { diff --git a/include/sta/GraphCmp.hh b/include/sta/GraphCmp.hh index add7530a..9c714d9c 100644 --- a/include/sta/GraphCmp.hh +++ b/include/sta/GraphCmp.hh @@ -24,9 +24,9 @@ #pragma once +#include "GraphClass.hh" #include "NetworkClass.hh" #include "NetworkCmp.hh" -#include "GraphClass.hh" namespace sta { diff --git a/include/sta/GraphDelayCalc.hh b/include/sta/GraphDelayCalc.hh index 5d2ae509..caf309b5 100644 --- a/include/sta/GraphDelayCalc.hh +++ b/include/sta/GraphDelayCalc.hh @@ -25,16 +25,16 @@ #pragma once #include -#include #include #include +#include -#include "NetworkClass.hh" -#include "GraphClass.hh" -#include "SearchClass.hh" -#include "SdcClass.hh" -#include "StaState.hh" #include "ArcDelayCalc.hh" +#include "GraphClass.hh" +#include "NetworkClass.hh" +#include "SdcClass.hh" +#include "SearchClass.hh" +#include "StaState.hh" namespace sta { @@ -104,7 +104,7 @@ public: float &pin_cap, float &wire_cap, float &fanout, - bool &has_set_load) const; + bool &has_net_load) const; void parasiticLoad(const Pin *drvr_pin, const RiseFall *rf, const Scene *scene, @@ -171,7 +171,7 @@ protected: Vertex *drvr_vertex, const RiseFall *rf, const LibertyPort *from_port, - float *from_slews, + const DriveCellSlews *from_slews, const LibertyPort *to_port, const Scene *scene, const MinMax *min_max, @@ -191,7 +191,7 @@ protected: ArcDelayCalc *arc_delay_calc, LoadPinIndexMap &load_pin_index_map); MultiDrvrNet *multiDrvrNet(const Vertex *drvr_vertex) const; - MultiDrvrNet *findMultiDrvrNet(Vertex *drvr_pin); + MultiDrvrNet *findMultiDrvrNet(Vertex *drvr_vertex); MultiDrvrNet *makeMultiDrvrNet(Vertex *drvr_vertex); bool hasMultiDrvrs(Vertex *drvr_vertex); Vertex *firstLoad(Vertex *drvr_vertex); @@ -235,7 +235,7 @@ protected: ArcDelayCalc *arc_delay_calc, bool propagate); DrvrLoadSlews loadSlews(LoadPinIndexMap &load_pin_index_map); - bool loadSlewsChanged(DrvrLoadSlews &prev_load_slews, + bool loadSlewsChanged(DrvrLoadSlews &load_slews_prev, LoadPinIndexMap &load_pin_index_map); void enqueueTimingChecksEdges(Vertex *vertex); bool annotateDelaysSlews(Edge *edge, @@ -294,10 +294,10 @@ protected: bool &has_net_load) const; // Observer for edge delay changes. - DelayCalcObserver *observer_; - bool delays_seeded_; - bool incremental_; - bool delays_exist_; + DelayCalcObserver *observer_{nullptr}; + bool delays_seeded_{false}; + bool incremental_{false}; + bool delays_exist_{false}; // Vertices with invalid -to delays. VertexSet invalid_delays_; // Timing check edges with invalid delays. @@ -313,7 +313,7 @@ protected: std::mutex multi_drvr_lock_; // Percentage (0.0:1.0) change in delay that causes downstream // delays to be recomputed during incremental delay calculation. - float incremental_delay_tolerance_; + float incremental_delay_tolerance_{0.0}; friend class FindVertexDelays; friend class MultiDrvrNet; @@ -334,7 +334,6 @@ public: class MultiDrvrNet { public: - MultiDrvrNet(); VertexSeq &drvrs() { return drvrs_; } const VertexSeq &drvrs() const { return drvrs_; } bool parallelGates(const Network *network) const; @@ -352,7 +351,7 @@ public: private: // Driver that triggers delay calculation for all the drivers on the net. - Vertex *dcalc_drvr_; + Vertex *dcalc_drvr_{nullptr}; VertexSeq drvrs_; // [drvr_rf->index][dcalc_ap->index] std::vector net_caps_; diff --git a/include/sta/Hash.hh b/include/sta/Hash.hh index ce68f03a..5cfd423d 100644 --- a/include/sta/Hash.hh +++ b/include/sta/Hash.hh @@ -24,8 +24,8 @@ #pragma once -#include #include +#include #include namespace sta { diff --git a/include/sta/InputDrive.hh b/include/sta/InputDrive.hh index a5dbdf2d..30bdd5f3 100644 --- a/include/sta/InputDrive.hh +++ b/include/sta/InputDrive.hh @@ -24,10 +24,11 @@ #pragma once -#include "MinMax.hh" #include "LibertyClass.hh" +#include "MinMax.hh" #include "NetworkClass.hh" #include "RiseFallMinMax.hh" +#include "SdcClass.hh" namespace sta { @@ -58,7 +59,7 @@ public: void setDriveCell(const LibertyLibrary *library, const LibertyCell *cell, const LibertyPort *from_port, - float *from_slews, + const DriveCellSlews &from_slews, const LibertyPort *to_port, const RiseFallBoth *rf, const MinMaxAll *min_max); @@ -67,7 +68,7 @@ public: // Return values. const LibertyCell *&cell, const LibertyPort *&from_port, - float *&from_slews, + const DriveCellSlews *&from_slews, const LibertyPort *&to_port) const; InputDriveCell *driveCell(const RiseFall *rf, const MinMax *min_max) const; @@ -94,7 +95,7 @@ public: InputDriveCell(const LibertyLibrary *library, const LibertyCell *cell, const LibertyPort *from_port, - float *from_slews, + const DriveCellSlews &from_slews, const LibertyPort *to_port); const LibertyLibrary *library() const { return library_; } void setLibrary(const LibertyLibrary *library); @@ -102,8 +103,8 @@ public: void setCell(const LibertyCell *cell); const LibertyPort *fromPort() const { return from_port_; } void setFromPort(const LibertyPort *from_port); - float *fromSlews() { return from_slews_; } - void setFromSlews(float *from_slews); + const DriveCellSlews &fromSlews() const { return from_slews_; } + void setFromSlews(const DriveCellSlews &from_slews); const LibertyPort *toPort() const { return to_port_; } void setToPort(const LibertyPort *to_port); bool equal(const InputDriveCell *drive) const; @@ -112,7 +113,7 @@ private: const LibertyLibrary *library_; const LibertyCell *cell_; const LibertyPort *from_port_; - float from_slews_[RiseFall::index_count]; + DriveCellSlews from_slews_; const LibertyPort *to_port_; }; diff --git a/include/sta/Liberty.hh b/include/sta/Liberty.hh index 20443127..5e5fef75 100644 --- a/include/sta/Liberty.hh +++ b/include/sta/Liberty.hh @@ -24,27 +24,27 @@ #pragma once -#include -#include #include #include -#include #include +#include +#include +#include #include #include #include -#include "ContainerHelpers.hh" -#include "MinMax.hh" -#include "RiseFallMinMax.hh" #include "ConcreteLibrary.hh" -#include "RiseFallValues.hh" -#include "MinMaxValues.hh" -#include "Transition.hh" +#include "ContainerHelpers.hh" #include "Delay.hh" #include "InternalPower.hh" #include "LeakagePower.hh" #include "LibertyClass.hh" +#include "MinMax.hh" +#include "MinMaxValues.hh" +#include "RiseFallMinMax.hh" +#include "RiseFallValues.hh" +#include "Transition.hh" namespace sta { diff --git a/include/sta/LibertyClass.hh b/include/sta/LibertyClass.hh index 17f547ad..4687cbbb 100644 --- a/include/sta/LibertyClass.hh +++ b/include/sta/LibertyClass.hh @@ -24,10 +24,10 @@ #pragma once -#include -#include #include +#include #include +#include namespace sta { diff --git a/include/sta/MinMax.hh b/include/sta/MinMax.hh index 5d5c8686..a23eda8e 100644 --- a/include/sta/MinMax.hh +++ b/include/sta/MinMax.hh @@ -25,8 +25,8 @@ #pragma once #include -#include #include +#include #include "Iterator.hh" diff --git a/include/sta/MinMaxValues.hh b/include/sta/MinMaxValues.hh index 6b2fcc9b..8fb8eeea 100644 --- a/include/sta/MinMaxValues.hh +++ b/include/sta/MinMaxValues.hh @@ -24,8 +24,8 @@ #pragma once -#include "MinMax.hh" #include "Error.hh" +#include "MinMax.hh" namespace sta { diff --git a/include/sta/Network.hh b/include/sta/Network.hh index 05eee68b..70580e90 100644 --- a/include/sta/Network.hh +++ b/include/sta/Network.hh @@ -29,11 +29,11 @@ #include #include -#include "StringUtil.hh" #include "LibertyClass.hh" -#include "VertexId.hh" #include "NetworkClass.hh" #include "StaState.hh" +#include "StringUtil.hh" +#include "VertexId.hh" namespace sta { @@ -93,7 +93,7 @@ using NetDrvrPinsMap = std::map; class Network : public StaState { public: - Network(); + Network() = default; ~Network() override; virtual void clear(); @@ -446,7 +446,7 @@ protected: void findInstancesMatching1(const Instance *context, size_t context_name_length, const PatternMatch *pattern, - InstanceSeq &insts) const; + InstanceSeq &matches) const; void findInstancesHierMatching1(const Instance *instance, const PatternMatch *pattern, InstanceSeq &matches) const; @@ -475,7 +475,7 @@ protected: const PatternMatch *pattern, // Return value. PinSeq &matches) const; - void findInstPinsHierMatching(const Instance *parent, + void findInstPinsHierMatching(const Instance *instance, const PatternMatch *pattern, // Return value. PinSeq &matches) const; @@ -490,9 +490,9 @@ protected: // nets may be connected across hierarchy levels. void clearNetDrvrPinMap(); - LibertyLibrary *default_liberty_; - char divider_; - char escape_; + LibertyLibrary *default_liberty_{nullptr}; + char divider_{'/'}; + char escape_{'\\'}; NetDrvrPinsMap net_drvr_pin_map_; }; @@ -500,7 +500,7 @@ protected: class NetworkEdit : public Network { public: - NetworkEdit(); + NetworkEdit() = default; bool isEditable() const override { return true; } virtual Instance *makeInstance(LibertyCell *cell, std::string_view name, @@ -619,7 +619,7 @@ private: PinSet &pins); const Network *network_; - PinSet constant_pins_[2]; + PinSet constant_pins_[2]{PinSet(network_), PinSet(network_)}; LogicValue value_; PinSet::iterator pin_iter_; }; diff --git a/include/sta/NetworkClass.hh b/include/sta/NetworkClass.hh index 0e72ff24..e32ce51a 100644 --- a/include/sta/NetworkClass.hh +++ b/include/sta/NetworkClass.hh @@ -25,11 +25,11 @@ #pragma once #include -#include -#include #include #include +#include #include +#include #include "Iterator.hh" diff --git a/include/sta/Parasitics.hh b/include/sta/Parasitics.hh index 7b4bfccf..c6706f90 100644 --- a/include/sta/Parasitics.hh +++ b/include/sta/Parasitics.hh @@ -28,11 +28,11 @@ #include #include -#include "StaState.hh" #include "LibertyClass.hh" #include "NetworkClass.hh" -#include "SdcClass.hh" #include "ParasiticsClass.hh" +#include "SdcClass.hh" +#include "StaState.hh" namespace sta { @@ -164,12 +164,12 @@ public: // Parasitic network component builders. virtual ParasiticNode *findParasiticNode(Parasitic *parasitic, const Net *net, - int id, + uint32_t id, const Network *network) const = 0; // Make a subnode of the parasitic network net. virtual ParasiticNode *ensureParasiticNode(Parasitic *parasitic, const Net *net, - int id, + uint32_t id, const Network *network) = 0; // Find the parasitic node connected to pin. virtual ParasiticNode *findParasiticNode(const Parasitic *parasitic, @@ -195,11 +195,11 @@ public: // Coupling capacitor between parasitic nodes on a net. virtual void makeCapacitor(Parasitic *parasitic, - size_t id, + uint32_t id, float cap, ParasiticNode *node1, ParasiticNode *node2) = 0; - virtual size_t id(const ParasiticCapacitor *capacitor) const = 0; + virtual uint32_t id(const ParasiticCapacitor *capacitor) const = 0; virtual float value(const ParasiticCapacitor *capacitor) const = 0; virtual ParasiticNode *node1(const ParasiticCapacitor *capacitor) const = 0; virtual ParasiticNode *node2(const ParasiticCapacitor *capacitor) const = 0; @@ -207,15 +207,15 @@ public: ParasiticNode *node) const; virtual void makeResistor(Parasitic *parasitic, - size_t id, + uint32_t id, float res, ParasiticNode *node1, ParasiticNode *node2) = 0; - virtual size_t id(const ParasiticResistor *resistor) const = 0; + virtual uint32_t id(const ParasiticResistor *resistor) const = 0; virtual float value(const ParasiticResistor *resistor) const = 0; virtual ParasiticNode *node1(const ParasiticResistor *resistor) const = 0; virtual ParasiticNode *node2(const ParasiticResistor *resistor) const = 0; - virtual ParasiticNode *otherNode(const ParasiticResistor *capacitor, + virtual ParasiticNode *otherNode(const ParasiticResistor *resistor, ParasiticNode *node) const; // Iteration over resistors connected to a nodes. @@ -287,7 +287,7 @@ protected: const Net *findParasiticNet(const Pin *pin) const; - float coupling_cap_factor_; + float coupling_cap_factor_ {1.0}; }; class ParasiticNodeLess diff --git a/include/sta/Path.hh b/include/sta/Path.hh index 81b37957..d04f9827 100644 --- a/include/sta/Path.hh +++ b/include/sta/Path.hh @@ -24,14 +24,14 @@ #pragma once +#include "Delay.hh" +#include "GraphClass.hh" #include "MinMax.hh" #include "NetworkClass.hh" #include "SdcClass.hh" -#include "Transition.hh" -#include "GraphClass.hh" -#include "Delay.hh" -#include "StaState.hh" #include "SearchClass.hh" +#include "StaState.hh" +#include "Transition.hh" namespace sta { diff --git a/include/sta/PathEnd.hh b/include/sta/PathEnd.hh index 2e252922..be54fa73 100644 --- a/include/sta/PathEnd.hh +++ b/include/sta/PathEnd.hh @@ -26,11 +26,11 @@ #include -#include "LibertyClass.hh" #include "GraphClass.hh" +#include "LibertyClass.hh" +#include "Path.hh" #include "SdcClass.hh" #include "SearchClass.hh" -#include "Path.hh" #include "StaState.hh" namespace sta { diff --git a/include/sta/PathExpanded.hh b/include/sta/PathExpanded.hh index b6c8ba2b..2a54e2a8 100644 --- a/include/sta/PathExpanded.hh +++ b/include/sta/PathExpanded.hh @@ -24,11 +24,11 @@ #pragma once -#include "TimingArc.hh" #include "GraphClass.hh" -#include "SearchClass.hh" #include "Path.hh" +#include "SearchClass.hh" #include "StaState.hh" +#include "TimingArc.hh" namespace sta { diff --git a/include/sta/PathGroup.hh b/include/sta/PathGroup.hh index 2d743fee..df180016 100644 --- a/include/sta/PathGroup.hh +++ b/include/sta/PathGroup.hh @@ -24,17 +24,17 @@ #pragma once +#include +#include #include #include #include -#include -#include -#include "SdcClass.hh" -#include "StaState.hh" -#include "SearchClass.hh" -#include "StringUtil.hh" #include "PathEnd.hh" +#include "SdcClass.hh" +#include "SearchClass.hh" +#include "StaState.hh" +#include "StringUtil.hh" namespace sta { diff --git a/include/sta/PortDelay.hh b/include/sta/PortDelay.hh index 3657cd4c..ab71151a 100644 --- a/include/sta/PortDelay.hh +++ b/include/sta/PortDelay.hh @@ -59,9 +59,9 @@ protected: const Pin *pin_; const ClockEdge *clk_edge_; - bool source_latency_included_; - bool network_latency_included_; - const Pin *ref_pin_; + bool source_latency_included_{false}; + bool network_latency_included_{false}; + const Pin *ref_pin_{nullptr}; RiseFallMinMax delays_; PinSet leaf_pins_; }; diff --git a/include/sta/PortExtCap.hh b/include/sta/PortExtCap.hh index d1c0d694..189ac33e 100644 --- a/include/sta/PortExtCap.hh +++ b/include/sta/PortExtCap.hh @@ -25,10 +25,10 @@ #pragma once #include "MinMax.hh" -#include "Transition.hh" -#include "RiseFallMinMax.hh" #include "MinMaxValues.hh" #include "NetworkClass.hh" +#include "RiseFallMinMax.hh" +#include "Transition.hh" namespace sta { @@ -38,7 +38,6 @@ using FanoutValues = MinMaxIntValues; class PortExtCap { public: - PortExtCap(); const Port *port() { return port_; } void pinCap(const RiseFall *rf, const MinMax *min_max, @@ -70,7 +69,7 @@ public: const FanoutValues *fanout() const { return &fanout_; } private: - const Port *port_; + const Port *port_{nullptr}; RiseFallMinMax pin_cap_; RiseFallMinMax wire_cap_; FanoutValues fanout_; diff --git a/include/sta/PowerClass.hh b/include/sta/PowerClass.hh index a3425631..0794fc4c 100644 --- a/include/sta/PowerClass.hh +++ b/include/sta/PowerClass.hh @@ -24,12 +24,13 @@ #pragma once -#include #include +#include namespace sta { class Power; +class Instance; enum class PwrActivityOrigin { diff --git a/include/sta/Property.hh b/include/sta/Property.hh index afb71765..e5834b61 100644 --- a/include/sta/Property.hh +++ b/include/sta/Property.hh @@ -24,16 +24,16 @@ #pragma once +#include #include #include #include -#include #include "LibertyClass.hh" #include "NetworkClass.hh" -#include "SearchClass.hh" -#include "SdcClass.hh" #include "PowerClass.hh" +#include "SdcClass.hh" +#include "SearchClass.hh" namespace sta { diff --git a/include/sta/Report.hh b/include/sta/Report.hh index 068a206a..c835a8ee 100644 --- a/include/sta/Report.hh +++ b/include/sta/Report.hh @@ -24,15 +24,15 @@ #pragma once -#include #include -#include -#include #include #include +#include +#include +#include -#include "Machine.hh" // __attribute__ #include "Format.hh" +#include "Machine.hh" // __attribute__ struct Tcl_Interp; diff --git a/include/sta/RiseFallMinMaxDelay.hh b/include/sta/RiseFallMinMaxDelay.hh index 0fd3975a..50c803aa 100644 --- a/include/sta/RiseFallMinMaxDelay.hh +++ b/include/sta/RiseFallMinMaxDelay.hh @@ -24,9 +24,9 @@ #pragma once +#include "Delay.hh" #include "MinMax.hh" #include "Transition.hh" -#include "Delay.hh" namespace sta { diff --git a/include/sta/Scene.hh b/include/sta/Scene.hh index a43a4cb4..4807136f 100644 --- a/include/sta/Scene.hh +++ b/include/sta/Scene.hh @@ -24,9 +24,9 @@ #pragma once +#include #include #include -#include #include "GraphClass.hh" #include "SearchClass.hh" diff --git a/include/sta/Sdc.hh b/include/sta/Sdc.hh index cea05abf..4d3f010d 100644 --- a/include/sta/Sdc.hh +++ b/include/sta/Sdc.hh @@ -24,25 +24,25 @@ #pragma once -#include #include -#include #include #include +#include +#include -#include "StringUtil.hh" -#include "MinMax.hh" -#include "StaState.hh" -#include "NetworkClass.hh" -#include "LibertyClass.hh" -#include "GraphClass.hh" -#include "SdcClass.hh" -#include "RiseFallValues.hh" #include "Clock.hh" -#include "DataCheck.hh" #include "CycleAccting.hh" +#include "DataCheck.hh" #include "ExceptionPath.hh" +#include "GraphClass.hh" +#include "LibertyClass.hh" +#include "MinMax.hh" +#include "NetworkClass.hh" #include "PinPair.hh" +#include "RiseFallValues.hh" +#include "SdcClass.hh" +#include "StaState.hh" +#include "StringUtil.hh" namespace sta { @@ -54,7 +54,7 @@ class DisabledPorts; class GraphLoop; class DeratingFactors; class DeratingFactorsGlobal; -class DeratingFactorsNet; +class DeratingFactors; class DeratingFactorsCell; class PatternMatch; class FindNetCaps; @@ -174,7 +174,7 @@ using InstancePvtMap = std::map; using PinMinPulseWidthMap = std::map; using ClockMinPulseWidthMap = std::map; using InstMinPulseWidthMap = std::map; -using NetDeratingFactorsMap = std::map; +using NetDeratingFactorsMap = std::map; using InstDeratingFactorsMap = std::map; using CellDeratingFactorsMap = std::map; using ClockGroupsSet = std::set; @@ -279,7 +279,7 @@ public: const LibertyCell *cell, const Port *port, const LibertyPort *from_port, - float *from_slews, + const DriveCellSlews &from_slews, const LibertyPort *to_port, const RiseFallBoth *rf, const MinMaxAll *min_max); diff --git a/include/sta/SdcClass.hh b/include/sta/SdcClass.hh index a22fee1e..62c24efe 100644 --- a/include/sta/SdcClass.hh +++ b/include/sta/SdcClass.hh @@ -29,9 +29,10 @@ #include #include "LibertyClass.hh" -#include "NetworkClass.hh" #include "MinMaxValues.hh" +#include "NetworkClass.hh" #include "PinPair.hh" +#include "Transition.hh" namespace sta { @@ -126,11 +127,13 @@ using ExceptionStateSet = std::set; // Constraint applies to clock or data paths. enum class PathClkOrData { clk, data }; -const int path_clk_or_data_count = 2; +const size_t path_clk_or_data_count = 2; enum class TimingDerateType { cell_delay, cell_check, net_delay }; -constexpr int timing_derate_type_count = 3; +constexpr size_t timing_derate_type_count = 3; enum class TimingDerateCellType { cell_delay, cell_check }; -constexpr int timing_derate_cell_type_count = 2; +constexpr size_t timing_derate_cell_type_count = 2; + +using DriveCellSlews = std::array; } // namespace sta diff --git a/include/sta/SdcNetwork.hh b/include/sta/SdcNetwork.hh index d23d18da..ea4c8304 100644 --- a/include/sta/SdcNetwork.hh +++ b/include/sta/SdcNetwork.hh @@ -217,15 +217,15 @@ public: InstanceSeq findInstancesMatching(const Instance *context, const PatternMatch *pattern) const override; Net *findNet(std::string_view path_name) const override; - Net *findNetRelative(const Instance *instance, - std::string_view net_name) const override; + Net *findNetRelative(const Instance *inst, + std::string_view path_name) const override; Net *findNet(const Instance *instance, std::string_view net_name) const override; NetSeq findNetsMatching(const Instance *parent, const PatternMatch *pattern) const override; void findInstNetsMatching(const Instance *instance, const PatternMatch *pattern, - NetSeq &nets) const override; + NetSeq &matches) const override; Instance *findChild(const Instance *parent, std::string_view name) const override; Pin *findPin(std::string_view path_name) const override; @@ -266,9 +266,9 @@ protected: std::string &path_tail) const; bool visitMatches(const Instance *parent, const PatternMatch *pattern, - std::function - visit_tail) const; + const std::function + &visit_tail) const; bool visitPinTail(const Instance *instance, const PatternMatch *tail, PinSeq &matches) const; diff --git a/include/sta/Search.hh b/include/sta/Search.hh index ec1fbdbc..47fb6247 100644 --- a/include/sta/Search.hh +++ b/include/sta/Search.hh @@ -24,23 +24,23 @@ #pragma once -#include #include +#include #include -#include "MinMax.hh" -#include "Transition.hh" -#include "LibertyClass.hh" -#include "NetworkClass.hh" -#include "GraphClass.hh" #include "Delay.hh" +#include "GraphClass.hh" +#include "LibertyClass.hh" +#include "MinMax.hh" +#include "NetworkClass.hh" +#include "Path.hh" #include "SdcClass.hh" -#include "StaState.hh" #include "SearchClass.hh" #include "SearchPred.hh" -#include "VertexVisitor.hh" -#include "Path.hh" +#include "StaState.hh" #include "StringUtil.hh" +#include "Transition.hh" +#include "VertexVisitor.hh" namespace sta { @@ -696,7 +696,6 @@ protected: // Class for visiting fanin/fanout paths of a vertex. // This used by forward/backward search to find arrival/required path times. -// NOLINTNEXTLINE(misc-multiple-inheritance) class PathVisitor : public VertexVisitor, public StaState { diff --git a/include/sta/SearchClass.hh b/include/sta/SearchClass.hh index 47f29563..9e3205b9 100644 --- a/include/sta/SearchClass.hh +++ b/include/sta/SearchClass.hh @@ -25,14 +25,14 @@ #pragma once #include -#include #include +#include -#include "VectorMap.hh" -#include "MinMaxValues.hh" #include "Delay.hh" -#include "NetworkClass.hh" #include "GraphClass.hh" +#include "MinMaxValues.hh" +#include "NetworkClass.hh" +#include "VectorMap.hh" namespace sta { diff --git a/include/sta/SearchPred.hh b/include/sta/SearchPred.hh index ab6b8dd3..9bcdf9b8 100644 --- a/include/sta/SearchPred.hh +++ b/include/sta/SearchPred.hh @@ -24,9 +24,9 @@ #pragma once -#include "NetworkClass.hh" #include "GraphClass.hh" #include "LibertyClass.hh" +#include "NetworkClass.hh" #include "StaState.hh" namespace sta { diff --git a/include/sta/Sta.hh b/include/sta/Sta.hh index 9da0e830..a8e80c55 100644 --- a/include/sta/Sta.hh +++ b/include/sta/Sta.hh @@ -24,27 +24,27 @@ #pragma once -#include +#include #include #include -#include +#include -#include "StringUtil.hh" -#include "LibertyClass.hh" -#include "NetworkClass.hh" -#include "SdcClass.hh" -#include "Scene.hh" -#include "GraphClass.hh" -#include "ParasiticsClass.hh" -#include "StaState.hh" -#include "VertexVisitor.hh" -#include "SearchClass.hh" -#include "PowerClass.hh" #include "ArcDelayCalc.hh" #include "CircuitSim.hh" -#include "Variables.hh" +#include "GraphClass.hh" +#include "LibertyClass.hh" +#include "NetworkClass.hh" +#include "ParasiticsClass.hh" +#include "PowerClass.hh" #include "Property.hh" #include "RiseFallMinMaxDelay.hh" +#include "Scene.hh" +#include "SdcClass.hh" +#include "SearchClass.hh" +#include "StaState.hh" +#include "StringUtil.hh" +#include "Variables.hh" +#include "VertexVisitor.hh" struct Tcl_Interp; @@ -267,7 +267,7 @@ public: const LibertyCell *cell, const Port *port, const LibertyPort *from_port, - float *from_slews, + const DriveCellSlews &from_slews, const LibertyPort *to_port, const RiseFallBoth *rf, const MinMaxAll *min_max, diff --git a/include/sta/StringUtil.hh b/include/sta/StringUtil.hh index 7d5fdbf0..35a8cda9 100644 --- a/include/sta/StringUtil.hh +++ b/include/sta/StringUtil.hh @@ -28,10 +28,10 @@ #include #include #include +#include #include #include #include -#include #include "Machine.hh" // __attribute__ diff --git a/include/sta/TableModel.hh b/include/sta/TableModel.hh index 46984d49..40855a75 100644 --- a/include/sta/TableModel.hh +++ b/include/sta/TableModel.hh @@ -30,10 +30,10 @@ #include #include -#include "MinMax.hh" -#include "Transition.hh" #include "LibertyClass.hh" +#include "MinMax.hh" #include "TimingModel.hh" +#include "Transition.hh" #include "Variables.hh" namespace sta { diff --git a/include/sta/TclTypeHelpers.hh b/include/sta/TclTypeHelpers.hh index 995b425f..628ee099 100644 --- a/include/sta/TclTypeHelpers.hh +++ b/include/sta/TclTypeHelpers.hh @@ -30,17 +30,17 @@ namespace sta { #if TCL_MAJOR_VERSION < 9 - typedef int Tcl_Size; + using Tcl_Size = int ; #endif StringSeq -tclListStringSeq(Tcl_Obj *const source, +tclListStringSeq(Tcl_Obj *source, Tcl_Interp *interp); StringSeq * -tclListStringSeqPtr(Tcl_Obj *const source, +tclListStringSeqPtr(Tcl_Obj *source, Tcl_Interp *interp); StringSet * -tclListStringSet(Tcl_Obj *const source, +tclListStringSet(Tcl_Obj *source, Tcl_Interp *interp); void diff --git a/include/sta/TimingArc.hh b/include/sta/TimingArc.hh index d9553830..4f9d5445 100644 --- a/include/sta/TimingArc.hh +++ b/include/sta/TimingArc.hh @@ -24,14 +24,14 @@ #pragma once +#include #include #include #include -#include -#include "Transition.hh" #include "Delay.hh" #include "LibertyClass.hh" +#include "Transition.hh" namespace sta { diff --git a/include/sta/Variables.hh b/include/sta/Variables.hh index a5bf2a1f..90c9fad2 100644 --- a/include/sta/Variables.hh +++ b/include/sta/Variables.hh @@ -34,7 +34,6 @@ enum class CrprMode { same_pin, same_transition }; class Variables { public: - Variables(); // TCL variable sta_crpr_enabled. bool crprEnabled() const { return crpr_enabled_; } void setCrprEnabled(bool enabled); @@ -78,23 +77,23 @@ public: PocvMode pocvMode() const { return pocv_mode_; } void setPocvMode(PocvMode mode); float pocvQuantile() const { return pocv_quantile_; } - void setPocvQuantile(float quartile); + void setPocvQuantile(float quantile); private: - bool crpr_enabled_; - CrprMode crpr_mode_; - bool propagate_gated_clock_enable_; - bool preset_clr_arcs_enabled_; - bool cond_default_arcs_enabled_; - bool bidirect_inst_paths_enabled_; - bool recovery_removal_checks_enabled_; - bool gated_clk_checks_enabled_; - bool clk_thru_tristate_enabled_; - bool dynamic_loop_breaking_; - bool propagate_all_clks_; - bool use_default_arrival_clock_; - PocvMode pocv_mode_; - float pocv_quantile_; + bool crpr_enabled_{true}; + CrprMode crpr_mode_{CrprMode::same_pin}; + bool propagate_gated_clock_enable_{true}; + bool preset_clr_arcs_enabled_{false}; + bool cond_default_arcs_enabled_{true}; + bool bidirect_inst_paths_enabled_{false}; + bool recovery_removal_checks_enabled_{true}; + bool gated_clk_checks_enabled_{true}; + bool clk_thru_tristate_enabled_{false}; + bool dynamic_loop_breaking_{false}; + bool propagate_all_clks_{false}; + bool use_default_arrival_clock_{false}; + PocvMode pocv_mode_{PocvMode::scalar}; + float pocv_quantile_{3.0}; }; } // namespace sta diff --git a/include/sta/VectorMap.hh b/include/sta/VectorMap.hh index 2273e3ab..5fa6990c 100644 --- a/include/sta/VectorMap.hh +++ b/include/sta/VectorMap.hh @@ -24,12 +24,12 @@ #pragma once -#include #include -#include #include #include #include +#include +#include namespace sta { diff --git a/include/sta/VerilogNamespace.hh b/include/sta/VerilogNamespace.hh index c004f629..441b6ba2 100644 --- a/include/sta/VerilogNamespace.hh +++ b/include/sta/VerilogNamespace.hh @@ -39,12 +39,12 @@ std::string portVerilogName(std::string_view sta_name); std::string -moduleVerilogToSta(std::string_view sta_name); +moduleVerilogToSta(std::string_view module_name); std::string -instanceVerilogToSta(std::string_view sta_name); +instanceVerilogToSta(std::string_view inst_name); std::string -netVerilogToSta(std::string_view sta_name); +netVerilogToSta(std::string_view net_name); std::string -portVerilogToSta(std::string_view sta_name); +portVerilogToSta(std::string_view port_name); } // namespace sta diff --git a/include/sta/VerilogReader.hh b/include/sta/VerilogReader.hh index 4a94269c..8d88e9e7 100644 --- a/include/sta/VerilogReader.hh +++ b/include/sta/VerilogReader.hh @@ -24,15 +24,15 @@ #pragma once +#include #include #include #include -#include #include "Format.hh" +#include "NetworkClass.hh" #include "Report.hh" #include "StringUtil.hh" -#include "NetworkClass.hh" namespace sta { @@ -104,12 +104,12 @@ public: ~VerilogReader(); bool read(std::string_view filename); - void makeModule(std::string_view module_name, + void makeModule(std::string_view module_vname, VerilogNetSeq *ports, VerilogStmtSeq *stmts, VerilogAttrStmtSeq *attr_stmts, int line); - void makeModule(std::string_view module_name, + void makeModule(std::string_view module_vname, VerilogStmtSeq *port_dcls, VerilogStmtSeq *stmts, VerilogAttrStmtSeq *attr_stmts, @@ -122,8 +122,8 @@ public: VerilogDclArg *arg, VerilogAttrStmtSeq *attr_stmts, int line); - VerilogDclArg *makeDclArg(std::string_view net_name); - VerilogDclArg*makeDclArg(VerilogAssign *assign); + VerilogDclArg *makeDclArg(std::string_view net_vname); + VerilogDclArg *makeDclArg(VerilogAssign *assign); VerilogDclBus *makeDclBus(PortDirection *dir, int from_index, int to_index, @@ -136,8 +136,8 @@ public: VerilogDclArgSeq *args, VerilogAttrStmtSeq *attr_stmts, int line); - VerilogInst *makeModuleInst(std::string_view module_name, - std::string_view inst_name, + VerilogInst *makeModuleInst(std::string_view module_vname, + std::string_view inst_vname, VerilogNetSeq *pins, VerilogAttrStmtSeq *attr_stmts, int line); @@ -146,17 +146,17 @@ public: int line); VerilogNetScalar *makeNetScalar(std::string_view name); VerilogNetPortRef *makeNetNamedPortRefScalarNet(std::string_view port_vname); - VerilogNetPortRef *makeNetNamedPortRefScalarNet(std::string_view port_name, - std::string_view net_name); - VerilogNetPortRef *makeNetNamedPortRefBitSelect(std::string_view port_name, - std::string_view bus_name, + VerilogNetPortRef *makeNetNamedPortRefScalarNet(std::string_view port_vname, + std::string_view net_vname); + VerilogNetPortRef *makeNetNamedPortRefBitSelect(std::string_view port_vname, + std::string_view bus_vname, int index); - VerilogNetPortRef *makeNetNamedPortRefScalar(std::string_view port_name, + VerilogNetPortRef *makeNetNamedPortRefScalar(std::string_view port_vname, VerilogNet *net); - VerilogNetPortRef *makeNetNamedPortRefBit(std::string_view port_name, + VerilogNetPortRef *makeNetNamedPortRefBit(std::string_view port_vname, int index, VerilogNet *net); - VerilogNetPortRef *makeNetNamedPortRefPart(std::string_view port_name, + VerilogNetPortRef *makeNetNamedPortRefPart(std::string_view port_vname, int from_index, int to_index, VerilogNet *net); @@ -306,8 +306,8 @@ protected: Debug *debug_; NetworkReader *network_; - Library *library_; - int black_box_index_; + Library *library_{nullptr}; + int black_box_index_{0}; VerilogModuleMap module_map_; VerilogErrorSeq link_errors_; const std::string zero_net_name_; diff --git a/include/sta/VertexVisitor.hh b/include/sta/VertexVisitor.hh index c7c8e981..e7aa7d36 100644 --- a/include/sta/VertexVisitor.hh +++ b/include/sta/VertexVisitor.hh @@ -24,8 +24,8 @@ #pragma once -#include "NetworkClass.hh" #include "GraphClass.hh" +#include "NetworkClass.hh" namespace sta { diff --git a/include/sta/VisitPathEnds.hh b/include/sta/VisitPathEnds.hh index ad52fbf7..8ac723f5 100644 --- a/include/sta/VisitPathEnds.hh +++ b/include/sta/VisitPathEnds.hh @@ -24,8 +24,8 @@ #pragma once -#include "SdcClass.hh" #include "GraphClass.hh" +#include "SdcClass.hh" #include "SearchClass.hh" #include "StaState.hh" diff --git a/network/ConcreteLibrary.cc b/network/ConcreteLibrary.cc index 3273cb69..77b335a1 100644 --- a/network/ConcreteLibrary.cc +++ b/network/ConcreteLibrary.cc @@ -28,11 +28,11 @@ #include #include +#include "ConcreteNetwork.hh" #include "ContainerHelpers.hh" +#include "ParseBus.hh" #include "PatternMatch.hh" #include "PortDirection.hh" -#include "ParseBus.hh" -#include "ConcreteNetwork.hh" namespace sta { @@ -44,9 +44,7 @@ ConcreteLibrary::ConcreteLibrary(std::string_view name, name_(name), id_(ConcreteNetwork::nextObjectId()), filename_(filename), - is_liberty_(is_liberty), - bus_brkt_left_('['), - bus_brkt_right_(']') + is_liberty_(is_liberty) { } @@ -125,9 +123,6 @@ ConcreteCell::ConcreteCell(std::string_view name, id_(ConcreteNetwork::nextObjectId()), filename_(filename), library_(library), - liberty_cell_(nullptr), - ext_cell_(nullptr), - port_bit_count_(0), is_leaf_(is_leaf) { } @@ -234,7 +229,7 @@ ConcreteCell::makeBusPortBit(ConcretePort *bus_port, } ConcretePort * -ConcreteCell::makePort(std::string bit_name, +ConcreteCell::makePort(std::string_view bit_name, int bit_index) { ConcretePort *port = new ConcretePort(bit_name, false, @@ -353,7 +348,7 @@ BusPort::addBusBit(ConcretePort *port, void ConcreteCell::groupBusPorts(char bus_brkt_left, char bus_brkt_right, - std::function port_msb_first) + const std::function &port_msb_first) { const char bus_brkts_left[2]{bus_brkt_left, '\0'}; const char bus_brkts_right[2]{bus_brkt_right, '\0'}; @@ -415,15 +410,11 @@ ConcretePort::ConcretePort(std::string_view name, id_(ConcreteNetwork::nextObjectId()), cell_(cell), direction_(PortDirection::unknown()), - liberty_port_(nullptr), - ext_port_(nullptr), - pin_index_(-1), is_bundle_(is_bundle), is_bus_(is_bus), from_index_(from_index), to_index_(to_index), - member_ports_(member_ports), - bundle_port_(nullptr) + member_ports_(member_ports) { } @@ -575,9 +566,7 @@ ConcretePort::memberIterator() const ConcreteCellPortBitIterator::ConcreteCellPortBitIterator(const ConcreteCell* cell) : ports_(cell->ports_), - port_iter_(ports_.begin()), - member_iter_(nullptr), - next_(nullptr) + port_iter_(ports_.begin()) { findNext(); } diff --git a/network/ConcreteNetwork.cc b/network/ConcreteNetwork.cc index dba9d286..df99ff9d 100644 --- a/network/ConcreteNetwork.cc +++ b/network/ConcreteNetwork.cc @@ -24,15 +24,16 @@ #include "ConcreteNetwork.hh" +#include #include #include -#include "PatternMatch.hh" -#include "Report.hh" -#include "Liberty.hh" -#include "PortDirection.hh" #include "ConcreteLibrary.hh" +#include "Liberty.hh" #include "Network.hh" +#include "PatternMatch.hh" +#include "PortDirection.hh" +#include "Report.hh" namespace sta { @@ -105,13 +106,12 @@ private: ConcreteInstanceNetMap *nets_; ConcreteInstanceNetMap::iterator iter_; - ConcreteNet *next_; + ConcreteNet *next_{nullptr}; }; ConcreteInstanceNetIterator:: ConcreteInstanceNetIterator(ConcreteInstanceNetMap *nets): - nets_(nets), - next_(nullptr) + nets_(nets) { if (nets) { iter_ = nets->begin(); @@ -161,7 +161,7 @@ private: const ConcretePinSeq &pins_; int pin_count_; - int pin_index_; + int pin_index_{0}; ConcretePin *next_; }; @@ -169,8 +169,7 @@ ConcreteInstancePinIterator:: ConcreteInstancePinIterator(const ConcreteInstance *inst, int pin_count) : pins_(inst->pins_), - pin_count_(pin_count), - pin_index_(0) + pin_count_(pin_count) { findNext(); } @@ -271,24 +270,31 @@ ObjectId ConcreteNetwork::object_id_ = 0; ConcreteNetwork::ConcreteNetwork() : NetworkReader(), - top_instance_(nullptr), - constant_nets_{NetSet(this), NetSet(this)}, link_func_(nullptr) { } ConcreteNetwork::~ConcreteNetwork() { - clear(); + // Cannot call virtual functions in destructor. + clearImpl(); +} + +void +ConcreteNetwork::clearImpl() +{ + if (top_instance_) + deleteInstanceImpl(top_instance_); + top_instance_ = nullptr; + deleteCellNetworkViewsImpl(); + deleteContents(library_seq_); + library_map_.clear(); } void ConcreteNetwork::clear() { - deleteTopInstance(); - deleteCellNetworkViews(); - deleteContents(library_seq_); - library_map_.clear(); + clearImpl(); Network::clear(); } @@ -303,6 +309,12 @@ ConcreteNetwork::deleteTopInstance() void ConcreteNetwork::deleteCellNetworkViews() +{ + deleteCellNetworkViewsImpl(); +} + +void +ConcreteNetwork::deleteCellNetworkViewsImpl() { for (auto [cell, view] : cell_network_view_map_) { if (view) @@ -361,7 +373,6 @@ class ConcreteLibertyLibraryIterator : public Iterator { public: ConcreteLibertyLibraryIterator(const ConcreteNetwork *network); - virtual ~ConcreteLibertyLibraryIterator(); bool hasNext() override; LibertyLibrary *next() override; @@ -370,22 +381,17 @@ private: const ConcreteLibrarySeq &libs_; ConcreteLibrarySeq::const_iterator iter_; - LibertyLibrary *next_; + LibertyLibrary *next_{nullptr}; }; ConcreteLibertyLibraryIterator:: ConcreteLibertyLibraryIterator(const ConcreteNetwork *network): libs_(network->library_seq_), - iter_(libs_.begin()), - next_(nullptr) + iter_(libs_.begin()) { findNext(); } -ConcreteLibertyLibraryIterator::~ConcreteLibertyLibraryIterator() -{ -} - bool ConcreteLibertyLibraryIterator::hasNext() { @@ -462,7 +468,7 @@ ConcreteNetwork::deleteLibrary(Library *library) { ConcreteLibrary *clib = reinterpret_cast(library); library_map_.erase(clib->name()); - library_seq_.erase(std::find(library_seq_.begin(), library_seq_.end(), clib)); + library_seq_.erase(std::ranges::find(library_seq_, clib)); delete clib; } @@ -721,7 +727,7 @@ class ConcreteCellPortIterator1 : public CellPortIterator { public: ConcreteCellPortIterator1(const ConcreteCell *cell); - ~ConcreteCellPortIterator1(); + ~ConcreteCellPortIterator1() override; bool hasNext() override { return iter_->hasNext(); } Port *next() override; @@ -758,7 +764,7 @@ class ConcreteCellPortBitIterator1 : public CellPortIterator { public: ConcreteCellPortBitIterator1(const ConcreteCell *cell); - ~ConcreteCellPortBitIterator1(); + ~ConcreteCellPortBitIterator1() override; bool hasNext() override { return iter_->hasNext(); } Port *next() override; @@ -905,19 +911,18 @@ class ConcretePortMemberIterator1 : public PortMemberIterator { public: ConcretePortMemberIterator1(const ConcretePort *port); - ~ConcretePortMemberIterator1(); + ~ConcretePortMemberIterator1() override; bool hasNext() override; Port *next() override; private: ConcretePortMemberIterator *iter_; - ConcretePort *next_; + ConcretePort *next_{nullptr}; }; ConcretePortMemberIterator1::ConcretePortMemberIterator1(const ConcretePort * port) : - iter_(port->memberIterator()), - next_(nullptr) + iter_(port->memberIterator()) { } @@ -1051,7 +1056,7 @@ ConcreteNetwork::findInstNetsMatching(const Instance *instance, { const ConcreteInstance *inst = reinterpret_cast(instance); - return inst->findNetsMatching(pattern, matches); + inst->findNetsMatching(pattern, matches); } //////////////////////////////////////////////////////////////// @@ -1191,13 +1196,13 @@ ConcreteNetwork::instance(const Net *net) const bool ConcreteNetwork::isPower(const Net *net) const { - return constant_nets_[int(LogicValue::one)].contains(const_cast(net)); + return constant_nets_[static_cast(LogicValue::one)].contains(const_cast(net)); } bool ConcreteNetwork::isGround(const Net *net) const { - return constant_nets_[int(LogicValue::zero)].contains(const_cast(net)); + return constant_nets_[static_cast(LogicValue::zero)].contains(const_cast(net)); } NetPinIterator * @@ -1308,6 +1313,12 @@ ConcreteNetwork::replaceCell(Instance *inst, void ConcreteNetwork::deleteInstance(Instance *inst) +{ + deleteInstanceImpl(inst); +} + +void +ConcreteNetwork::deleteInstanceImpl(Instance *inst) { ConcreteInstance *cinst = reinterpret_cast(inst); ConcreteInstanceNetMap *nets = cinst->nets_; @@ -1504,8 +1515,7 @@ ConcreteNetwork::deletePin(Pin *pin) ConcreteNet *cnet = cpin->net(); if (cnet) disconnectNetPin(cnet, cpin); - ConcreteInstance *cinst = - reinterpret_cast(cpin->instance()); + ConcreteInstance *cinst = cpin->instance(); if (cinst) cinst->deletePin(cpin); delete cpin; @@ -1533,16 +1543,15 @@ ConcreteNetwork::deleteNet(Net *net) pin->net_ = nullptr; } - constant_nets_[int(LogicValue::zero)].erase(net); - constant_nets_[int(LogicValue::one)].erase(net); + constant_nets_[static_cast(LogicValue::zero)].erase(net); + constant_nets_[static_cast(LogicValue::one)].erase(net); PinSet *drvrs = findKey(net_drvr_pin_map_, net); if (drvrs) { delete drvrs; net_drvr_pin_map_.erase(net); } - ConcreteInstance *cinst = - reinterpret_cast(cnet->instance()); + ConcreteInstance *cinst = cnet->instance(); cinst->deleteNet(cnet); delete cnet; } @@ -1550,8 +1559,8 @@ ConcreteNetwork::deleteNet(Net *net) void ConcreteNetwork::clearConstantNets() { - constant_nets_[int(LogicValue::zero)].clear(); - constant_nets_[int(LogicValue::one)].clear(); + constant_nets_[static_cast(LogicValue::zero)].clear(); + constant_nets_[static_cast(LogicValue::one)].clear(); } void @@ -1560,15 +1569,15 @@ ConcreteNetwork::addConstantNet(Net *net, { if (value == LogicValue::zero || value == LogicValue::one) - constant_nets_[int(value)].insert(net); + constant_nets_[static_cast(value)].insert(net); } ConstantPinIterator * ConcreteNetwork::constantPinIterator() { return new NetworkConstantPinIterator(this, - constant_nets_[int(LogicValue::zero)], - constant_nets_[int(LogicValue::one)]); + constant_nets_[static_cast(LogicValue::zero)], + constant_nets_[static_cast(LogicValue::one)]); } //////////////////////////////////////////////////////////////// @@ -1617,9 +1626,7 @@ ConcreteInstance::ConcreteInstance(std::string_view name, name_(name), id_(ConcreteNetwork::nextObjectId()), cell_(cell), - parent_(parent), - children_(nullptr), - nets_(nullptr) + parent_(parent) { initPins(); } @@ -1738,13 +1745,13 @@ ConcreteInstance::addChild(ConcreteInstance *child) { if (children_ == nullptr) children_ = new ConcreteInstanceChildMap; - (*children_)[child->name().data()] = child; + (*children_)[child->name()] = child; } void ConcreteInstance::deleteChild(ConcreteInstance *child) { - children_->erase(child->name().data()); + children_->erase(child->name()); } void @@ -1769,7 +1776,7 @@ ConcreteInstance::addNet(ConcreteNet *net) { if (nets_ == nullptr) nets_ = new ConcreteInstanceNetMap; - (*nets_)[net->name().data()] = net; + (*nets_)[net->name()] = net; } void @@ -1778,13 +1785,13 @@ ConcreteInstance::addNet(std::string_view, { if (nets_ == nullptr) nets_ = new ConcreteInstanceNetMap; - (*nets_)[net->name().data()] = net; + (*nets_)[net->name()] = net; } void ConcreteInstance::deleteNet(ConcreteNet *net) { - nets_->erase(net->name().data()); + nets_->erase(net->name()); } void @@ -1801,15 +1808,11 @@ ConcretePin::ConcretePin(ConcreteInstance *instance, instance_(instance), port_(port), net_(net), - term_(nullptr), - id_(ConcreteNetwork::nextObjectId()), - net_next_(nullptr), - net_prev_(nullptr), - vertex_id_(vertex_id_null) + id_(ConcreteNetwork::nextObjectId()) { } -std::string_view +const std::string& ConcretePin::name() const { return port_->name(); @@ -1823,12 +1826,11 @@ ConcretePin::setVertexId(VertexId id) //////////////////////////////////////////////////////////////// -std::string_view +const std::string & ConcreteTerm::name() const { ConcretePin *cpin = reinterpret_cast(pin_); - const ConcretePort *cport = - reinterpret_cast(cpin->port()); + const ConcretePort *cport = cpin->port(); return cport->name(); } @@ -1836,8 +1838,7 @@ ConcreteTerm::ConcreteTerm(ConcretePin *pin, ConcreteNet *net) : pin_(pin), net_(net), - id_(ConcreteNetwork::nextObjectId()), - net_next_(nullptr) + id_(ConcreteNetwork::nextObjectId()) { } @@ -1847,10 +1848,7 @@ ConcreteNet::ConcreteNet(std::string_view name, ConcreteInstance *instance) : name_(name), id_(ConcreteNetwork::nextObjectId()), - instance_(instance), - pins_(nullptr), - terms_(nullptr), - merged_into_(nullptr) + instance_(instance) { } diff --git a/network/HpinDrvrLoad.cc b/network/HpinDrvrLoad.cc index 032b0ff3..8aaf57b4 100644 --- a/network/HpinDrvrLoad.cc +++ b/network/HpinDrvrLoad.cc @@ -32,7 +32,7 @@ namespace sta { -typedef std::set HpinDrvrLoads; +using HpinDrvrLoads = std::set; static void visitPinsAboveNet2(const Pin *hpin, @@ -52,8 +52,8 @@ visitPinsBelowNet2(const Pin *hpin, PinSet *hpin_path, const Network *network); static void -visitHpinDrvrLoads(HpinDrvrLoads drvrs, - HpinDrvrLoads loads, +visitHpinDrvrLoads(HpinDrvrLoads &drvrs, + HpinDrvrLoads &loads, HpinDrvrLoadVisitor *visitor); void @@ -249,8 +249,8 @@ visitPinsBelowNet2(const Pin *hpin, } static void -visitHpinDrvrLoads(HpinDrvrLoads drvrs, - HpinDrvrLoads loads, +visitHpinDrvrLoads(HpinDrvrLoads &drvrs, + HpinDrvrLoads &loads, HpinDrvrLoadVisitor *visitor) { for (HpinDrvrLoad *drvr : drvrs) { diff --git a/network/Network.cc b/network/Network.cc index 0252c801..d096d842 100644 --- a/network/Network.cc +++ b/network/Network.cc @@ -29,22 +29,15 @@ #include #include "ContainerHelpers.hh" -#include "StringUtil.hh" -#include "PatternMatch.hh" #include "Liberty.hh" +#include "ParseBus.hh" +#include "PatternMatch.hh" #include "PortDirection.hh" #include "Scene.hh" -#include "ParseBus.hh" +#include "StringUtil.hh" namespace sta { -Network::Network() : - default_liberty_(nullptr), - divider_('/'), - escape_('\\') -{ -} - Network::~Network() { deleteContents(net_drvr_pin_map_); @@ -264,7 +257,7 @@ Network::pathName(const Instance *instance) const InstanceSeq inst_path; path(instance, inst_path); std::string path_name; - while (inst_path.size()) { + while (!inst_path.empty()) { const Instance *inst = inst_path.back(); path_name += name(inst); inst_path.pop_back(); @@ -1184,7 +1177,7 @@ Network::setPathEscape(char escape) //////////////////////////////////////////////////////////////// -typedef std::vector InstanceChildIteratorSeq; +using InstanceChildIteratorSeq = std::vector; class LeafInstanceIterator1 : public LeafInstanceIterator { @@ -1200,15 +1193,14 @@ private: const Network *network_; InstanceChildIteratorSeq pending_child_iters_; InstanceChildIterator *child_iter_; - Instance *next_; + Instance *next_{nullptr}; }; LeafInstanceIterator1::LeafInstanceIterator1(const Instance *inst, const Network *network) : network_(network), - child_iter_(network->childIterator(inst)), - next_(nullptr) + child_iter_(network->childIterator(inst)) { pending_child_iters_.reserve(8); nextInst(); @@ -1632,7 +1624,6 @@ Network::pathNameLast(std::string_view path_name, char divider = pathDivider(); size_t div_pos = path_name.rfind(divider); - size_t path_end = path_name.size(); while (div_pos > 0) { if (div_pos == std::string_view::npos) return; @@ -1642,27 +1633,18 @@ Network::pathNameLast(std::string_view path_name, last = path_name.substr(div_pos + 1); return; } - path_end = div_pos - 1; - div_pos = path_name.rfind(divider, path_end); + div_pos = path_name.rfind(divider, div_pos - 1); } } //////////////////////////////////////////////////////////////// -NetworkEdit::NetworkEdit() : - Network() -{ -} - -//////////////////////////////////////////////////////////////// - NetworkConstantPinIterator:: NetworkConstantPinIterator(const Network *network, NetSet &zero_nets, NetSet &one_nets) : ConstantPinIterator(), - network_(network), - constant_pins_{PinSet(network), PinSet(network)} + network_(network) { findConstantPins(zero_nets, constant_pins_[0]); findConstantPins(one_nets, constant_pins_[1]); @@ -1687,7 +1669,7 @@ NetworkConstantPinIterator::findConstantPins(NetSet &nets, bool NetworkConstantPinIterator::hasNext() { - if (pin_iter_ != constant_pins_[(int)value_].end()) + if (pin_iter_ != constant_pins_[static_cast(value_)].end()) return true; else if (value_ == LogicValue::zero) { value_ = LogicValue::one; @@ -1818,8 +1800,8 @@ visitPinsBelowNet1(const Pin *hpin, } static void -visitDrvrLoads(PinSet drvrs, - PinSet loads, +visitDrvrLoads(PinSet &drvrs, + PinSet &loads, HierPinThruVisitor *visitor) { for (const Pin *drvr : drvrs) { @@ -1921,8 +1903,8 @@ visitDrvrLoadsThruNet(const Net *net, char logicValueString(LogicValue value) { - static char str[] = "01X^v"; - return str[int(value)]; + static char names[] = "01X^v"; + return names[static_cast(value)]; } //////////////////////////////////////////////////////////////// diff --git a/network/Network.i b/network/Network.i index 6af7c8a3..f36a91a0 100644 --- a/network/Network.i +++ b/network/Network.i @@ -28,8 +28,10 @@ %{ #include "Network.hh" -#include "StringUtil.hh" + #include + +#include "StringUtil.hh" %} //////////////////////////////////////////////////////////////// diff --git a/network/NetworkCmp.cc b/network/NetworkCmp.cc index 2d75bb01..2d0db2db 100644 --- a/network/NetworkCmp.cc +++ b/network/NetworkCmp.cc @@ -26,9 +26,9 @@ #include -#include "StringUtil.hh" #include "Liberty.hh" #include "Network.hh" +#include "StringUtil.hh" namespace sta { diff --git a/network/ParseBus.cc b/network/ParseBus.cc index 16300d69..8205dead 100644 --- a/network/ParseBus.cc +++ b/network/ParseBus.cc @@ -88,7 +88,7 @@ parseBusName(std::string_view name, size_t left = name.rfind(brkt_left_ch); if (left != std::string_view::npos) { is_bus = true; - bus_name.append(name.data(), left); + bus_name.append(name.substr(0, left)); // Simple bus subscript. index = std::stoi(std::string(name.substr(left + 1))); } @@ -142,7 +142,7 @@ parseBusName(std::string_view name, size_t left = name.rfind(brkt_left_ch); if (left != std::string_view::npos) { is_bus = true; - bus_name.append(name.data(), left); + bus_name.append(name.substr(0, left)); // Check for bus range. size_t range = name.find(':', left); if (range != std::string_view::npos) { diff --git a/network/SdcNetwork.cc b/network/SdcNetwork.cc index 50f95fc0..0542f95a 100644 --- a/network/SdcNetwork.cc +++ b/network/SdcNetwork.cc @@ -24,14 +24,13 @@ #include "SdcNetwork.hh" -#include "StringUtil.hh" -#include "PatternMatch.hh" #include "ParseBus.hh" +#include "PatternMatch.hh" +#include "StringUtil.hh" namespace sta { NetworkNameAdapter::NetworkNameAdapter(Network *network) : - NetworkEdit(), network_(network), network_edit_(dynamic_cast(network)) { @@ -822,9 +821,8 @@ SdcNetwork::findInstancesMatching1(const Instance *context, InstanceSeq &matches) const { visitMatches(context, pattern, - [&](const Instance *instance, - const PatternMatch *tail) - { + [&] (const Instance *instance, + const PatternMatch *tail) { size_t match_count = matches.size(); network_->findChildrenMatching(instance, tail, matches); return matches.size() != match_count; @@ -1193,7 +1191,7 @@ SdcNetwork::visitMatches(const Instance *parent, const PatternMatch *pattern, const std::function - visit_tail) const + &visit_tail) const { int divider_count, path_length; scanPath(pattern->pattern(), divider_count, path_length); diff --git a/network/VerilogNamespace.cc b/network/VerilogNamespace.cc index e0094688..ed63cd3e 100644 --- a/network/VerilogNamespace.cc +++ b/network/VerilogNamespace.cc @@ -26,8 +26,8 @@ #include -#include "StringUtil.hh" #include "ParseBus.hh" +#include "StringUtil.hh" namespace sta { @@ -38,7 +38,7 @@ staToVerilog(std::string_view sta_name); static std::string staToVerilog2(std::string_view sta_name); static std::string -verilogToSta(const std::string_view verilog_name); +verilogToSta(std::string_view verilog_name); std::string cellVerilogName(std::string_view sta_name) diff --git a/parasitics/ConcreteParasitics.cc b/parasitics/ConcreteParasitics.cc index 27d74bf6..e015d5e2 100644 --- a/parasitics/ConcreteParasitics.cc +++ b/parasitics/ConcreteParasitics.cc @@ -26,18 +26,18 @@ #include // max -#include "Report.hh" +#include "ConcreteParasiticsPvt.hh" #include "Debug.hh" #include "Error.hh" -#include "Mutex.hh" -#include "MinMax.hh" -#include "Network.hh" -#include "Wireload.hh" #include "Liberty.hh" -#include "Sdc.hh" +#include "MinMax.hh" +#include "Mutex.hh" +#include "Network.hh" #include "Parasitics.hh" -#include "ConcreteParasiticsPvt.hh" +#include "Report.hh" #include "Scene.hh" +#include "Sdc.hh" +#include "Wireload.hh" // Multiple inheritance is used to share elmore and pi model base // classes, but care is taken to make sure there are no loops in the @@ -45,10 +45,6 @@ namespace sta { -ConcreteParasitic::~ConcreteParasitic() -{ -} - bool ConcreteParasitic::isPiElmore() const { @@ -138,8 +134,7 @@ ConcretePi::ConcretePi(float c2, float c1) : c2_(c2), rpi_(rpi), - c1_(c1), - is_reduced_(false) + c1_(c1) { } @@ -257,12 +252,6 @@ ConcretePiElmore::unannotatedLoads(const Pin *drvr_pin, //////////////////////////////////////////////////////////////// -ConcretePoleResidue::ConcretePoleResidue() : - poles_(nullptr), - residues_(nullptr) -{ -} - ConcretePoleResidue::~ConcretePoleResidue() { delete poles_; @@ -380,7 +369,7 @@ ConcretePiPoleResidue::unannotatedLoads(const Pin *drvr_pin, //////////////////////////////////////////////////////////////// ConcreteParasiticNode::ConcreteParasiticNode(const Net *net, - int id, + uint32_t id, bool is_external) : is_net_(true), is_external_(is_external), @@ -449,7 +438,7 @@ ConcreteParasiticNode::net(const Network *network) const //////////////////////////////////////////////////////////////// -ConcreteParasiticDevice::ConcreteParasiticDevice(size_t id, +ConcreteParasiticDevice::ConcreteParasiticDevice(uint32_t id, float value, ConcreteParasiticNode *node1, ConcreteParasiticNode *node2) : @@ -470,7 +459,7 @@ ConcreteParasiticDevice::replaceNode(ConcreteParasiticNode *from_node, node2_ = to_node; } -ConcreteParasiticResistor::ConcreteParasiticResistor(size_t id, +ConcreteParasiticResistor::ConcreteParasiticResistor(uint32_t id, float value, ConcreteParasiticNode *node1, ConcreteParasiticNode *node2) : @@ -478,7 +467,7 @@ ConcreteParasiticResistor::ConcreteParasiticResistor(size_t id, { } -ConcreteParasiticCapacitor::ConcreteParasiticCapacitor(size_t id, +ConcreteParasiticCapacitor::ConcreteParasiticCapacitor(uint32_t id, float value, ConcreteParasiticNode *node1, ConcreteParasiticNode *node2) : @@ -494,15 +483,15 @@ ConcreteParasiticNetwork::ConcreteParasiticNetwork(const Net *net, net_(net), sub_nodes_(network), pin_nodes_(network), - max_node_id_(0), includes_pin_caps_(includes_pin_caps) { } -ConcreteParasiticNetwork::ConcreteParasiticNetwork(ConcreteParasiticNetwork &¶sitic): +ConcreteParasiticNetwork::ConcreteParasiticNetwork(ConcreteParasiticNetwork &¶sitic) + noexcept : net_(parasitic.net_), - sub_nodes_(parasitic.sub_nodes_), - pin_nodes_(parasitic.pin_nodes_), + sub_nodes_(std::move(parasitic.sub_nodes_)), + pin_nodes_(std::move(parasitic.pin_nodes_)), max_node_id_(parasitic.max_node_id_), includes_pin_caps_(parasitic.includes_pin_caps_) { @@ -586,7 +575,7 @@ ConcreteParasiticNetwork::capacitance() const ConcreteParasiticNode * ConcreteParasiticNetwork::findParasiticNode(const Net *net, - int id, + uint32_t id, const Network *) const { NetIdPair net_id(net, id); @@ -609,7 +598,7 @@ ConcreteParasiticNetwork::findParasiticNode(const Pin *pin) const ConcreteParasiticNode * ConcreteParasiticNetwork::ensureParasiticNode(const Net *net, - int id, + uint32_t id, const Network *network) { ConcreteParasiticNode *node; @@ -620,7 +609,7 @@ ConcreteParasiticNetwork::ensureParasiticNode(const Net *net, node = new ConcreteParasiticNode(net, id, network->highestNetAbove(net1) != net_); sub_nodes_[net_id] = node; if (net == net_) - max_node_id_ = std::max((int) max_node_id_, id); + max_node_id_ = std::max(max_node_id_, id); } else node = id_node->second; @@ -763,7 +752,7 @@ ConcreteParasitics::ConcreteParasitics(std::string_view name, ConcreteParasitics::~ConcreteParasitics() { - deleteParasitics(); + deleteParasiticsImpl(); } bool @@ -781,6 +770,12 @@ ConcreteParasitics::clear() void ConcreteParasitics::deleteParasitics() +{ + deleteParasiticsImpl(); +} + +void +ConcreteParasitics::deleteParasiticsImpl() { for (auto &[drvr, parasitics] : drvr_parasitic_map_) { for (size_t i = 0; i < min_max_rise_fall_count; i++) @@ -1209,7 +1204,7 @@ ConcreteParasitics::includesPinCaps(const Parasitic *parasitic) const ParasiticNode * ConcreteParasitics::findParasiticNode(Parasitic *parasitic, const Net *net, - int id, + uint32_t id, const Network *network) const { const ConcreteParasiticNetwork *cparasitic = @@ -1220,7 +1215,7 @@ ConcreteParasitics::findParasiticNode(Parasitic *parasitic, ParasiticNode * ConcreteParasitics::ensureParasiticNode(Parasitic *parasitic, const Net *net, - int id, + uint32_t id, const Network *network) { ConcreteParasiticNetwork *cparasitic = @@ -1257,7 +1252,7 @@ ConcreteParasitics::incrCap(ParasiticNode *node, void ConcreteParasitics::makeCapacitor(Parasitic *parasitic, - size_t index, + uint32_t id, float cap, ParasiticNode *node1, ParasiticNode *node2) @@ -1265,7 +1260,7 @@ ConcreteParasitics::makeCapacitor(Parasitic *parasitic, ConcreteParasiticNode *cnode1 = static_cast(node1); ConcreteParasiticNode *cnode2 = static_cast(node2); ConcreteParasiticCapacitor *capacitor = - new ConcreteParasiticCapacitor(index, cap, cnode1, cnode2); + new ConcreteParasiticCapacitor(id, cap, cnode1, cnode2); ConcreteParasiticNetwork *cparasitic = static_cast(parasitic); cparasitic->addCapacitor(capacitor); @@ -1273,14 +1268,14 @@ ConcreteParasitics::makeCapacitor(Parasitic *parasitic, void ConcreteParasitics::makeResistor(Parasitic *parasitic, - size_t index, + uint32_t id, float res, ParasiticNode *node1, ParasiticNode *node2) { ConcreteParasiticNode *cnode1 = static_cast(node1); ConcreteParasiticNode *cnode2 = static_cast(node2); - ParasiticResistor *resistor = new ConcreteParasiticResistor(index, res, + ParasiticResistor *resistor = new ConcreteParasiticResistor(id, res, cnode1, cnode2); ConcreteParasiticNetwork *cparasitic = static_cast(parasitic); @@ -1363,7 +1358,7 @@ ConcreteParasitics::isExternal(const ParasiticNode *node) const //////////////////////////////////////////////////////////////// -size_t +uint32_t ConcreteParasitics::id(const ParasiticResistor *resistor) const { const ConcreteParasiticResistor *cresistor = @@ -1397,7 +1392,7 @@ ConcreteParasitics::node2(const ParasiticResistor *resistor) const //////////////////////////////////////////////////////////////// -size_t +uint32_t ConcreteParasitics::id(const ParasiticCapacitor *capacitor) const { const ConcreteParasiticCapacitor *ccapacitor = diff --git a/parasitics/ConcreteParasitics.hh b/parasitics/ConcreteParasitics.hh index e866e8e7..936609c1 100644 --- a/parasitics/ConcreteParasitics.hh +++ b/parasitics/ConcreteParasitics.hh @@ -50,10 +50,10 @@ using ConcreteParasiticNetworkMap = std::map + #include "Liberty.hh" -#include "PortDirection.hh" #include "Network.hh" -#include "Sdc.hh" #include "Parasitics.hh" +#include "PortDirection.hh" +#include "Sdc.hh" +#include "Wireload.hh" namespace sta { @@ -205,8 +207,7 @@ EstimateParasitics::estimatePiElmoreBalanced(const Pin *drvr_pin, else { c1 = static_cast(y2 * y2 / y3); c2 = static_cast(y1 - y2 * y2 / y3); - if (c2 < 0.0) - c2 = 0.0; + c2 = std::max(c2, 0.0f); rpi = static_cast(-y3 * y3 / (y2 * y2 * y2)); } elmore_res = static_cast(res_fanout); @@ -215,28 +216,4 @@ EstimateParasitics::estimatePiElmoreBalanced(const Pin *drvr_pin, } } -#if 0 -static void -selectWireload(Network *network) -{ - // Look for a default wireload selection group. - WireloadSelection *selection; - float area = instanceArea(network->topInstance(), network); - Wireload *wireload = selection->findWireload(area); -} - -static float -instanceArea(Instance *inst, - Network *network) -{ - float area = 0.0; - LeafInstanceIterator *inst_iter = network->leafInstanceIterator(); - while (network->hasNext(inst_iter)) { - Instance *leaf = network->next(inst_iter); - area += network->cell(leaf)->area(); - } - return area; -} -#endif - } // namespace sta diff --git a/parasitics/EstimateParasitics.hh b/parasitics/EstimateParasitics.hh index 97e6fa62..f762198f 100644 --- a/parasitics/EstimateParasitics.hh +++ b/parasitics/EstimateParasitics.hh @@ -24,11 +24,11 @@ #pragma once -#include "StaState.hh" #include "LibertyClass.hh" #include "NetworkClass.hh" -#include "SdcClass.hh" #include "ParasiticsClass.hh" +#include "SdcClass.hh" +#include "StaState.hh" namespace sta { @@ -57,8 +57,8 @@ public: protected: void estimatePiElmoreBest(const Pin *drvr_pin, - float net_pin_cap, float wireload_cap, + float net_pin_cap, const RiseFall *rf, const Scene *scene, const MinMax *min_max, diff --git a/parasitics/Parasitics.cc b/parasitics/Parasitics.cc index 69187f95..086ad9b4 100644 --- a/parasitics/Parasitics.cc +++ b/parasitics/Parasitics.cc @@ -24,23 +24,22 @@ #include "Parasitics.hh" -#include "Error.hh" #include "Debug.hh" -#include "Units.hh" +#include "Error.hh" +#include "EstimateParasitics.hh" #include "Liberty.hh" -#include "Wireload.hh" #include "Network.hh" #include "PortDirection.hh" -#include "Sdc.hh" -#include "Scene.hh" #include "ReduceParasitics.hh" -#include "EstimateParasitics.hh" +#include "Scene.hh" +#include "Sdc.hh" +#include "Units.hh" +#include "Wireload.hh" namespace sta { Parasitics::Parasitics(StaState *sta) : - StaState(sta), - coupling_cap_factor_(1.0) + StaState(sta) { } diff --git a/parasitics/ReduceParasitics.cc b/parasitics/ReduceParasitics.cc index 0f56860f..231cdeba 100644 --- a/parasitics/ReduceParasitics.cc +++ b/parasitics/ReduceParasitics.cc @@ -28,21 +28,21 @@ #include #include -#include "Error.hh" #include "Debug.hh" -#include "MinMax.hh" +#include "Error.hh" #include "Liberty.hh" +#include "MinMax.hh" #include "Network.hh" -#include "Sdc.hh" -#include "Scene.hh" #include "Parasitics.hh" +#include "Scene.hh" +#include "Sdc.hh" namespace sta { -typedef std::map ParasiticNodeValueMap; -typedef std::map ResistorCurrentMap; -typedef std::set ParasiticResistorSet; -typedef std::set ParasiticNodeSet; +using ParasiticNodeValueMap = std::map; +using ResistorCurrentMap = std::map; +using ParasiticResistorSet = std::set; +using ParasiticNodeSet = std::set; class ReduceToPi : public StaState { @@ -82,26 +82,21 @@ protected: Parasitics *parasitics_; bool includes_pin_caps_; - float coupling_cap_multiplier_; - const RiseFall *rf_; - const Scene *scene_; - const MinMax *min_max_; + float coupling_cap_multiplier_ {1.0}; + const RiseFall *rf_ {nullptr}; + const Scene *scene_ {nullptr}; + const MinMax *min_max_ {nullptr}; ParasiticNodeResistorMap resistor_map_; ParasiticNodeCapacitorMap capacitor_map_; ParasiticNodeSet visited_nodes_; ParasiticNodeValueMap node_values_; ParasiticResistorSet loop_resistors_; - bool pin_caps_one_value_; + bool pin_caps_one_value_ {true}; }; ReduceToPi::ReduceToPi(StaState *sta) : - StaState(sta), - coupling_cap_multiplier_(1.0), - rf_(nullptr), - scene_(nullptr), - min_max_(nullptr), - pin_caps_one_value_(true) + StaState(sta) { } @@ -340,7 +335,7 @@ ReduceToPiElmore::makePiElmore(const Parasitic *parasitic_network, Parasitic *pi_elmore = parasitics_->makePiElmore(drvr_pin, rf, min_max, c2, rpi, c1); parasitics_->setIsReducedParasiticNetwork(pi_elmore, true); - reduceElmoreDfs(drvr_pin, drvr_node, 0, 0.0, pi_elmore); + reduceElmoreDfs(drvr_pin, drvr_node, nullptr, 0.0, pi_elmore); return pi_elmore; } @@ -383,7 +378,7 @@ class ReduceToPiPoleResidue2 : public ReduceToPi { public: ReduceToPiPoleResidue2(StaState *sta); - ~ReduceToPiPoleResidue2(); + ~ReduceToPiPoleResidue2() override; void findPolesResidues(const Parasitic *parasitic_network, Parasitic *pi_pole_residue, const Pin *drvr_pin, @@ -424,12 +419,11 @@ private: // Resistor/capacitor currents. ResistorCurrentMap currents_; - ParasiticNodeValueMap *moments_; + ParasiticNodeValueMap *moments_ {nullptr}; }; ReduceToPiPoleResidue2::ReduceToPiPoleResidue2(StaState *sta) : - ReduceToPi(sta), - moments_(nullptr) + ReduceToPi(sta) { } @@ -526,10 +520,10 @@ ReduceToPiPoleResidue2::findMoments(const Pin *drvr_pin, // current thru the resistors. Thus, there is no point in doing a // pass to find the zero'th moments. for (int moment_index = 1; moment_index < moment_count; moment_index++) { - double rd_i = findBranchCurrents(drvr_pin, drvr_node, 0, moment_index); + double rd_i = findBranchCurrents(drvr_pin, drvr_node, nullptr, moment_index); double rd_volt = rd_i * rd; setMoment(drvr_node, 0.0, moment_index); - findMoments(drvr_pin, drvr_node, -rd_volt, 0, moment_index); + findMoments(drvr_pin, drvr_node, -rd_volt, nullptr, moment_index); } } diff --git a/parasitics/ReportParasiticAnnotation.cc b/parasitics/ReportParasiticAnnotation.cc index f91db926..f9651e57 100644 --- a/parasitics/ReportParasiticAnnotation.cc +++ b/parasitics/ReportParasiticAnnotation.cc @@ -24,15 +24,15 @@ #include "ReportParasiticAnnotation.hh" +#include "ArcDelayCalc.hh" #include "ContainerHelpers.hh" -#include "Report.hh" +#include "Graph.hh" #include "Network.hh" #include "NetworkCmp.hh" -#include "PortDirection.hh" -#include "Graph.hh" -#include "Scene.hh" #include "Parasitics.hh" -#include "ArcDelayCalc.hh" +#include "PortDirection.hh" +#include "Report.hh" +#include "Scene.hh" namespace sta { @@ -43,7 +43,7 @@ public: bool report_unannotated, const Scene *scene, StaState *sta); - void report(); + void reportAnnotation(); private: void reportAnnotationCounts(); @@ -67,7 +67,7 @@ reportParasiticAnnotation(Parasitics *parasitics, { ReportParasiticAnnotation report_annotation(parasitics, report_unannotated, scene, sta); - report_annotation.report(); + report_annotation.reportAnnotation(); } ReportParasiticAnnotation::ReportParasiticAnnotation(Parasitics *parasitics, @@ -83,7 +83,7 @@ ReportParasiticAnnotation::ReportParasiticAnnotation(Parasitics *parasitics, } void -ReportParasiticAnnotation::report() +ReportParasiticAnnotation::reportAnnotation() { findCounts(); reportAnnotationCounts(); @@ -132,7 +132,7 @@ ReportParasiticAnnotation::findCounts() arc_delay_calc_->findParasitic(pin, RiseFall::rise(), scene_, min_max_); if (parasitic) { PinSet unannotated_loads = parasitics_->unannotatedLoads(parasitic, pin); - if (unannotated_loads.size() > 0) + if (!unannotated_loads.empty()) partially_annotated_.push_back(pin); } else diff --git a/parasitics/SpefParse.yy b/parasitics/SpefParse.yy index e527d781..fed603c0 100755 --- a/parasitics/SpefParse.yy +++ b/parasitics/SpefParse.yy @@ -47,10 +47,18 @@ sta::SpefParse::error(const location_type &loc, %code requires { #include +#include "StringUtil.hh" namespace sta { // Bison's C++ variant skeleton cannot use void as a semantic type. struct SpefParseVoid {}; +class SpefReader; +class SpefScanner; +class Net; +class Pin; +class PortDirection; +class SpefRspfPi; +class SpefTriple; } } diff --git a/parasitics/SpefReader.cc b/parasitics/SpefReader.cc index 30613dd5..05141673 100644 --- a/parasitics/SpefReader.cc +++ b/parasitics/SpefReader.cc @@ -28,21 +28,21 @@ #include #include -#include "Zlib.hh" -#include "Stats.hh" -#include "Report.hh" +#include "ArcDelayCalc.hh" #include "Debug.hh" -#include "StringUtil.hh" -#include "Transition.hh" #include "Liberty.hh" #include "Network.hh" -#include "PortDirection.hh" -#include "Sdc.hh" #include "Parasitics.hh" +#include "PortDirection.hh" +#include "Report.hh" #include "Scene.hh" -#include "ArcDelayCalc.hh" -#include "SpefReaderPvt.hh" +#include "Sdc.hh" #include "SpefNamespace.hh" +#include "SpefReaderPvt.hh" +#include "Stats.hh" +#include "StringUtil.hh" +#include "Transition.hh" +#include "Zlib.hh" #include "parasitics/SpefScanner.hh" namespace sta { @@ -84,19 +84,7 @@ SpefReader::SpefReader(std::string_view filename, reduce_(reduce), scene_(scene), min_max_(min_max), - // defaults - divider_('\0'), - delimiter_('\0'), - bus_brkt_left_('\0'), - bus_brkt_right_('\0'), - net_(nullptr), - triple_index_(0), - time_scale_(1.0), - cap_scale_(1.0), - res_scale_(1.0), - induct_scale_(1.0), - parasitics_(parasitics), - parasitic_(nullptr) + parasitics_(parasitics) { parasitics->setCouplingCapFactor(coupling_cap_factor); } @@ -452,7 +440,7 @@ SpefReader::findParasiticNode(std::string_view name, if (net) { // : if (isDigits(name2)) { - int id = std::stoi(name2); + uint32_t id = std::stoi(name2); if (local_only && !network_->isConnected(net, net_)) warn(1653, "{}{}{} not connected to net {}.", name1, delimiter_, name2, network_->pathName(net_)); @@ -487,7 +475,7 @@ SpefReader::findParasiticNode(std::string_view name, } void -SpefReader::makeCapacitor(int, +SpefReader::makeCapacitor(uint32_t, std::string_view node_name, SpefTriple *cap) { @@ -500,7 +488,7 @@ SpefReader::makeCapacitor(int, } void -SpefReader::makeCapacitor(int id, +SpefReader::makeCapacitor(uint32_t id, std::string_view node_name1, std::string_view node_name2, SpefTriple *cap) @@ -523,7 +511,7 @@ SpefReader::makeCapacitor(int id, } void -SpefReader::makeResistor(int id, +SpefReader::makeResistor(uint32_t id, std::string_view node_name1, std::string_view node_name2, SpefTriple *res) diff --git a/parasitics/SpefReader.hh b/parasitics/SpefReader.hh index f1187e1d..4708fc1c 100644 --- a/parasitics/SpefReader.hh +++ b/parasitics/SpefReader.hh @@ -27,9 +27,9 @@ #include #include -#include "Zlib.hh" #include "MinMax.hh" #include "ParasiticsClass.hh" +#include "Zlib.hh" namespace sta { @@ -52,7 +52,7 @@ readSpefFile(std::string_view filename, bool reduce, const Scene *scene, const MinMaxAll *min_max, - Parasitics *parasirics, + Parasitics *parasitics, StaState *sta); } // namespace sta diff --git a/parasitics/SpefReaderPvt.hh b/parasitics/SpefReaderPvt.hh index 9ba21cde..4b1b90ff 100644 --- a/parasitics/SpefReaderPvt.hh +++ b/parasitics/SpefReaderPvt.hh @@ -28,11 +28,11 @@ #include #include -#include "Zlib.hh" -#include "StringUtil.hh" #include "NetworkClass.hh" #include "ParasiticsClass.hh" #include "StaState.hh" +#include "StringUtil.hh" +#include "Zlib.hh" namespace sta { @@ -58,7 +58,7 @@ public: const MinMaxAll *min_max, Parasitics *parasitics, StaState *sta); - virtual ~SpefReader() = default; + ~SpefReader() override = default; bool read(); char divider() const { return divider_; } void setDivider(char divider); @@ -94,14 +94,14 @@ public: void dspfBegin(Net *net, SpefTriple *total_cap); void dspfFinish(); - void makeCapacitor(int id, + void makeCapacitor(uint32_t id, std::string_view node_name, SpefTriple *cap); - void makeCapacitor(int id, + void makeCapacitor(uint32_t id, std::string_view node_name1, std::string_view node_name2, SpefTriple *cap); - void makeResistor(int id, + void makeResistor(uint32_t id, std::string_view node_name1, std::string_view node_name2, SpefTriple *res); @@ -134,21 +134,21 @@ private: const Scene *scene_; const MinMaxAll *min_max_; // Normally no need to keep device names. - char divider_; - char delimiter_; - char bus_brkt_left_; - char bus_brkt_right_; - Net *net_; + char divider_{'\0'}; + char delimiter_{'\0'}; + char bus_brkt_left_{'\0'}; + char bus_brkt_right_{'\0'}; + Net *net_{nullptr}; - int triple_index_; - float time_scale_; - float cap_scale_; - float res_scale_; - float induct_scale_; + int triple_index_{0}; + float time_scale_{1.0}; + float cap_scale_{1.0}; + float res_scale_{1.0}; + float induct_scale_{1.0}; SpefNameMap name_map_; StringSeq design_flow_; Parasitics *parasitics_; - Parasitic *parasitic_; + Parasitic *parasitic_{nullptr}; }; class SpefTriple diff --git a/parasitics/SpefScanner.hh b/parasitics/SpefScanner.hh index 58e64025..d9c21b86 100644 --- a/parasitics/SpefScanner.hh +++ b/parasitics/SpefScanner.hh @@ -46,7 +46,7 @@ public: std::string_view filename, SpefReader *reader, Report *report); - virtual int lex(SpefParse::semantic_type *const yylval, + virtual int lex(SpefParse::semantic_type *yylval, SpefParse::location_type *yylloc); // YY_DECL defined in SpefLex.ll // Method body created by flex in SpefLex.cc diff --git a/power/Power.cc b/power/Power.cc index 114d802e..da1b5e08 100644 --- a/power/Power.cc +++ b/power/Power.cc @@ -31,8 +31,6 @@ #include #include -#include "cudd.h" - #include "Bfs.hh" #include "ClkNetwork.hh" #include "Clock.hh" @@ -71,6 +69,7 @@ #include "Transition.hh" #include "Units.hh" #include "VertexVisitor.hh" +#include "cudd.h" #include "search/Levelize.hh" #include "search/Sim.hh" @@ -570,7 +569,6 @@ ActivitySrchPred::searchTo(const Vertex *, //////////////////////////////////////////////////////////////// -// NOLINTNEXTLINE(misc-multiple-inheritance) class PropActivityVisitor : public VertexVisitor, StaState { public: diff --git a/power/Power.hh b/power/Power.hh index 9bb72e65..8a19f309 100644 --- a/power/Power.hh +++ b/power/Power.hh @@ -24,16 +24,16 @@ #pragma once -#include #include #include +#include -#include "StaConfig.hh" // CUDD -#include "Network.hh" -#include "SdcClass.hh" -#include "PowerClass.hh" -#include "StaState.hh" #include "Bdd.hh" +#include "Network.hh" +#include "PowerClass.hh" +#include "SdcClass.hh" +#include "StaConfig.hh" // CUDD +#include "StaState.hh" struct DdNode; struct DdManager; diff --git a/power/Power.i b/power/Power.i index bc818668..52d77af7 100644 --- a/power/Power.i +++ b/power/Power.i @@ -25,12 +25,13 @@ %module power %{ -#include "Sta.hh" -#include "Sdc.hh" -#include "Mode.hh" #include "power/Power.hh" -#include "power/VcdReader.hh" + +#include "Mode.hh" +#include "Sdc.hh" +#include "Sta.hh" #include "power/SaifReader.hh" +#include "power/VcdReader.hh" using namespace sta; diff --git a/power/ReportPower.cc b/power/ReportPower.cc index 00407ff6..16de910a 100644 --- a/power/ReportPower.cc +++ b/power/ReportPower.cc @@ -24,12 +24,12 @@ #include "ReportPower.hh" -#include #include +#include -#include "Report.hh" -#include "Network.hh" #include "Format.hh" +#include "Network.hh" +#include "Report.hh" namespace sta { diff --git a/power/ReportPower.hh b/power/ReportPower.hh index 4d905e88..105a9a00 100644 --- a/power/ReportPower.hh +++ b/power/ReportPower.hh @@ -26,9 +26,9 @@ #include -#include "StaState.hh" #include "NetworkClass.hh" #include "PowerClass.hh" +#include "StaState.hh" namespace sta { diff --git a/power/SaifParse.yy b/power/SaifParse.yy index 9413cbce..a447a0cb 100644 --- a/power/SaifParse.yy +++ b/power/SaifParse.yy @@ -60,6 +60,10 @@ sta::SaifParse::error(const location_type &loc, %define api.parser.class {SaifParse} %define api.value.type variant +%code requires { +#include "power/SaifReaderPvt.hh" +} + // expected shift/reduce conflicts %expect 2 diff --git a/power/SaifReader.cc b/power/SaifReader.cc index 98e21e76..b05b6c12 100644 --- a/power/SaifReader.cc +++ b/power/SaifReader.cc @@ -29,18 +29,18 @@ #include #include -#include "Error.hh" #include "Debug.hh" -#include "Stats.hh" -#include "Report.hh" +#include "Error.hh" +#include "Liberty.hh" #include "Network.hh" #include "PortDirection.hh" -#include "Liberty.hh" -#include "Sdc.hh" #include "Power.hh" +#include "Report.hh" +#include "Sdc.hh" +#include "Sta.hh" +#include "Stats.hh" #include "power/SaifReaderPvt.hh" #include "power/SaifScanner.hh" -#include "Sta.hh" namespace sta { @@ -60,11 +60,6 @@ SaifReader::SaifReader(const char *filename, StaState(sta), filename_(filename), scope_(scope), - divider_('/'), - escape_('\\'), - timescale_(1.0E-9F), // default units of ns - duration_(0.0), - in_scope_level_(0), power_(sta->power()) { } diff --git a/power/SaifReaderPvt.hh b/power/SaifReaderPvt.hh index 6443dfa9..243e14dc 100644 --- a/power/SaifReaderPvt.hh +++ b/power/SaifReaderPvt.hh @@ -24,15 +24,15 @@ #pragma once -#include -#include -#include -#include #include +#include +#include +#include +#include -#include "Zlib.hh" #include "NetworkClass.hh" #include "StaState.hh" +#include "Zlib.hh" // Header for SaifReader.cc to communicate with SaifLex.cc, SaifParse.cc @@ -72,13 +72,13 @@ private: const char *filename_; const char *scope_; // Divider delimited scope to begin annotation. - char divider_; - char escape_; - double timescale_; - int64_t duration_; + char divider_ = '/'; + char escape_ = '\\'; + double timescale_ = 1.0E-9; // default units of ns + int64_t duration_ = 0; std::vector saif_scope_; // Scope during parsing. - size_t in_scope_level_; + size_t in_scope_level_ = 0; std::vector path_; // Path within scope. std::set annotated_pins_; Power *power_; diff --git a/power/SaifScanner.hh b/power/SaifScanner.hh index 945ddc6a..9ca6867f 100644 --- a/power/SaifScanner.hh +++ b/power/SaifScanner.hh @@ -36,6 +36,7 @@ namespace sta { class Report; +class SaifReader; class SaifScanner : public SaifFlexLexer { @@ -44,7 +45,7 @@ public: const std::string &filename, SaifReader *reader, Report *report); - virtual int lex(SaifParse::semantic_type *const yylval, + virtual int lex(SaifParse::semantic_type *yylval, SaifParse::location_type *yylloc); // YY_DECL defined in SaifLex.ll // Method body created by flex in SaifLex.cc diff --git a/power/VcdParse.cc b/power/VcdParse.cc index ea0d71a7..2a841427 100644 --- a/power/VcdParse.cc +++ b/power/VcdParse.cc @@ -28,10 +28,10 @@ #include #include -#include "Stats.hh" -#include "Report.hh" -#include "Error.hh" #include "EnumNameMap.hh" +#include "Error.hh" +#include "Report.hh" +#include "Stats.hh" namespace sta { @@ -106,11 +106,6 @@ VcdParse::read(const char *filename, VcdParse::VcdParse(Report *report, Debug *debug) : - reader_(nullptr), - file_line_(0), - stmt_line_(0), - time_(0), - prev_time_(0), report_(report), debug_(debug) { @@ -237,7 +232,7 @@ VcdParse::parseVarValues() report_->fileError(807, filename_, file_line_, "unknown variable {}", id); else { // Reverse the bus value to match the bit order in the VCD file. - std::reverse(bus_value.begin(), bus_value.end()); + std::ranges::reverse(bus_value); reader_->varAppendBusValue(id, time_, bus_value); } } diff --git a/power/VcdParse.hh b/power/VcdParse.hh index 82702222..66f5d28f 100644 --- a/power/VcdParse.hh +++ b/power/VcdParse.hh @@ -28,8 +28,8 @@ #include #include -#include "Zlib.hh" #include "StaState.hh" +#include "Zlib.hh" namespace sta { @@ -78,15 +78,15 @@ private: std::string readStmtString(); std::vector readStmtTokens(); - VcdReader *reader_; + VcdReader *reader_ = nullptr; gzFile stream_; std::string token_; const char *filename_; - int file_line_; - int stmt_line_; + int file_line_ = 0; + int stmt_line_ = 0; - VcdTime time_; - VcdTime prev_time_; + VcdTime time_ = 0; + VcdTime prev_time_ = 0; VcdScope scope_; Report *report_; diff --git a/power/VcdReader.cc b/power/VcdReader.cc index ee6e6037..66373022 100644 --- a/power/VcdReader.cc +++ b/power/VcdReader.cc @@ -25,21 +25,21 @@ #include "VcdReader.hh" #include -#include +#include #include #include -#include "VcdParse.hh" #include "Debug.hh" -#include "Network.hh" #include "Liberty.hh" -#include "PortDirection.hh" -#include "VerilogNamespace.hh" -#include "ParseBus.hh" -#include "Sdc.hh" #include "Mode.hh" +#include "Network.hh" +#include "ParseBus.hh" +#include "PortDirection.hh" #include "Power.hh" +#include "Sdc.hh" #include "Sta.hh" +#include "VcdParse.hh" +#include "VerilogNamespace.hh" namespace sta { @@ -60,17 +60,13 @@ public: private: PinSeq pins_; - VcdTime prev_time_; - char prev_value_; - VcdTime high_time_; - double transition_count_; + VcdTime prev_time_ = -1; + char prev_value_ = '\0'; + VcdTime high_time_ = 0; + double transition_count_ = 0; }; -VcdCount::VcdCount() : - prev_time_(-1), - prev_value_('\0'), - high_time_(0), - transition_count_(0) +VcdCount::VcdCount() { } @@ -157,9 +153,9 @@ private: const std::string scope_; - double time_scale_; - VcdTime time_min_; - VcdTime time_max_; + double time_scale_ = 1.0; + VcdTime time_min_ = 0; + VcdTime time_max_ = 0; VcdIdCountsMap vcd_count_map_; const Network *sdc_network_; @@ -172,9 +168,6 @@ VcdCountReader::VcdCountReader(std::string_view scope, Report *report, Debug *debug) : scope_(scope), - time_scale_(1.0), - time_min_(0), - time_max_(0), sdc_network_(sdc_network), report_(report), debug_(debug) @@ -299,16 +292,14 @@ VcdCountReader::varAppendValue(const std::string &id, if (itr != vcd_count_map_.end()) { VcdCounts &vcd_counts = itr->second; if (debug_->check("read_vcd", 3)) { - for (size_t bit_idx = 0; bit_idx < vcd_counts.size(); bit_idx++) { - VcdCount &vcd_count = vcd_counts[bit_idx]; + for (auto &vcd_count : vcd_counts) { for (const Pin *pin : vcd_count.pins()) { debugPrint(debug_, "read_vcd", 3, "{} time {} value {}", sdc_network_->pathName(pin), time, value); } } } - for (size_t bit_idx = 0; bit_idx < vcd_counts.size(); bit_idx++) { - VcdCount &vcd_count = vcd_counts[bit_idx]; + for (auto &vcd_count : vcd_counts) { vcd_count.incrCounts(time, value); } } diff --git a/sdc/Clock.cc b/sdc/Clock.cc index 1772b60f..d38e384b 100644 --- a/sdc/Clock.cc +++ b/sdc/Clock.cc @@ -25,17 +25,18 @@ #include "Clock.hh" #include +#include #include "ContainerHelpers.hh" #include "Error.hh" #include "Format.hh" -#include "StringUtil.hh" -#include "MinMax.hh" -#include "Transition.hh" -#include "TimingRole.hh" -#include "Network.hh" #include "Graph.hh" +#include "MinMax.hh" +#include "Network.hh" #include "Sdc.hh" +#include "StringUtil.hh" +#include "TimingRole.hh" +#include "Transition.hh" namespace sta { @@ -47,26 +48,8 @@ Clock::Clock(std::string_view name, const Network *network) : name_(name), pins_(network), - add_to_pins_(false), leaf_pins_(network), - period_(0.0), - waveform_(nullptr), - waveform_valid_(false), - index_(index), - clk_edges_(nullptr), - is_propagated_(false), - uncertainties_(nullptr), - is_generated_(false), - src_pin_(nullptr), - master_clk_(nullptr), - master_clk_infered_(false), - divide_by_(0), - multiply_by_(0), - duty_cycle_(0), - invert_(false), - combinational_(false), - edges_(nullptr), - edge_shifts_(nullptr) + index_(index) { makeClkEdges(); } @@ -87,7 +70,7 @@ Clock::initClk(PinSet *pins, waveform_valid_ = true; period_ = period; setClkEdgeTimes(); - setComment(std::move(comment)); + setComment(comment); } bool @@ -248,7 +231,7 @@ Clock::setSlewLimit(const RiseFallBoth *rf, const MinMax *min_max, float slew) { - slew_limits_[int(clk_data)].setValue(rf, min_max, slew); + slew_limits_[static_cast(clk_data)].setValue(rf, min_max, slew); } void @@ -259,7 +242,7 @@ Clock::slewLimit(const RiseFall *rf, float &slew, bool &exists) const { - slew_limits_[int(clk_data)].value(rf, min_max, slew, exists); + slew_limits_[static_cast(clk_data)].value(rf, min_max, slew, exists); } void @@ -343,7 +326,7 @@ Clock::initGeneratedClk(PinSet *pins, invert_ = invert; combinational_ = combinational; is_propagated_ = is_propagated; - setComment(std::move(comment)); + setComment(comment); delete edges_; if (edges @@ -451,25 +434,29 @@ Clock::generateEdgesClk(const Clock *src_clk) if (edges_->size() == 3) { const FloatSeq *src_wave = src_clk->waveform(); size_t src_size = src_wave->size(); + int src_size_int = static_cast(src_size); float src_period = src_clk->period(); int edge0_1 = (*edges_)[0] - 1; - float rise = (*src_wave)[edge0_1 % src_size] - + (edge0_1 / src_size) * src_period; + div_t edge0_div = std::div(edge0_1, src_size_int); + float rise = (*src_wave)[edge0_div.rem] + + static_cast(edge0_div.quot) * src_period; if (edge_shifts_) rise += (*edge_shifts_)[0]; waveform_->push_back(rise); int edge1_1 = (*edges_)[1] - 1; - float fall = (*src_wave)[edge1_1 % src_size] - + (edge1_1 / src_size) * src_period; + div_t edge1_div = std::div(edge1_1, src_size_int); + float fall = (*src_wave)[edge1_div.rem] + + static_cast(edge1_div.quot) * src_period; if (edge_shifts_) fall += (*edge_shifts_)[1]; waveform_->push_back(fall); int edge2_1 = (*edges_)[2] - 1; - period_ = (*src_wave)[edge2_1 % src_size] - + (edge2_1 / src_size) * src_period - rise; + div_t edge2_div = std::div(edge2_1, src_size_int); + period_ = (*src_wave)[edge2_div.rem] + + static_cast(edge2_div.quot) * src_period - rise; if (edge_shifts_) period_ += (*edge_shifts_)[2]; } @@ -522,7 +509,7 @@ Clock::isDivideByOneCombinational() const return combinational_ && divide_by_ == 1 && multiply_by_ == 0 - && edge_shifts_ == 0; + && edge_shifts_ == nullptr; } //////////////////////////////////////////////////////////////// @@ -532,15 +519,10 @@ ClockEdge::ClockEdge(Clock *clock, clock_(clock), rf_(rf), name_(sta::format("{} {}", clock_->name(), rf_->shortName())), - time_(0.0), index_(clock_->index() * RiseFall::index_count + rf_->index()) { } -ClockEdge::~ClockEdge() -{ -} - void ClockEdge::setTime(float time) { diff --git a/sdc/ClockGatingCheck.cc b/sdc/ClockGatingCheck.cc index 96d134d3..a8cb5763 100644 --- a/sdc/ClockGatingCheck.cc +++ b/sdc/ClockGatingCheck.cc @@ -26,11 +26,6 @@ namespace sta { -ClockGatingCheck::ClockGatingCheck() : - active_value_(LogicValue::unknown) -{ -} - void ClockGatingCheck::setActiveValue(LogicValue value) { diff --git a/sdc/CycleAccting.cc b/sdc/CycleAccting.cc index 8f4b4b32..8c0ca1eb 100644 --- a/sdc/CycleAccting.cc +++ b/sdc/CycleAccting.cc @@ -24,16 +24,16 @@ #include "CycleAccting.hh" -#include // ceil #include // max +#include // ceil +#include "Clock.hh" #include "ContainerHelpers.hh" #include "Debug.hh" #include "Fuzzy.hh" -#include "Units.hh" -#include "TimingRole.hh" -#include "Clock.hh" #include "Sdc.hh" +#include "TimingRole.hh" +#include "Units.hh" namespace sta { @@ -110,8 +110,7 @@ CycleAcctings::reportClkToClkMaxCycleWarnings(Report *report) CycleAccting::CycleAccting(const ClockEdge *src, const ClockEdge *tgt) : src_(src), - tgt_(tgt), - max_cycles_exceeded_(false) + tgt_(tgt) { for (int i = 0; i <= TimingRole::index_max; i++) { delay_[i] = MinMax::min()->initValue(); diff --git a/sdc/DataCheck.cc b/sdc/DataCheck.cc index dbba2422..a538c6a0 100644 --- a/sdc/DataCheck.cc +++ b/sdc/DataCheck.cc @@ -46,8 +46,8 @@ DataCheck::margin(const RiseFall *from_rf, float &margin, bool &exists) const { - return margins_[from_rf->index()].value(to_rf, setup_hold, - margin, exists); + margins_[from_rf->index()].value(to_rf, setup_hold, + margin, exists); } void diff --git a/sdc/DeratingFactors.cc b/sdc/DeratingFactors.cc index f5534cee..8b13bf2c 100644 --- a/sdc/DeratingFactors.cc +++ b/sdc/DeratingFactors.cc @@ -26,16 +26,16 @@ namespace sta { -inline int +inline size_t index(TimingDerateType type) { - return int(type); + return static_cast(type); } -inline int +inline size_t index(TimingDerateCellType type) { - return int(type); + return static_cast(type); } DeratingFactors::DeratingFactors() @@ -49,8 +49,8 @@ DeratingFactors::setFactor(PathClkOrData clk_data, const EarlyLate *early_late, float factor) { - for (auto rf1 : rf->range()) - factors_[int(clk_data)].setValue(rf1, early_late, factor); + for (const RiseFall *rf1 : rf->range()) + factors_[static_cast(clk_data)].setValue(rf1, early_late, factor); } void @@ -60,14 +60,14 @@ DeratingFactors::factor(PathClkOrData clk_data, float &factor, bool &exists) const { - factors_[int(clk_data)].value(rf, early_late, factor, exists); + factors_[static_cast(clk_data)].value(rf, early_late, factor, exists); } void DeratingFactors::clear() { - for (int clk_data = 0; clk_data < path_clk_or_data_count;clk_data++) - factors_[int(clk_data)].clear(); + for (RiseFallMinMax &factors : factors_) + factors.clear(); } void @@ -91,7 +91,7 @@ DeratingFactors::isOneValue(PathClkOrData clk_data, bool &is_one_value, float &value) const { - is_one_value = factors_[int(clk_data)].isOneValue(early_late, value); + is_one_value = factors_[static_cast(clk_data)].isOneValue(early_late, value); } bool @@ -143,8 +143,8 @@ DeratingFactorsGlobal::factor(TimingDerateCellType type, void DeratingFactorsGlobal::clear() { - for (int type = 0; type < timing_derate_type_count; type++) - factors_[type].clear(); + for (DeratingFactors &factors : factors_) + factors.clear(); } DeratingFactors * @@ -184,8 +184,8 @@ DeratingFactorsCell::factor(TimingDerateCellType type, void DeratingFactorsCell::clear() { - for (int type = 0; type < timing_derate_cell_type_count; type++) - factors_[type].clear(); + for (DeratingFactors &factors : factors_) + factors.clear(); } DeratingFactors * @@ -211,10 +211,4 @@ DeratingFactorsCell::isOneValue(const EarlyLate *early_late, value = value1; } -//////////////////////////////////////////////////////////////// - -DeratingFactorsNet::DeratingFactorsNet() -{ -} - } // namespace sta diff --git a/sdc/DisabledPorts.cc b/sdc/DisabledPorts.cc index 9c3fa921..311a2439 100644 --- a/sdc/DisabledPorts.cc +++ b/sdc/DisabledPorts.cc @@ -26,21 +26,13 @@ #include -#include "StringUtil.hh" -#include "TimingRole.hh" #include "Liberty.hh" #include "Network.hh" +#include "StringUtil.hh" +#include "TimingRole.hh" namespace sta { -DisabledPorts::DisabledPorts() : - all_(false), - from_(nullptr), - to_(nullptr), - from_to_(nullptr) -{ -} - DisabledPorts::~DisabledPorts() { delete from_; @@ -122,9 +114,7 @@ DisabledPorts::isDisabled(LibertyPort *from, //////////////////////////////////////////////////////////////// DisabledCellPorts::DisabledCellPorts(LibertyCell *cell) : - DisabledPorts(), - cell_(cell), - arc_sets_(nullptr) + cell_(cell) { } @@ -159,15 +149,10 @@ DisabledCellPorts::isDisabled(TimingArcSet *arc_set) const class DisabledCellPortsLess { public: - DisabledCellPortsLess(); bool operator()(const DisabledCellPorts *disable1, const DisabledCellPorts *disable2); }; -DisabledCellPortsLess::DisabledCellPortsLess() -{ -} - bool DisabledCellPortsLess::operator()(const DisabledCellPorts *disable1, const DisabledCellPorts *disable2) @@ -190,7 +175,6 @@ sortByName(const DisabledCellPortsMap *cell_map) //////////////////////////////////////////////////////////////// DisabledInstancePorts::DisabledInstancePorts(Instance *inst) : - DisabledPorts(), inst_(inst) { } @@ -263,4 +247,4 @@ sortByName(const LibertyPortPairSet *set) return pairs; } -} +} // namespace sta diff --git a/sdc/ExceptionPath.cc b/sdc/ExceptionPath.cc index 69ad2b57..151c98ad 100644 --- a/sdc/ExceptionPath.cc +++ b/sdc/ExceptionPath.cc @@ -26,16 +26,16 @@ #include -#include "Format.hh" +#include "Clock.hh" #include "ContainerHelpers.hh" +#include "Format.hh" #include "MinMax.hh" -#include "TimingRole.hh" -#include "Units.hh" -#include "Transition.hh" -#include "PortDirection.hh" #include "Network.hh" #include "NetworkCmp.hh" -#include "Clock.hh" +#include "PortDirection.hh" +#include "TimingRole.hh" +#include "Transition.hh" +#include "Units.hh" namespace sta { @@ -99,8 +99,7 @@ ExceptionPath::ExceptionPath(ExceptionFrom *from, to_(to), min_max_(min_max), own_pts_(own_pts), - priority_(priority), - id_(0) + priority_(priority) { makeStates(); } @@ -827,10 +826,6 @@ GroupPath::GroupPath(std::string_view name, { } -GroupPath::~GroupPath() -{ -} - std::string_view GroupPath::typeString() const { @@ -882,8 +877,7 @@ const int ExceptionPt::to_string_max_objects_ = 20; ExceptionPt::ExceptionPt(const RiseFallBoth *rf, bool own_pts) : rf_(rf), - own_pts_(own_pts), - hash_(0) + own_pts_(own_pts) { } @@ -922,7 +916,7 @@ ExceptionFromTo::ExceptionFromTo(PinSet *pins, delete insts_; insts_ = nullptr; } - findHash(network); + ExceptionFromTo::findHash(network); } ExceptionFromTo::~ExceptionFromTo() @@ -1484,7 +1478,6 @@ ExceptionThru::ExceptionThru(PinSet *pins, const Network *network) : ExceptionPt(rf, own_pts), pins_(pins), - edges_(nullptr), nets_(nets), insts_(insts) { @@ -2103,9 +2096,7 @@ ExceptionThru::deletePinBefore(const Pin *pin, //////////////////////////////////////////////////////////////// ExceptionPtIterator::ExceptionPtIterator(const ExceptionPath *exception) : - exception_(exception), - from_done_(false), - to_done_(false) + exception_(exception) { if (exception->thrus()) thru_iter_ = exception->thrus()->begin(); @@ -2177,7 +2168,7 @@ ExpandedExceptionVisitor::visitExpansions() } } else - expandThrus(0); + expandThrus(nullptr); } void @@ -2282,7 +2273,6 @@ ExceptionState::ExceptionState(ExceptionPath *exception, int index) : exception_(exception), next_thru_(next_thru), - next_state_(nullptr), index_(index) { } @@ -2385,11 +2375,10 @@ class InsertPinPairsThru : public HierPinThruVisitor public: InsertPinPairsThru(PinPairSet *pairs, const Network *network); + void visit(const Pin *drvr, + const Pin *load) override; protected: - virtual void visit(const Pin *drvr, - const Pin *load); - PinPairSet *pairs_; const Network *network_; }; @@ -2432,11 +2421,10 @@ class DeletePinPairsThru : public HierPinThruVisitor public: DeletePinPairsThru(PinPairSet *pairs, const Network *network); + void visit(const Pin *drvr, + const Pin *load) override; protected: - virtual void visit(const Pin *drvr, - const Pin *load); - PinPairSet *pairs_; const Network *network_; }; diff --git a/sdc/FilterObjects.cc b/sdc/FilterObjects.cc index cf303377..509e48df 100644 --- a/sdc/FilterObjects.cc +++ b/sdc/FilterObjects.cc @@ -24,12 +24,12 @@ #include "FilterObjects.hh" +#include +#include #include #include -#include -#include -#include #include +#include #include #include #include @@ -42,15 +42,15 @@ #include "GraphCmp.hh" #include "Liberty.hh" #include "LibertyClass.hh" -#include "NetworkClass.hh" #include "Network.hh" -#include "SearchClass.hh" -#include "StringUtil.hh" -#include "Property.hh" +#include "NetworkClass.hh" #include "PathEnd.hh" #include "PatternMatch.hh" +#include "Property.hh" #include "SdcClass.hh" +#include "SearchClass.hh" #include "Sta.hh" +#include "StringUtil.hh" namespace sta { @@ -86,7 +86,7 @@ public: PredicateToken(std::string_view property, std::string_view op, std::string_view arg); - virtual ~PredicateToken() = default; + ~PredicateToken() override = default; const std::string &property() const { return property_; } const std::string &op() const { return op_; } const std::string &arg() const { return arg_; } diff --git a/sdc/InputDrive.cc b/sdc/InputDrive.cc index 1b558b96..8f93a7f8 100644 --- a/sdc/InputDrive.cc +++ b/sdc/InputDrive.cc @@ -24,6 +24,8 @@ #include "InputDrive.hh" +#include "SdcClass.hh" + namespace sta { InputDrive::InputDrive() @@ -90,7 +92,7 @@ void InputDrive::setDriveCell(const LibertyLibrary *library, const LibertyCell *cell, const LibertyPort *from_port, - float *from_slews, + const DriveCellSlews &from_slews, const LibertyPort *to_port, const RiseFallBoth *rf, const MinMaxAll *min_max) @@ -120,20 +122,21 @@ InputDrive::driveCell(const RiseFall *rf, // Return values. const LibertyCell *&cell, const LibertyPort *&from_port, - float *&from_slews, + const DriveCellSlews *&from_slews, const LibertyPort *&to_port) const { InputDriveCell *drive = drive_cells_[rf->index()][min_max->index()]; if (drive) { cell = drive->cell(); from_port = drive->fromPort(); - from_slews = drive->fromSlews(); + from_slews = &drive->fromSlews(); to_port = drive->toPort(); } else { cell = nullptr; from_port = nullptr; - from_slews = nullptr; + static constexpr DriveCellSlews slews_zero{0.0, 0.0}; + from_slews = &slews_zero; to_port = nullptr; } } @@ -182,14 +185,14 @@ InputDrive::slew(const RiseFall *rf, InputDriveCell::InputDriveCell(const LibertyLibrary *library, const LibertyCell *cell, const LibertyPort *from_port, - float *from_slews, + const DriveCellSlews &from_slews, const LibertyPort *to_port) : library_(library), cell_(cell), from_port_(from_port), + from_slews_(from_slews), to_port_(to_port) { - setFromSlews(from_slews); } void @@ -217,10 +220,9 @@ InputDriveCell::setToPort(const LibertyPort *to_port) } void -InputDriveCell::setFromSlews(float *from_slews) +InputDriveCell::setFromSlews(const DriveCellSlews &from_slews) { - for (auto rf_index : RiseFall::rangeIndex()) - from_slews_[rf_index] = from_slews[rf_index]; + from_slews_ = from_slews; } bool diff --git a/sdc/PortDelay.cc b/sdc/PortDelay.cc index cd6dbba9..94d3bbb2 100644 --- a/sdc/PortDelay.cc +++ b/sdc/PortDelay.cc @@ -24,8 +24,8 @@ #include "PortDelay.hh" -#include "Sdc.hh" #include "Network.hh" +#include "Sdc.hh" namespace sta { @@ -34,10 +34,6 @@ PortDelay::PortDelay(const Pin *pin, const Network *network) : pin_(pin), clk_edge_(clk_edge), - source_latency_included_(false), - network_latency_included_(false), - ref_pin_(nullptr), - delays_(), leaf_pins_(network) { } diff --git a/sdc/PortExtCap.cc b/sdc/PortExtCap.cc index a17f353c..9802628c 100644 --- a/sdc/PortExtCap.cc +++ b/sdc/PortExtCap.cc @@ -26,11 +26,6 @@ namespace sta { -PortExtCap::PortExtCap() : - port_(nullptr) -{ -} - void PortExtCap::pinCap(const RiseFall *rf, const MinMax *min_max, diff --git a/sdc/Sdc.cc b/sdc/Sdc.cc index 08510aea..ed8b54ac 100644 --- a/sdc/Sdc.cc +++ b/sdc/Sdc.cc @@ -579,9 +579,9 @@ Sdc::setTimingDerate(const Net *net, const EarlyLate *early_late, float derate) { - DeratingFactorsNet *factors = findKey(net_derating_factors_, net); + DeratingFactors *factors = findKey(net_derating_factors_, net); if (factors == nullptr) { - factors = new DeratingFactorsNet; + factors = new DeratingFactors; net_derating_factors_[net] = factors; } factors->setFactor(clk_data, rf, early_late, derate); @@ -665,7 +665,7 @@ Sdc::timingDerateNet(const Pin *pin, const EarlyLate *early_late) const { const Net *net = network_->net(pin); - DeratingFactorsNet *factors = findKey(net_derating_factors_, net); + DeratingFactors *factors = findKey(net_derating_factors_, net); if (factors) { float factor; bool exists; @@ -719,7 +719,7 @@ Sdc::setDriveCell(const LibertyLibrary *library, const LibertyCell *cell, const Port *port, const LibertyPort *from_port, - float *from_slews, + const DriveCellSlews &from_slews, const LibertyPort *to_port, const RiseFallBoth *rf, const MinMaxAll *min_max) @@ -1960,7 +1960,7 @@ Sdc::makeClockGroups(std::string_view name, ClockGroups *groups = new ClockGroups(group_name, logically_exclusive, physically_exclusive, asynchronous, allow_paths, - std::move(comment)); + comment); clk_groups_name_map_[groups->name()] = groups; return groups; } diff --git a/sdc/Sdc.i b/sdc/Sdc.i index 60107704..996424b3 100644 --- a/sdc/Sdc.i +++ b/sdc/Sdc.i @@ -27,15 +27,17 @@ %include "std_string.i" %{ +#include "Sdc.hh" + #include -#include "Sdc.hh" -#include "Wireload.hh" #include "Clock.hh" +#include "FilterObjects.hh" #include "PortDelay.hh" #include "Property.hh" -#include "FilterObjects.hh" +#include "SdcClass.hh" #include "Sta.hh" +#include "Wireload.hh" using namespace sta; @@ -1076,7 +1078,7 @@ set_drive_cell_cmd(LibertyLibrary *library, { Sta *sta = Sta::sta(); Sdc *sdc = sta->cmdSdc(); - float from_slews[RiseFall::index_count]; + DriveCellSlews from_slews; from_slews[RiseFall::riseIndex()] = from_slew_rise; from_slews[RiseFall::fallIndex()] = from_slew_fall; sta->setDriveCell(library, cell, port, from_port, from_slews, diff --git a/sdc/SdcCmdComment.cc b/sdc/SdcCmdComment.cc index 805bb194..adbf6e4a 100644 --- a/sdc/SdcCmdComment.cc +++ b/sdc/SdcCmdComment.cc @@ -22,9 +22,10 @@ // // This notice may not be removed or altered from any source distribution. -#include "StringUtil.hh" #include "SdcCmdComment.hh" +#include "StringUtil.hh" + namespace sta { SdcCmdComment::SdcCmdComment(std::string_view comment) : diff --git a/sdc/Variables.cc b/sdc/Variables.cc index 90534a80..81650eb4 100644 --- a/sdc/Variables.cc +++ b/sdc/Variables.cc @@ -26,24 +26,6 @@ namespace sta { -Variables::Variables() : - crpr_enabled_(true), - crpr_mode_(CrprMode::same_pin), - propagate_gated_clock_enable_(true), - preset_clr_arcs_enabled_(false), - cond_default_arcs_enabled_(true), - bidirect_inst_paths_enabled_(false), - recovery_removal_checks_enabled_(true), - gated_clk_checks_enabled_(true), - clk_thru_tristate_enabled_(false), - dynamic_loop_breaking_(false), - propagate_all_clks_(false), - use_default_arrival_clock_(false), - pocv_mode_(PocvMode::scalar), - pocv_quantile_(3.0) -{ -} - void Variables::setCrprEnabled(bool enabled) { diff --git a/sdc/WriteSdc.cc b/sdc/WriteSdc.cc index c812c1ea..8f6d8caa 100644 --- a/sdc/WriteSdc.cc +++ b/sdc/WriteSdc.cc @@ -26,47 +26,47 @@ #include #include -#include #include #include #include +#include -#include "ContainerHelpers.hh" -#include "Format.hh" -#include "Zlib.hh" -#include "Report.hh" -#include "Error.hh" -#include "Units.hh" -#include "Transition.hh" -#include "Liberty.hh" -#include "Wireload.hh" -#include "Network.hh" -#include "PortDirection.hh" -#include "NetworkCmp.hh" -#include "Graph.hh" -#include "GraphCmp.hh" -#include "RiseFallValues.hh" -#include "PortDelay.hh" -#include "ExceptionPath.hh" -#include "PortExtCap.hh" -#include "DisabledPorts.hh" #include "ClockGroups.hh" #include "ClockInsertion.hh" #include "ClockLatency.hh" -#include "InputDrive.hh" +#include "ContainerHelpers.hh" #include "DataCheck.hh" #include "DeratingFactors.hh" -#include "Sdc.hh" +#include "DisabledPorts.hh" +#include "Error.hh" +#include "ExceptionPath.hh" +#include "Format.hh" #include "Fuzzy.hh" -#include "StaState.hh" +#include "Graph.hh" +#include "GraphCmp.hh" +#include "InputDrive.hh" +#include "Liberty.hh" +#include "Network.hh" +#include "NetworkCmp.hh" +#include "PortDelay.hh" +#include "PortDirection.hh" +#include "PortExtCap.hh" +#include "Report.hh" +#include "RiseFallValues.hh" #include "Scene.hh" +#include "Sdc.hh" +#include "StaState.hh" +#include "Transition.hh" +#include "Units.hh" #include "Variables.hh" +#include "Wireload.hh" #include "WriteSdcPvt.hh" +#include "Zlib.hh" namespace sta { -typedef std::set ClockSenseSet; -typedef std::vector ClockSenseSeq; +using ClockSenseSet = std::set; +using ClockSenseSeq = std::vector; static std::string_view transRiseFallFlag(const RiseFall *rf); @@ -88,7 +88,7 @@ timingDerateTypeKeyword(TimingDerateType type); class WriteSdcObject { public: - WriteSdcObject() {} + WriteSdcObject() = default; virtual ~WriteSdcObject() = default; virtual void write() const = 0; }; @@ -98,7 +98,7 @@ class WriteGetPort : public WriteSdcObject public: WriteGetPort(const Port *port, const WriteSdc *writer); - virtual void write() const; + void write() const override; private: const Port *port_; @@ -125,7 +125,7 @@ public: bool map_hpin_to_drvr, const Clock *clk, const WriteSdc *writer); - virtual void write() const; + void write() const override; private: const Pin *pin_; @@ -159,7 +159,7 @@ public: WriteGetPin(const Pin *pin, bool map_hpin_to_drvr, const WriteSdc *writer); - virtual void write() const; + void write() const override; private: const Pin *pin_; @@ -187,7 +187,7 @@ class WriteGetNet : public WriteSdcObject public: WriteGetNet(const Net *net, const WriteSdc *writer); - virtual void write() const; + void write() const override; private: const Net *net_; @@ -212,7 +212,7 @@ class WriteGetInstance : public WriteSdcObject public: WriteGetInstance(const Instance *inst, const WriteSdc *writer); - virtual void write() const; + void write() const override; private: const Instance *inst_; @@ -237,7 +237,7 @@ class WriteGetLibCell : public WriteSdcObject public: WriteGetLibCell(const LibertyCell *cell, const WriteSdc *writer); - virtual void write() const; + void write() const override; private: const LibertyCell *cell_; @@ -262,7 +262,7 @@ class WriteGetClock : public WriteSdcObject public: WriteGetClock(const Clock *clk, const WriteSdc *writer); - virtual void write() const; + void write() const override; private: const Clock *clk_; @@ -321,10 +321,6 @@ WriteSdc::WriteSdc(const Sdc *sdc, { } -WriteSdc::~WriteSdc() -{ -} - void WriteSdc::write(std::string_view filename, bool gzip) @@ -1666,7 +1662,7 @@ WriteSdc::writeDrivingCell(Port *port, const LibertyCell *cell = drive_cell->cell(); const LibertyPort *from_port = drive_cell->fromPort(); const LibertyPort *to_port = drive_cell->toPort(); - float *from_slews = drive_cell->fromSlews(); + const DriveCellSlews &from_slews = drive_cell->fromSlews(); const LibertyLibrary *lib = drive_cell->library(); sta::print(stream_, "set_driving_cell"); if (rf) @@ -1888,7 +1884,7 @@ WriteSdc::writeDerating(DeratingFactorsGlobal *factors) const } } else { - for (int type_index = 0; + for (size_t type_index = 0; type_index < timing_derate_type_count; type_index++) { TimingDerateType type = static_cast(type_index); @@ -1935,7 +1931,7 @@ WriteSdc::writeDerating(DeratingFactors *factors, } } else { - for (int clk_data_index = 0; + for (size_t clk_data_index = 0; clk_data_index < path_clk_or_data_count; clk_data_index++) { PathClkOrData clk_data = static_cast(clk_data_index); @@ -2855,7 +2851,7 @@ setupHoldFlag(const MinMax *min_max) void WriteSdc::writeCmdComment(SdcCmdComment *cmd) const { - const std::string comment = cmd->comment(); + const std::string &comment = cmd->comment(); if (!comment.empty()) sta::print(stream_, " -comment {{{}}}", comment); } diff --git a/sdc/WriteSdcPvt.hh b/sdc/WriteSdcPvt.hh index ad6b3c58..94a1a591 100644 --- a/sdc/WriteSdcPvt.hh +++ b/sdc/WriteSdcPvt.hh @@ -27,10 +27,10 @@ #include #include -#include "Zlib.hh" -#include "NetworkClass.hh" #include "GraphClass.hh" +#include "NetworkClass.hh" #include "Sdc.hh" +#include "Zlib.hh" namespace sta { @@ -46,7 +46,7 @@ public: bool native, int digits, bool no_timestamp); - virtual ~WriteSdc(); + ~WriteSdc() override = default; void write(std::string_view filename, bool gzip); diff --git a/sdf/ReportAnnotation.cc b/sdf/ReportAnnotation.cc index dce57ee1..cca76e65 100644 --- a/sdf/ReportAnnotation.cc +++ b/sdf/ReportAnnotation.cc @@ -26,15 +26,15 @@ #include -#include "StringUtil.hh" -#include "Report.hh" -#include "TimingRole.hh" -#include "TimingArc.hh" -#include "Liberty.hh" -#include "Network.hh" #include "Graph.hh" #include "GraphCmp.hh" +#include "Liberty.hh" +#include "Network.hh" +#include "Report.hh" #include "Sdc.hh" +#include "StringUtil.hh" +#include "TimingArc.hh" +#include "TimingRole.hh" namespace sta { @@ -126,16 +126,16 @@ void reportAnnotatedDelay(const Scene *scene, bool report_cells, bool report_nets, - bool from_in_ports, - bool to_out_ports, + bool report_in_ports, + bool report_out_ports, int max_lines, bool report_annotated, bool report_unannotated, bool report_constant_arcs, StaState *sta) { - ReportAnnotated report(scene, report_cells, report_nets, from_in_ports, - to_out_ports, max_lines, report_annotated, + ReportAnnotated report(scene, report_cells, report_nets, report_in_ports, + report_out_ports, max_lines, report_annotated, report_unannotated, report_constant_arcs, sta); report.reportDelayAnnotation(); } diff --git a/sdf/Sdf.i b/sdf/Sdf.i index 89b1fdd2..271e9f60 100644 --- a/sdf/Sdf.i +++ b/sdf/Sdf.i @@ -26,10 +26,11 @@ %{ #include -#include "sdf/ReportAnnotation.hh" -#include "sdf/SdfWriter.hh" + #include "Search.hh" #include "Sta.hh" +#include "sdf/ReportAnnotation.hh" +#include "sdf/SdfWriter.hh" using sta::Sta; using sta::AnalysisType; diff --git a/sdf/SdfParse.yy b/sdf/SdfParse.yy index 7570f5df..68e05c57 100644 --- a/sdf/SdfParse.yy +++ b/sdf/SdfParse.yy @@ -44,6 +44,22 @@ sta::SdfParse::error(const location_type &loc, } %} +%code requires { +#include +#include +#include "StringUtil.hh" + +namespace sta { +class SdfScanner; +class SdfReader; +class Transition; +class SdfPortSpec; +class SdfTriple; + +using SdfTripleSeq = std::vector; +} +} + %require "3.2" %skeleton "lalr1.cc" %debug diff --git a/sdf/SdfReader.cc b/sdf/SdfReader.cc index 6a5bfd0b..007de2ba 100644 --- a/sdf/SdfReader.cc +++ b/sdf/SdfReader.cc @@ -24,24 +24,24 @@ #include "sdf/SdfReader.hh" -#include #include +#include #include #include #include "ContainerHelpers.hh" -#include "Zlib.hh" -#include "Error.hh" #include "Debug.hh" -#include "Stats.hh" -#include "Report.hh" -#include "MinMax.hh" -#include "TimingArc.hh" -#include "Network.hh" -#include "SdcNetwork.hh" +#include "Error.hh" #include "Graph.hh" +#include "MinMax.hh" +#include "Network.hh" +#include "Report.hh" #include "Scene.hh" #include "Sdc.hh" +#include "SdcNetwork.hh" +#include "Stats.hh" +#include "TimingArc.hh" +#include "Zlib.hh" #include "sdf/SdfReaderPvt.hh" #include "sdf/SdfScanner.hh" @@ -107,20 +107,12 @@ SdfReader::SdfReader(std::string_view filename, StaState(sta), filename_(filename), path_(path), - triple_min_index_(0), - triple_max_index_(2), arc_delay_min_index_(arc_min_index), arc_delay_max_index_(arc_max_index), analysis_type_(analysis_type), unescaped_dividers_(unescaped_dividers), is_incremental_only_(is_incremental_only), - cond_use_(cond_use), - divider_('/'), - escape_('\\'), - instance_(nullptr), - in_timing_check_(false), - in_incremental_(false), - timescale_(1.0E-9F) // default units of ns + cond_use_(cond_use) { if (unescaped_dividers) network_ = makeSdcNetwork(network_); @@ -747,7 +739,7 @@ SdfReader::setEdgeArcDelaysCondUse(Edge *edge, void SdfReader::setEdgeArcDelaysCondUse(Edge *edge, TimingArc *arc, - float *value, + const float *value, int triple_index, int arc_delay_index, const MinMax *min_max) @@ -819,11 +811,11 @@ SdfReader::makeCondPortSpec(std::string_view cond_port) // Search from end to find port name because condition may contain spaces. std::string cond_port1(cond_port); trimRight(cond_port1); - auto port_idx = cond_port1.find_last_of(" "); - if (port_idx != cond_port1.npos) { + auto port_idx = cond_port1.find_last_of(' '); + if (port_idx != std::string::npos) { std::string port1 = cond_port1.substr(port_idx + 1); - size_t cond_end = cond_port1.find_last_not_of(" ", port_idx); - if (cond_end != cond_port1.npos) { + size_t cond_end = cond_port1.find_last_not_of(' ', port_idx); + if (cond_end != std::string::npos) { std::string cond1 = cond_port1.substr(0, cond_end + 1); return new SdfPortSpec(Transition::riseFall(), port1, cond1); } @@ -847,7 +839,7 @@ SdfReader::deleteTripleSeq(SdfTripleSeq *triples) SdfTriple * SdfReader::makeTriple() { - return new SdfTriple(0, 0, 0); + return new SdfTriple(nullptr, nullptr, nullptr); } SdfTriple * diff --git a/sdf/SdfReaderPvt.hh b/sdf/SdfReaderPvt.hh index 226e3151..3a53e391 100644 --- a/sdf/SdfReaderPvt.hh +++ b/sdf/SdfReaderPvt.hh @@ -28,14 +28,14 @@ #include #include -#include "TimingRole.hh" -#include "Transition.hh" +#include "GraphClass.hh" #include "LibertyClass.hh" #include "NetworkClass.hh" -#include "GraphClass.hh" #include "Report.hh" #include "SdcClass.hh" #include "StaState.hh" +#include "TimingRole.hh" +#include "Transition.hh" namespace sta { @@ -58,7 +58,7 @@ public: bool is_incremental_only, MinMaxAll *cond_use, StaState *sta); - ~SdfReader(); + ~SdfReader() override; bool read(); void setDivider(char divider); @@ -80,7 +80,7 @@ public: SdfTriple *triple); void setEdgeArcDelaysCondUse(Edge *edge, TimingArc *arc, - float *value, + const float *value, int triple_index, int arc_delay_index, const MinMax *min_max); @@ -126,7 +126,7 @@ public: void port(std::string_view o_pin_name, SdfTripleSeq *triples); void device(SdfTripleSeq *triples); - void device(std::string_view to_pin_name, + void device(std::string_view to_port_name, SdfTripleSeq *triples); SdfTriple *makeTriple(); @@ -151,7 +151,7 @@ public: void setInTimingCheck(bool in); bool inIncremental() const { return in_incremental_; } void setInIncremental(bool incr); - std::string makeBusName(std::string_view bus_name, + std::string makeBusName(std::string_view base_name, int index); std::string_view filename() const { return filename_; } int sdfLine() const; @@ -209,8 +209,8 @@ private: SdfScanner *scanner_; std::string_view path_; // Which values to pull out of the sdf triples. - int triple_min_index_; - int triple_max_index_; + int triple_min_index_{0}; + int triple_max_index_{2}; // Which arc delay value to deposit the sdf values into. int arc_delay_min_index_; int arc_delay_max_index_; @@ -219,13 +219,13 @@ private: bool is_incremental_only_; MinMaxAll *cond_use_; - char divider_; - char escape_; - Instance *instance_; + char divider_{'/'}; + char escape_{'\\'}; + Instance *instance_{nullptr}; std::string cell_name_; - bool in_timing_check_; - bool in_incremental_; - float timescale_; + bool in_timing_check_{false}; + bool in_incremental_{false}; + float timescale_{1.0E-9F}; // default units of ns static const int null_index_ = -1; }; diff --git a/sdf/SdfScanner.hh b/sdf/SdfScanner.hh index 87fc8587..8d0d5b43 100644 --- a/sdf/SdfScanner.hh +++ b/sdf/SdfScanner.hh @@ -46,7 +46,7 @@ public: std::string_view filename, SdfReader *reader, Report *report); - virtual int lex(SdfParse::semantic_type *const yylval, + virtual int lex(SdfParse::semantic_type *yylval, SdfParse::location_type *yylloc); // YY_DECL defined in SdfLex.ll // Method body created by flex in SdfLex.cc diff --git a/sdf/SdfWriter.cc b/sdf/SdfWriter.cc index 7607af78..79750e88 100644 --- a/sdf/SdfWriter.cc +++ b/sdf/SdfWriter.cc @@ -30,21 +30,21 @@ #include #include "Format.hh" -#include "Zlib.hh" -#include "StaConfig.hh" // STA_VERSION #include "Fuzzy.hh" -#include "StringUtil.hh" -#include "Units.hh" -#include "TimingRole.hh" -#include "TimingArc.hh" -#include "Liberty.hh" -#include "Sdc.hh" -#include "MinMaxValues.hh" -#include "Network.hh" #include "Graph.hh" #include "GraphDelayCalc.hh" -#include "StaState.hh" +#include "Liberty.hh" +#include "MinMaxValues.hh" +#include "Network.hh" #include "Scene.hh" +#include "Sdc.hh" +#include "StaConfig.hh" // STA_VERSION +#include "StaState.hh" +#include "StringUtil.hh" +#include "TimingArc.hh" +#include "TimingRole.hh" +#include "Units.hh" +#include "Zlib.hh" namespace sta { @@ -118,7 +118,7 @@ private: bool include_typ_; float timescale_; - char sdf_escape_; + char sdf_escape_{'\\'}; char network_escape_; int digits_; @@ -146,7 +146,6 @@ writeSdf(std::string_view filename, SdfWriter::SdfWriter(StaState *sta) : StaState(sta), - sdf_escape_('\\'), network_escape_(network_->pathEscape()) { } diff --git a/search/CheckCapacitances.cc b/search/CheckCapacitances.cc index cb6a7b47..24983ba5 100644 --- a/search/CheckCapacitances.cc +++ b/search/CheckCapacitances.cc @@ -160,7 +160,7 @@ CheckCapacitances::findLimit(const Pin *pin, for (auto rf : RiseFall::range()) { const LibertyCell *cell; const LibertyPort *from_port; - float *from_slews; + const DriveCellSlews *from_slews; const LibertyPort *to_port; drive->driveCell(rf, min_max, cell, from_port, from_slews, to_port); if (to_port) { diff --git a/search/CheckFanouts.cc b/search/CheckFanouts.cc index 7b3dc2c1..b5ffae22 100644 --- a/search/CheckFanouts.cc +++ b/search/CheckFanouts.cc @@ -111,10 +111,10 @@ CheckFanouts::findLimit(const Pin *pin, } InputDrive *drive = sdc->findInputDrive(port); if (drive) { - for (auto rf : RiseFall::range()) { + for (const RiseFall *rf : RiseFall::range()) { const LibertyCell *cell; const LibertyPort *from_port; - float *from_slews; + const DriveCellSlews *from_slews; const LibertyPort *to_port; drive->driveCell(rf, min_max, cell, from_port, from_slews, to_port); if (to_port) { diff --git a/search/CheckSlews.cc b/search/CheckSlews.cc index 5ba9436a..748cc336 100644 --- a/search/CheckSlews.cc +++ b/search/CheckSlews.cc @@ -297,7 +297,7 @@ CheckSlews::findLimit(const Pin *pin, for (auto rf : RiseFall::range()) { const LibertyCell *cell; const LibertyPort *from_port; - float *from_slews; + const DriveCellSlews *from_slews; const LibertyPort *to_port; drive->driveCell(rf, min_max, cell, from_port, from_slews, to_port); if (to_port) { diff --git a/search/Sta.cc b/search/Sta.cc index 0aca01e0..c6230d42 100644 --- a/search/Sta.cc +++ b/search/Sta.cc @@ -956,7 +956,7 @@ Sta::setDriveCell(const LibertyLibrary *library, const LibertyCell *cell, const Port *port, const LibertyPort *from_port, - float *from_slews, + const DriveCellSlews &from_slews, const LibertyPort *to_port, const RiseFallBoth *rf, const MinMaxAll *min_max, diff --git a/spice/WritePathSpice.cc b/spice/WritePathSpice.cc index c414317d..842b2620 100644 --- a/spice/WritePathSpice.cc +++ b/spice/WritePathSpice.cc @@ -24,35 +24,36 @@ #include "WritePathSpice.hh" +#include #include #include #include #include "Debug.hh" #include "Error.hh" -#include "Report.hh" #include "Format.hh" -#include "StringUtil.hh" #include "FuncExpr.hh" -#include "Units.hh" -#include "Sequential.hh" -#include "Liberty.hh" -#include "TimingArc.hh" -#include "TableModel.hh" -#include "PortDirection.hh" -#include "Network.hh" #include "Graph.hh" -#include "Sdc.hh" +#include "Liberty.hh" +#include "Network.hh" #include "Parasitics.hh" #include "Path.hh" #include "PathExpanded.hh" +#include "PortDirection.hh" +#include "Report.hh" +#include "Sdc.hh" +#include "Sequential.hh" #include "StaState.hh" -#include "search/Sim.hh" +#include "StringUtil.hh" +#include "TableModel.hh" +#include "TimingArc.hh" +#include "Units.hh" #include "WriteSpice.hh" +#include "search/Sim.hh" namespace sta { -typedef int Stage; +using Stage = int; //////////////////////////////////////////////////////////////// @@ -138,7 +139,7 @@ private: const Path *path_; PathExpanded path_expanded_; // Input clock waveform cycles. - int clk_cycle_count_; + int clk_cycle_count_{3}; InstanceSet written_insts_; @@ -184,7 +185,6 @@ WritePathSpice::WritePathSpice(const Path *path, path->scene(sta), path->minMax(sta), sta), path_(path), path_expanded_(sta), - clk_cycle_count_(3), written_insts_(network_) { initPowerGnd(); @@ -269,13 +269,11 @@ WritePathSpice::pathMaxTime() Edge *edge = edge_iter.next(); Vertex *load = edge->to(graph_); float load_slew = railToRailSlew(findSlew(load, rf, nullptr), rf); - if (load_slew > path_max_slew) - path_max_slew = load_slew; + path_max_slew = std::max(load_slew, path_max_slew); } } float path_max_time = delayAsFloat(path->arrival()) + path_max_slew * 2.0; - if (path_max_time > max_time) - max_time = path_max_time; + max_time = std::max(path_max_time, max_time); } return max_time; } diff --git a/spice/WriteSpice.cc b/spice/WriteSpice.cc index 1823080c..6d3f9395 100644 --- a/spice/WriteSpice.cc +++ b/spice/WriteSpice.cc @@ -30,26 +30,25 @@ #include #include -#include "cudd.h" - +#include "Bdd.hh" +#include "Clock.hh" #include "ContainerHelpers.hh" #include "Debug.hh" -#include "Units.hh" -#include "TableModel.hh" -#include "TimingRole.hh" #include "FuncExpr.hh" -#include "Sequential.hh" -#include "PortDirection.hh" -#include "TimingArc.hh" -#include "Liberty.hh" -#include "Network.hh" #include "Graph.hh" -#include "search/Sim.hh" -#include "Clock.hh" -#include "Path.hh" -#include "Bdd.hh" -#include "Sdc.hh" +#include "Liberty.hh" #include "Mode.hh" +#include "Network.hh" +#include "Path.hh" +#include "PortDirection.hh" +#include "Sdc.hh" +#include "Sequential.hh" +#include "TableModel.hh" +#include "TimingArc.hh" +#include "TimingRole.hh" +#include "Units.hh" +#include "cudd.h" +#include "search/Sim.hh" namespace sta { @@ -78,10 +77,6 @@ WriteSpice::WriteSpice(std::string_view spice_filename, scene_(scene), min_max_(min_max), default_library_(network_->defaultLibertyLibrary()), - short_ckt_resistance_(.0001), - cap_index_(1), - res_index_(1), - volt_index_(1), bdd_(sta), parasitics_(scene->parasitics(min_max)) { diff --git a/spice/WriteSpice.hh b/spice/WriteSpice.hh index 2ac35b33..5230b72b 100644 --- a/spice/WriteSpice.hh +++ b/spice/WriteSpice.hh @@ -25,19 +25,19 @@ #pragma once #include +#include #include #include -#include #include -#include "Format.hh" -#include "StaState.hh" -#include "StringUtil.hh" -#include "Liberty.hh" -#include "GraphClass.hh" -#include "Parasitics.hh" #include "Bdd.hh" #include "CircuitSim.hh" +#include "Format.hh" +#include "GraphClass.hh" +#include "Liberty.hh" +#include "Parasitics.hh" +#include "StaState.hh" +#include "StringUtil.hh" namespace sta { @@ -96,7 +96,7 @@ protected: const NetSet &coupling_nets); void writeParasiticNetwork(const Pin *drvr_pin, const Parasitic *parasitic, - const NetSet &aggressor_nets); + const NetSet &coupling_nets); void writePiElmore(const Pin *drvr_pin, const Parasitic *parasitic); void writeNullParasitic(const Pin *drvr_pin); @@ -181,12 +181,12 @@ protected: float gnd_voltage_; float max_time_; // Resistance to use to simulate a short circuit between spice nodes. - float short_ckt_resistance_; + float short_ckt_resistance_{0.0001F}; // Input clock waveform cycles. // Sequential device numbers. - int cap_index_; - int res_index_; - int volt_index_; + int cap_index_{1}; + int res_index_{1}; + int volt_index_{1}; CellSpicePortNames cell_spice_port_names_; Bdd bdd_; Parasitics *parasitics_; diff --git a/util/Error.cc b/util/Error.cc index 553bc29a..2ca81a1d 100644 --- a/util/Error.cc +++ b/util/Error.cc @@ -32,10 +32,6 @@ namespace sta { -Exception::Exception() -{ -} - ExceptionMsg::ExceptionMsg(const std::string &msg, bool suppressed) : msg_(msg), diff --git a/util/FlexDisableRegister.hh b/util/FlexDisableRegister.hh index 64983ba7..52943946 100644 --- a/util/FlexDisableRegister.hh +++ b/util/FlexDisableRegister.hh @@ -3,4 +3,3 @@ #if !(YY_FLEX_MAJOR_VERSION >= 2 && YY_FLEX_MINOR_VERSION >= 6) && __cplusplus > 199711L #define register #endif - diff --git a/util/gzstream.hh b/util/gzstream.hh index 26e85352..26b16174 100644 --- a/util/gzstream.hh +++ b/util/gzstream.hh @@ -211,4 +211,4 @@ public: } }; -} // namespace GZSTREAM_NAMESPACE +} // namespace gzstream diff --git a/verilog/Verilog.i b/verilog/Verilog.i index 3a60be30..82647cff 100644 --- a/verilog/Verilog.i +++ b/verilog/Verilog.i @@ -25,8 +25,8 @@ %module verilog %{ -#include "VerilogWriter.hh" #include "Sta.hh" +#include "VerilogWriter.hh" %} %inline %{ diff --git a/verilog/VerilogParse.yy b/verilog/VerilogParse.yy index c5a1c8cd..3103c3be 100644 --- a/verilog/VerilogParse.yy +++ b/verilog/VerilogParse.yy @@ -49,6 +49,31 @@ sta::VerilogParse::error(const location_type &loc, %} +%code requires { +#include +#include + +namespace sta { +class PortDirection; +class VerilogAssign; +class VerilogAttr; +class VerilogAttrEntry; +class VerilogAttrStmt; +class VerilogDclArg; +class VerilogNet; +class VerilogReader; +class VerilogScanner; +class VerilogStmt; + +using VerilogAttrEntrySeq = std::vector; +using VerilogAttrSeq = std::vector; +using VerilogAttrStmtSeq = std::vector; +using VerilogDclArgSeq = std::vector; +using VerilogNetSeq = std::vector; +using VerilogStmtSeq = std::vector; +} +} + %require "3.2" %skeleton "lalr1.cc" %debug diff --git a/verilog/VerilogReader.cc b/verilog/VerilogReader.cc index d9f76747..263acb4a 100644 --- a/verilog/VerilogReader.cc +++ b/verilog/VerilogReader.cc @@ -24,27 +24,28 @@ #include "VerilogReader.hh" +#include #include #include #include #include "ContainerHelpers.hh" -#include "Zlib.hh" #include "Debug.hh" -#include "Report.hh" #include "Error.hh" -#include "Stats.hh" #include "Liberty.hh" -#include "PortDirection.hh" #include "Network.hh" -#include "VerilogNamespace.hh" +#include "PortDirection.hh" +#include "Report.hh" +#include "Stats.hh" #include "StringUtil.hh" +#include "VerilogNamespace.hh" +#include "Zlib.hh" #include "verilog/VerilogReaderPvt.hh" #include "verilog/VerilogScanner.hh" namespace sta { -using VerilogConstant10 = unsigned long long; +using VerilogConstant10 = std::uint64_t; static std::string verilogBusBitName(std::string_view bus_name, @@ -111,8 +112,6 @@ VerilogReader::VerilogReader(NetworkReader *network) : report_(network->report()), debug_(network->debug()), network_(network), - library_(nullptr), - black_box_index_(0), zero_net_name_("zero_"), one_net_name_("one_") { @@ -476,7 +475,7 @@ bool VerilogReader::hasScalarNamedPortRefs(LibertyCell *liberty_cell, VerilogNetSeq *pins) { - if (pins && pins->size() > 0 && (*pins)[0]->isNamedPortRef()) { + if (pins && !pins->empty() && (*pins)[0]->isNamedPortRef()) { for (VerilogNet *vpin : *pins) { std::string_view port_name = vpin->name(); LibertyPort *port = liberty_cell->findLibertyPort(port_name); @@ -724,13 +723,13 @@ VerilogModuleInst::~VerilogModuleInst() bool VerilogModuleInst::hasPins() { - return pins_ && pins_->size() > 0; + return pins_ && !pins_->empty(); } bool VerilogModuleInst::namedPins() { - return pins_ && pins_->size() > 0 && (*pins_)[0]->isNamedPortRef(); + return pins_ && !pins_->empty() && (*pins_)[0]->isNamedPortRef(); } VerilogLibertyInst::VerilogLibertyInst(LibertyCell *cell, @@ -879,12 +878,11 @@ public: protected: std::string name_; - bool has_next_; + bool has_next_{true}; }; VerilogOneNetNameIterator::VerilogOneNetNameIterator(const std::string &name) : - name_(name), - has_next_(true) + name_(name) { } @@ -904,7 +902,7 @@ VerilogOneNetNameIterator::next() class VerilogBusNetNameIterator : public VerilogNetNameIterator { public: - VerilogBusNetNameIterator(const std::string bus_name, + VerilogBusNetNameIterator(std::string_view bus_name, int from_index, int to_index); bool hasNext() override; @@ -918,7 +916,7 @@ protected: std::string bit_name_; }; -VerilogBusNetNameIterator::VerilogBusNetNameIterator(const std::string bus_name, +VerilogBusNetNameIterator::VerilogBusNetNameIterator(std::string_view bus_name, int from_index, int to_index) : bus_name_(bus_name), @@ -1007,7 +1005,7 @@ private: VerilogReader *reader_; VerilogNetSeq *nets_; VerilogNetSeq::iterator net_iter_; - VerilogNetNameIterator *net_name_iter_; + VerilogNetNameIterator *net_name_iter_{nullptr}; }; VerilogNetConcatNameIterator::VerilogNetConcatNameIterator(VerilogNetSeq *nets, @@ -1016,8 +1014,7 @@ VerilogNetConcatNameIterator::VerilogNetConcatNameIterator(VerilogNetSeq *nets, module_(module), reader_(reader), nets_(nets), - net_iter_(nets->begin()), - net_name_iter_(nullptr) + net_iter_(nets->begin()) { if (net_iter_ != nets_->end()) { VerilogNet *net = *net_iter_++; diff --git a/verilog/VerilogReaderPvt.hh b/verilog/VerilogReaderPvt.hh index e3569c61..c425a387 100644 --- a/verilog/VerilogReaderPvt.hh +++ b/verilog/VerilogReaderPvt.hh @@ -24,12 +24,13 @@ #pragma once +#include #include #include #include -#include #include "StringUtil.hh" +#include "VerilogReader.hh" namespace sta { @@ -98,10 +99,10 @@ public: VerilogDclArg *arg, VerilogAttrStmtSeq *attr_stmts, int line); - virtual ~VerilogDcl(); + ~VerilogDcl() override; const std::string &portName(); virtual bool isBus() const { return false; } - virtual bool isDeclaration() const { return true; } + bool isDeclaration() const override { return true; } VerilogDclArgSeq *args() const { return args_; } void appendArg(VerilogDclArg *arg); PortDirection *direction() const { return dir_; } @@ -177,7 +178,7 @@ class VerilogInst : public VerilogStmt public: VerilogInst(std::string_view inst_name, VerilogAttrStmtSeq *attr_stmts, - const int line); + int line); ~VerilogInst() override; bool isInstance() const override { return true; } const std::string &instanceName() const { return inst_name_; } @@ -196,7 +197,7 @@ public: std::string_view inst_name, VerilogNetSeq *pins, VerilogAttrStmtSeq *attr_stmts, - const int line); + int line); ~VerilogModuleInst() override; bool isModuleInst() const override { return true; } const std::string &moduleName() const { return module_name_; } @@ -219,7 +220,7 @@ public: std::string_view inst_name, const StringSeq &net_names, VerilogAttrStmtSeq *attr_stmts, - const int line); + int line); bool isLibertyInst() const override { return true; } LibertyCell *cell() const { return cell_; } const StringSeq &netNames() const { return net_names_; } @@ -246,7 +247,6 @@ public: class VerilogNetUnnamed : public VerilogNet { public: - VerilogNetUnnamed() {} bool isNamed() const override { return false; } const std::string &name() const override { return null_; } diff --git a/verilog/VerilogScanner.hh b/verilog/VerilogScanner.hh index 92b0d395..092c7285 100644 --- a/verilog/VerilogScanner.hh +++ b/verilog/VerilogScanner.hh @@ -39,6 +39,7 @@ namespace sta { class Report; +class VerilogReader; class VerilogScanner : public VerilogFlexLexer { @@ -46,7 +47,7 @@ public: VerilogScanner(std::istream *stream, std::string_view filename, Report *report); - virtual int lex(VerilogParse::semantic_type *const yylval, + virtual int lex(VerilogParse::semantic_type *yylval, VerilogParse::location_type *yylloc); // YY_DECL defined in VerilogLex.ll // Method body created by flex in VerilogLex.cc diff --git a/verilog/VerilogWriter.cc b/verilog/VerilogWriter.cc index 954c560a..4f5e5fc6 100644 --- a/verilog/VerilogWriter.cc +++ b/verilog/VerilogWriter.cc @@ -33,11 +33,11 @@ #include "Error.hh" #include "Format.hh" #include "Liberty.hh" -#include "PortDirection.hh" #include "Network.hh" #include "NetworkCmp.hh" -#include "VerilogNamespace.hh" #include "ParseBus.hh" +#include "PortDirection.hh" +#include "VerilogNamespace.hh" namespace sta { @@ -84,7 +84,7 @@ protected: CellSet remove_cells_; FILE *stream_; Network *network_; - int unconnected_net_index_; + int unconnected_net_index_{1}; }; void @@ -115,8 +115,7 @@ VerilogWriter::VerilogWriter(const char *filename, include_pwr_gnd_(include_pwr_gnd), remove_cells_(network), stream_(stream), - network_(network), - unconnected_net_index_(1) + network_(network) { if (remove_cells) { for(Cell *lib_cell : *remove_cells)