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power gated clks 

Signed-off-by: James Cherry <cherry@parallaxsw.com>
This commit is contained in:
James Cherry 2022-12-16 11:27:52 -10:00
parent 61b10cd221
commit 1ac7d48d02
1 changed files with 11 additions and 15 deletions
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26
power/Power.cc
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@ -395,28 +395,24 @@ PropActivityVisitor::visit(Vertex *vertex)
}
}
LibertyCell *cell = network_->libertyCell(inst);
if (network_->isLoad(pin)) {
if (cell && cell->hasSequentials()) {
if (network_->isLoad(pin) && cell) {
if (cell->hasSequentials()) {
debugPrint(debug_, "power_activity", 3, "pending seq %s",
network_->pathName(inst));
visited_regs_->insert(inst);
found_reg_without_activity_ |= input_without_activity;
}
}
bfs_->enqueueAdjacentVertices(vertex);
// ca53 gf12 failing
#if 0
// Gated clock cells latch the enable so there is no EN->GCLK timing arc.
if (cell && cell->isClockGate()) {
const Pin *enable, *clk, *gclk;
power_->clockGatePins(inst, enable, clk, gclk);
if (gclk) {
Vertex *gclk_vertex = graph_->pinDrvrVertex(gclk);
bfs_->enqueue(gclk_vertex);
// Gated clock cells latch the enable so there is no EN->GCLK timing arc.
if (cell->isClockGate()) {
const Pin *enable, *clk, *gclk;
power_->clockGatePins(inst, enable, clk, gclk);
if (gclk) {
Vertex *gclk_vertex = graph_->pinDrvrVertex(gclk);
bfs_->enqueue(gclk_vertex);
}
}
}
#endif
bfs_->enqueueAdjacentVertices(vertex);
}
void