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tmp rm gated clk power 

Signed-off-by: James Cherry <cherry@parallaxsw.com>
This commit is contained in:
James Cherry 2022-12-15 17:42:41 -10:00
parent 2f9541386d
commit 61b10cd221
1 changed files with 7 additions and 2 deletions
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9
power/Power.cc
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@ -405,13 +405,18 @@ PropActivityVisitor::visit(Vertex *vertex)
}
bfs_->enqueueAdjacentVertices(vertex);
// ca53 gf12 failing
#if 0
// Gated clock cells latch the enable so there is no EN->GCLK timing arc.
if (cell && cell->isClockGate()) {
const Pin *enable, *clk, *gclk;
power_->clockGatePins(inst, enable, clk, gclk);
Vertex *gclk_vertex = graph_->pinDrvrVertex(gclk);
bfs_->enqueue(gclk_vertex);
if (gclk) {
Vertex *gclk_vertex = graph_->pinDrvrVertex(gclk);
bfs_->enqueue(gclk_vertex);
}
}
#endif
}
void