Tag::clkInfo const
Signed-off-by: James Cherry <cherry@parallaxsw.com>
This commit is contained in:
parent
8580cfd813
commit
17cf87b4c6
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@ -41,7 +41,7 @@ class Path
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{
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{
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public:
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public:
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Path();
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Path();
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Path(Path *path);
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Path(const Path *path);
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Path(Vertex *vertex,
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Path(Vertex *vertex,
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Tag *tag,
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Tag *tag,
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const StaState *sta);
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const StaState *sta);
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@ -89,7 +89,7 @@ public:
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TagIndex tagIndex(const StaState *sta) const;
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TagIndex tagIndex(const StaState *sta) const;
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void setTag(Tag *tag);
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void setTag(Tag *tag);
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size_t pathIndex(const StaState *sta) const;
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size_t pathIndex(const StaState *sta) const;
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ClkInfo *clkInfo(const StaState *sta) const;
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const ClkInfo *clkInfo(const StaState *sta) const;
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const ClockEdge *clkEdge(const StaState *sta) const;
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const ClockEdge *clkEdge(const StaState *sta) const;
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const Clock *clock(const StaState *sta) const;
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const Clock *clock(const StaState *sta) const;
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bool isClock(const StaState *sta) const;
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bool isClock(const StaState *sta) const;
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@ -64,7 +64,7 @@ class CheckCrpr;
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class Genclks;
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class Genclks;
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class Corner;
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class Corner;
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typedef Set<ClkInfo*, ClkInfoLess> ClkInfoSet;
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typedef Set<const ClkInfo*, ClkInfoLess> ClkInfoSet;
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typedef UnorderedSet<Tag*, TagHash, TagEqual> TagSet;
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typedef UnorderedSet<Tag*, TagHash, TagEqual> TagSet;
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typedef UnorderedSet<TagGroup*, TagGroupHash, TagGroupEqual> TagGroupSet;
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typedef UnorderedSet<TagGroup*, TagGroupHash, TagGroupEqual> TagGroupSet;
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typedef Map<Vertex*, Slack> VertexSlackMap;
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typedef Map<Vertex*, Slack> VertexSlackMap;
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@ -158,7 +158,7 @@ public:
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// Clock arrival respecting ideal clock insertion delay and latency.
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// Clock arrival respecting ideal clock insertion delay and latency.
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Arrival clkPathArrival(const Path *clk_path) const;
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Arrival clkPathArrival(const Path *clk_path) const;
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Arrival clkPathArrival(const Path *clk_path,
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Arrival clkPathArrival(const Path *clk_path,
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ClkInfo *clk_info,
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const ClkInfo *clk_info,
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const ClockEdge *clk_edge,
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const ClockEdge *clk_edge,
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const MinMax *min_max,
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const MinMax *min_max,
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const PathAnalysisPt *path_ap) const;
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const PathAnalysisPt *path_ap) const;
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@ -244,7 +244,7 @@ public:
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const RiseFall *from_rf,
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const RiseFall *from_rf,
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const Clock *clk,
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const Clock *clk,
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const RiseFall *clk_rf,
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const RiseFall *clk_rf,
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ClkInfo *clk_info,
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const ClkInfo *clk_info,
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const Pin *to_pin,
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const Pin *to_pin,
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const RiseFall *to_rf,
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const RiseFall *to_rf,
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const MinMax *min_max,
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const MinMax *min_max,
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@ -263,20 +263,20 @@ public:
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bool arc_delay_min_max_eq,
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bool arc_delay_min_max_eq,
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const MinMax *min_max,
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const MinMax *min_max,
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const PathAnalysisPt *path_ap);
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const PathAnalysisPt *path_ap);
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ClkInfo *thruClkInfo(Path *from_path,
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const ClkInfo *thruClkInfo(Path *from_path,
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Vertex *from_vertex,
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Vertex *from_vertex,
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ClkInfo *from_clk_info,
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const ClkInfo *from_clk_info,
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bool from_is_clk,
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bool from_is_clk,
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Edge *edge,
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Edge *edge,
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Vertex *to_vertex,
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Vertex *to_vertex,
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const Pin *to_pin,
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const Pin *to_pin,
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bool to_is_clk,
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bool to_is_clk,
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bool arc_delay_min_max_eq,
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bool arc_delay_min_max_eq,
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const MinMax *min_max,
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const MinMax *min_max,
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const PathAnalysisPt *path_ap);
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const PathAnalysisPt *path_ap);
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ClkInfo *clkInfoWithCrprClkPath(ClkInfo *from_clk_info,
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const ClkInfo *clkInfoWithCrprClkPath(const ClkInfo *from_clk_info,
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Path *from_path,
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Path *from_path,
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const PathAnalysisPt *path_ap);
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const PathAnalysisPt *path_ap);
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void seedClkArrivals(const Pin *pin,
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void seedClkArrivals(const Pin *pin,
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Vertex *vertex,
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Vertex *vertex,
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TagGroupBldr *tag_bldr);
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TagGroupBldr *tag_bldr);
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@ -323,7 +323,7 @@ public:
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Tag *findTag(const RiseFall *rf,
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Tag *findTag(const RiseFall *rf,
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const PathAnalysisPt *path_ap,
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const PathAnalysisPt *path_ap,
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ClkInfo *tag_clk,
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const ClkInfo *tag_clk,
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bool is_clk,
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bool is_clk,
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InputDelay *input_delay,
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InputDelay *input_delay,
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bool is_segment_start,
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bool is_segment_start,
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@ -331,22 +331,22 @@ public:
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bool own_states);
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bool own_states);
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void reportTags() const;
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void reportTags() const;
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void reportClkInfos() const;
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void reportClkInfos() const;
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virtual ClkInfo *findClkInfo(const ClockEdge *clk_edge,
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const ClkInfo *findClkInfo(const ClockEdge *clk_edge,
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const Pin *clk_src,
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const Pin *clk_src,
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bool is_propagated,
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bool is_propagated,
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const Pin *gen_clk_src,
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const Pin *gen_clk_src,
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bool gen_clk_src_path,
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bool gen_clk_src_path,
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const RiseFall *pulse_clk_sense,
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const RiseFall *pulse_clk_sense,
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Arrival insertion,
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Arrival insertion,
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float latency,
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float latency,
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ClockUncertainties *uncertainties,
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ClockUncertainties *uncertainties,
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const PathAnalysisPt *path_ap,
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const PathAnalysisPt *path_ap,
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Path *crpr_clk_path);
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Path *crpr_clk_path);
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ClkInfo *findClkInfo(const ClockEdge *clk_edge,
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const ClkInfo *findClkInfo(const ClockEdge *clk_edge,
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const Pin *clk_src,
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const Pin *clk_src,
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bool is_propagated,
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bool is_propagated,
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Arrival insertion,
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Arrival insertion,
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const PathAnalysisPt *path_ap);
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const PathAnalysisPt *path_ap);
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// Timing derated arc delay for a path analysis point.
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// Timing derated arc delay for a path analysis point.
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ArcDelay deratedDelay(const Vertex *from_vertex,
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ArcDelay deratedDelay(const Vertex *from_vertex,
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const TimingArc *arc,
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const TimingArc *arc,
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@ -515,13 +515,13 @@ protected:
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const Pin *from_pin,
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const Pin *from_pin,
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const RiseFall *from_rf,
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const RiseFall *from_rf,
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bool from_is_clk,
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bool from_is_clk,
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ClkInfo *from_clk_info,
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const ClkInfo *from_clk_info,
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const Pin *to_pin,
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const Pin *to_pin,
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const RiseFall *to_rf,
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const RiseFall *to_rf,
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bool to_is_clk,
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bool to_is_clk,
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bool to_is_reg_clk,
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bool to_is_reg_clk,
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bool to_is_segment_start,
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bool to_is_segment_start,
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ClkInfo *to_clk_info,
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const ClkInfo *to_clk_info,
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InputDelay *to_input_delay,
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InputDelay *to_input_delay,
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const MinMax *min_max,
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const MinMax *min_max,
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const PathAnalysisPt *path_ap);
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const PathAnalysisPt *path_ap);
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@ -322,17 +322,17 @@ MinPulseWidthCheck::closePath(const StaState *sta) const
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const RiseFall *open_rf = open_path_->transition(sta);
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const RiseFall *open_rf = open_path_->transition(sta);
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const RiseFall *close_rf = open_rf->opposite();
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const RiseFall *close_rf = open_rf->opposite();
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Tag *open_tag = open_path_->tag(sta);
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Tag *open_tag = open_path_->tag(sta);
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ClkInfo *open_clk_info = open_tag->clkInfo();
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const ClkInfo *open_clk_info = open_tag->clkInfo();
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ClkInfo close_clk_info(open_clk_info->clkEdge()->opposite(),
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const ClkInfo close_clk_info(open_clk_info->clkEdge()->opposite(),
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open_clk_info->clkSrc(),
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open_clk_info->clkSrc(),
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open_clk_info->isPropagated(),
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open_clk_info->isPropagated(),
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open_clk_info->genClkSrc(),
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open_clk_info->genClkSrc(),
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open_clk_info->isGenClkSrcPath(),
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open_clk_info->isGenClkSrcPath(),
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open_clk_info->pulseClkSense(),
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open_clk_info->pulseClkSense(),
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delay_zero, 0.0, nullptr,
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delay_zero, 0.0, nullptr,
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open_clk_info->pathAPIndex(),
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open_clk_info->pathAPIndex(),
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open_clk_info->crprClkPath(sta),
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open_clk_info->crprClkPath(sta),
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sta);
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sta);
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Tag close_tag(0,
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Tag close_tag(0,
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close_rf->index(),
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close_rf->index(),
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close_ap->index(),
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close_ap->index(),
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@ -394,7 +394,7 @@ const ClockEdge *
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MinPulseWidthCheck::closeClkEdge(const StaState *sta) const
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MinPulseWidthCheck::closeClkEdge(const StaState *sta) const
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{
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{
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Tag *open_tag = open_path_->tag(sta);
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Tag *open_tag = open_path_->tag(sta);
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ClkInfo *open_clk_info = open_tag->clkInfo();
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const ClkInfo *open_clk_info = open_tag->clkInfo();
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return open_clk_info->clkEdge()->opposite();
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return open_clk_info->clkEdge()->opposite();
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}
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}
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@ -47,7 +47,7 @@ ClkInfo::ClkInfo(const ClockEdge *clk_edge,
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float latency,
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float latency,
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ClockUncertainties *uncertainties,
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ClockUncertainties *uncertainties,
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PathAPIndex path_ap_index,
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PathAPIndex path_ap_index,
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Path *crpr_clk_path,
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const Path *crpr_clk_path,
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const StaState *sta) :
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const StaState *sta) :
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clk_edge_(clk_edge),
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clk_edge_(clk_edge),
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clk_src_(clk_src),
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clk_src_(clk_src),
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@ -254,6 +254,7 @@ ClkInfo::equal(const ClkInfo *clk_info1,
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|| Path::equal(clk_info1->crprClkPathRaw(),
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|| Path::equal(clk_info1->crprClkPathRaw(),
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clk_info2->crprClkPathRaw(),
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clk_info2->crprClkPathRaw(),
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sta))
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sta))
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// || clk_info1->crprClkVertexId(sta) == clk_info2->crprClkVertexId(sta))
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&& ((uncertainties1 == nullptr
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&& ((uncertainties1 == nullptr
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&& uncertainties2 == nullptr)
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&& uncertainties2 == nullptr)
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|| (uncertainties1 && uncertainties2
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|| (uncertainties1 && uncertainties2
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float latency,
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float latency,
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ClockUncertainties *uncertainties,
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ClockUncertainties *uncertainties,
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PathAPIndex path_ap_index,
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PathAPIndex path_ap_index,
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Path *crpr_clk_path,
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const Path *crpr_clk_path,
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const StaState *sta);
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const StaState *sta);
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~ClkInfo();
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~ClkInfo();
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std::string to_string(const StaState *sta) const;
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std::string to_string(const StaState *sta) const;
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@ -293,7 +293,7 @@ ClkDelays::insertionDelay(Path *clk_path,
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const ClockEdge *clk_edge = clk_path->clkEdge(sta);
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const ClockEdge *clk_edge = clk_path->clkEdge(sta);
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const Clock *clk = clk_edge->clock();
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const Clock *clk = clk_edge->clock();
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const RiseFall *clk_rf = clk_edge->transition();
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const RiseFall *clk_rf = clk_edge->transition();
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ClkInfo *clk_info = clk_path->clkInfo(sta);
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const ClkInfo *clk_info = clk_path->clkInfo(sta);
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const Pin *src_pin = clk_info->clkSrc();
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const Pin *src_pin = clk_info->clkSrc();
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const PathAnalysisPt *path_ap = clk_path->pathAnalysisPt(sta);
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const PathAnalysisPt *path_ap = clk_path->pathAnalysisPt(sta);
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const MinMax *min_max = clk_path->minMax(sta);
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const MinMax *min_max = clk_path->minMax(sta);
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// Find the maximum possible crpr (clock min/max delta delay) for a
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// Find the maximum possible crpr (clock min/max delta delay) for a
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// path from it's ClkInfo.
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// path from it's ClkInfo.
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Arrival
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Arrival
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CheckCrpr::maxCrpr(ClkInfo *clk_info)
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CheckCrpr::maxCrpr(const ClkInfo *clk_info)
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{
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{
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const Path *crpr_clk_path = clk_info->crprClkPath(this);
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const Path *crpr_clk_path = clk_info->crprClkPath(this);
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if (crpr_clk_path) {
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if (crpr_clk_path) {
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@ -126,8 +126,8 @@ CheckCrpr::checkCrpr1(const Path *src_path,
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crpr = 0.0;
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crpr = 0.0;
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crpr_pin = nullptr;
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crpr_pin = nullptr;
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const Tag *src_tag = src_path->tag(this);
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const Tag *src_tag = src_path->tag(this);
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ClkInfo *src_clk_info = src_tag->clkInfo();
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const ClkInfo *src_clk_info = src_tag->clkInfo();
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ClkInfo *tgt_clk_info = tgt_clk_path->tag(this)->clkInfo();
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const ClkInfo *tgt_clk_info = tgt_clk_path->tag(this)->clkInfo();
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const Clock *src_clk = src_clk_info->clock();
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const Clock *src_clk = src_clk_info->clock();
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const Clock *tgt_clk = tgt_clk_info->clock();
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const Clock *tgt_clk = tgt_clk_info->clock();
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const Path *src_clk_path = nullptr;
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const Path *src_clk_path = nullptr;
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@ -246,7 +246,7 @@ ConstPathSeq
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CheckCrpr::genClkSrcPaths(const Path *path)
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CheckCrpr::genClkSrcPaths(const Path *path)
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{
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{
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ConstPathSeq gclk_paths;
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ConstPathSeq gclk_paths;
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ClkInfo *clk_info = path->clkInfo(this);
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const ClkInfo *clk_info = path->clkInfo(this);
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const ClockEdge *clk_edge = clk_info->clkEdge();
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const ClockEdge *clk_edge = clk_info->clkEdge();
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const Pin *clk_src = clk_info->clkSrc();
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const Pin *clk_src = clk_info->clkSrc();
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PathAnalysisPt *path_ap = path->pathAnalysisPt(this);
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PathAnalysisPt *path_ap = path->pathAnalysisPt(this);
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@ -350,7 +350,7 @@ CheckCrpr::outputDelayCrpr1(const Path *src_path,
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{
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{
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crpr = 0.0;
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crpr = 0.0;
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crpr_pin = nullptr;
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crpr_pin = nullptr;
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ClkInfo *src_clk_info = src_path->tag(this)->clkInfo();
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const ClkInfo *src_clk_info = src_path->tag(this)->clkInfo();
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const Clock *tgt_clk = tgt_clk_edge->clock();
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const Clock *tgt_clk = tgt_clk_edge->clock();
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const Clock *src_clk = src_path->clock(this);
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const Clock *src_clk = src_path->clock(this);
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if (src_clk && tgt_clk
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if (src_clk && tgt_clk
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explicit CheckCrpr(StaState *sta);
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explicit CheckCrpr(StaState *sta);
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// Find the maximum possible crpr (clock min/max delta delay) for path.
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// Find the maximum possible crpr (clock min/max delta delay) for path.
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Arrival maxCrpr(ClkInfo *clk_info);
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Arrival maxCrpr(const ClkInfo *clk_info);
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// Timing check CRPR.
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// Timing check CRPR.
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Crpr checkCrpr(const Path *src_clk_path,
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Crpr checkCrpr(const Path *src_clk_path,
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const Path *tgt_clk_path);
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const Path *tgt_clk_path);
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@ -711,12 +711,12 @@ Genclks::makeTag(const Clock *gclk,
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state = state->nextState();
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state = state->nextState();
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ExceptionStateSet *states = new ExceptionStateSet();
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ExceptionStateSet *states = new ExceptionStateSet();
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states->insert(state);
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states->insert(state);
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ClkInfo *clk_info = search_->findClkInfo(master_clk->edge(master_rf),
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const ClkInfo *clk_info = search_->findClkInfo(master_clk->edge(master_rf),
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master_pin, true, nullptr, true,
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master_pin, true, nullptr, true,
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nullptr, insert, 0.0, nullptr,
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nullptr, insert, 0.0, nullptr,
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path_ap, nullptr);
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path_ap, nullptr);
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return search_->findTag(master_rf, path_ap, clk_info, false, nullptr, false,
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return search_->findTag(master_rf, path_ap, clk_info, false,
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states, true);
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nullptr, false, states, true);
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}
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}
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class GenClkArrivalSearchPred : public EvalPred
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class GenClkArrivalSearchPred : public EvalPred
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@ -331,7 +331,7 @@ Latches::latchOutArrival(const Path *data_path,
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tgt_clk_path_ap, this);
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tgt_clk_path_ap, this);
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while (enable_iter.hasNext()) {
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while (enable_iter.hasNext()) {
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Path *enable_path = enable_iter.next();
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Path *enable_path = enable_iter.next();
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ClkInfo *en_clk_info = enable_path->clkInfo(this);
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const ClkInfo *en_clk_info = enable_path->clkInfo(this);
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const ClockEdge *en_clk_edge = en_clk_info->clkEdge();
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const ClockEdge *en_clk_edge = en_clk_info->clkEdge();
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if (enable_path->isClock(this)) {
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if (enable_path->isClock(this)) {
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ExceptionPath *excpt = exceptionTo(data_path, en_clk_edge);
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ExceptionPath *excpt = exceptionTo(data_path, en_clk_edge);
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@ -353,7 +353,7 @@ Latches::latchOutArrival(const Path *data_path,
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// Tag switcheroo - data passing thru gets latch enable tag.
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// Tag switcheroo - data passing thru gets latch enable tag.
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// States and path ap come from Q, everything else from enable.
|
// States and path ap come from Q, everything else from enable.
|
||||||
Path *crpr_clk_path = crprActive() ? enable_path : nullptr;
|
Path *crpr_clk_path = crprActive() ? enable_path : nullptr;
|
||||||
ClkInfo *q_clk_info =
|
const ClkInfo *q_clk_info =
|
||||||
search_->findClkInfo(en_clk_edge,
|
search_->findClkInfo(en_clk_edge,
|
||||||
en_clk_info->clkSrc(),
|
en_clk_info->clkSrc(),
|
||||||
en_clk_info->isPropagated(),
|
en_clk_info->isPropagated(),
|
||||||
|
|
|
||||||
|
|
@ -49,7 +49,7 @@ Path::Path() :
|
||||||
{
|
{
|
||||||
}
|
}
|
||||||
|
|
||||||
Path::Path(Path *path) :
|
Path::Path(const Path *path) :
|
||||||
prev_path_(path ? path->prev_path_ : nullptr),
|
prev_path_(path ? path->prev_path_ : nullptr),
|
||||||
arrival_(path ? path->arrival_ : 0.0),
|
arrival_(path ? path->arrival_ : 0.0),
|
||||||
required_(path ? path->required_ : 0.0),
|
required_(path ? path->required_ : 0.0),
|
||||||
|
|
@ -279,7 +279,7 @@ Path::pathIndex(const StaState *sta) const
|
||||||
return this - paths;
|
return this - paths;
|
||||||
}
|
}
|
||||||
|
|
||||||
ClkInfo *
|
const ClkInfo *
|
||||||
Path::clkInfo(const StaState *sta) const
|
Path::clkInfo(const StaState *sta) const
|
||||||
{
|
{
|
||||||
return tag(sta)->clkInfo();
|
return tag(sta)->clkInfo();
|
||||||
|
|
|
||||||
|
|
@ -330,7 +330,7 @@ PathEnd::checkTgtClkDelay(const Path *tgt_clk_path,
|
||||||
const MinMax *min_max = tgt_clk_path->minMax(sta);
|
const MinMax *min_max = tgt_clk_path->minMax(sta);
|
||||||
const EarlyLate *early_late = check_role->tgtClkEarlyLate();
|
const EarlyLate *early_late = check_role->tgtClkEarlyLate();
|
||||||
const PathAnalysisPt *tgt_path_ap = tgt_clk_path->pathAnalysisPt(sta);
|
const PathAnalysisPt *tgt_path_ap = tgt_clk_path->pathAnalysisPt(sta);
|
||||||
ClkInfo *clk_info = tgt_clk_path->clkInfo(sta);
|
const ClkInfo *clk_info = tgt_clk_path->clkInfo(sta);
|
||||||
const Pin *tgt_src_pin = clk_info->clkSrc();
|
const Pin *tgt_src_pin = clk_info->clkSrc();
|
||||||
const Clock *tgt_clk = tgt_clk_edge->clock();
|
const Clock *tgt_clk = tgt_clk_edge->clock();
|
||||||
const RiseFall *tgt_clk_rf = tgt_clk_edge->transition();
|
const RiseFall *tgt_clk_rf = tgt_clk_edge->transition();
|
||||||
|
|
@ -560,14 +560,14 @@ PathEndClkConstrained::sourceClkOffset(const ClockEdge *src_clk_edge,
|
||||||
Arrival
|
Arrival
|
||||||
PathEndClkConstrained::sourceClkLatency(const StaState *sta) const
|
PathEndClkConstrained::sourceClkLatency(const StaState *sta) const
|
||||||
{
|
{
|
||||||
ClkInfo *clk_info = path_->clkInfo(sta);
|
const ClkInfo *clk_info = path_->clkInfo(sta);
|
||||||
return clk_info->latency();
|
return clk_info->latency();
|
||||||
}
|
}
|
||||||
|
|
||||||
Arrival
|
Arrival
|
||||||
PathEndClkConstrained::sourceClkInsertionDelay(const StaState *sta) const
|
PathEndClkConstrained::sourceClkInsertionDelay(const StaState *sta) const
|
||||||
{
|
{
|
||||||
ClkInfo *clk_info = path_->clkInfo(sta);
|
const ClkInfo *clk_info = path_->clkInfo(sta);
|
||||||
return clk_info->insertion();
|
return clk_info->insertion();
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
@ -1033,7 +1033,7 @@ PathEndCheck::sourceClkDelay(const StaState *sta) const
|
||||||
PathExpanded expanded(path_, sta);
|
PathExpanded expanded(path_, sta);
|
||||||
const Path *src_clk_path = expanded.clkPath();
|
const Path *src_clk_path = expanded.clkPath();
|
||||||
if (src_clk_path) {
|
if (src_clk_path) {
|
||||||
ClkInfo *src_clk_info = path_->tag(sta)->clkInfo();
|
const ClkInfo *src_clk_info = path_->tag(sta)->clkInfo();
|
||||||
if (src_clk_info->isPropagated()) {
|
if (src_clk_info->isPropagated()) {
|
||||||
// Propagated clock. Propagated arrival is seeded with insertion delay.
|
// Propagated clock. Propagated arrival is seeded with insertion delay.
|
||||||
Arrival clk_arrival = src_clk_path->arrival();
|
Arrival clk_arrival = src_clk_path->arrival();
|
||||||
|
|
@ -1280,7 +1280,7 @@ PathEndLatchCheck::targetClkWidth(const StaState *sta) const
|
||||||
const Search *search = sta->search();
|
const Search *search = sta->search();
|
||||||
Arrival disable_arrival = search->clkPathArrival(disable_path_);
|
Arrival disable_arrival = search->clkPathArrival(disable_path_);
|
||||||
Arrival enable_arrival = search->clkPathArrival(clk_path_);
|
Arrival enable_arrival = search->clkPathArrival(clk_path_);
|
||||||
ClkInfo *enable_clk_info = clk_path_->clkInfo(sta);
|
const ClkInfo *enable_clk_info = clk_path_->clkInfo(sta);
|
||||||
if (enable_clk_info->isPulseClk())
|
if (enable_clk_info->isPulseClk())
|
||||||
return disable_arrival - enable_arrival;
|
return disable_arrival - enable_arrival;
|
||||||
else {
|
else {
|
||||||
|
|
|
||||||
|
|
@ -644,7 +644,7 @@ PathEnum::updatePathHeadDelays(PathSeq &paths,
|
||||||
Path *after_div)
|
Path *after_div)
|
||||||
{
|
{
|
||||||
Tag *prev_tag = after_div->tag(this);
|
Tag *prev_tag = after_div->tag(this);
|
||||||
ClkInfo *prev_clk_info = prev_tag->clkInfo();
|
const ClkInfo *prev_clk_info = prev_tag->clkInfo();
|
||||||
Arrival prev_arrival = search_->clkPathArrival(after_div);
|
Arrival prev_arrival = search_->clkPathArrival(after_div);
|
||||||
int path_idx_max = paths.size() - 1;
|
int path_idx_max = paths.size() - 1;
|
||||||
// paths[0] is the path endpoint
|
// paths[0] is the path endpoint
|
||||||
|
|
|
||||||
|
|
@ -2112,7 +2112,7 @@ ReportPath::reportSrcClkAndPath(const Path *path,
|
||||||
else if (clk_used_as_data
|
else if (clk_used_as_data
|
||||||
&& pathFromGenPropClk(path, path->minMax(this))) {
|
&& pathFromGenPropClk(path, path->minMax(this))) {
|
||||||
reportClkLine(clk, clk_name.c_str(), clk_end_rf, clk_time, min_max);
|
reportClkLine(clk, clk_name.c_str(), clk_end_rf, clk_time, min_max);
|
||||||
ClkInfo *clk_info = path->tag(search_)->clkInfo();
|
const ClkInfo *clk_info = path->tag(search_)->clkInfo();
|
||||||
if (clk_info->isPropagated())
|
if (clk_info->isPropagated())
|
||||||
reportClkSrcLatency(clk_insertion, clk_time, early_late);
|
reportClkSrcLatency(clk_insertion, clk_time, early_late);
|
||||||
reportPath1(path, expanded, true, time_offset);
|
reportPath1(path, expanded, true, time_offset);
|
||||||
|
|
@ -2259,7 +2259,7 @@ ReportPath::tgtClkInsertionOffet(const Path *clk_path,
|
||||||
const EarlyLate *early_late,
|
const EarlyLate *early_late,
|
||||||
const PathAnalysisPt *path_ap) const
|
const PathAnalysisPt *path_ap) const
|
||||||
{
|
{
|
||||||
ClkInfo *clk_info = clk_path->clkInfo(this);
|
const ClkInfo *clk_info = clk_path->clkInfo(this);
|
||||||
const Pin *src_pin = clk_info->clkSrc();
|
const Pin *src_pin = clk_info->clkSrc();
|
||||||
const ClockEdge *clk_edge = clk_info->clkEdge();
|
const ClockEdge *clk_edge = clk_info->clkEdge();
|
||||||
const Clock *clk = clk_edge->clock();
|
const Clock *clk = clk_edge->clock();
|
||||||
|
|
@ -2278,7 +2278,7 @@ bool
|
||||||
ReportPath::pathFromGenPropClk(const Path *clk_path,
|
ReportPath::pathFromGenPropClk(const Path *clk_path,
|
||||||
const EarlyLate *early_late) const
|
const EarlyLate *early_late) const
|
||||||
{
|
{
|
||||||
ClkInfo *clk_info = clk_path->tag(search_)->clkInfo();
|
const ClkInfo *clk_info = clk_path->tag(search_)->clkInfo();
|
||||||
const ClockEdge *clk_edge = clk_info->clkEdge();
|
const ClockEdge *clk_edge = clk_info->clkEdge();
|
||||||
if (clk_edge) {
|
if (clk_edge) {
|
||||||
const Clock *clk = clk_edge->clock();
|
const Clock *clk = clk_edge->clock();
|
||||||
|
|
@ -2393,7 +2393,7 @@ ReportPath::reportGenClkSrcPath1(const Clock *clk,
|
||||||
const Path *src_path = search_->genclks()->srcPath(clk, clk_pin,
|
const Path *src_path = search_->genclks()->srcPath(clk, clk_pin,
|
||||||
clk_rf, insert_ap);
|
clk_rf, insert_ap);
|
||||||
if (src_path) {
|
if (src_path) {
|
||||||
ClkInfo *src_clk_info = src_path->clkInfo(this);
|
const ClkInfo *src_clk_info = src_path->clkInfo(this);
|
||||||
const ClockEdge *src_clk_edge = src_clk_info->clkEdge();
|
const ClockEdge *src_clk_edge = src_clk_info->clkEdge();
|
||||||
const Clock *src_clk = src_clk_info->clock();
|
const Clock *src_clk = src_clk_info->clock();
|
||||||
if (src_clk) {
|
if (src_clk) {
|
||||||
|
|
|
||||||
|
|
@ -589,7 +589,7 @@ void
|
||||||
Search::deleteFilterClkInfos()
|
Search::deleteFilterClkInfos()
|
||||||
{
|
{
|
||||||
for (auto itr = clk_info_set_->cbegin(); itr != clk_info_set_->cend(); ) {
|
for (auto itr = clk_info_set_->cbegin(); itr != clk_info_set_->cend(); ) {
|
||||||
ClkInfo *clk_info = *itr;
|
const ClkInfo *clk_info = *itr;
|
||||||
if (clk_info->crprPathRefsFilter()) {
|
if (clk_info->crprPathRefsFilter()) {
|
||||||
itr = clk_info_set_->erase(itr);
|
itr = clk_info_set_->erase(itr);
|
||||||
delete clk_info;
|
delete clk_info;
|
||||||
|
|
@ -1324,7 +1324,7 @@ ArrivalVisitor::visitFromToPath(const Pin * /* from_pin */,
|
||||||
from_tag->to_string(this).c_str());
|
from_tag->to_string(this).c_str());
|
||||||
debugPrint(debug_, "search", 3, " to tag : %s",
|
debugPrint(debug_, "search", 3, " to tag : %s",
|
||||||
to_tag->to_string(this).c_str());
|
to_tag->to_string(this).c_str());
|
||||||
ClkInfo *to_clk_info = to_tag->clkInfo();
|
const ClkInfo *to_clk_info = to_tag->clkInfo();
|
||||||
bool to_is_clk = to_tag->isClock();
|
bool to_is_clk = to_tag->isClock();
|
||||||
Path *match;
|
Path *match;
|
||||||
size_t path_index;
|
size_t path_index;
|
||||||
|
|
@ -1361,7 +1361,7 @@ ArrivalVisitor::pruneCrprArrivals()
|
||||||
for (auto path_itr = path_index_map.cbegin(); path_itr != path_index_map.cend(); ) {
|
for (auto path_itr = path_index_map.cbegin(); path_itr != path_index_map.cend(); ) {
|
||||||
Tag *tag = path_itr->first;
|
Tag *tag = path_itr->first;
|
||||||
size_t path_index = path_itr->second;
|
size_t path_index = path_itr->second;
|
||||||
ClkInfo *clk_info = tag->clkInfo();
|
const ClkInfo *clk_info = tag->clkInfo();
|
||||||
bool deleted_tag = false;
|
bool deleted_tag = false;
|
||||||
if (!tag->isClock()
|
if (!tag->isClock()
|
||||||
&& clk_info->hasCrprClkPin()) {
|
&& clk_info->hasCrprClkPin()) {
|
||||||
|
|
@ -1370,7 +1370,7 @@ ArrivalVisitor::pruneCrprArrivals()
|
||||||
Path *path_no_crpr = tag_bldr_no_crpr_->tagMatchPath(tag);
|
Path *path_no_crpr = tag_bldr_no_crpr_->tagMatchPath(tag);
|
||||||
if (path_no_crpr) {
|
if (path_no_crpr) {
|
||||||
Arrival max_arrival = path_no_crpr->arrival();
|
Arrival max_arrival = path_no_crpr->arrival();
|
||||||
ClkInfo *clk_info_no_crpr = path_no_crpr->clkInfo(this);
|
const ClkInfo *clk_info_no_crpr = path_no_crpr->clkInfo(this);
|
||||||
Arrival max_crpr = crpr->maxCrpr(clk_info_no_crpr);
|
Arrival max_crpr = crpr->maxCrpr(clk_info_no_crpr);
|
||||||
Arrival max_arrival_max_crpr = (min_max == MinMax::max())
|
Arrival max_arrival_max_crpr = (min_max == MinMax::max())
|
||||||
? max_arrival - max_crpr
|
? max_arrival - max_crpr
|
||||||
|
|
@ -1608,9 +1608,9 @@ Search::seedClkArrival(const Pin *pin,
|
||||||
// Propagate liberty "pulse_clock" transition to transitive fanout.
|
// Propagate liberty "pulse_clock" transition to transitive fanout.
|
||||||
LibertyPort *port = network_->libertyPort(pin);
|
LibertyPort *port = network_->libertyPort(pin);
|
||||||
const RiseFall *pulse_clk_sense = (port ? port->pulseClkSense() : nullptr);
|
const RiseFall *pulse_clk_sense = (port ? port->pulseClkSense() : nullptr);
|
||||||
ClkInfo *clk_info = findClkInfo(clk_edge, pin, is_propagated, nullptr, false,
|
const ClkInfo *clk_info = findClkInfo(clk_edge, pin, is_propagated, nullptr, false,
|
||||||
pulse_clk_sense, insertion, latency,
|
pulse_clk_sense, insertion, latency,
|
||||||
uncertainties, path_ap, nullptr);
|
uncertainties, path_ap, nullptr);
|
||||||
// Only false_paths -from apply to clock tree pins.
|
// Only false_paths -from apply to clock tree pins.
|
||||||
ExceptionStateSet *states = nullptr;
|
ExceptionStateSet *states = nullptr;
|
||||||
sdc_->exceptionFromClkStates(pin,rf,clk,rf,min_max,states);
|
sdc_->exceptionFromClkStates(pin,rf,clk,rf,min_max,states);
|
||||||
|
|
@ -1650,8 +1650,8 @@ Search::clkDataTag(const Pin *pin,
|
||||||
if (sdc_->exceptionFromStates(pin, rf, clk, rf, min_max, states)) {
|
if (sdc_->exceptionFromStates(pin, rf, clk, rf, min_max, states)) {
|
||||||
bool is_propagated = (clk->isPropagated()
|
bool is_propagated = (clk->isPropagated()
|
||||||
|| sdc_->isPropagatedClock(pin));
|
|| sdc_->isPropagatedClock(pin));
|
||||||
ClkInfo *clk_info = findClkInfo(clk_edge, pin, is_propagated,
|
const ClkInfo *clk_info = findClkInfo(clk_edge, pin, is_propagated,
|
||||||
insertion, path_ap);
|
insertion, path_ap);
|
||||||
return findTag(rf, path_ap, clk_info, false, nullptr, false, states, true);
|
return findTag(rf, path_ap, clk_info, false, nullptr, false, states, true);
|
||||||
}
|
}
|
||||||
else
|
else
|
||||||
|
|
@ -1886,7 +1886,7 @@ Search::inputDelayRefPinArrival(Path *ref_path,
|
||||||
{
|
{
|
||||||
Clock *clk = clk_edge->clock();
|
Clock *clk = clk_edge->clock();
|
||||||
if (clk->isPropagated()) {
|
if (clk->isPropagated()) {
|
||||||
ClkInfo *clk_info = ref_path->clkInfo(this);
|
const ClkInfo *clk_info = ref_path->clkInfo(this);
|
||||||
ref_arrival = delayAsFloat(ref_path->arrival());
|
ref_arrival = delayAsFloat(ref_path->arrival());
|
||||||
ref_insertion = delayAsFloat(clk_info->insertion());
|
ref_insertion = delayAsFloat(clk_info->insertion());
|
||||||
ref_latency = clk_info->latency();
|
ref_latency = clk_info->latency();
|
||||||
|
|
@ -2009,15 +2009,15 @@ Search::inputDelayTag(const Pin *pin,
|
||||||
ExceptionStateSet *states = nullptr;
|
ExceptionStateSet *states = nullptr;
|
||||||
Tag *tag = nullptr;
|
Tag *tag = nullptr;
|
||||||
if (sdc_->exceptionFromStates(pin,rf,clk,clk_rf,min_max,states)) {
|
if (sdc_->exceptionFromStates(pin,rf,clk,clk_rf,min_max,states)) {
|
||||||
ClkInfo *clk_info = findClkInfo(clk_edge, clk_pin, is_propagated, nullptr,
|
const ClkInfo *clk_info = findClkInfo(clk_edge, clk_pin, is_propagated, nullptr,
|
||||||
false, nullptr, clk_insertion, clk_latency,
|
false, nullptr, clk_insertion, clk_latency,
|
||||||
clk_uncertainties, path_ap, nullptr);
|
clk_uncertainties, path_ap, nullptr);
|
||||||
tag = findTag(rf, path_ap, clk_info, false, input_delay, is_segment_start,
|
tag = findTag(rf, path_ap, clk_info, false, input_delay, is_segment_start,
|
||||||
states, true);
|
states, true);
|
||||||
}
|
}
|
||||||
|
|
||||||
if (tag) {
|
if (tag) {
|
||||||
ClkInfo *clk_info = tag->clkInfo();
|
const ClkInfo *clk_info = tag->clkInfo();
|
||||||
// Check for state changes on existing tag exceptions (pending -thru pins).
|
// Check for state changes on existing tag exceptions (pending -thru pins).
|
||||||
tag = mutateTag(tag, pin, rf, false, clk_info,
|
tag = mutateTag(tag, pin, rf, false, clk_info,
|
||||||
pin, rf, false, false, is_segment_start, clk_info,
|
pin, rf, false, false, is_segment_start, clk_info,
|
||||||
|
|
@ -2149,7 +2149,7 @@ PathVisitor::visitFromPath(const Pin *from_pin,
|
||||||
{
|
{
|
||||||
const TimingRole *role = edge->role();
|
const TimingRole *role = edge->role();
|
||||||
Tag *from_tag = from_path->tag(this);
|
Tag *from_tag = from_path->tag(this);
|
||||||
ClkInfo *from_clk_info = from_tag->clkInfo();
|
const ClkInfo *from_clk_info = from_tag->clkInfo();
|
||||||
Tag *to_tag = nullptr;
|
Tag *to_tag = nullptr;
|
||||||
const ClockEdge *clk_edge = from_clk_info->clkEdge();
|
const ClockEdge *clk_edge = from_clk_info->clkEdge();
|
||||||
const Clock *clk = from_clk_info->clock();
|
const Clock *clk = from_clk_info->clock();
|
||||||
|
|
@ -2219,7 +2219,7 @@ PathVisitor::visitFromPath(const Pin *from_pin,
|
||||||
// passed thru reg/latch D->Q edges.
|
// passed thru reg/latch D->Q edges.
|
||||||
&& from_tag->isClock())) {
|
&& from_tag->isClock())) {
|
||||||
const RiseFall *clk_rf = clk_edge ? clk_edge->transition() : nullptr;
|
const RiseFall *clk_rf = clk_edge ? clk_edge->transition() : nullptr;
|
||||||
ClkInfo *to_clk_info = from_clk_info;
|
const ClkInfo *to_clk_info = from_clk_info;
|
||||||
if (from_clk_info->crprClkPath(this) == nullptr
|
if (from_clk_info->crprClkPath(this) == nullptr
|
||||||
|| network_->direction(to_pin)->isInternal())
|
|| network_->direction(to_pin)->isInternal())
|
||||||
to_clk_info = search_->clkInfoWithCrprClkPath(from_clk_info,
|
to_clk_info = search_->clkInfoWithCrprClkPath(from_clk_info,
|
||||||
|
|
@ -2302,7 +2302,7 @@ PathVisitor::visitFromPath(const Pin *from_pin,
|
||||||
Arrival
|
Arrival
|
||||||
Search::clkPathArrival(const Path *clk_path) const
|
Search::clkPathArrival(const Path *clk_path) const
|
||||||
{
|
{
|
||||||
ClkInfo *clk_info = clk_path->clkInfo(this);
|
const ClkInfo *clk_info = clk_path->clkInfo(this);
|
||||||
const ClockEdge *clk_edge = clk_info->clkEdge();
|
const ClockEdge *clk_edge = clk_info->clkEdge();
|
||||||
const PathAnalysisPt *path_ap = clk_path->pathAnalysisPt(this);
|
const PathAnalysisPt *path_ap = clk_path->pathAnalysisPt(this);
|
||||||
const MinMax *min_max = path_ap->pathMinMax();
|
const MinMax *min_max = path_ap->pathMinMax();
|
||||||
|
|
@ -2311,7 +2311,7 @@ Search::clkPathArrival(const Path *clk_path) const
|
||||||
|
|
||||||
Arrival
|
Arrival
|
||||||
Search::clkPathArrival(const Path *clk_path,
|
Search::clkPathArrival(const Path *clk_path,
|
||||||
ClkInfo *clk_info,
|
const ClkInfo *clk_info,
|
||||||
const ClockEdge *clk_edge,
|
const ClockEdge *clk_edge,
|
||||||
const MinMax *min_max,
|
const MinMax *min_max,
|
||||||
const PathAnalysisPt *path_ap) const
|
const PathAnalysisPt *path_ap) const
|
||||||
|
|
@ -2336,7 +2336,7 @@ Search::clkPathArrival(const Path *clk_path,
|
||||||
Arrival
|
Arrival
|
||||||
Search::pathClkPathArrival(const Path *path) const
|
Search::pathClkPathArrival(const Path *path) const
|
||||||
{
|
{
|
||||||
ClkInfo *clk_info = path->clkInfo(this);
|
const ClkInfo *clk_info = path->clkInfo(this);
|
||||||
if (clk_info->isPropagated()) {
|
if (clk_info->isPropagated()) {
|
||||||
const Path *src_clk_path = pathClkPathArrival1(path);
|
const Path *src_clk_path = pathClkPathArrival1(path);
|
||||||
if (src_clk_path)
|
if (src_clk_path)
|
||||||
|
|
@ -2391,7 +2391,7 @@ Search::fromUnclkedInputTag(const Pin *pin,
|
||||||
ExceptionStateSet *states = nullptr;
|
ExceptionStateSet *states = nullptr;
|
||||||
if (sdc_->exceptionFromStates(pin, rf, nullptr, nullptr, min_max, states)
|
if (sdc_->exceptionFromStates(pin, rf, nullptr, nullptr, min_max, states)
|
||||||
&& (!require_exception || states)) {
|
&& (!require_exception || states)) {
|
||||||
ClkInfo *clk_info = findClkInfo(nullptr, nullptr, false, 0.0, path_ap);
|
const ClkInfo *clk_info = findClkInfo(nullptr, nullptr, false, 0.0, path_ap);
|
||||||
return findTag(rf, path_ap, clk_info, false, nullptr,
|
return findTag(rf, path_ap, clk_info, false, nullptr,
|
||||||
is_segment_start, states, true);
|
is_segment_start, states, true);
|
||||||
}
|
}
|
||||||
|
|
@ -2403,7 +2403,7 @@ Search::fromRegClkTag(const Pin *from_pin,
|
||||||
const RiseFall *from_rf,
|
const RiseFall *from_rf,
|
||||||
const Clock *clk,
|
const Clock *clk,
|
||||||
const RiseFall *clk_rf,
|
const RiseFall *clk_rf,
|
||||||
ClkInfo *clk_info,
|
const ClkInfo *clk_info,
|
||||||
const Pin *to_pin,
|
const Pin *to_pin,
|
||||||
const RiseFall *to_rf,
|
const RiseFall *to_rf,
|
||||||
const MinMax *min_max,
|
const MinMax *min_max,
|
||||||
|
|
@ -2421,8 +2421,8 @@ Search::fromRegClkTag(const Pin *from_pin,
|
||||||
}
|
}
|
||||||
|
|
||||||
// Insert from_path as ClkInfo crpr_clk_path.
|
// Insert from_path as ClkInfo crpr_clk_path.
|
||||||
ClkInfo *
|
const ClkInfo *
|
||||||
Search::clkInfoWithCrprClkPath(ClkInfo *from_clk_info,
|
Search::clkInfoWithCrprClkPath(const ClkInfo *from_clk_info,
|
||||||
Path *from_path,
|
Path *from_path,
|
||||||
const PathAnalysisPt *path_ap)
|
const PathAnalysisPt *path_ap)
|
||||||
{
|
{
|
||||||
|
|
@ -2454,7 +2454,7 @@ Search::thruTag(Tag *from_tag,
|
||||||
Vertex *to_vertex = edge->to(graph_);
|
Vertex *to_vertex = edge->to(graph_);
|
||||||
const Pin *to_pin = to_vertex->pin();
|
const Pin *to_pin = to_vertex->pin();
|
||||||
const RiseFall *from_rf = from_tag->transition();
|
const RiseFall *from_rf = from_tag->transition();
|
||||||
ClkInfo *from_clk_info = from_tag->clkInfo();
|
const ClkInfo *from_clk_info = from_tag->clkInfo();
|
||||||
bool to_is_reg_clk = to_vertex->isRegClk();
|
bool to_is_reg_clk = to_vertex->isRegClk();
|
||||||
Tag *to_tag = mutateTag(from_tag, from_pin, from_rf, false, from_clk_info,
|
Tag *to_tag = mutateTag(from_tag, from_pin, from_rf, false, from_clk_info,
|
||||||
to_pin, to_rf, false, to_is_reg_clk, false,
|
to_pin, to_rf, false, to_is_reg_clk, false,
|
||||||
|
|
@ -2479,7 +2479,7 @@ Search::thruClkTag(Path *from_path,
|
||||||
Vertex *to_vertex = edge->to(graph_);
|
Vertex *to_vertex = edge->to(graph_);
|
||||||
const Pin *to_pin = to_vertex->pin();
|
const Pin *to_pin = to_vertex->pin();
|
||||||
const RiseFall *from_rf = from_tag->transition();
|
const RiseFall *from_rf = from_tag->transition();
|
||||||
ClkInfo *from_clk_info = from_tag->clkInfo();
|
const ClkInfo *from_clk_info = from_tag->clkInfo();
|
||||||
bool from_is_clk = from_tag->isClock();
|
bool from_is_clk = from_tag->isClock();
|
||||||
bool to_is_reg_clk = to_vertex->isRegClk();
|
bool to_is_reg_clk = to_vertex->isRegClk();
|
||||||
const TimingRole *role = edge->role();
|
const TimingRole *role = edge->role();
|
||||||
|
|
@ -2487,19 +2487,20 @@ Search::thruClkTag(Path *from_path,
|
||||||
&& to_propagates_clk
|
&& to_propagates_clk
|
||||||
&& (role->isWire()
|
&& (role->isWire()
|
||||||
|| role == TimingRole::combinational()));
|
|| role == TimingRole::combinational()));
|
||||||
ClkInfo *to_clk_info = thruClkInfo(from_path, from_vertex, from_clk_info, from_is_clk,
|
const ClkInfo *to_clk_info = thruClkInfo(from_path, from_vertex,
|
||||||
edge, to_vertex, to_pin, to_is_clk,
|
from_clk_info, from_is_clk,
|
||||||
arc_delay_min_max_eq, min_max, path_ap);
|
edge, to_vertex, to_pin, to_is_clk,
|
||||||
|
arc_delay_min_max_eq, min_max, path_ap);
|
||||||
Tag *to_tag = mutateTag(from_tag,from_pin,from_rf,from_is_clk,from_clk_info,
|
Tag *to_tag = mutateTag(from_tag,from_pin,from_rf,from_is_clk,from_clk_info,
|
||||||
to_pin, to_rf, to_is_clk, to_is_reg_clk, false,
|
to_pin, to_rf, to_is_clk, to_is_reg_clk, false,
|
||||||
to_clk_info, nullptr, min_max, path_ap);
|
to_clk_info, nullptr, min_max, path_ap);
|
||||||
return to_tag;
|
return to_tag;
|
||||||
}
|
}
|
||||||
|
|
||||||
ClkInfo *
|
const ClkInfo *
|
||||||
Search::thruClkInfo(Path *from_path,
|
Search::thruClkInfo(Path *from_path,
|
||||||
Vertex *from_vertex,
|
Vertex *from_vertex,
|
||||||
ClkInfo *from_clk_info,
|
const ClkInfo *from_clk_info,
|
||||||
bool from_is_clk,
|
bool from_is_clk,
|
||||||
Edge *edge,
|
Edge *edge,
|
||||||
Vertex *to_vertex,
|
Vertex *to_vertex,
|
||||||
|
|
@ -2596,11 +2597,13 @@ Search::thruClkInfo(Path *from_path,
|
||||||
}
|
}
|
||||||
|
|
||||||
if (changed) {
|
if (changed) {
|
||||||
ClkInfo *to_clk_info = findClkInfo(from_clk_edge, from_clk_info->clkSrc(),
|
const ClkInfo *to_clk_info = findClkInfo(from_clk_edge,
|
||||||
to_clk_prop, gen_clk_src,
|
from_clk_info->clkSrc(),
|
||||||
from_clk_info->isGenClkSrcPath(),
|
to_clk_prop, gen_clk_src,
|
||||||
to_pulse_sense, to_insertion, to_latency,
|
from_clk_info->isGenClkSrcPath(),
|
||||||
to_uncertainties, path_ap, to_crpr_clk_path);
|
to_pulse_sense, to_insertion, to_latency,
|
||||||
|
to_uncertainties, path_ap,
|
||||||
|
to_crpr_clk_path);
|
||||||
return to_clk_info;
|
return to_clk_info;
|
||||||
}
|
}
|
||||||
return from_clk_info;
|
return from_clk_info;
|
||||||
|
|
@ -2612,13 +2615,13 @@ Search::mutateTag(Tag *from_tag,
|
||||||
const Pin *from_pin,
|
const Pin *from_pin,
|
||||||
const RiseFall *from_rf,
|
const RiseFall *from_rf,
|
||||||
bool from_is_clk,
|
bool from_is_clk,
|
||||||
ClkInfo *from_clk_info,
|
const ClkInfo *from_clk_info,
|
||||||
const Pin *to_pin,
|
const Pin *to_pin,
|
||||||
const RiseFall *to_rf,
|
const RiseFall *to_rf,
|
||||||
bool to_is_clk,
|
bool to_is_clk,
|
||||||
bool to_is_reg_clk,
|
bool to_is_reg_clk,
|
||||||
bool to_is_segment_start,
|
bool to_is_segment_start,
|
||||||
ClkInfo *to_clk_info,
|
const ClkInfo *to_clk_info,
|
||||||
InputDelay *to_input_delay,
|
InputDelay *to_input_delay,
|
||||||
const MinMax *min_max,
|
const MinMax *min_max,
|
||||||
const PathAnalysisPt *path_ap)
|
const PathAnalysisPt *path_ap)
|
||||||
|
|
@ -2965,7 +2968,7 @@ Search::tagCount() const
|
||||||
Tag *
|
Tag *
|
||||||
Search::findTag(const RiseFall *rf,
|
Search::findTag(const RiseFall *rf,
|
||||||
const PathAnalysisPt *path_ap,
|
const PathAnalysisPt *path_ap,
|
||||||
ClkInfo *clk_info,
|
const ClkInfo *clk_info,
|
||||||
bool is_clk,
|
bool is_clk,
|
||||||
InputDelay *input_delay,
|
InputDelay *input_delay,
|
||||||
bool is_segment_start,
|
bool is_segment_start,
|
||||||
|
|
@ -3035,17 +3038,17 @@ Search::reportTags() const
|
||||||
void
|
void
|
||||||
Search::reportClkInfos() const
|
Search::reportClkInfos() const
|
||||||
{
|
{
|
||||||
Vector<ClkInfo*> clk_infos;
|
Vector<const ClkInfo*> clk_infos;
|
||||||
// set -> vector for sorting.
|
// set -> vector for sorting.
|
||||||
for (ClkInfo *clk_info : *clk_info_set_)
|
for (const ClkInfo *clk_info : *clk_info_set_)
|
||||||
clk_infos.push_back(clk_info);
|
clk_infos.push_back(clk_info);
|
||||||
sort(clk_infos, ClkInfoLess(this));
|
sort(clk_infos, ClkInfoLess(this));
|
||||||
for (ClkInfo *clk_info : clk_infos)
|
for (const ClkInfo *clk_info : clk_infos)
|
||||||
report_->reportLine("%s", clk_info->to_string(this).c_str());
|
report_->reportLine("%s", clk_info->to_string(this).c_str());
|
||||||
report_->reportLine("%zu clk infos", clk_info_set_->size());
|
report_->reportLine("%zu clk infos", clk_info_set_->size());
|
||||||
}
|
}
|
||||||
|
|
||||||
ClkInfo *
|
const ClkInfo *
|
||||||
Search::findClkInfo(const ClockEdge *clk_edge,
|
Search::findClkInfo(const ClockEdge *clk_edge,
|
||||||
const Pin *clk_src,
|
const Pin *clk_src,
|
||||||
bool is_propagated,
|
bool is_propagated,
|
||||||
|
|
@ -3062,7 +3065,7 @@ Search::findClkInfo(const ClockEdge *clk_edge,
|
||||||
pulse_clk_sense, insertion, latency, uncertainties,
|
pulse_clk_sense, insertion, latency, uncertainties,
|
||||||
path_ap->index(), crpr_clk_path, this);
|
path_ap->index(), crpr_clk_path, this);
|
||||||
LockGuard lock(clk_info_lock_);
|
LockGuard lock(clk_info_lock_);
|
||||||
ClkInfo *clk_info = clk_info_set_->findKey(&probe);
|
const ClkInfo *clk_info = clk_info_set_->findKey(&probe);
|
||||||
if (clk_info == nullptr) {
|
if (clk_info == nullptr) {
|
||||||
clk_info = new ClkInfo(clk_edge, clk_src,
|
clk_info = new ClkInfo(clk_edge, clk_src,
|
||||||
is_propagated, gen_clk_src, gen_clk_src_path,
|
is_propagated, gen_clk_src, gen_clk_src_path,
|
||||||
|
|
@ -3073,7 +3076,7 @@ Search::findClkInfo(const ClockEdge *clk_edge,
|
||||||
return clk_info;
|
return clk_info;
|
||||||
}
|
}
|
||||||
|
|
||||||
ClkInfo *
|
const ClkInfo *
|
||||||
Search::findClkInfo(const ClockEdge *clk_edge,
|
Search::findClkInfo(const ClockEdge *clk_edge,
|
||||||
const Pin *clk_src,
|
const Pin *clk_src,
|
||||||
bool is_propagated,
|
bool is_propagated,
|
||||||
|
|
|
||||||
|
|
@ -2881,7 +2881,7 @@ Sta::vertexArrival(Vertex *vertex,
|
||||||
while (path_iter.hasNext()) {
|
while (path_iter.hasNext()) {
|
||||||
Path *path = path_iter.next();
|
Path *path = path_iter.next();
|
||||||
const Arrival &path_arrival = path->arrival();
|
const Arrival &path_arrival = path->arrival();
|
||||||
ClkInfo *clk_info = path->clkInfo(search_);
|
const ClkInfo *clk_info = path->clkInfo(search_);
|
||||||
if ((clk_edge == clk_edge_wildcard
|
if ((clk_edge == clk_edge_wildcard
|
||||||
|| clk_info->clkEdge() == clk_edge)
|
|| clk_info->clkEdge() == clk_edge)
|
||||||
&& !clk_info->isGenClkSrcPath()
|
&& !clk_info->isGenClkSrcPath()
|
||||||
|
|
|
||||||
|
|
@ -41,7 +41,7 @@ namespace sta {
|
||||||
Tag::Tag(TagIndex index,
|
Tag::Tag(TagIndex index,
|
||||||
int rf_index,
|
int rf_index,
|
||||||
PathAPIndex path_ap_index,
|
PathAPIndex path_ap_index,
|
||||||
ClkInfo *clk_info,
|
const ClkInfo *clk_info,
|
||||||
bool is_clk,
|
bool is_clk,
|
||||||
InputDelay *input_delay,
|
InputDelay *input_delay,
|
||||||
bool is_segment_start,
|
bool is_segment_start,
|
||||||
|
|
@ -305,8 +305,8 @@ Tag::cmp(const Tag *tag1,
|
||||||
if (tag1 == tag2)
|
if (tag1 == tag2)
|
||||||
return 0;
|
return 0;
|
||||||
|
|
||||||
ClkInfo *clk_info1 = tag1->clkInfo();
|
const ClkInfo *clk_info1 = tag1->clkInfo();
|
||||||
ClkInfo *clk_info2 = tag2->clkInfo();
|
const ClkInfo *clk_info2 = tag2->clkInfo();
|
||||||
int clk_cmp = ClkInfo::cmp(clk_info1, clk_info2, sta);
|
int clk_cmp = ClkInfo::cmp(clk_info1, clk_info2, sta);
|
||||||
if (clk_cmp != 0)
|
if (clk_cmp != 0)
|
||||||
return clk_cmp;
|
return clk_cmp;
|
||||||
|
|
|
||||||
|
|
@ -54,7 +54,7 @@ public:
|
||||||
Tag(TagIndex index,
|
Tag(TagIndex index,
|
||||||
int rf_index,
|
int rf_index,
|
||||||
PathAPIndex path_ap_index,
|
PathAPIndex path_ap_index,
|
||||||
ClkInfo *clk_info,
|
const ClkInfo *clk_info,
|
||||||
bool is_clk,
|
bool is_clk,
|
||||||
InputDelay *input_delay,
|
InputDelay *input_delay,
|
||||||
bool is_segment_start,
|
bool is_segment_start,
|
||||||
|
|
@ -66,7 +66,7 @@ public:
|
||||||
std::string to_string(bool report_index,
|
std::string to_string(bool report_index,
|
||||||
bool report_rf_min_max,
|
bool report_rf_min_max,
|
||||||
const StaState *sta) const;
|
const StaState *sta) const;
|
||||||
ClkInfo *clkInfo() const { return clk_info_; }
|
const ClkInfo *clkInfo() const { return clk_info_; }
|
||||||
bool isClock() const { return is_clk_; }
|
bool isClock() const { return is_clk_; }
|
||||||
const ClockEdge *clkEdge() const;
|
const ClockEdge *clkEdge() const;
|
||||||
const Clock *clock() const;
|
const Clock *clock() const;
|
||||||
|
|
@ -126,7 +126,7 @@ protected:
|
||||||
const Tag *tag2);
|
const Tag *tag2);
|
||||||
|
|
||||||
private:
|
private:
|
||||||
ClkInfo *clk_info_;
|
const ClkInfo *clk_info_;
|
||||||
InputDelay *input_delay_;
|
InputDelay *input_delay_;
|
||||||
ExceptionStateSet *states_;
|
ExceptionStateSet *states_;
|
||||||
size_t hash_;
|
size_t hash_;
|
||||||
|
|
|
||||||
|
|
@ -162,7 +162,7 @@ VisitPathEnds::visitCheckEnd(const Pin *pin,
|
||||||
tgt_clk_path_ap, this);
|
tgt_clk_path_ap, this);
|
||||||
while (tgt_clk_path_iter.hasNext()) {
|
while (tgt_clk_path_iter.hasNext()) {
|
||||||
Path *tgt_clk_path = tgt_clk_path_iter.next();
|
Path *tgt_clk_path = tgt_clk_path_iter.next();
|
||||||
ClkInfo *tgt_clk_info = tgt_clk_path->clkInfo(this);
|
const ClkInfo *tgt_clk_info = tgt_clk_path->clkInfo(this);
|
||||||
const ClockEdge *tgt_clk_edge = tgt_clk_path->clkEdge(this);
|
const ClockEdge *tgt_clk_edge = tgt_clk_path->clkEdge(this);
|
||||||
const Clock *tgt_clk = tgt_clk_path->clock(this);
|
const Clock *tgt_clk = tgt_clk_path->clock(this);
|
||||||
const Pin *tgt_pin = tgt_clk_vertex->pin();
|
const Pin *tgt_pin = tgt_clk_vertex->pin();
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue