diff --git a/include/sta/Path.hh b/include/sta/Path.hh
index 7316eff0..09763f73 100644
--- a/include/sta/Path.hh
+++ b/include/sta/Path.hh
@@ -41,7 +41,7 @@ class Path
 {
 public:
   Path();
-  Path(Path *path);
+  Path(const Path *path);
   Path(Vertex *vertex,
        Tag *tag,
        const StaState *sta);
@@ -89,7 +89,7 @@ public:
   TagIndex tagIndex(const StaState *sta) const;
   void setTag(Tag *tag);
   size_t pathIndex(const StaState *sta) const;
-  ClkInfo *clkInfo(const StaState *sta) const;
+  const ClkInfo *clkInfo(const StaState *sta) const;
   const ClockEdge *clkEdge(const StaState *sta) const;
   const Clock *clock(const StaState *sta) const;
   bool isClock(const StaState *sta) const;
diff --git a/include/sta/Search.hh b/include/sta/Search.hh
index a6258e33..934c1006 100644
--- a/include/sta/Search.hh
+++ b/include/sta/Search.hh
@@ -64,7 +64,7 @@ class CheckCrpr;
 class Genclks;
 class Corner;
 
-typedef Set<ClkInfo*, ClkInfoLess> ClkInfoSet;
+typedef Set<const ClkInfo*, ClkInfoLess> ClkInfoSet;
 typedef UnorderedSet<Tag*, TagHash, TagEqual> TagSet;
 typedef UnorderedSet<TagGroup*, TagGroupHash, TagGroupEqual> TagGroupSet;
 typedef Map<Vertex*, Slack> VertexSlackMap;
@@ -158,7 +158,7 @@ public:
   // Clock arrival respecting ideal clock insertion delay and latency.
   Arrival clkPathArrival(const Path *clk_path) const;
   Arrival clkPathArrival(const Path *clk_path,
-			 ClkInfo *clk_info,
+			 const ClkInfo *clk_info,
 			 const ClockEdge *clk_edge,
 			 const MinMax *min_max,
 			 const PathAnalysisPt *path_ap) const;
@@ -244,7 +244,7 @@ public:
 		     const RiseFall *from_rf,
 		     const Clock *clk,
 		     const RiseFall *clk_rf,
-		     ClkInfo *clk_info,
+		     const ClkInfo *clk_info,
 		     const Pin *to_pin,
 		     const RiseFall *to_rf,
 		     const MinMax *min_max,
@@ -263,20 +263,20 @@ public:
                   bool arc_delay_min_max_eq,
                   const MinMax *min_max,
                   const PathAnalysisPt *path_ap);
-  ClkInfo *thruClkInfo(Path *from_path,
-                       Vertex *from_vertex,
-                       ClkInfo *from_clk_info,
-                       bool from_is_clk,
-                       Edge *edge,
-                       Vertex *to_vertex,
-                       const Pin *to_pin,
-                       bool to_is_clk,
-                       bool arc_delay_min_max_eq,
-                       const MinMax *min_max,
-                       const PathAnalysisPt *path_ap);
-  ClkInfo *clkInfoWithCrprClkPath(ClkInfo *from_clk_info,
-				  Path *from_path,
-				  const PathAnalysisPt *path_ap);
+  const ClkInfo *thruClkInfo(Path *from_path,
+			     Vertex *from_vertex,
+			     const ClkInfo *from_clk_info,
+			     bool from_is_clk,
+			     Edge *edge,
+			     Vertex *to_vertex,
+			     const Pin *to_pin,
+			     bool to_is_clk,
+			     bool arc_delay_min_max_eq,
+			     const MinMax *min_max,
+			     const PathAnalysisPt *path_ap);
+  const ClkInfo *clkInfoWithCrprClkPath(const ClkInfo *from_clk_info,
+					Path *from_path,
+					const PathAnalysisPt *path_ap);
   void seedClkArrivals(const Pin *pin,
 		       Vertex *vertex,
 		       TagGroupBldr *tag_bldr);
@@ -323,7 +323,7 @@ public:
 
   Tag *findTag(const RiseFall *rf,
 	       const PathAnalysisPt *path_ap,
-	       ClkInfo *tag_clk,
+	       const ClkInfo *tag_clk,
 	       bool is_clk,
 	       InputDelay *input_delay,
 	       bool is_segment_start,
@@ -331,22 +331,22 @@ public:
 	       bool own_states);
   void reportTags() const;
   void reportClkInfos() const;
-  virtual ClkInfo *findClkInfo(const ClockEdge *clk_edge,
-			       const Pin *clk_src,
-			       bool is_propagated,
-			       const Pin *gen_clk_src,
-			       bool gen_clk_src_path,
-			       const RiseFall *pulse_clk_sense,
-			       Arrival insertion,
-			       float latency,
-			       ClockUncertainties *uncertainties,
-			       const PathAnalysisPt *path_ap,
-			       Path *crpr_clk_path);
-  ClkInfo *findClkInfo(const ClockEdge *clk_edge,
-		       const Pin *clk_src,
-		       bool is_propagated,
-		       Arrival insertion,
-		       const PathAnalysisPt *path_ap);
+  const ClkInfo *findClkInfo(const ClockEdge *clk_edge,
+			     const Pin *clk_src,
+			     bool is_propagated,
+			     const Pin *gen_clk_src,
+			     bool gen_clk_src_path,
+			     const RiseFall *pulse_clk_sense,
+			     Arrival insertion,
+			     float latency,
+			     ClockUncertainties *uncertainties,
+			     const PathAnalysisPt *path_ap,
+			     Path *crpr_clk_path);
+  const ClkInfo *findClkInfo(const ClockEdge *clk_edge,
+			     const Pin *clk_src,
+			     bool is_propagated,
+			     Arrival insertion,
+			     const PathAnalysisPt *path_ap);
   // Timing derated arc delay for a path analysis point.
   ArcDelay deratedDelay(const Vertex *from_vertex,
 			const TimingArc *arc,
@@ -515,13 +515,13 @@ protected:
 		 const Pin *from_pin,
 		 const RiseFall *from_rf,
 		 bool from_is_clk,
-		 ClkInfo *from_clk_info,
+		 const ClkInfo *from_clk_info,
 		 const Pin *to_pin,
 		 const RiseFall *to_rf,
 		 bool to_is_clk,
 		 bool to_is_reg_clk,
 		 bool to_is_segment_start,
-		 ClkInfo *to_clk_info,
+		 const ClkInfo *to_clk_info,
 		 InputDelay *to_input_delay,
 		 const MinMax *min_max,
 		 const PathAnalysisPt *path_ap);
diff --git a/search/CheckMinPulseWidths.cc b/search/CheckMinPulseWidths.cc
index d732c01f..395327ea 100644
--- a/search/CheckMinPulseWidths.cc
+++ b/search/CheckMinPulseWidths.cc
@@ -322,17 +322,17 @@ MinPulseWidthCheck::closePath(const StaState *sta) const
   const RiseFall *open_rf = open_path_->transition(sta);
   const RiseFall *close_rf = open_rf->opposite();
   Tag *open_tag = open_path_->tag(sta);
-  ClkInfo *open_clk_info = open_tag->clkInfo();
-  ClkInfo close_clk_info(open_clk_info->clkEdge()->opposite(),
-			 open_clk_info->clkSrc(),
-			 open_clk_info->isPropagated(),
-			 open_clk_info->genClkSrc(),
-			 open_clk_info->isGenClkSrcPath(),
-			 open_clk_info->pulseClkSense(),
-			 delay_zero, 0.0, nullptr,
-			 open_clk_info->pathAPIndex(),
-			 open_clk_info->crprClkPath(sta),
-			 sta);
+  const ClkInfo *open_clk_info = open_tag->clkInfo();
+  const ClkInfo close_clk_info(open_clk_info->clkEdge()->opposite(),
+			       open_clk_info->clkSrc(),
+			       open_clk_info->isPropagated(),
+			       open_clk_info->genClkSrc(),
+			       open_clk_info->isGenClkSrcPath(),
+			       open_clk_info->pulseClkSense(),
+			       delay_zero, 0.0, nullptr,
+			       open_clk_info->pathAPIndex(),
+			       open_clk_info->crprClkPath(sta),
+			       sta);
   Tag close_tag(0,
 		close_rf->index(),
 		close_ap->index(),
@@ -394,7 +394,7 @@ const ClockEdge *
 MinPulseWidthCheck::closeClkEdge(const StaState *sta) const
 {
   Tag *open_tag = open_path_->tag(sta);
-  ClkInfo *open_clk_info = open_tag->clkInfo();
+  const ClkInfo *open_clk_info = open_tag->clkInfo();
   return open_clk_info->clkEdge()->opposite();
 }
 
diff --git a/search/ClkInfo.cc b/search/ClkInfo.cc
index 1ab560ed..5d1c5805 100644
--- a/search/ClkInfo.cc
+++ b/search/ClkInfo.cc
@@ -47,7 +47,7 @@ ClkInfo::ClkInfo(const ClockEdge *clk_edge,
 		 float latency,
 		 ClockUncertainties *uncertainties,
                  PathAPIndex path_ap_index,
-		 Path *crpr_clk_path,
+		 const Path *crpr_clk_path,
 		 const StaState *sta) :
   clk_edge_(clk_edge),
   clk_src_(clk_src),
@@ -254,6 +254,7 @@ ClkInfo::equal(const ClkInfo *clk_info1,
 	|| Path::equal(clk_info1->crprClkPathRaw(),
                        clk_info2->crprClkPathRaw(),
                        sta))
+    //	|| clk_info1->crprClkVertexId(sta) == clk_info2->crprClkVertexId(sta))
     && ((uncertainties1 == nullptr
 	 && uncertainties2 == nullptr)
 	|| (uncertainties1 && uncertainties2
diff --git a/search/ClkInfo.hh b/search/ClkInfo.hh
index ac89ebfc..5a3a58dd 100644
--- a/search/ClkInfo.hh
+++ b/search/ClkInfo.hh
@@ -46,7 +46,7 @@ public:
 	  float latency,
 	  ClockUncertainties *uncertainties,
           PathAPIndex path_ap_index,
-	  Path *crpr_clk_path,
+	  const Path *crpr_clk_path,
 	  const StaState *sta);
   ~ClkInfo();
   std::string to_string(const StaState *sta) const;
diff --git a/search/ClkLatency.cc b/search/ClkLatency.cc
index 52edbe42..d9b4a68f 100644
--- a/search/ClkLatency.cc
+++ b/search/ClkLatency.cc
@@ -293,7 +293,7 @@ ClkDelays::insertionDelay(Path *clk_path,
   const ClockEdge *clk_edge = clk_path->clkEdge(sta);
   const Clock *clk = clk_edge->clock();
   const RiseFall *clk_rf = clk_edge->transition();
-  ClkInfo *clk_info = clk_path->clkInfo(sta);
+  const ClkInfo *clk_info = clk_path->clkInfo(sta);
   const Pin *src_pin = clk_info->clkSrc();
   const PathAnalysisPt *path_ap = clk_path->pathAnalysisPt(sta);
   const MinMax *min_max = clk_path->minMax(sta);
diff --git a/search/Crpr.cc b/search/Crpr.cc
index 6d227bb8..46b5917f 100644
--- a/search/Crpr.cc
+++ b/search/Crpr.cc
@@ -56,7 +56,7 @@ CheckCrpr::CheckCrpr(StaState *sta) :
 // Find the maximum possible crpr (clock min/max delta delay) for a
 // path from it's ClkInfo.
 Arrival
-CheckCrpr::maxCrpr(ClkInfo *clk_info)
+CheckCrpr::maxCrpr(const ClkInfo *clk_info)
 {
   const Path *crpr_clk_path = clk_info->crprClkPath(this);
   if (crpr_clk_path) {
@@ -126,8 +126,8 @@ CheckCrpr::checkCrpr1(const Path *src_path,
   crpr = 0.0;
   crpr_pin = nullptr;
   const Tag *src_tag = src_path->tag(this);
-  ClkInfo *src_clk_info = src_tag->clkInfo();
-  ClkInfo *tgt_clk_info = tgt_clk_path->tag(this)->clkInfo();
+  const ClkInfo *src_clk_info = src_tag->clkInfo();
+  const ClkInfo *tgt_clk_info = tgt_clk_path->tag(this)->clkInfo();
   const Clock *src_clk = src_clk_info->clock();
   const Clock *tgt_clk = tgt_clk_info->clock();
   const Path *src_clk_path = nullptr;
@@ -246,7 +246,7 @@ ConstPathSeq
 CheckCrpr::genClkSrcPaths(const Path *path)
 {
   ConstPathSeq gclk_paths;
-  ClkInfo *clk_info = path->clkInfo(this);
+  const ClkInfo *clk_info = path->clkInfo(this);
   const ClockEdge *clk_edge = clk_info->clkEdge();
   const Pin *clk_src = clk_info->clkSrc();
   PathAnalysisPt *path_ap = path->pathAnalysisPt(this);
@@ -350,7 +350,7 @@ CheckCrpr::outputDelayCrpr1(const Path *src_path,
 {
   crpr = 0.0;
   crpr_pin = nullptr;
-  ClkInfo *src_clk_info = src_path->tag(this)->clkInfo();
+  const ClkInfo *src_clk_info = src_path->tag(this)->clkInfo();
   const Clock *tgt_clk = tgt_clk_edge->clock();
   const Clock *src_clk = src_path->clock(this);
   if (src_clk && tgt_clk
diff --git a/search/Crpr.hh b/search/Crpr.hh
index bed17295..e26353aa 100644
--- a/search/Crpr.hh
+++ b/search/Crpr.hh
@@ -39,7 +39,7 @@ public:
   explicit CheckCrpr(StaState *sta);
 
   // Find the maximum possible crpr (clock min/max delta delay) for path.
-  Arrival maxCrpr(ClkInfo *clk_info);
+  Arrival maxCrpr(const ClkInfo *clk_info);
   // Timing check CRPR.
   Crpr checkCrpr(const Path *src_clk_path,
 		 const Path *tgt_clk_path);
diff --git a/search/Genclks.cc b/search/Genclks.cc
index c2914159..7b72c8e6 100644
--- a/search/Genclks.cc
+++ b/search/Genclks.cc
@@ -711,12 +711,12 @@ Genclks::makeTag(const Clock *gclk,
     state = state->nextState();
   ExceptionStateSet *states = new ExceptionStateSet();
   states->insert(state);
-  ClkInfo *clk_info = search_->findClkInfo(master_clk->edge(master_rf),
-					   master_pin, true, nullptr, true,
-					   nullptr, insert, 0.0, nullptr,
-					   path_ap, nullptr);
-  return search_->findTag(master_rf, path_ap, clk_info, false, nullptr, false,
-			  states, true);
+  const ClkInfo *clk_info = search_->findClkInfo(master_clk->edge(master_rf),
+						 master_pin, true, nullptr, true,
+						 nullptr, insert, 0.0, nullptr,
+						 path_ap, nullptr);
+  return search_->findTag(master_rf, path_ap, clk_info, false,
+			  nullptr, false, states, true);
 }
 
 class GenClkArrivalSearchPred : public EvalPred
diff --git a/search/Latches.cc b/search/Latches.cc
index c75028b1..f9328082 100644
--- a/search/Latches.cc
+++ b/search/Latches.cc
@@ -331,7 +331,7 @@ Latches::latchOutArrival(const Path *data_path,
 				   tgt_clk_path_ap, this);
     while (enable_iter.hasNext()) {
       Path *enable_path = enable_iter.next();
-       ClkInfo *en_clk_info = enable_path->clkInfo(this);
+       const ClkInfo *en_clk_info = enable_path->clkInfo(this);
        const ClockEdge *en_clk_edge = en_clk_info->clkEdge();
        if (enable_path->isClock(this)) {
 	 ExceptionPath *excpt = exceptionTo(data_path, en_clk_edge);
@@ -353,7 +353,7 @@ Latches::latchOutArrival(const Path *data_path,
 	     // Tag switcheroo - data passing thru gets latch enable tag.
 	     // States and path ap come from Q, everything else from enable.
 	     Path *crpr_clk_path = crprActive() ? enable_path : nullptr;
-	     ClkInfo *q_clk_info = 
+	     const ClkInfo *q_clk_info = 
 	       search_->findClkInfo(en_clk_edge,
 				    en_clk_info->clkSrc(),
 				    en_clk_info->isPropagated(),
diff --git a/search/Path.cc b/search/Path.cc
index b3436613..d9a6333b 100644
--- a/search/Path.cc
+++ b/search/Path.cc
@@ -49,7 +49,7 @@ Path::Path() :
 {
 }
 
-Path::Path(Path *path) :
+Path::Path(const Path *path) :
   prev_path_(path ? path->prev_path_ : nullptr),
   arrival_(path ? path->arrival_ : 0.0),
   required_(path ? path->required_ : 0.0),
@@ -279,7 +279,7 @@ Path::pathIndex(const StaState *sta) const
   return this - paths;
 }
 
-ClkInfo *
+const ClkInfo *
 Path::clkInfo(const StaState *sta) const
 {
   return tag(sta)->clkInfo();
diff --git a/search/PathEnd.cc b/search/PathEnd.cc
index aa3e7ac9..55430f32 100644
--- a/search/PathEnd.cc
+++ b/search/PathEnd.cc
@@ -330,7 +330,7 @@ PathEnd::checkTgtClkDelay(const Path *tgt_clk_path,
     const MinMax *min_max = tgt_clk_path->minMax(sta);
     const EarlyLate *early_late = check_role->tgtClkEarlyLate();
     const PathAnalysisPt *tgt_path_ap = tgt_clk_path->pathAnalysisPt(sta);
-    ClkInfo *clk_info = tgt_clk_path->clkInfo(sta);
+    const ClkInfo *clk_info = tgt_clk_path->clkInfo(sta);
     const Pin *tgt_src_pin = clk_info->clkSrc();
     const Clock *tgt_clk = tgt_clk_edge->clock();
     const RiseFall *tgt_clk_rf = tgt_clk_edge->transition();
@@ -560,14 +560,14 @@ PathEndClkConstrained::sourceClkOffset(const ClockEdge *src_clk_edge,
 Arrival
 PathEndClkConstrained::sourceClkLatency(const StaState *sta) const
 {
-  ClkInfo *clk_info = path_->clkInfo(sta);
+  const ClkInfo *clk_info = path_->clkInfo(sta);
   return clk_info->latency();
 }
 
 Arrival
 PathEndClkConstrained::sourceClkInsertionDelay(const StaState *sta) const
 {
-  ClkInfo *clk_info = path_->clkInfo(sta);
+  const ClkInfo *clk_info = path_->clkInfo(sta);
   return clk_info->insertion();
 }
 
@@ -1033,7 +1033,7 @@ PathEndCheck::sourceClkDelay(const StaState *sta) const
   PathExpanded expanded(path_, sta);
   const Path *src_clk_path = expanded.clkPath();
   if (src_clk_path) {
-    ClkInfo *src_clk_info = path_->tag(sta)->clkInfo();
+    const ClkInfo *src_clk_info = path_->tag(sta)->clkInfo();
     if (src_clk_info->isPropagated()) {
       // Propagated clock.  Propagated arrival is seeded with insertion delay.
       Arrival clk_arrival = src_clk_path->arrival();
@@ -1280,7 +1280,7 @@ PathEndLatchCheck::targetClkWidth(const StaState *sta) const
   const Search *search = sta->search();
   Arrival disable_arrival = search->clkPathArrival(disable_path_);
   Arrival enable_arrival = search->clkPathArrival(clk_path_);
-  ClkInfo *enable_clk_info = clk_path_->clkInfo(sta);
+  const ClkInfo *enable_clk_info = clk_path_->clkInfo(sta);
   if (enable_clk_info->isPulseClk())
     return disable_arrival - enable_arrival;
   else {
diff --git a/search/PathEnum.cc b/search/PathEnum.cc
index 7a8d15b6..46b6f020 100644
--- a/search/PathEnum.cc
+++ b/search/PathEnum.cc
@@ -644,7 +644,7 @@ PathEnum::updatePathHeadDelays(PathSeq &paths,
 			       Path *after_div)
 {
   Tag *prev_tag = after_div->tag(this);
-  ClkInfo *prev_clk_info = prev_tag->clkInfo();
+  const ClkInfo *prev_clk_info = prev_tag->clkInfo();
   Arrival prev_arrival = search_->clkPathArrival(after_div);
   int path_idx_max = paths.size() - 1;
   // paths[0] is the path endpoint
diff --git a/search/ReportPath.cc b/search/ReportPath.cc
index 889f5d53..d9a633dc 100644
--- a/search/ReportPath.cc
+++ b/search/ReportPath.cc
@@ -2112,7 +2112,7 @@ ReportPath::reportSrcClkAndPath(const Path *path,
       else if (clk_used_as_data 
  	       && pathFromGenPropClk(path, path->minMax(this))) {
 	reportClkLine(clk, clk_name.c_str(), clk_end_rf, clk_time, min_max);
- 	ClkInfo *clk_info = path->tag(search_)->clkInfo();
+ 	const ClkInfo *clk_info = path->tag(search_)->clkInfo();
  	if (clk_info->isPropagated())
  	  reportClkSrcLatency(clk_insertion, clk_time, early_late);
 	reportPath1(path, expanded, true, time_offset);
@@ -2259,7 +2259,7 @@ ReportPath::tgtClkInsertionOffet(const Path *clk_path,
 				 const EarlyLate *early_late,
 				 const PathAnalysisPt *path_ap) const
 {
-  ClkInfo *clk_info = clk_path->clkInfo(this);
+  const ClkInfo *clk_info = clk_path->clkInfo(this);
   const Pin *src_pin = clk_info->clkSrc();
   const ClockEdge *clk_edge = clk_info->clkEdge();
   const Clock *clk = clk_edge->clock();
@@ -2278,7 +2278,7 @@ bool
 ReportPath::pathFromGenPropClk(const Path *clk_path,
 			       const EarlyLate *early_late) const
 {
-  ClkInfo *clk_info = clk_path->tag(search_)->clkInfo();
+  const ClkInfo *clk_info = clk_path->tag(search_)->clkInfo();
   const ClockEdge *clk_edge = clk_info->clkEdge();
   if (clk_edge) {
     const Clock *clk = clk_edge->clock();
@@ -2393,7 +2393,7 @@ ReportPath::reportGenClkSrcPath1(const Clock *clk,
   const Path *src_path = search_->genclks()->srcPath(clk, clk_pin,
                                                      clk_rf, insert_ap);
   if (src_path) {
-    ClkInfo *src_clk_info = src_path->clkInfo(this);
+    const ClkInfo *src_clk_info = src_path->clkInfo(this);
     const ClockEdge *src_clk_edge = src_clk_info->clkEdge();
     const Clock *src_clk = src_clk_info->clock();
     if (src_clk) {
diff --git a/search/Search.cc b/search/Search.cc
index a138267b..2e60efb5 100644
--- a/search/Search.cc
+++ b/search/Search.cc
@@ -589,7 +589,7 @@ void
 Search::deleteFilterClkInfos()
 {
   for (auto itr = clk_info_set_->cbegin(); itr != clk_info_set_->cend(); ) {
-    ClkInfo *clk_info = *itr;
+    const ClkInfo *clk_info = *itr;
     if (clk_info->crprPathRefsFilter()) {
       itr = clk_info_set_->erase(itr);
       delete clk_info;
@@ -1324,7 +1324,7 @@ ArrivalVisitor::visitFromToPath(const Pin * /* from_pin */,
              from_tag->to_string(this).c_str());
   debugPrint(debug_, "search", 3, "  to tag  : %s",
              to_tag->to_string(this).c_str());
-  ClkInfo *to_clk_info = to_tag->clkInfo();
+  const ClkInfo *to_clk_info = to_tag->clkInfo();
   bool to_is_clk = to_tag->isClock();
   Path *match;
   size_t path_index;
@@ -1361,7 +1361,7 @@ ArrivalVisitor::pruneCrprArrivals()
   for (auto path_itr = path_index_map.cbegin(); path_itr != path_index_map.cend(); ) {
     Tag *tag = path_itr->first;
     size_t path_index = path_itr->second;
-    ClkInfo *clk_info = tag->clkInfo();
+    const ClkInfo *clk_info = tag->clkInfo();
     bool deleted_tag = false;
     if (!tag->isClock()
 	&& clk_info->hasCrprClkPin()) {
@@ -1370,7 +1370,7 @@ ArrivalVisitor::pruneCrprArrivals()
       Path *path_no_crpr = tag_bldr_no_crpr_->tagMatchPath(tag);
       if (path_no_crpr) {
         Arrival max_arrival = path_no_crpr->arrival();
-	ClkInfo *clk_info_no_crpr = path_no_crpr->clkInfo(this);
+	const ClkInfo *clk_info_no_crpr = path_no_crpr->clkInfo(this);
 	Arrival max_crpr = crpr->maxCrpr(clk_info_no_crpr);
 	Arrival max_arrival_max_crpr = (min_max == MinMax::max())
 	  ? max_arrival - max_crpr
@@ -1608,9 +1608,9 @@ Search::seedClkArrival(const Pin *pin,
   // Propagate liberty "pulse_clock" transition to transitive fanout.
   LibertyPort *port = network_->libertyPort(pin);
   const RiseFall *pulse_clk_sense = (port ? port->pulseClkSense() : nullptr);
-  ClkInfo *clk_info = findClkInfo(clk_edge, pin, is_propagated, nullptr, false,
-				  pulse_clk_sense, insertion, latency,
-				  uncertainties, path_ap, nullptr);
+  const ClkInfo *clk_info = findClkInfo(clk_edge, pin, is_propagated, nullptr, false,
+					pulse_clk_sense, insertion, latency,
+					uncertainties, path_ap, nullptr);
   // Only false_paths -from apply to clock tree pins.
   ExceptionStateSet *states = nullptr;
   sdc_->exceptionFromClkStates(pin,rf,clk,rf,min_max,states);
@@ -1650,8 +1650,8 @@ Search::clkDataTag(const Pin *pin,
   if (sdc_->exceptionFromStates(pin, rf, clk, rf, min_max, states)) {
     bool is_propagated = (clk->isPropagated()
 			  || sdc_->isPropagatedClock(pin));
-    ClkInfo *clk_info = findClkInfo(clk_edge, pin, is_propagated,
-				    insertion, path_ap);
+    const ClkInfo *clk_info = findClkInfo(clk_edge, pin, is_propagated,
+					  insertion, path_ap);
     return findTag(rf, path_ap, clk_info, false, nullptr, false, states, true);
   }
   else
@@ -1886,7 +1886,7 @@ Search::inputDelayRefPinArrival(Path *ref_path,
 {
   Clock *clk = clk_edge->clock();
   if (clk->isPropagated()) {
-    ClkInfo *clk_info = ref_path->clkInfo(this);
+    const ClkInfo *clk_info = ref_path->clkInfo(this);
     ref_arrival = delayAsFloat(ref_path->arrival());
     ref_insertion = delayAsFloat(clk_info->insertion());
     ref_latency = clk_info->latency();
@@ -2009,15 +2009,15 @@ Search::inputDelayTag(const Pin *pin,
   ExceptionStateSet *states = nullptr;
   Tag *tag = nullptr;
   if (sdc_->exceptionFromStates(pin,rf,clk,clk_rf,min_max,states)) {
-    ClkInfo *clk_info = findClkInfo(clk_edge, clk_pin, is_propagated, nullptr,
-				    false, nullptr, clk_insertion, clk_latency,
-				    clk_uncertainties, path_ap, nullptr);
+    const ClkInfo *clk_info = findClkInfo(clk_edge, clk_pin, is_propagated, nullptr,
+					  false, nullptr, clk_insertion, clk_latency,
+					  clk_uncertainties, path_ap, nullptr);
     tag = findTag(rf, path_ap, clk_info, false, input_delay, is_segment_start,
 		  states, true);
   }
 
   if (tag) {
-    ClkInfo *clk_info = tag->clkInfo();
+    const ClkInfo *clk_info = tag->clkInfo();
     // Check for state changes on existing tag exceptions (pending -thru pins).
     tag = mutateTag(tag, pin, rf, false, clk_info,
 		    pin, rf, false, false, is_segment_start, clk_info,
@@ -2149,7 +2149,7 @@ PathVisitor::visitFromPath(const Pin *from_pin,
 {
   const TimingRole *role = edge->role();
   Tag *from_tag = from_path->tag(this);
-  ClkInfo *from_clk_info = from_tag->clkInfo();
+  const ClkInfo *from_clk_info = from_tag->clkInfo();
   Tag *to_tag = nullptr;
   const ClockEdge *clk_edge = from_clk_info->clkEdge();
   const Clock *clk = from_clk_info->clock();
@@ -2219,7 +2219,7 @@ PathVisitor::visitFromPath(const Pin *from_pin,
 	      // passed thru reg/latch D->Q edges.
 	      && from_tag->isClock())) {
 	const RiseFall *clk_rf = clk_edge ? clk_edge->transition() : nullptr;
-	ClkInfo *to_clk_info = from_clk_info;
+	const ClkInfo *to_clk_info = from_clk_info;
 	if (from_clk_info->crprClkPath(this) == nullptr
             || network_->direction(to_pin)->isInternal())
 	  to_clk_info = search_->clkInfoWithCrprClkPath(from_clk_info,
@@ -2302,7 +2302,7 @@ PathVisitor::visitFromPath(const Pin *from_pin,
 Arrival
 Search::clkPathArrival(const Path *clk_path) const
 {
-  ClkInfo *clk_info = clk_path->clkInfo(this);
+  const ClkInfo *clk_info = clk_path->clkInfo(this);
   const ClockEdge *clk_edge = clk_info->clkEdge();
   const PathAnalysisPt *path_ap = clk_path->pathAnalysisPt(this);
   const MinMax *min_max = path_ap->pathMinMax();
@@ -2311,7 +2311,7 @@ Search::clkPathArrival(const Path *clk_path) const
 
 Arrival
 Search::clkPathArrival(const Path *clk_path,
-		       ClkInfo *clk_info,
+		       const ClkInfo *clk_info,
 		       const ClockEdge *clk_edge,
 		       const MinMax *min_max,
 		       const PathAnalysisPt *path_ap) const
@@ -2336,7 +2336,7 @@ Search::clkPathArrival(const Path *clk_path,
 Arrival
 Search::pathClkPathArrival(const Path *path) const
 {
-  ClkInfo *clk_info = path->clkInfo(this);
+  const ClkInfo *clk_info = path->clkInfo(this);
   if (clk_info->isPropagated()) {
     const Path *src_clk_path = pathClkPathArrival1(path);
     if (src_clk_path)
@@ -2391,7 +2391,7 @@ Search::fromUnclkedInputTag(const Pin *pin,
   ExceptionStateSet *states = nullptr;
   if (sdc_->exceptionFromStates(pin, rf, nullptr, nullptr, min_max, states)
       && (!require_exception || states)) {
-    ClkInfo *clk_info = findClkInfo(nullptr, nullptr, false, 0.0, path_ap);
+    const ClkInfo *clk_info = findClkInfo(nullptr, nullptr, false, 0.0, path_ap);
     return findTag(rf, path_ap, clk_info, false, nullptr,
                    is_segment_start, states, true);
   }
@@ -2403,7 +2403,7 @@ Search::fromRegClkTag(const Pin *from_pin,
 		      const RiseFall *from_rf,
 		      const Clock *clk,
 		      const RiseFall *clk_rf,
-		      ClkInfo *clk_info,
+		      const ClkInfo *clk_info,
 		      const Pin *to_pin,
 		      const RiseFall *to_rf,
 		      const MinMax *min_max,
@@ -2421,8 +2421,8 @@ Search::fromRegClkTag(const Pin *from_pin,
 }
 
 // Insert from_path as ClkInfo crpr_clk_path.
-ClkInfo *
-Search::clkInfoWithCrprClkPath(ClkInfo *from_clk_info,
+const ClkInfo *
+Search::clkInfoWithCrprClkPath(const ClkInfo *from_clk_info,
 			       Path *from_path,
 			       const PathAnalysisPt *path_ap)
 {
@@ -2454,7 +2454,7 @@ Search::thruTag(Tag *from_tag,
   Vertex *to_vertex = edge->to(graph_);
   const Pin *to_pin = to_vertex->pin();
   const RiseFall *from_rf = from_tag->transition();
-  ClkInfo *from_clk_info = from_tag->clkInfo();
+  const ClkInfo *from_clk_info = from_tag->clkInfo();
   bool to_is_reg_clk = to_vertex->isRegClk();
   Tag *to_tag = mutateTag(from_tag, from_pin, from_rf, false, from_clk_info,
 			  to_pin, to_rf, false, to_is_reg_clk, false,
@@ -2479,7 +2479,7 @@ Search::thruClkTag(Path *from_path,
   Vertex *to_vertex = edge->to(graph_);
   const Pin *to_pin = to_vertex->pin();
   const RiseFall *from_rf = from_tag->transition();
-  ClkInfo *from_clk_info = from_tag->clkInfo();
+  const ClkInfo *from_clk_info = from_tag->clkInfo();
   bool from_is_clk = from_tag->isClock();
   bool to_is_reg_clk = to_vertex->isRegClk();
   const TimingRole *role = edge->role();
@@ -2487,19 +2487,20 @@ Search::thruClkTag(Path *from_path,
 		    && to_propagates_clk
 		    && (role->isWire()
 			|| role == TimingRole::combinational()));
-  ClkInfo *to_clk_info = thruClkInfo(from_path, from_vertex, from_clk_info, from_is_clk,
-				     edge, to_vertex, to_pin, to_is_clk,
-                                     arc_delay_min_max_eq, min_max, path_ap);
+  const ClkInfo *to_clk_info = thruClkInfo(from_path, from_vertex,
+					   from_clk_info, from_is_clk,
+					   edge, to_vertex, to_pin, to_is_clk,
+					   arc_delay_min_max_eq, min_max, path_ap);
   Tag *to_tag = mutateTag(from_tag,from_pin,from_rf,from_is_clk,from_clk_info,
 			  to_pin, to_rf, to_is_clk, to_is_reg_clk, false,
 			  to_clk_info, nullptr, min_max, path_ap);
   return to_tag;
 }
 
-ClkInfo *
+const ClkInfo *
 Search::thruClkInfo(Path *from_path,
 		    Vertex *from_vertex,
-		    ClkInfo *from_clk_info,
+		    const ClkInfo *from_clk_info,
                     bool from_is_clk,
 		    Edge *edge,
 		    Vertex *to_vertex,
@@ -2596,11 +2597,13 @@ Search::thruClkInfo(Path *from_path,
   }
 
   if (changed) {
-    ClkInfo *to_clk_info = findClkInfo(from_clk_edge, from_clk_info->clkSrc(),
-                                       to_clk_prop, gen_clk_src,
-                                       from_clk_info->isGenClkSrcPath(),
-                                       to_pulse_sense, to_insertion, to_latency,
-                                       to_uncertainties, path_ap, to_crpr_clk_path);
+    const ClkInfo *to_clk_info = findClkInfo(from_clk_edge,
+					     from_clk_info->clkSrc(),
+					     to_clk_prop, gen_clk_src,
+					     from_clk_info->isGenClkSrcPath(),
+					     to_pulse_sense, to_insertion, to_latency,
+					     to_uncertainties, path_ap,
+					     to_crpr_clk_path);
     return to_clk_info;
   }
   return from_clk_info;
@@ -2612,13 +2615,13 @@ Search::mutateTag(Tag *from_tag,
 		  const Pin *from_pin,
 		  const RiseFall *from_rf,
 		  bool from_is_clk,
-		  ClkInfo *from_clk_info,
+		  const ClkInfo *from_clk_info,
 		  const Pin *to_pin,
 		  const RiseFall *to_rf,
 		  bool to_is_clk,
 		  bool to_is_reg_clk,
 		  bool to_is_segment_start,
-		  ClkInfo *to_clk_info,
+		  const ClkInfo *to_clk_info,
 		  InputDelay *to_input_delay,
 		  const MinMax *min_max,
 		  const PathAnalysisPt *path_ap)
@@ -2965,7 +2968,7 @@ Search::tagCount() const
 Tag *
 Search::findTag(const RiseFall *rf,
 		const PathAnalysisPt *path_ap,
-		ClkInfo *clk_info,
+		const ClkInfo *clk_info,
 		bool is_clk,
 		InputDelay *input_delay,
 		bool is_segment_start,
@@ -3035,17 +3038,17 @@ Search::reportTags() const
 void
 Search::reportClkInfos() const
 {
-  Vector<ClkInfo*> clk_infos;
+  Vector<const ClkInfo*> clk_infos;
   // set -> vector for sorting.
-  for (ClkInfo *clk_info : *clk_info_set_)
+  for (const ClkInfo *clk_info : *clk_info_set_)
     clk_infos.push_back(clk_info);
   sort(clk_infos, ClkInfoLess(this));
-  for (ClkInfo *clk_info : clk_infos)
+  for (const ClkInfo *clk_info : clk_infos)
     report_->reportLine("%s", clk_info->to_string(this).c_str());
   report_->reportLine("%zu clk infos", clk_info_set_->size());
 }
 
-ClkInfo *
+const ClkInfo *
 Search::findClkInfo(const ClockEdge *clk_edge,
 		    const Pin *clk_src,
 		    bool is_propagated,
@@ -3062,7 +3065,7 @@ Search::findClkInfo(const ClockEdge *clk_edge,
 		pulse_clk_sense, insertion, latency, uncertainties,
 		path_ap->index(), crpr_clk_path, this);
   LockGuard lock(clk_info_lock_);
-  ClkInfo *clk_info = clk_info_set_->findKey(&probe);
+  const ClkInfo *clk_info = clk_info_set_->findKey(&probe);
   if (clk_info == nullptr) {
     clk_info = new ClkInfo(clk_edge, clk_src,
 			   is_propagated, gen_clk_src, gen_clk_src_path,
@@ -3073,7 +3076,7 @@ Search::findClkInfo(const ClockEdge *clk_edge,
   return clk_info;
 }
 
-ClkInfo *
+const ClkInfo *
 Search::findClkInfo(const ClockEdge *clk_edge,
 		    const Pin *clk_src,
 		    bool is_propagated,
diff --git a/search/Sta.cc b/search/Sta.cc
index f384a820..8a1d962a 100644
--- a/search/Sta.cc
+++ b/search/Sta.cc
@@ -2881,7 +2881,7 @@ Sta::vertexArrival(Vertex *vertex,
   while (path_iter.hasNext()) {
     Path *path = path_iter.next();
     const Arrival &path_arrival = path->arrival();
-    ClkInfo *clk_info = path->clkInfo(search_);
+    const ClkInfo *clk_info = path->clkInfo(search_);
     if ((clk_edge == clk_edge_wildcard
 	 || clk_info->clkEdge() == clk_edge)
 	&& !clk_info->isGenClkSrcPath()
diff --git a/search/Tag.cc b/search/Tag.cc
index a95b5122..0ebfde38 100644
--- a/search/Tag.cc
+++ b/search/Tag.cc
@@ -41,7 +41,7 @@ namespace sta {
 Tag::Tag(TagIndex index,
 	 int rf_index,
 	 PathAPIndex path_ap_index,
-	 ClkInfo *clk_info,
+	 const ClkInfo *clk_info,
 	 bool is_clk,
 	 InputDelay *input_delay,
 	 bool is_segment_start,
@@ -305,8 +305,8 @@ Tag::cmp(const Tag *tag1,
   if (tag1 == tag2)
     return 0;
 
-  ClkInfo *clk_info1 = tag1->clkInfo();
-  ClkInfo *clk_info2 = tag2->clkInfo();
+  const ClkInfo *clk_info1 = tag1->clkInfo();
+  const ClkInfo *clk_info2 = tag2->clkInfo();
   int clk_cmp = ClkInfo::cmp(clk_info1, clk_info2, sta);
   if (clk_cmp != 0)
     return clk_cmp;
diff --git a/search/Tag.hh b/search/Tag.hh
index 7e6369f7..c158a2b4 100644
--- a/search/Tag.hh
+++ b/search/Tag.hh
@@ -54,7 +54,7 @@ public:
   Tag(TagIndex index,
       int rf_index,
       PathAPIndex path_ap_index,
-      ClkInfo *clk_info,
+      const ClkInfo *clk_info,
       bool is_clk,
       InputDelay *input_delay,
       bool is_segment_start,
@@ -66,7 +66,7 @@ public:
   std::string to_string(bool report_index,
                         bool report_rf_min_max,
                         const StaState *sta) const;
-  ClkInfo *clkInfo() const { return clk_info_; }
+  const ClkInfo *clkInfo() const { return clk_info_; }
   bool isClock() const { return is_clk_; }
   const ClockEdge *clkEdge() const;
   const Clock *clock() const;
@@ -126,7 +126,7 @@ protected:
 			     const Tag *tag2);
 
 private:
-  ClkInfo *clk_info_;
+  const ClkInfo *clk_info_;
   InputDelay *input_delay_;
   ExceptionStateSet *states_;
   size_t hash_;
diff --git a/search/VisitPathEnds.cc b/search/VisitPathEnds.cc
index 9e0ca3bc..b5a762d5 100644
--- a/search/VisitPathEnds.cc
+++ b/search/VisitPathEnds.cc
@@ -162,7 +162,7 @@ VisitPathEnds::visitCheckEnd(const Pin *pin,
 					       tgt_clk_path_ap, this);
 	  while (tgt_clk_path_iter.hasNext()) {
 	    Path *tgt_clk_path = tgt_clk_path_iter.next();
-	    ClkInfo *tgt_clk_info = tgt_clk_path->clkInfo(this);
+	    const ClkInfo *tgt_clk_info = tgt_clk_path->clkInfo(this);
 	    const ClockEdge *tgt_clk_edge = tgt_clk_path->clkEdge(this);
 	    const Clock *tgt_clk = tgt_clk_path->clock(this);
 	    const Pin *tgt_pin = tgt_clk_vertex->pin();