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Improve test case clarity

This commit is contained in:
Akash Levy 2024-07-31 21:12:00 -07:00
parent 84847676b7
commit 17a2a240cc
5 changed files with 100 additions and 90 deletions
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68
test/one2one.lib
View File

@ -20,35 +20,30 @@ library (one_to_one_mismatched_width_test) {
nom_process : 1.0;
nom_temperature : 85.0;
nom_voltage : 0.75;
type (bus20) {
type (bus8) {
base_type : "array";
data_type : "bit";
bit_width : 20;
bit_from : 19;
bit_width : 8;
bit_from : 7;
bit_to : 0;
}
type (bus32) {
type (bus4) {
base_type : "array";
data_type : "bit";
bit_width : 32;
bit_from : 31;
bit_width : 4;
bit_from : 3;
bit_to : 0;
}
cell (or_32_to_20) {
cell (inv_8_to_4) {
bus (A) {
capacitance : 1;
bus_type : "bus32";
direction : "input";
}
bus (B) {
capacitance : 1;
bus_type : "bus32";
bus_type : "bus8";
direction : "input";
}
bus (Y) {
function : "A | B";
bus_type : "bus20";
function : "!A";
bus_type : "bus4";
direction : "output";
timing () {
related_pin : "A";
@ -65,38 +60,18 @@ library (one_to_one_mismatched_width_test) {
values ("1");
}
}
timing () {
related_pin : "B";
cell_rise (scalar) {
values ("1");
}
cell_fall (scalar) {
values ("1");
}
rise_transition (scalar) {
values ("1");
}
fall_transition (scalar) {
values ("1");
}
}
}
}
cell (or_20_to_32) {
cell (inv_4_to_8) {
bus (A) {
capacitance : 1;
bus_type : "bus20";
direction : "input";
}
bus (B) {
capacitance : 1;
bus_type : "bus20";
bus_type : "bus4";
direction : "input";
}
bus (Y) {
function : "A | B";
bus_type : "bus32";
function : "!A";
bus_type : "bus8";
direction : "output";
timing () {
related_pin : "A";
@ -113,21 +88,6 @@ library (one_to_one_mismatched_width_test) {
values ("1");
}
}
timing () {
related_pin : "B";
cell_rise (scalar) {
values ("1");
}
cell_fall (scalar) {
values ("1");
}
rise_transition (scalar) {
values ("1");
}
fall_transition (scalar) {
values ("1");
}
}
}
}
}

104
test/one2one.ok
View File

@ -1,7 +1,5 @@
Warning: one2one.lib line 53, timing port A and related port Y are different sizes.
Warning: one2one.lib line 68, timing port B and related port Y are different sizes.
Warning: one2one.lib line 101, timing port A and related port Y are different sizes.
Warning: one2one.lib line 116, timing port B and related port Y are different sizes.
Warning: one2one.lib line 48, timing port A and related port Y are different sizes.
Warning: one2one.lib line 76, timing port A and related port Y are different sizes.
TEST 1:
Startpoint: a[0] (input port clocked by clk)
Endpoint: y[0] (output port clocked by clk)
@ -14,7 +12,7 @@ Path Type: max
0.00 0.00 clock network delay (ideal)
0.00 0.00 v input external delay
0.00 0.00 v a[0] (in)
1.00 1.00 ^ partial_wide_or_cell/Y[0] (or_32_to_20)
1.00 1.00 ^ partial_wide_inv_cell/Y[0] (inv_8_to_4)
0.00 1.00 ^ y[0] (out)
1.00 data arrival time
@ -30,8 +28,8 @@ Path Type: max
-1.00 slack (VIOLATED)
Startpoint: a[10] (input port clocked by clk)
Endpoint: y[10] (output port clocked by clk)
Startpoint: a[1] (input port clocked by clk)
Endpoint: y[1] (output port clocked by clk)
Path Group: clk
Path Type: max
@ -40,9 +38,9 @@ Path Type: max
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 v input external delay
0.00 0.00 v a[10] (in)
1.00 1.00 ^ partial_wide_or_cell/Y[10] (or_32_to_20)
0.00 1.00 ^ y[10] (out)
0.00 0.00 v a[1] (in)
1.00 1.00 ^ partial_wide_inv_cell/Y[1] (inv_8_to_4)
0.00 1.00 ^ y[1] (out)
1.00 data arrival time
0.00 0.00 clock clk (rise edge)
@ -57,8 +55,8 @@ Path Type: max
-1.00 slack (VIOLATED)
Startpoint: a[11] (input port clocked by clk)
Endpoint: y[11] (output port clocked by clk)
Startpoint: a[2] (input port clocked by clk)
Endpoint: y[2] (output port clocked by clk)
Path Group: clk
Path Type: max
@ -67,9 +65,36 @@ Path Type: max
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 v input external delay
0.00 0.00 v a[11] (in)
1.00 1.00 ^ partial_wide_or_cell/Y[11] (or_32_to_20)
0.00 1.00 ^ y[11] (out)
0.00 0.00 v a[2] (in)
1.00 1.00 ^ partial_wide_inv_cell/Y[2] (inv_8_to_4)
0.00 1.00 ^ y[2] (out)
1.00 data arrival time
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 clock reconvergence pessimism
0.00 0.00 output external delay
0.00 data required time
---------------------------------------------------------
0.00 data required time
-1.00 data arrival time
---------------------------------------------------------
-1.00 slack (VIOLATED)
Startpoint: a[3] (input port clocked by clk)
Endpoint: y[3] (output port clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 v input external delay
0.00 0.00 v a[3] (in)
1.00 1.00 ^ partial_wide_inv_cell/Y[3] (inv_8_to_4)
0.00 1.00 ^ y[3] (out)
1.00 data arrival time
0.00 0.00 clock clk (rise edge)
@ -96,7 +121,7 @@ Path Type: max
0.00 0.00 clock network delay (ideal)
0.00 0.00 v input external delay
0.00 0.00 v a[0] (in)
1.00 1.00 ^ wide_or_cell/Y[0] (or_20_to_32)
1.00 1.00 ^ partial_wide_inv_cell/Y[0] (inv_4_to_8)
0.00 1.00 ^ y[0] (out)
1.00 data arrival time
@ -112,8 +137,8 @@ Path Type: max
-1.00 slack (VIOLATED)
Startpoint: a[10] (input port clocked by clk)
Endpoint: y[10] (output port clocked by clk)
Startpoint: a[1] (input port clocked by clk)
Endpoint: y[1] (output port clocked by clk)
Path Group: clk
Path Type: max
@ -122,9 +147,9 @@ Path Type: max
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 v input external delay
0.00 0.00 v a[10] (in)
1.00 1.00 ^ wide_or_cell/Y[10] (or_20_to_32)
0.00 1.00 ^ y[10] (out)
0.00 0.00 v a[1] (in)
1.00 1.00 ^ partial_wide_inv_cell/Y[1] (inv_4_to_8)
0.00 1.00 ^ y[1] (out)
1.00 data arrival time
0.00 0.00 clock clk (rise edge)
@ -139,8 +164,8 @@ Path Type: max
-1.00 slack (VIOLATED)
Startpoint: a[11] (input port clocked by clk)
Endpoint: y[11] (output port clocked by clk)
Startpoint: a[2] (input port clocked by clk)
Endpoint: y[2] (output port clocked by clk)
Path Group: clk
Path Type: max
@ -149,9 +174,36 @@ Path Type: max
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 v input external delay
0.00 0.00 v a[11] (in)
1.00 1.00 ^ wide_or_cell/Y[11] (or_20_to_32)
0.00 1.00 ^ y[11] (out)
0.00 0.00 v a[2] (in)
1.00 1.00 ^ partial_wide_inv_cell/Y[2] (inv_4_to_8)
0.00 1.00 ^ y[2] (out)
1.00 data arrival time
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 clock reconvergence pessimism
0.00 0.00 output external delay
0.00 data required time
---------------------------------------------------------
0.00 data required time
-1.00 data arrival time
---------------------------------------------------------
-1.00 slack (VIOLATED)
Startpoint: a[3] (input port clocked by clk)
Endpoint: y[3] (output port clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 v input external delay
0.00 0.00 v a[3] (in)
1.00 1.00 ^ partial_wide_inv_cell/Y[3] (inv_4_to_8)
0.00 1.00 ^ y[3] (out)
1.00 data arrival time
0.00 0.00 clock clk (rise edge)

4
test/one2one.tcl
View File

@ -6,7 +6,7 @@ link_design one2one_test1
create_clock -name clk -period 0
set_input_delay -clock clk 0 [all_inputs]
set_output_delay -clock clk 0 [all_outputs]
report_checks -group_count 3
report_checks -group_count 5
puts "TEST 2:"
read_verilog one2one_test2.v
@ -14,4 +14,4 @@ link_design one2one_test2
create_clock -name clk -period 0
set_input_delay -clock clk 0 [all_inputs]
set_output_delay -clock clk 0 [all_outputs]
report_checks -group_count 3
report_checks -group_count 5

7
test/one2one_test1.v
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@ -1,13 +1,12 @@
// Liberty file test: one-to-one mapping with mismatched bit widths
// Should generate warning but still create timing arcs between bits with same index
module one2one_test1 (
input wire [31:0] a,
output wire [19:0] y
input wire [7:0] a,
output wire [3:0] y
);
or_32_to_20 partial_wide_or_cell (
inv_8_to_4 partial_wide_inv_cell (
.A(a),
.B(32'b0),
.Y(y)
);

7
test/one2one_test2.v
View File

@ -1,13 +1,12 @@
// Liberty file test: one-to-one mapping with mismatched bit widths
// Should generate warning but still create timing arcs between bits with same index
module one2one_test2 (
input wire [19:0] a,
output wire [31:0] y
input wire [3:0] a,
output wire [7:0] y
);
or_20_to_32 partial_wide_or_cell (
inv_4_to_8 partial_wide_inv_cell (
.A(a),
.B(20'b0),
.Y(y)
);