221 lines
7.4 KiB
Plaintext
221 lines
7.4 KiB
Plaintext
Warning: one2one.lib line 48, timing port A and related port Y are different sizes.
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Warning: one2one.lib line 76, timing port A and related port Y are different sizes.
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TEST 1:
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Startpoint: a[0] (input port clocked by clk)
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Endpoint: y[0] (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v a[0] (in)
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1.00 1.00 ^ partial_wide_inv_cell/Y[0] (inv_8_to_4)
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0.00 1.00 ^ y[0] (out)
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1.00 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 0.00 output external delay
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0.00 data required time
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---------------------------------------------------------
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0.00 data required time
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-1.00 data arrival time
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---------------------------------------------------------
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-1.00 slack (VIOLATED)
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Startpoint: a[1] (input port clocked by clk)
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Endpoint: y[1] (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v a[1] (in)
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1.00 1.00 ^ partial_wide_inv_cell/Y[1] (inv_8_to_4)
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0.00 1.00 ^ y[1] (out)
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1.00 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 0.00 output external delay
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0.00 data required time
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---------------------------------------------------------
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0.00 data required time
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-1.00 data arrival time
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---------------------------------------------------------
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-1.00 slack (VIOLATED)
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Startpoint: a[2] (input port clocked by clk)
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Endpoint: y[2] (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v a[2] (in)
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1.00 1.00 ^ partial_wide_inv_cell/Y[2] (inv_8_to_4)
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0.00 1.00 ^ y[2] (out)
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1.00 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 0.00 output external delay
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0.00 data required time
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---------------------------------------------------------
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0.00 data required time
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-1.00 data arrival time
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---------------------------------------------------------
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-1.00 slack (VIOLATED)
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Startpoint: a[3] (input port clocked by clk)
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Endpoint: y[3] (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v a[3] (in)
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1.00 1.00 ^ partial_wide_inv_cell/Y[3] (inv_8_to_4)
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0.00 1.00 ^ y[3] (out)
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1.00 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 0.00 output external delay
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0.00 data required time
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---------------------------------------------------------
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0.00 data required time
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-1.00 data arrival time
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---------------------------------------------------------
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-1.00 slack (VIOLATED)
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TEST 2:
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Startpoint: a[0] (input port clocked by clk)
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Endpoint: y[0] (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v a[0] (in)
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1.00 1.00 ^ partial_wide_inv_cell/Y[0] (inv_4_to_8)
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0.00 1.00 ^ y[0] (out)
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1.00 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 0.00 output external delay
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0.00 data required time
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---------------------------------------------------------
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0.00 data required time
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-1.00 data arrival time
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---------------------------------------------------------
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-1.00 slack (VIOLATED)
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Startpoint: a[1] (input port clocked by clk)
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Endpoint: y[1] (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v a[1] (in)
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1.00 1.00 ^ partial_wide_inv_cell/Y[1] (inv_4_to_8)
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0.00 1.00 ^ y[1] (out)
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1.00 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 0.00 output external delay
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0.00 data required time
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---------------------------------------------------------
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0.00 data required time
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-1.00 data arrival time
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---------------------------------------------------------
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-1.00 slack (VIOLATED)
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Startpoint: a[2] (input port clocked by clk)
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Endpoint: y[2] (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v a[2] (in)
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1.00 1.00 ^ partial_wide_inv_cell/Y[2] (inv_4_to_8)
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0.00 1.00 ^ y[2] (out)
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1.00 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 0.00 output external delay
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0.00 data required time
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---------------------------------------------------------
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0.00 data required time
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-1.00 data arrival time
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---------------------------------------------------------
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-1.00 slack (VIOLATED)
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Startpoint: a[3] (input port clocked by clk)
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Endpoint: y[3] (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v a[3] (in)
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1.00 1.00 ^ partial_wide_inv_cell/Y[3] (inv_4_to_8)
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0.00 1.00 ^ y[3] (out)
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1.00 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 0.00 output external delay
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0.00 data required time
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---------------------------------------------------------
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0.00 data required time
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-1.00 data arrival time
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---------------------------------------------------------
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-1.00 slack (VIOLATED)
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