diff --git a/doc/ApiChanges.txt b/doc/ApiChanges.txt
index 9cda8fa7..d2ad43f8 100644
--- a/doc/ApiChanges.txt
+++ b/doc/ApiChanges.txt
@@ -53,6 +53,9 @@ The following classes now return const objects.
Liberty PgPorts are now LibertyPorts with additional member functions for
liberty pg_pins.
+The write_verilog command always sorts the verilog file instances.
+The -sort argument is ignored.
+
Release 2.6.1 2025/03/??
-------------------------
diff --git a/doc/OpenSTA.fodt b/doc/OpenSTA.fodt
index 84751fab..f7a17c62 100644
--- a/doc/OpenSTA.fodt
+++ b/doc/OpenSTA.fodt
@@ -13772,18 +13772,9 @@
write_verilog
- [-sort]
[-include_pwr_gnd][-remove_cells lib_cells]filename
-
-
- -sort
-
-
- Sort the instances in the netlist.
-
-
-include_pwr_gnd
@@ -13809,7 +13800,7 @@
- The write_verilog command writes a Verilog netlist to filename. Use -sort to sort the instances so the results are reproducible across operating systems. Use -remove_cells to remove instances of lib_cells from the netlist.
+ The write_verilog command writes a Verilog netlist to filename. Instances are always sorted so the results are reproducible across operating systems. Use -remove_cells to remove instances of lib_cells from the netlist.
Filter Expressions
The get_cells, get_pins, get_ports and get_timing_edges functions support filtering the returned objects by property values. Supported filter expressions are shown below.
diff --git a/include/sta/VerilogWriter.hh b/include/sta/VerilogWriter.hh
index ec44dd30..b4a08e8c 100644
--- a/include/sta/VerilogWriter.hh
+++ b/include/sta/VerilogWriter.hh
@@ -30,7 +30,6 @@ namespace sta {
void
writeVerilog(const char *filename,
- bool sort,
bool include_pwr_gnd,
CellSeq *remove_cells,
Network *network);
diff --git a/verilog/Verilog.i b/verilog/Verilog.i
index 63561423..5e1744ef 100644
--- a/verilog/Verilog.i
+++ b/verilog/Verilog.i
@@ -39,14 +39,13 @@ read_verilog_cmd(const char *filename)
void
write_verilog_cmd(const char *filename,
- bool sort,
bool include_pwr_gnd,
CellSeq *remove_cells)
{
// This does NOT want the SDC (cmd) network because it wants
// to see the sta internal names.
Network *network = Sta::sta()->network();
- writeVerilog(filename, sort, include_pwr_gnd, remove_cells, network);
+ writeVerilog(filename, include_pwr_gnd, remove_cells, network);
delete remove_cells;
}
diff --git a/verilog/Verilog.tcl b/verilog/Verilog.tcl
index bf024119..f4a459f5 100644
--- a/verilog/Verilog.tcl
+++ b/verilog/Verilog.tcl
@@ -31,22 +31,25 @@ proc_redirect read_verilog {
read_verilog_cmd [file nativename [lindex $args 0]]
}
-define_cmd_args "write_verilog" {[-sort] [-include_pwr_gnd]\
+define_cmd_args "write_verilog" {[-include_pwr_gnd]\
[-remove_cells cells] filename}
proc write_verilog { args } {
+ # -sort deprecated 12/12/2025
parse_key_args "write_verilog" args keys {-remove_cells} \
flags {-sort -include_pwr_gnd}
+ if { [info exists flags(-sort)] } {
+ sta_warn 1338 "The -sort flag is ignored."
+ }
set remove_cells {}
if { [info exists keys(-remove_cells)] } {
set remove_cells [parse_cell_arg $keys(-remove_cells)]
}
- set sort [info exists flags(-sort)]
set include_pwr_gnd [info exists flags(-include_pwr_gnd)]
check_argc_eq1 "write_verilog" $args
set filename [file nativename [lindex $args 0]]
- write_verilog_cmd $filename $sort $include_pwr_gnd $remove_cells
+ write_verilog_cmd $filename $include_pwr_gnd $remove_cells
}
# sta namespace end
diff --git a/verilog/VerilogWriter.cc b/verilog/VerilogWriter.cc
index 52c9d548..dd856d7b 100644
--- a/verilog/VerilogWriter.cc
+++ b/verilog/VerilogWriter.cc
@@ -45,7 +45,6 @@ class VerilogWriter
{
public:
VerilogWriter(const char *filename,
- bool sort,
bool include_pwr_gnd,
CellSeq *remove_cells,
FILE *stream,
@@ -81,7 +80,6 @@ protected:
const Port *port);
const char *filename_;
- bool sort_;
bool include_pwr_gnd_;
CellSet remove_cells_;
FILE *stream_;
@@ -91,7 +89,6 @@ protected:
void
writeVerilog(const char *filename,
- bool sort,
bool include_pwr_gnd,
CellSeq *remove_cells,
Network *network)
@@ -99,7 +96,7 @@ writeVerilog(const char *filename,
if (network->topInstance()) {
FILE *stream = fopen(filename, "w");
if (stream) {
- VerilogWriter writer(filename, sort, include_pwr_gnd,
+ VerilogWriter writer(filename, include_pwr_gnd,
remove_cells, stream, network);
writer.writeModules();
fclose(stream);
@@ -110,13 +107,11 @@ writeVerilog(const char *filename,
}
VerilogWriter::VerilogWriter(const char *filename,
- bool sort,
bool include_pwr_gnd,
CellSeq *remove_cells,
FILE *stream,
Network *network) :
filename_(filename),
- sort_(sort),
include_pwr_gnd_(include_pwr_gnd),
remove_cells_(network),
stream_(stream),
@@ -146,13 +141,12 @@ VerilogWriter::findHierChildren()
CellSet cells(network_);
findHierChildren(network_->topInstance(), children, cells);
- if (sort_)
- sort(children, [this](const Instance *inst1,
- const Instance *inst2) {
- const char *cell_name1 = network_->cellName(inst1);
- const char *cell_name2 = network_->cellName(inst2);
- return stringLess(cell_name1, cell_name2);
- });
+ sort(children, [this](const Instance *inst1,
+ const Instance *inst2) {
+ const char *cell_name1 = network_->cellName(inst1);
+ const char *cell_name2 = network_->cellName(inst2);
+ return stringLess(cell_name1, cell_name2);
+ });
return children;
}
@@ -327,11 +321,10 @@ VerilogWriter::writeChildren(const Instance *inst)
}
delete child_iter;
- if (sort_)
- sort(children, [this](const Instance *inst1,
- const Instance *inst2) {
- return stringLess(network_->name(inst1), network_->name(inst2));
- });
+ sort(children, [this](const Instance *inst1,
+ const Instance *inst2) {
+ return stringLess(network_->name(inst1), network_->name(inst2));
+ });
for (auto child : children)
writeChild(child);