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OpenSTA
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compile warnings 

Signed-off-by: James Cherry <cherry@parallaxsw.com>
This commit is contained in:
James Cherry 2024-04-13 21:18:39 -07:00
parent be82087bdf
commit 057a5dd283
8 changed files with 15 additions and 12 deletions
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2
dcalc/CcsCeffDelayCalc.cc
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@ -87,7 +87,7 @@ CcsCeffDelayCalc::gateDelay(const Pin *drvr_pin,
vth_ = drvr_library->outputThreshold(rf) * vdd_;
vl_ = drvr_library->slewLowerThreshold(rf) * vdd_;
vh_ = drvr_library->slewUpperThreshold(rf) * vdd_;
in_slew_ = in_slew;
in_slew_ = delayAsFloat(in_slew);
load_cap_ = load_cap;
parasitic_ = parasitic;
drvr_cell->ensureVoltageWaveforms();

4
include/sta/PathEnd.hh
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@ -143,7 +143,7 @@ public:
// PathEndDataCheck data clock path.
virtual const PathVertex *dataClkPath() const { return nullptr; }
virtual int setupDefaultCycles() const { return 1; }
virtual float clkSkew(const StaState *sta);
virtual Delay clkSkew(const StaState *sta);
static bool less(const PathEnd *path_end1,
const PathEnd *path_end2,
@ -328,7 +328,7 @@ public:
virtual int exceptPathCmp(const PathEnd *path_end,
const StaState *sta) const;
virtual Delay sourceClkDelay(const StaState *sta) const;
virtual float clkSkew(const StaState *sta);
virtual Delay clkSkew(const StaState *sta);
protected:
PathEndCheck(Path *path,

2
liberty/Liberty.cc
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@ -1896,7 +1896,7 @@ void
LibertyCell::ensureVoltageWaveforms()
{
if (!have_voltage_waveforms_) {
float vdd;
float vdd = 0.0; // shutup gcc
bool vdd_exists;
liberty_library_->supplyVoltage("VDD", vdd, vdd_exists);
if (!vdd_exists || vdd == 0.0)

5
search/ClkLatency.cc
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@ -280,7 +280,8 @@ ClkDelays::insertionDelay(PathVertex *clk_path,
const Pin *src_pin = clk_info->clkSrc();
const PathAnalysisPt *path_ap = clk_path->pathAnalysisPt(sta);
const MinMax *min_max = clk_path->minMax(sta);
return sta->search()->clockInsertion(clk, src_pin, clk_rf, min_max, min_max, path_ap);
return delayAsFloat(sta->search()->clockInsertion(clk, src_pin, clk_rf, min_max,
min_max, path_ap));
}
float
@ -292,7 +293,7 @@ ClkDelays::clkTreeDelay(PathVertex *clk_path,
const LibertyPort *port = sta->network()->libertyPort(pin);
const MinMax *min_max = clk_path->minMax(sta);
const RiseFall *rf = clk_path->transition(sta);
Slew slew = clk_path->slew(sta);
float slew = delayAsFloat(clk_path->slew(sta));
return port->clkTreeDelay(slew, rf, min_max);
}

2
search/ClkSkew.cc
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@ -133,7 +133,7 @@ ClkSkew::clkTreeDelay(PathVertex &clk_path,
const LibertyPort *port = sta->network()->libertyPort(pin);
const MinMax *min_max = clk_path.minMax(sta);
const RiseFall *rf = clk_path.transition(sta);
Slew slew = clk_path.slew(sta);
float slew = delayAsFloat(clk_path.slew(sta));
return port->clkTreeDelay(slew, rf, min_max);
}

6
search/PathEnd.cc
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@ -1069,7 +1069,7 @@ PathEndCheck::sourceClkDelay(const StaState *sta) const
// Propagated clock. Propagated arrival is seeded with insertion delay.
Arrival clk_arrival = src_clk_path.arrival(sta);
const ClockEdge *src_clk_edge = src_clk_info->clkEdge();
float insertion = sourceClkInsertionDelay(sta);
Delay insertion = sourceClkInsertionDelay(sta);
return delayRemove(clk_arrival - src_clk_edge->time(), insertion);
}
else
@ -1080,7 +1080,7 @@ PathEndCheck::sourceClkDelay(const StaState *sta) const
return 0.0;
}
float
Delay
PathEndCheck::clkSkew(const StaState *sta)
{
commonClkPessimism(sta);
@ -1858,7 +1858,7 @@ PathEndPathDelay::sourceClkOffset(const StaState *sta) const
return pathDelaySrcClkOffset(path_, path_delay_, src_clk_arrival_, sta);
}
float
Delay
PathEnd::clkSkew(const StaState *)
{
return 0.0;

4
search/Sta.cc
View File

@ -5167,7 +5167,9 @@ instMaxSlew(const Instance *inst,
Pin *pin = pin_iter->next();
if (network->isDriver(pin)) {
Vertex *vertex = graph->pinDrvrVertex(pin);
max_slew = max(max_slew, sta->vertexSlew(vertex, MinMax::max()));
Slew slew = sta->vertexSlew(vertex, MinMax::max());
if (delayGreater(slew, max_slew, sta))
max_slew = slew;
}
}
delete pin_iter;

2
tcl/StaTcl.i
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@ -4940,7 +4940,7 @@ bool path_delay_margin_is_external()
Crpr common_clk_pessimism() { return self->commonClkPessimism(Sta::sta()); }
RiseFall *target_clk_end_trans()
{ return const_cast<RiseFall*>(self->targetClkEndTrans(Sta::sta())); }
float clk_skew() { return self->clkSkew(Sta::sta()); }
Delay clk_skew() { return self->clkSkew(Sta::sta()); }
}