380 lines
12 KiB
Plaintext
380 lines
12 KiB
Plaintext
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--- Test 1: log file with large output ---
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Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ r2/CK (DFF_X1)
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0.08 0.08 v r2/Q (DFF_X1)
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0.02 0.10 v u1/Z (BUF_X1)
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0.03 0.13 v u2/ZN (AND2_X1)
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0.00 0.13 v r3/D (DFF_X1)
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0.13 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ r3/CK (DFF_X1)
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-0.04 9.96 library setup time
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9.96 data required time
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---------------------------------------------------------
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9.96 data required time
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-0.13 data arrival time
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---------------------------------------------------------
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9.83 slack (MET)
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Startpoint: in1 (input port clocked by clk)
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Endpoint: r1 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: min
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v in1 (in)
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0.00 0.00 v r1/D (DFF_X1)
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0.00 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 ^ r1/CK (DFF_X1)
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0.05 0.05 library hold time
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0.05 data required time
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---------------------------------------------------------
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0.05 data required time
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-0.00 data arrival time
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---------------------------------------------------------
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-0.05 slack (VIOLATED)
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Warning: util_report_string_log.tcl line 1, unknown field nets.
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Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Fanout Cap Slew Delay Time Description
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-----------------------------------------------------------------------------
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0.00 0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 0.00 ^ r2/CK (DFF_X1)
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1 0.88 0.01 0.08 0.08 v r2/Q (DFF_X1)
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0.01 0.00 0.08 v u1/A (BUF_X1)
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1 0.89 0.00 0.02 0.10 v u1/Z (BUF_X1)
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0.00 0.00 0.10 v u2/A2 (AND2_X1)
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1 1.06 0.01 0.03 0.13 v u2/ZN (AND2_X1)
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0.01 0.00 0.13 v r3/D (DFF_X1)
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0.13 data arrival time
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0.00 10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ r3/CK (DFF_X1)
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-0.04 9.96 library setup time
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9.96 data required time
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-----------------------------------------------------------------------------
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9.96 data required time
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-0.13 data arrival time
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-----------------------------------------------------------------------------
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9.83 slack (MET)
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Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ r2/CK (DFF_X1)
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0.08 0.08 v r2/Q (DFF_X1)
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0.02 0.10 v u1/Z (BUF_X1)
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0.03 0.13 v u2/ZN (AND2_X1)
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0.00 0.13 v r3/D (DFF_X1)
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0.13 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ r3/CK (DFF_X1)
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-0.04 9.96 library setup time
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9.96 data required time
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---------------------------------------------------------
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9.96 data required time
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-0.13 data arrival time
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---------------------------------------------------------
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9.83 slack (MET)
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Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ r2/CK (DFF_X1)
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0.08 0.08 v r2/Q (DFF_X1)
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0.02 0.10 v u1/Z (BUF_X1)
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0.03 0.13 v u2/ZN (AND2_X1)
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0.00 0.13 v r3/D (DFF_X1)
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0.13 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ r3/CK (DFF_X1)
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-0.04 9.96 library setup time
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9.96 data required time
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---------------------------------------------------------
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9.96 data required time
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-0.13 data arrival time
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---------------------------------------------------------
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9.83 slack (MET)
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Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ r2/CK (DFF_X1)
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0.08 0.08 v r2/Q (DFF_X1)
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0.02 0.10 v u1/Z (BUF_X1)
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0.03 0.13 v u2/ZN (AND2_X1)
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0.00 0.13 v r3/D (DFF_X1)
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0.13 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ r3/CK (DFF_X1)
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-0.04 9.96 library setup time
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9.96 data required time
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---------------------------------------------------------
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9.96 data required time
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-0.13 data arrival time
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---------------------------------------------------------
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9.83 slack (MET)
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Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ r2/CK (DFF_X1)
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0.08 0.08 v r2/Q (DFF_X1)
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0.02 0.10 v u1/Z (BUF_X1)
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0.03 0.13 v u2/ZN (AND2_X1)
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0.00 0.13 v r3/D (DFF_X1)
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0.13 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ r3/CK (DFF_X1)
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-0.04 9.96 library setup time
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9.96 data required time
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---------------------------------------------------------
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9.96 data required time
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-0.13 data arrival time
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---------------------------------------------------------
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9.83 slack (MET)
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Startpoint: r3 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: out (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ r3/CK (DFF_X1)
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0.08 0.08 ^ r3/Q (DFF_X1)
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0.00 0.08 ^ out (out)
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0.08 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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0.00 10.00 output external delay
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10.00 data required time
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---------------------------------------------------------
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10.00 data required time
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-0.08 data arrival time
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---------------------------------------------------------
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9.92 slack (MET)
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Startpoint: in1 (input port clocked by clk)
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Endpoint: r1 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v in1 (in)
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0.00 0.00 v r1/D (DFF_X1)
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0.00 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ r1/CK (DFF_X1)
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-0.07 9.93 library setup time
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9.93 data required time
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---------------------------------------------------------
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9.93 data required time
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-0.00 data arrival time
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---------------------------------------------------------
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9.93 slack (MET)
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Startpoint: in2 (input port clocked by clk)
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Endpoint: r2 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v in2 (in)
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0.00 0.00 v r2/D (DFF_X1)
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0.00 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ r2/CK (DFF_X1)
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-0.07 9.93 library setup time
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9.93 data required time
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---------------------------------------------------------
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9.93 data required time
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-0.00 data arrival time
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---------------------------------------------------------
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9.93 slack (MET)
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time 1ns
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capacitance 1fF
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resistance 1kohm
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voltage 1v
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current 1mA
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power 1nW
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distance 1um
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time 1ps
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capacitance 1fF
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resistance 1kohm
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voltage 1v
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current 1mA
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power 1nW
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distance 1um
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time 1ns
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capacitance 1pF
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resistance 1kohm
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voltage 1v
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current 1mA
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power 1nW
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distance 1um
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time 1ns
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capacitance 1pF
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resistance 1kohm
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voltage 1v
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current 1mA
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power 1nW
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distance 1um
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PASS: log file with large output
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log file size: 10600
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PASS: log file has significant content
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--- Test 2: log + redirect simultaneous ---
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PASS: simultaneous log + redirect
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log size: 3326, redirect size: 3326
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PASS: both files have content
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--- Test 3: redirect string ---
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redirect string length: 2002
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PASS: redirect string captured large content
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cycle 0 string length: 95
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cycle 1 string length: 95
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cycle 2 string length: 95
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cycle 3 string length: 95
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cycle 4 string length: 95
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PASS: redirect string cycles
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--- Test 4: with_output_to_variable ---
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v1 length: 994
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v2 length: 913
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v3 length: 95
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v4 length: 2002
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PASS: combined output >= single
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PASS: with_output_to_variable
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--- Test 5: redirect file append ---
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before append: 95, after append: 1089
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PASS: append grew file
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PASS: redirect file append
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--- Test 6: error paths ---
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PASS: caught FileNotReadable
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PASS: caught FileNotWritable
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Warning: /workspace/sta/OpenSTA/util/test/results/bad_verilog.v line 2, module NONEXISTENT_CELL not found. Creating black box for u1.
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bad verilog result: rc=0
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PASS: bad verilog error path
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--- Test 7: message suppression ---
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PASS: suppress range
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PASS: unsuppress range
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PASS: suppress SPEF warnings
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PASS: unsuppress SPEF warnings
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--- Test 8: debug levels ---
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PASS: debug level setting
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PASS: higher debug levels
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--- Test 9: format functions ---
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format_time(1e-9) = 1.0000
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format_time(1e-10) = 0.1000
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format_time(1e-11) = 0.0100
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format_time(1e-12) = 0.0010
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format_time(5.5e-9) = 5.5000
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format_time(0.0) = 0.0000
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format_capacitance(1e-12) = 1.0000
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format_capacitance(1e-13) = 0.1000
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format_capacitance(1e-14) = 0.0100
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format_capacitance(1e-15) = 0.0010
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format_capacitance(5.5e-12) = 5.5000
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format_capacitance(0.0) = 0.0000
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format_resistance(100) = 0.1000
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format_resistance(1000) = 1.0000
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format_resistance(10000) = 10.0000
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format_resistance(0.1) = 0.0001
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format_resistance(0.0) = 0.0000
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format_power(1e-3) = 1000000.0625
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format_power(1e-6) = 1000.0000
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format_power(1e-9) = 1.0000
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format_power(5.5e-3) = 5500000.0000
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format_power(0.0) = 0.0000
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PASS: format functions
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ALL PASSED
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