303 lines
14 KiB
Plaintext
303 lines
14 KiB
Plaintext
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--- read SPEF for interconnect ---
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PASS: read SPEF (DSPEF)
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Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (propagated)
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0.00 0.00 ^ r2/CK (DFF_X1)
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0.99 0.99 ^ r2/Q (DFF_X1)
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0.69 1.69 ^ u1/Z (BUF_X1)
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0.74 2.42 ^ u2/ZN (AND2_X1)
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0.00 2.42 ^ r3/D (DFF_X1)
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2.42 data arrival time
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500.00 500.00 clock clk (rise edge)
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0.00 500.00 clock network delay (propagated)
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0.00 500.00 clock reconvergence pessimism
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500.00 ^ r3/CK (DFF_X1)
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-0.11 499.89 library setup time
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499.89 data required time
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---------------------------------------------------------
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499.89 data required time
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-2.42 data arrival time
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---------------------------------------------------------
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497.47 slack (MET)
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PASS: report_checks with SPEF
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--- write_sdf with interconnect ---
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PASS: write_sdf default size=2688
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--- write_sdf -include_typ ---
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PASS: write_sdf -include_typ size=2980
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--- write_sdf -divider . ---
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PASS: write_sdf -divider . size=2688
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--- write_sdf -digits ---
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PASS: write_sdf -digits 2 size=2576
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PASS: write_sdf -digits 4 size=2800
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PASS: write_sdf -digits 6 size=3024
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PASS: write_sdf -digits 8 size=3248
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--- write_sdf -no_timestamp -no_version ---
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PASS: write_sdf clean size=2634
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--- write_sdf -gzip ---
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PASS: write_sdf -gzip created non-empty file
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--- write_sdf all options ---
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PASS: write_sdf all options size=3094
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--- read back SDF ---
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PASS: read back written SDF
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Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (propagated)
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0.00 0.00 ^ r2/CK (DFF_X1)
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0.99 0.99 ^ r2/Q (DFF_X1)
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0.69 1.68 ^ u1/Z (BUF_X1)
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0.74 2.42 ^ u2/ZN (AND2_X1)
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0.00 2.42 ^ r3/D (DFF_X1)
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2.42 data arrival time
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500.00 500.00 clock clk (rise edge)
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0.00 500.00 clock network delay (propagated)
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0.00 500.00 clock reconvergence pessimism
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500.00 ^ r3/CK (DFF_X1)
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-0.11 499.89 library setup time
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499.89 data required time
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---------------------------------------------------------
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499.89 data required time
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-2.42 data arrival time
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---------------------------------------------------------
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497.47 slack (MET)
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PASS: report_checks after SDF roundtrip
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--- annotated delay with interconnect ---
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Not
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Delay type Total Annotated Annotated
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----------------------------------------------------------------
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cell arcs 9 9 0
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----------------------------------------------------------------
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9 9 0
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PASS: annotated delay -cell
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Not
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Delay type Total Annotated Annotated
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----------------------------------------------------------------
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internal net arcs 4 4 0
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----------------------------------------------------------------
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4 4 0
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PASS: annotated delay -net
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Not
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Delay type Total Annotated Annotated
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----------------------------------------------------------------
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cell arcs 9 9 0
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internal net arcs 4 4 0
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----------------------------------------------------------------
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13 13 0
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PASS: annotated delay -cell -net
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Not
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Delay type Total Annotated Annotated
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----------------------------------------------------------------
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net arcs from primary inputs 5 5 0
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net arcs to primary outputs 1 1 0
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----------------------------------------------------------------
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6 6 0
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PASS: annotated delay from/to ports
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Not
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Delay type Total Annotated Annotated
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----------------------------------------------------------------
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cell arcs 9 9 0
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internal net arcs 4 4 0
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net arcs from primary inputs 5 5 0
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net arcs to primary outputs 1 1 0
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----------------------------------------------------------------
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19 19 0
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Annotated Arcs
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primary input net clk1 -> r1/CK
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primary input net clk2 -> r2/CK
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primary input net clk3 -> r3/CK
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primary input net in1 -> r1/D
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primary input net in2 -> r2/D
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delay r1/CK -> r1/QN
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delay r1/CK -> r1/Q
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internal net r1/Q -> u2/A1
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delay r2/CK -> r2/QN
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delay r2/CK -> r2/Q
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internal net r2/Q -> u1/A
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delay r3/CK -> r3/QN
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delay r3/CK -> r3/Q
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primary output net r3/Q -> out
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delay u1/A -> u1/Z
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internal net u1/Z -> u2/A2
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delay u2/A1 -> u2/ZN
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delay u2/A2 -> u2/ZN
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internal net u2/ZN -> r3/D
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PASS: annotated delay -report_annotated
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Not
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Delay type Total Annotated Annotated
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----------------------------------------------------------------
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cell arcs 9 9 0
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internal net arcs 4 4 0
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net arcs from primary inputs 5 5 0
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net arcs to primary outputs 1 1 0
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----------------------------------------------------------------
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19 19 0
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Unannotated Arcs
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PASS: annotated delay -report_unannotated
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Not
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Delay type Total Annotated Annotated
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----------------------------------------------------------------
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cell arcs 9 9 0
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constant arcs 0 0
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internal net arcs 4 4 0
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constant arcs 0 0
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net arcs from primary inputs 5 5 0
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constant arcs 0 0
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net arcs to primary outputs 1 1 0
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constant arcs 0 0
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----------------------------------------------------------------
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19 19 0
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PASS: annotated delay -constant_arcs
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Not
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Delay type Total Annotated Annotated
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----------------------------------------------------------------
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cell arcs 9 9 0
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internal net arcs 4 4 0
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net arcs from primary inputs 5 5 0
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net arcs to primary outputs 1 1 0
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----------------------------------------------------------------
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19 19 0
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PASS: annotated delay -max_lines 5
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--- annotated check with interconnect ---
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Not
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Check type Total Annotated Annotated
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----------------------------------------------------------------
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cell setup arcs 3 3 0
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cell hold arcs 3 3 0
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cell width arcs 3 3 0
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----------------------------------------------------------------
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9 9 0
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PASS: annotated check all
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Not
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Check type Total Annotated Annotated
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----------------------------------------------------------------
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cell setup arcs 3 3 0
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----------------------------------------------------------------
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3 3 0
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PASS: annotated check -setup
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Not
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Check type Total Annotated Annotated
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----------------------------------------------------------------
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cell hold arcs 3 3 0
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----------------------------------------------------------------
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3 3 0
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PASS: annotated check -hold
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Not
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Check type Total Annotated Annotated
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----------------------------------------------------------------
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cell setup arcs 3 3 0
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cell hold arcs 3 3 0
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----------------------------------------------------------------
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6 6 0
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PASS: annotated check -setup -hold
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Not
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Check type Total Annotated Annotated
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----------------------------------------------------------------
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cell setup arcs 3 3 0
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cell hold arcs 3 3 0
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cell width arcs 3 3 0
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----------------------------------------------------------------
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9 9 0
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Annotated Arcs
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width r1/CK -> r1/CK
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setup r1/CK -> r1/D
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hold r1/CK -> r1/D
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width r2/CK -> r2/CK
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setup r2/CK -> r2/D
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hold r2/CK -> r2/D
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width r3/CK -> r3/CK
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setup r3/CK -> r3/D
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hold r3/CK -> r3/D
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PASS: annotated check -report_annotated
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Not
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Check type Total Annotated Annotated
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----------------------------------------------------------------
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cell setup arcs 3 3 0
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cell hold arcs 3 3 0
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cell width arcs 3 3 0
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----------------------------------------------------------------
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9 9 0
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Unannotated Arcs
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PASS: annotated check -report_unannotated
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Not
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Check type Total Annotated Annotated
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----------------------------------------------------------------
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cell setup arcs 3 3 0
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cell hold arcs 3 3 0
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cell width arcs 3 3 0
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----------------------------------------------------------------
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9 9 0
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PASS: annotated check -max_lines 3
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--- read original example SDF ---
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PASS: read example1.sdf
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Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (propagated)
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0.00 0.00 ^ r2/CK (DFF_X1)
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1.10 1.10 v r2/Q (DFF_X1)
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1.10 2.20 v u1/Z (BUF_X1)
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1.10 3.30 v u2/ZN (AND2_X1)
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0.00 3.30 v r3/D (DFF_X1)
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3.30 data arrival time
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500.00 500.00 clock clk (rise edge)
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0.00 500.00 clock network delay (propagated)
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0.00 500.00 clock reconvergence pessimism
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500.00 ^ r3/CK (DFF_X1)
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-0.50 499.50 library setup time
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499.50 data required time
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---------------------------------------------------------
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499.50 data required time
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-3.30 data arrival time
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---------------------------------------------------------
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496.20 slack (MET)
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PASS: report_checks with example1.sdf
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Not
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Delay type Total Annotated Annotated
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----------------------------------------------------------------
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cell arcs 9 9 0
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internal net arcs 4 4 0
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----------------------------------------------------------------
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13 13 0
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PASS: annotated delay after example1.sdf
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Not
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Check type Total Annotated Annotated
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----------------------------------------------------------------
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cell setup arcs 3 3 0
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cell hold arcs 3 3 0
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----------------------------------------------------------------
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6 6 0
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PASS: annotated check after example1.sdf
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--- write SDF after SDF annotation ---
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PASS: write_sdf after annotation size=2214
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ALL PASSED
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