29 lines
804 B
Plaintext
29 lines
804 B
Plaintext
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PASS: clocks created
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PASS: generated clock created
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PASS: delays set
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PASS: uncertainty set
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PASS: latency set
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PASS: transition set
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PASS: driving cell set
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PASS: load set
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PASS: input transition set
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PASS: false path set
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PASS: multicycle set
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PASS: max delay set
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PASS: design limits set
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PASS: case analysis set
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PASS: operating conditions set
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PASS: wire load model set
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PASS: timing derate set
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PASS: propagated clock set
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PASS: write_sdc
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No paths found.
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PASS: report_checks before clear
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Clock Period Waveform
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----------------------------------------------------
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clk1 10.00 0.00 5.00
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clk2 20.00 0.00 10.00
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gen_div2 20.00 0.00 10.00 (generated)
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PASS: report_clock_properties before clear
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ALL PASSED
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