110 lines
3.6 KiB
Plaintext
110 lines
3.6 KiB
Plaintext
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PASS: basic setup
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PASS: set_false_path -from -to
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PASS: set_false_path -from -through -to
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PASS: set_false_path -rise_from -fall_to
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PASS: set_false_path -from clk -to clk
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No paths found.
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PASS: report_checks after false_path
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PASS: unset_path_exceptions specific
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PASS: unset_path_exceptions with -through
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PASS: unset_path_exceptions rise_from/fall_to
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PASS: unset_path_exceptions clock domain
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PASS: set_multicycle_path -setup 2
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PASS: set_multicycle_path -hold 1
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PASS: set_multicycle_path -setup 3 pin-to-pin
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No paths found.
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PASS: report_checks after multicycle
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PASS: unset multicycle setup
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PASS: unset multicycle hold
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PASS: unset multicycle pin-to-pin
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PASS: set_max_delay
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PASS: set_min_delay
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No paths found.
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PASS: report_checks after max/min delay
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PASS: unset max/min delay paths
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PASS: group_path -name -from
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PASS: group_path -name -from -to
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Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
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Endpoint: out1 (output port clocked by clk1)
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Path Group: group_clk1
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk1 (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg2/CK (DFF_X1)
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0.08 0.08 ^ reg2/Q (DFF_X1)
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0.00 0.08 ^ out1 (out)
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0.08 data arrival time
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10.00 10.00 clock clk1 (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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-3.00 7.00 output external delay
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7.00 data required time
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---------------------------------------------------------
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7.00 data required time
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-0.08 data arrival time
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---------------------------------------------------------
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6.92 slack (MET)
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PASS: report_checks -path_group group_clk1
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No paths found.
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PASS: report_checks -path_group group_io
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Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
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Endpoint: out1 (output port clocked by clk1)
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Path Group: group_clk1
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk1 (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg2/CK (DFF_X1)
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0.08 0.08 ^ reg2/Q (DFF_X1)
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0.00 0.08 ^ out1 (out)
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0.08 data arrival time
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10.00 10.00 clock clk1 (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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-3.00 7.00 output external delay
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7.00 data required time
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---------------------------------------------------------
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7.00 data required time
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-0.08 data arrival time
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---------------------------------------------------------
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6.92 slack (MET)
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Startpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
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Endpoint: out2 (output port clocked by clk2)
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Path Group: clk2
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk2 (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg3/CK (DFF_X1)
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0.08 0.08 ^ reg3/Q (DFF_X1)
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0.00 0.08 ^ out2 (out)
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0.08 data arrival time
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20.00 20.00 clock clk2 (rise edge)
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0.00 20.00 clock network delay (ideal)
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0.00 20.00 clock reconvergence pessimism
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-3.00 17.00 output external delay
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17.00 data required time
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---------------------------------------------------------
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17.00 data required time
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-0.08 data arrival time
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---------------------------------------------------------
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16.92 slack (MET)
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PASS: final report_checks
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ALL PASSED
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