107 lines
3.5 KiB
Plaintext
107 lines
3.5 KiB
Plaintext
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PASS: setup
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PASS: max_transition design
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PASS: max_transition ports
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PASS: max_transition clock clk1 clk_path/data_path
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PASS: max_transition clock clk2 rise/fall per path type
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PASS: max_capacitance design
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PASS: max_capacitance ports
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PASS: max_capacitance pin
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PASS: min_capacitance design
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PASS: min_capacitance port
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PASS: max_fanout design
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PASS: max_fanout ports
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PASS: set_max_area
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PASS: min_pulse_width global
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PASS: min_pulse_width clock high/low
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PASS: min_pulse_width clock same
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PASS: min_pulse_width pins
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PASS: min_pulse_width instance
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PASS: max_time_borrow clocks
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PASS: max_time_borrow pin
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PASS: max_time_borrow instance
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PASS: max_transition input ports
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PASS: write_sdc
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PASS: write_sdc compatible
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PASS: write_sdc digits 8
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Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
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Endpoint: out1 (output port clocked by clk1)
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Path Group: clk1
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk1 (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg2/CK (DFF_X1)
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0.08 0.08 ^ reg2/Q (DFF_X1)
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0.00 0.08 ^ out1 (out)
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0.08 data arrival time
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10.00 10.00 clock clk1 (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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-3.00 7.00 output external delay
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7.00 data required time
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---------------------------------------------------------
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7.00 data required time
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-0.08 data arrival time
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---------------------------------------------------------
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6.92 slack (MET)
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
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Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
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Path Group: clk2
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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10.00 10.00 clock clk1 (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 ^ reg1/CK (DFF_X1)
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0.08 10.08 v reg1/Q (DFF_X1)
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0.00 10.08 v reg3/D (DFF_X1)
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10.08 data arrival time
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20.00 20.00 clock clk2 (rise edge)
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0.00 20.00 clock network delay (ideal)
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0.00 20.00 clock reconvergence pessimism
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20.00 ^ reg3/CK (DFF_X1)
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-0.04 19.96 library setup time
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19.96 data required time
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---------------------------------------------------------
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19.96 data required time
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-10.08 data arrival time
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---------------------------------------------------------
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9.88 slack (MET)
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PASS: read_sdc roundtrip
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max slew
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Pin Limit Slew Slack
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------------------------------------------------------------
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nor1/ZN 0.20 0.01 0.19 (MET)
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max fanout
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Pin Limit Fanout Slack
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---------------------------------------------------------
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in1 10 1 9 (MET)
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max capacitance
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Pin Limit Cap Slack
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------------------------------------------------------------
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or1/ZN 0.20 3.32 -3.12 (VIOLATED)
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PASS: report_check_types
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Required Actual
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Pin Width Width Slack
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------------------------------------------------------------
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reg2/CK (high) 0.35 5.00 4.65 (MET)
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PASS: report_check_types pulse_width
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PASS: write_sdc after re-read
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ALL PASSED
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