OpenSTA/network/test/network_multi_lib.ok

PASS: read Nangate45
PASS: read Nangate45 fast
PASS: read Sky130
PASS: read IHP
--- library queries ---
total libraries: 4
PASS: find NangateOpenCellLibrary
  name: NangateOpenCellLibrary
PASS: find NangateOpenCellLibrary_fast
PASS: find sky130 lib
PASS: find IHP lib
PASS: liberty_library_iterator
VDD supply exists: 1
VSS supply exists: 1
GND supply exists: 0
NONEXISTENT: 0
--- cross-library cell queries ---
PASS: find_liberty_cell INV_X1
  from library: NangateOpenCellLibrary
PASS: find_liberty_cell sky130 inv
  from library: sky130_fd_sc_hd__tt_025C_1v80
PASS: find_liberty_cell IHP inv
  from library: sg13g2_stdcell_typ_1p20V_25C
--- cell pattern matching ---
Nangate INV*: 6
Nangate BUF*: 6
Nangate DFF*: 8
Nangate SDFF*: 8
Nangate all: 134
Sky130 *inv*: 30
Sky130 *buf*: 46
Sky130 *dfxtp*: 10
Sky130 *dlx*: 7
Sky130 all: 428
IHP all: 78
--- cell port queries ---
PASS: INV_X1 ports A and ZN found
INV_X1 port match *: 4
PASS: DFF_X1 ports D, CK, Q, QN found
DFF_X1 port match *: 8
SDFF_X1 port match *: 10
PASS: SDFF_X1 scan ports SE, SI found
FA_X1 port match *: 7
CLKGATETST_X1 port match *: 7
INV_X1 timing_arc_sets: 1
DFF_X1 timing_arc_sets: 5
SDFF_X1 timing_arc_sets: 9
CLKGATETST_X1 timing_arc_sets: 9
PASS: cell port queries
Startpoint: in1 (input port clocked by clk)
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max

  Delay    Time   Description
---------------------------------------------------------
   0.00    0.00   clock clk (rise edge)
   0.00    0.00   clock network delay (ideal)
   0.00    0.00 v input external delay
   0.00    0.00 v in1 (in)
   0.04    0.04 v buf1/Z (BUF_X1)
   0.02    0.06 v and1/ZN (AND2_X1)
   0.00    0.06 v reg1/D (DFF_X1)
           0.06   data arrival time

  10.00   10.00   clock clk (rise edge)
   0.00   10.00   clock network delay (ideal)
   0.00   10.00   clock reconvergence pessimism
          10.00 ^ reg1/CK (DFF_X1)
  -0.02    9.98   library setup time
           9.98   data required time
---------------------------------------------------------
           9.98   data required time
          -0.06   data arrival time
---------------------------------------------------------
           9.92   slack (MET)


PASS: timing with multi-library
Startpoint: in1 (input port clocked by clk)
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max

  Delay    Time   Description
---------------------------------------------------------
   0.00    0.00   clock clk (rise edge)
   0.00    0.00   clock network delay (ideal)
   0.00    0.00 v input external delay
   0.00    0.00 v in1 (in)
   0.04    0.04 v buf1/Z (BUF_X2)
   0.02    0.05 v and1/ZN (AND2_X1)
   0.00    0.05 v reg1/D (DFF_X1)
           0.05   data arrival time

  10.00   10.00   clock clk (rise edge)
   0.00   10.00   clock network delay (ideal)
   0.00   10.00   clock reconvergence pessimism
          10.00 ^ reg1/CK (DFF_X1)
  -0.02    9.98   library setup time
           9.98   data required time
---------------------------------------------------------
           9.98   data required time
          -0.05   data arrival time
---------------------------------------------------------
           9.92   slack (MET)


PASS: replace_cell with multi-lib
--- equiv cells multi-lib ---
INV_X1 equivs: 6
BUF_X1 equivs: 9
PASS: find_library_buffers: 9
PASS: equiv cells
ALL PASSED