OpenSTA/dcalc/test/dcalc_annotated_incremental.ok

--- setIncrementalDelayTolerance ---
PASS: incremental delay tolerance 0.01
PASS: incremental delay tolerance 0.0
PASS: incremental delay tolerance 0.1
--- report_net for various nets ---
Net n1
 Pin capacitance: 1.55-1.70
 Wire capacitance: 0.00
 Total capacitance: 1.55-1.70
 Number of drivers: 1
 Number of loads: 1
 Number of pins: 2

Driver pins
 buf1/Z output (BUF_X1)

Load pins
 inv1/A input (INV_X1) 1.55-1.70

Net n2
 Pin capacitance: 1.59-1.78
 Wire capacitance: 0.00
 Total capacitance: 1.59-1.78
 Number of drivers: 1
 Number of loads: 1
 Number of pins: 2

Driver pins
 inv1/ZN output (INV_X1)

Load pins
 buf2/A input (BUF_X2) 1.59-1.78

Net n3
 Pin capacitance: 0.79-0.95
 Wire capacitance: 0.00
 Total capacitance: 0.79-0.95
 Number of drivers: 1
 Number of loads: 1
 Number of pins: 2

Driver pins
 buf2/Z output (BUF_X2)

Load pins
 or1/A1 input (OR2_X1) 0.79-0.95

Net n4
 Pin capacitance: 0.87-0.92
 Wire capacitance: 0.00
 Total capacitance: 0.87-0.92
 Number of drivers: 1
 Number of loads: 1
 Number of pins: 2

Driver pins
 buf3/Z output (BUF_X4)

Load pins
 and1/A1 input (AND2_X1) 0.87-0.92

Net n5
 Pin capacitance: 0.90-0.94
 Wire capacitance: 0.00
 Total capacitance: 0.90-0.94
 Number of drivers: 1
 Number of loads: 1
 Number of pins: 2

Driver pins
 and1/ZN output (AND2_X1)

Load pins
 or1/A2 input (OR2_X1) 0.90-0.94

Net n6
 Pin capacitance: 3.82-4.29
 Wire capacitance: 0.00
 Total capacitance: 3.82-4.29
 Number of drivers: 1
 Number of loads: 3
 Number of pins: 4

Driver pins
 or1/ZN output (OR2_X1)

Load pins
 buf_out/A input (BUF_X1) 0.88-0.97
 nand1/A1 input (NAND2_X1) 1.53-1.60
 nor1/A1 input (NOR2_X1) 1.41-1.71

Net n7
 Pin capacitance: 1.06-1.14
 Wire capacitance: 0.00
 Total capacitance: 1.06-1.14
 Number of drivers: 1
 Number of loads: 1
 Number of pins: 2

Driver pins
 nand1/ZN output (NAND2_X1)

Load pins
 reg1/D input (DFF_X1) 1.06-1.14

Net n8
 Pin capacitance: 1.06-1.14
 Wire capacitance: 0.00
 Total capacitance: 1.06-1.14
 Number of drivers: 1
 Number of loads: 1
 Number of pins: 2

Driver pins
 nor1/ZN output (NOR2_X1)

Load pins
 reg2/D input (DFF_X1) 1.06-1.14

PASS: report_net all nets
--- report_net with loads ---
Net n6
 Pin capacitance: 3.82-4.29
 Wire capacitance: 0.00
 Total capacitance: 3.82-4.29
 Number of drivers: 1
 Number of loads: 3
 Number of pins: 4

Driver pins
 or1/ZN output (OR2_X1)

Load pins
 buf_out/A input (BUF_X1) 0.88-0.97
 nand1/A1 input (NAND2_X1) 1.53-1.60
 nor1/A1 input (NOR2_X1) 1.41-1.71

Net n7
 Pin capacitance: 1.06-1.14
 Wire capacitance: 0.00
 Total capacitance: 1.06-1.14
 Number of drivers: 1
 Number of loads: 1
 Number of pins: 2

Driver pins
 nand1/ZN output (NAND2_X1)

Load pins
 reg1/D input (DFF_X1) 1.06-1.14

Net n8
 Pin capacitance: 1.06-1.14
 Wire capacitance: 0.00
 Total capacitance: 1.06-1.14
 Number of drivers: 1
 Number of loads: 1
 Number of pins: 2

Driver pins
 nor1/ZN output (NOR2_X1)

Load pins
 reg2/D input (DFF_X1) 1.06-1.14

PASS: report_net with loads
--- report_net with digits ---
Net n1
 Pin capacitance: 1.549360-1.700230
 Wire capacitance: 0.000000
 Total capacitance: 1.549360-1.700230
 Number of drivers: 1
 Number of loads: 1
 Number of pins: 2

Driver pins
 buf1/Z output (BUF_X1)

Load pins
 inv1/A input (INV_X1) 1.549360-1.700230

Net n6
 Pin capacitance: 3.82-4.29
 Wire capacitance: 0.00
 Total capacitance: 3.82-4.29
 Number of drivers: 1
 Number of loads: 3
 Number of pins: 4

Driver pins
 or1/ZN output (OR2_X1)

Load pins
 buf_out/A input (BUF_X1) 0.88-0.97
 nand1/A1 input (NAND2_X1) 1.53-1.60
 nor1/A1 input (NOR2_X1) 1.41-1.71

PASS: report_net digits
--- incremental with wire caps ---
Startpoint: in2 (input port clocked by clk)
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max

  Delay    Time   Description
---------------------------------------------------------
   0.00    0.00   clock clk (rise edge)
   0.00    0.00   clock network delay (ideal)
   0.00    0.00 v input external delay
   0.00    0.00 v in2 (in)
   0.05    0.05 v buf3/Z (BUF_X4)
   0.03    0.08 v and1/ZN (AND2_X1)
   0.05    0.13 v or1/ZN (OR2_X1)
   0.02    0.15 ^ nor1/ZN (NOR2_X1)
   0.00    0.15 ^ reg2/D (DFF_X1)
           0.15   data arrival time

  10.00   10.00   clock clk (rise edge)
   0.00   10.00   clock network delay (ideal)
   0.00   10.00   clock reconvergence pessimism
          10.00 ^ reg2/CK (DFF_X1)
  -0.04    9.96   library setup time
           9.96   data required time
---------------------------------------------------------
           9.96   data required time
          -0.15   data arrival time
---------------------------------------------------------
           9.81   slack (MET)


PASS: wire cap n1
Startpoint: in2 (input port clocked by clk)
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max

  Delay    Time   Description
---------------------------------------------------------
   0.00    0.00   clock clk (rise edge)
   0.00    0.00   clock network delay (ideal)
   0.00    0.00 v input external delay
   0.00    0.00 v in2 (in)
   0.05    0.05 v buf3/Z (BUF_X4)
   0.03    0.08 v and1/ZN (AND2_X1)
   0.05    0.13 v or1/ZN (OR2_X1)
   0.02    0.15 ^ nor1/ZN (NOR2_X1)
   0.00    0.15 ^ reg2/D (DFF_X1)
           0.15   data arrival time

  10.00   10.00   clock clk (rise edge)
   0.00   10.00   clock network delay (ideal)
   0.00   10.00   clock reconvergence pessimism
          10.00 ^ reg2/CK (DFF_X1)
  -0.04    9.96   library setup time
           9.96   data required time
---------------------------------------------------------
           9.96   data required time
          -0.15   data arrival time
---------------------------------------------------------
           9.81   slack (MET)


PASS: wire cap n6
--- rapid constraint changes ---
No paths found.
No paths found.
No paths found.
No paths found.
No paths found.
No paths found.
PASS: rapid constraint changes
--- input transition incremental ---
No paths found.
No paths found.
No paths found.
No paths found.
No paths found.
No paths found.
No paths found.
No paths found.
PASS: input transition incremental
--- clock period incremental ---
Startpoint: in2 (input port clocked by clk)
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max

  Delay    Time   Description
---------------------------------------------------------
   0.00    0.00   clock clk (rise edge)
   0.00    0.00   clock network delay (ideal)
   0.00    0.00 v input external delay
   0.00    0.00 v in2 (in)
   0.05    0.05 v buf3/Z (BUF_X4)
   0.03    0.08 v and1/ZN (AND2_X1)
   0.05    0.13 v or1/ZN (OR2_X1)
   0.02    0.15 ^ nor1/ZN (NOR2_X1)
   0.00    0.15 ^ reg2/D (DFF_X1)
           0.15   data arrival time

   5.00    5.00   clock clk (rise edge)
   0.00    5.00   clock network delay (ideal)
   0.00    5.00   clock reconvergence pessimism
           5.00 ^ reg2/CK (DFF_X1)
  -0.04    4.96   library setup time
           4.96   data required time
---------------------------------------------------------
           4.96   data required time
          -0.15   data arrival time
---------------------------------------------------------
           4.81   slack (MET)


Startpoint: in2 (input port clocked by clk)
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max

  Delay    Time   Description
---------------------------------------------------------
   0.00    0.00   clock clk (rise edge)
   0.00    0.00   clock network delay (ideal)
   0.00    0.00 v input external delay
   0.00    0.00 v in2 (in)
   0.05    0.05 v buf3/Z (BUF_X4)
   0.03    0.08 v and1/ZN (AND2_X1)
   0.05    0.13 v or1/ZN (OR2_X1)
   0.02    0.15 ^ nor1/ZN (NOR2_X1)
   0.00    0.15 ^ reg2/D (DFF_X1)
           0.15   data arrival time

  20.00   20.00   clock clk (rise edge)
   0.00   20.00   clock network delay (ideal)
   0.00   20.00   clock reconvergence pessimism
          20.00 ^ reg2/CK (DFF_X1)
  -0.04   19.96   library setup time
          19.96   data required time
---------------------------------------------------------
          19.96   data required time
          -0.15   data arrival time
---------------------------------------------------------
          19.81   slack (MET)


Startpoint: in2 (input port clocked by clk)
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max

  Delay    Time   Description
---------------------------------------------------------
   0.00    0.00   clock clk (rise edge)
   0.00    0.00   clock network delay (ideal)
   0.00    0.00 v input external delay
   0.00    0.00 v in2 (in)
   0.05    0.05 v buf3/Z (BUF_X4)
   0.03    0.08 v and1/ZN (AND2_X1)
   0.05    0.13 v or1/ZN (OR2_X1)
   0.02    0.15 ^ nor1/ZN (NOR2_X1)
   0.00    0.15 ^ reg2/D (DFF_X1)
           0.15   data arrival time

   2.00    2.00   clock clk (rise edge)
   0.00    2.00   clock network delay (ideal)
   0.00    2.00   clock reconvergence pessimism
           2.00 ^ reg2/CK (DFF_X1)
  -0.04    1.96   library setup time
           1.96   data required time
---------------------------------------------------------
           1.96   data required time
          -0.15   data arrival time
---------------------------------------------------------
           1.81   slack (MET)


Startpoint: in2 (input port clocked by clk)
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max

  Delay    Time   Description
---------------------------------------------------------
   0.00    0.00   clock clk (rise edge)
   0.00    0.00   clock network delay (ideal)
   0.00    0.00 v input external delay
   0.00    0.00 v in2 (in)
   0.05    0.05 v buf3/Z (BUF_X4)
   0.03    0.08 v and1/ZN (AND2_X1)
   0.05    0.13 v or1/ZN (OR2_X1)
   0.02    0.15 ^ nor1/ZN (NOR2_X1)
   0.00    0.15 ^ reg2/D (DFF_X1)
           0.15   data arrival time

  10.00   10.00   clock clk (rise edge)
   0.00   10.00   clock network delay (ideal)
   0.00   10.00   clock reconvergence pessimism
          10.00 ^ reg2/CK (DFF_X1)
  -0.04    9.96   library setup time
           9.96   data required time
---------------------------------------------------------
           9.96   data required time
          -0.15   data arrival time
---------------------------------------------------------
           9.81   slack (MET)


PASS: clock period incremental
--- delay calc after constraint changes ---
No paths found.
No paths found.
No paths found.
PASS: constraint change incremental
--- driving cell changes ---
No paths found.
No paths found.
No paths found.
PASS: driving cell changes
--- write and read SDF ---
Startpoint: in2 (input port clocked by clk)
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max

  Delay    Time   Description
---------------------------------------------------------
   0.00    0.00   clock clk (rise edge)
   0.00    0.00   clock network delay (ideal)
   0.00    0.00 v input external delay
   0.00    0.00 v in2 (in)
   0.05    0.05 v buf3/Z (BUF_X4)
   0.03    0.08 v and1/ZN (AND2_X1)
   0.05    0.13 v or1/ZN (OR2_X1)
   0.02    0.15 ^ nor1/ZN (NOR2_X1)
   0.00    0.15 ^ reg2/D (DFF_X1)
           0.15   data arrival time

  10.00   10.00   clock clk (rise edge)
   0.00   10.00   clock network delay (ideal)
   0.00   10.00   clock reconvergence pessimism
          10.00 ^ reg2/CK (DFF_X1)
  -0.04    9.97   library setup time
           9.97   data required time
---------------------------------------------------------
           9.97   data required time
          -0.15   data arrival time
---------------------------------------------------------
           9.81   slack (MET)


Warning: dcalc_annotated_incremental.tcl line 1, -list_annotated is deprecated. Use -report_annotated.
                                                          Not   
Delay type                        Total    Annotated   Annotated
----------------------------------------------------------------
cell arcs                            17          17           0
internal net arcs                    10          10           0
net arcs from primary inputs          7           7           0
net arcs to primary outputs           3           3           0
----------------------------------------------------------------
                                     37          37           0

Annotated Arcs
 primary input net  clk -> reg1/CK 
 primary input net  clk -> reg2/CK 
 primary input net  in1 -> buf1/A 
 primary input net  in2 -> buf3/A 
 primary input net  in3 -> and1/A2 
 primary input net  in4 -> nor1/A2 
 primary input net  sel -> nand1/A2 
 delay              and1/A1 -> and1/ZN 
 delay              and1/A2 -> and1/ZN 
 internal net       and1/ZN -> or1/A2 
 delay              buf1/A -> buf1/Z 
 internal net       buf1/Z -> inv1/A 
 delay              buf2/A -> buf2/Z 
 internal net       buf2/Z -> or1/A1 
 delay              buf3/A -> buf3/Z 
 internal net       buf3/Z -> and1/A1 
 delay              buf_out/A -> buf_out/Z 
 primary output net buf_out/Z -> out3 
 delay              inv1/A -> inv1/ZN 
 internal net       inv1/ZN -> buf2/A 
 delay              nand1/A1 -> nand1/ZN 
 delay              nand1/A2 -> nand1/ZN 
 internal net       nand1/ZN -> reg1/D 
 delay              nor1/A1 -> nor1/ZN 
 delay              nor1/A2 -> nor1/ZN 
 internal net       nor1/ZN -> reg2/D 
 delay              or1/A1 -> or1/ZN 
 delay              or1/A2 -> or1/ZN 
 internal net       or1/ZN -> nand1/A1 
 internal net       or1/ZN -> nor1/A1 
 internal net       or1/ZN -> buf_out/A 
 delay              reg1/CK -> reg1/QN 
 delay              reg1/CK -> reg1/Q 
 primary output net reg1/Q -> out1 
 delay              reg2/CK -> reg2/QN 
 delay              reg2/CK -> reg2/Q 
 primary output net reg2/Q -> out2 
Warning: dcalc_annotated_incremental.tcl line 1, -list_annotated is deprecated. Use -report_annotated.
                                                          Not   
Check type                        Total    Annotated   Annotated
----------------------------------------------------------------
cell setup arcs                       2           2           0
cell hold arcs                        2           2           0
----------------------------------------------------------------
                                      4           4           0

Annotated Arcs
 setup              reg1/CK -> reg1/D 
 hold               reg1/CK -> reg1/D 
 setup              reg2/CK -> reg2/D 
 hold               reg2/CK -> reg2/D 
PASS: write/read SDF
--- remove annotations ---
Startpoint: in2 (input port clocked by clk)
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max

  Delay    Time   Description
---------------------------------------------------------
   0.00    0.00   clock clk (rise edge)
   0.00    0.00   clock network delay (ideal)
   0.00    0.00 v input external delay
   0.00    0.00 v in2 (in)
   0.05    0.05 v buf3/Z (BUF_X4)
   0.03    0.08 v and1/ZN (AND2_X1)
   0.05    0.13 v or1/ZN (OR2_X1)
   0.02    0.15 ^ nor1/ZN (NOR2_X1)
   0.00    0.15 ^ reg2/D (DFF_X1)
           0.15   data arrival time

  10.00   10.00   clock clk (rise edge)
   0.00   10.00   clock network delay (ideal)
   0.00   10.00   clock reconvergence pessimism
          10.00 ^ reg2/CK (DFF_X1)
  -0.04    9.96   library setup time
           9.96   data required time
---------------------------------------------------------
           9.96   data required time
          -0.15   data arrival time
---------------------------------------------------------
           9.81   slack (MET)


PASS: remove annotations
--- calculator switch incremental ---
No paths found.
No paths found.
No paths found.
No paths found.
PASS: calculator switch incremental
ALL PASSED