OpenSTA/include/sta/VerilogNamespace.hh

// OpenSTA, Static Timing Analyzer
// Copyright (c) 2024, Parallax Software, Inc.
// 
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
// 
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
// 
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <https://www.gnu.org/licenses/>.

#pragma once

#include <string>

namespace sta {

using std::string;

string
cellVerilogName(const char *sta_name);
string
instanceVerilogName(const char *sta_name);
string
netVerilogName(const char *sta_name);
string
portVerilogName(const char *sta_name);

string
moduleVerilogToSta(const string *sta_name);
string
instanceVerilogToSta(const string *sta_name);
string
netVerilogToSta(const string *sta_name);
string
portVerilogToSta(const string *sta_name);

} // namespace